1 /* $OpenBSD: fxp.c,v 1.78 2006/05/22 20:35:12 krw Exp $ */
2 /* $NetBSD: if_fxp.c,v 1.2 1997/06/05 02:01:55 thorpej Exp $ */
3
4 /*
5 * Copyright (c) 1995, David Greenman
6 * All rights reserved.
7 *
8 * Modifications to support NetBSD:
9 * Copyright (c) 1997 Jason R. Thorpe. All rights reserved.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice unmodified, this list of conditions, and the following
16 * disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 *
33 * Id: if_fxp.c,v 1.55 1998/08/04 08:53:12 dg Exp
34 */
35
36 /*
37 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver
38 */
39
40 #include "bpfilter.h"
41 #include "vlan.h"
42
43 #include <sys/param.h>
44 #include <sys/systm.h>
45 #include <sys/mbuf.h>
46 #include <sys/malloc.h>
47 #include <sys/kernel.h>
48 #include <sys/socket.h>
49 #include <sys/syslog.h>
50 #include <sys/timeout.h>
51
52 #include <net/if.h>
53 #include <net/if_dl.h>
54 #include <net/if_media.h>
55 #include <net/if_types.h>
56
57 #ifdef INET
58 #include <netinet/in.h>
59 #include <netinet/in_systm.h>
60 #include <netinet/in_var.h>
61 #include <netinet/ip.h>
62 #endif
63
64 #ifdef IPX
65 #include <netipx/ipx.h>
66 #include <netipx/ipx_if.h>
67 #endif
68
69 #if NBPFILTER > 0
70 #include <net/bpf.h>
71 #endif
72
73 #include <sys/ioctl.h>
74 #include <sys/errno.h>
75 #include <sys/device.h>
76
77 #include <netinet/if_ether.h>
78
79 #include <machine/cpu.h>
80 #include <machine/bus.h>
81 #include <machine/intr.h>
82
83 #include <dev/mii/miivar.h>
84
85 #include <dev/ic/fxpreg.h>
86 #include <dev/ic/fxpvar.h>
87
88 /*
89 * NOTE! On the Alpha, we have an alignment constraint. The
90 * card DMAs the packet immediately following the RFA. However,
91 * the first thing in the packet is a 14-byte Ethernet header.
92 * This means that the packet is misaligned. To compensate,
93 * we actually offset the RFA 2 bytes into the cluster. This
94 * aligns the packet after the Ethernet header at a 32-bit
95 * boundary. HOWEVER! This means that the RFA is misaligned!
96 */
97 #define RFA_ALIGNMENT_FUDGE (2 + sizeof(bus_dmamap_t *))
98
99 /*
100 * Inline function to copy a 16-bit aligned 32-bit quantity.
101 */
102 static __inline void fxp_lwcopy(volatile u_int32_t *,
103 volatile u_int32_t *);
104 static __inline void
fxp_lwcopy(src,dst)105 fxp_lwcopy(src, dst)
106 volatile u_int32_t *src, *dst;
107 {
108 volatile u_int16_t *a = (u_int16_t *)src;
109 volatile u_int16_t *b = (u_int16_t *)dst;
110
111 b[0] = a[0];
112 b[1] = a[1];
113 }
114
115 /*
116 * Template for default configuration parameters.
117 * See struct fxp_cb_config for the bit definitions.
118 * Note, cb_command is filled in later.
119 */
120 static u_char fxp_cb_config_template[] = {
121 0x0, 0x0, /* cb_status */
122 0x0, 0x0, /* cb_command */
123 0xff, 0xff, 0xff, 0xff, /* link_addr */
124 0x16, /* 0 Byte count. */
125 0x08, /* 1 Fifo limit */
126 0x00, /* 2 Adaptive ifs */
127 0x00, /* 3 ctrl0 */
128 0x00, /* 4 rx_dma_bytecount */
129 0x80, /* 5 tx_dma_bytecount */
130 0xb2, /* 6 ctrl 1*/
131 0x03, /* 7 ctrl 2*/
132 0x01, /* 8 mediatype */
133 0x00, /* 9 void2 */
134 0x26, /* 10 ctrl3 */
135 0x00, /* 11 linear priority */
136 0x60, /* 12 interfrm_spacing */
137 0x00, /* 13 void31 */
138 0xf2, /* 14 void32 */
139 0x48, /* 15 promiscuous */
140 0x00, /* 16 void41 */
141 0x40, /* 17 void42 */
142 0xf3, /* 18 stripping */
143 0x00, /* 19 fdx_pin */
144 0x3f, /* 20 multi_ia */
145 0x05 /* 21 mc_all */
146 };
147
148 void fxp_eeprom_shiftin(struct fxp_softc *, int, int);
149 void fxp_eeprom_putword(struct fxp_softc *, int, u_int16_t);
150 void fxp_write_eeprom(struct fxp_softc *, u_short *, int, int);
151 int fxp_mediachange(struct ifnet *);
152 void fxp_mediastatus(struct ifnet *, struct ifmediareq *);
153 void fxp_scb_wait(struct fxp_softc *);
154 void fxp_start(struct ifnet *);
155 int fxp_ioctl(struct ifnet *, u_long, caddr_t);
156 void fxp_init(void *);
157 void fxp_stop(struct fxp_softc *, int);
158 void fxp_watchdog(struct ifnet *);
159 int fxp_add_rfabuf(struct fxp_softc *, struct mbuf *);
160 int fxp_mdi_read(struct device *, int, int);
161 void fxp_mdi_write(struct device *, int, int, int);
162 void fxp_autosize_eeprom(struct fxp_softc *);
163 void fxp_statchg(struct device *);
164 void fxp_read_eeprom(struct fxp_softc *, u_int16_t *,
165 int, int);
166 void fxp_stats_update(void *);
167 void fxp_mc_setup(struct fxp_softc *, int);
168 void fxp_scb_cmd(struct fxp_softc *, u_int8_t);
169
170 /*
171 * Set initial transmit threshold at 64 (512 bytes). This is
172 * increased by 64 (512 bytes) at a time, to maximum of 192
173 * (1536 bytes), if an underrun occurs.
174 */
175 static int tx_threshold = 64;
176
177 /*
178 * Interrupts coalescing code params
179 */
180 int fxp_int_delay = FXP_INT_DELAY;
181 int fxp_bundle_max = FXP_BUNDLE_MAX;
182 int fxp_min_size_mask = FXP_MIN_SIZE_MASK;
183
184 /*
185 * TxCB list index mask. This is used to do list wrap-around.
186 */
187 #define FXP_TXCB_MASK (FXP_NTXCB - 1)
188
189 /*
190 * Maximum number of seconds that the receiver can be idle before we
191 * assume it's dead and attempt to reset it by reprogramming the
192 * multicast filter. This is part of a work-around for a bug in the
193 * NIC. See fxp_stats_update().
194 */
195 #define FXP_MAX_RX_IDLE 15
196
197 /*
198 * Wait for the previous command to be accepted (but not necessarily
199 * completed).
200 */
201 void
fxp_scb_wait(sc)202 fxp_scb_wait(sc)
203 struct fxp_softc *sc;
204 {
205 int i = 10000;
206
207 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i)
208 DELAY(2);
209 if (i == 0)
210 printf("%s: warning: SCB timed out\n", sc->sc_dev.dv_xname);
211 }
212
213 void
fxp_eeprom_shiftin(struct fxp_softc * sc,int data,int length)214 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length)
215 {
216 u_int16_t reg;
217 int x;
218
219 /*
220 * Shift in data.
221 */
222 for (x = 1 << (length - 1); x; x >>= 1) {
223 if (data & x)
224 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
225 else
226 reg = FXP_EEPROM_EECS;
227 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
228 DELAY(1);
229 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
230 DELAY(1);
231 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
232 DELAY(1);
233 }
234 }
235
236 void
fxp_eeprom_putword(struct fxp_softc * sc,int offset,u_int16_t data)237 fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data)
238 {
239 int i;
240
241 /*
242 * Erase/write enable.
243 */
244 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
245 fxp_eeprom_shiftin(sc, 0x4, 3);
246 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size);
247 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
248 DELAY(1);
249 /*
250 * Shift in write opcode, address, data.
251 */
252 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
253 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3);
254 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size);
255 fxp_eeprom_shiftin(sc, data, 16);
256 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
257 DELAY(1);
258 /*
259 * Wait for EEPROM to finish up.
260 */
261 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
262 DELAY(1);
263 for (i = 0; i < 1000; i++) {
264 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
265 break;
266 DELAY(50);
267 }
268 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
269 DELAY(1);
270 /*
271 * Erase/write disable.
272 */
273 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
274 fxp_eeprom_shiftin(sc, 0x4, 3);
275 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size);
276 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
277 DELAY(1);
278 }
279
280 void
fxp_write_eeprom(struct fxp_softc * sc,u_short * data,int offset,int words)281 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
282 {
283 int i;
284
285 for (i = 0; i < words; i++)
286 fxp_eeprom_putword(sc, offset + i, data[i]);
287 }
288
289 /*************************************************************
290 * Operating system-specific autoconfiguration glue
291 *************************************************************/
292
293 void fxp_shutdown(void *);
294 void fxp_power(int, void *);
295
296 struct cfdriver fxp_cd = {
297 NULL, "fxp", DV_IFNET
298 };
299
300 /*
301 * Device shutdown routine. Called at system shutdown after sync. The
302 * main purpose of this routine is to shut off receiver DMA so that
303 * kernel memory doesn't get clobbered during warmboot.
304 */
305 void
fxp_shutdown(sc)306 fxp_shutdown(sc)
307 void *sc;
308 {
309 fxp_stop((struct fxp_softc *) sc, 0);
310 }
311
312 /*
313 * Power handler routine. Called when the system is transitioning
314 * into/out of power save modes. As with fxp_shutdown, the main
315 * purpose of this routine is to shut off receiver DMA so it doesn't
316 * clobber kernel memory at the wrong time.
317 */
318 void
fxp_power(why,arg)319 fxp_power(why, arg)
320 int why;
321 void *arg;
322 {
323 struct fxp_softc *sc = arg;
324 struct ifnet *ifp;
325 int s;
326
327 s = splnet();
328 if (why != PWR_RESUME)
329 fxp_stop(sc, 0);
330 else {
331 ifp = &sc->sc_arpcom.ac_if;
332 if (ifp->if_flags & IFF_UP)
333 fxp_init(sc);
334 }
335 splx(s);
336 }
337
338 /*************************************************************
339 * End of operating system-specific autoconfiguration glue
340 *************************************************************/
341
342 /*
343 * Do generic parts of attach.
344 */
345 int
fxp_attach_common(sc,intrstr)346 fxp_attach_common(sc, intrstr)
347 struct fxp_softc *sc;
348 const char *intrstr;
349 {
350 struct ifnet *ifp;
351 struct mbuf *m;
352 bus_dmamap_t rxmap;
353 u_int16_t data;
354 u_int8_t enaddr[6];
355 int i, err;
356
357 /*
358 * Reset to a stable state.
359 */
360 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
361 DELAY(10);
362
363 if (bus_dmamem_alloc(sc->sc_dmat, sizeof(struct fxp_ctrl),
364 PAGE_SIZE, 0, &sc->sc_cb_seg, 1, &sc->sc_cb_nseg, BUS_DMA_NOWAIT))
365 goto fail;
366 if (bus_dmamem_map(sc->sc_dmat, &sc->sc_cb_seg, sc->sc_cb_nseg,
367 sizeof(struct fxp_ctrl), (caddr_t *)&sc->sc_ctrl,
368 BUS_DMA_NOWAIT)) {
369 bus_dmamem_free(sc->sc_dmat, &sc->sc_cb_seg, sc->sc_cb_nseg);
370 goto fail;
371 }
372 if (bus_dmamap_create(sc->sc_dmat, sizeof(struct fxp_ctrl),
373 1, sizeof(struct fxp_ctrl), 0, BUS_DMA_NOWAIT,
374 &sc->tx_cb_map)) {
375 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_ctrl,
376 sizeof(struct fxp_ctrl));
377 bus_dmamem_free(sc->sc_dmat, &sc->sc_cb_seg, sc->sc_cb_nseg);
378 goto fail;
379 }
380 if (bus_dmamap_load(sc->sc_dmat, sc->tx_cb_map, (caddr_t)sc->sc_ctrl,
381 sizeof(struct fxp_ctrl), NULL, BUS_DMA_NOWAIT)) {
382 bus_dmamap_destroy(sc->sc_dmat, sc->tx_cb_map);
383 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_ctrl,
384 sizeof(struct fxp_ctrl));
385 bus_dmamem_free(sc->sc_dmat, &sc->sc_cb_seg, sc->sc_cb_nseg);
386 }
387
388 for (i = 0; i < FXP_NTXCB; i++) {
389 if ((err = bus_dmamap_create(sc->sc_dmat, MCLBYTES,
390 FXP_NTXSEG, MCLBYTES, 0, 0, &sc->txs[i].tx_map)) != 0) {
391 printf("%s: unable to create tx dma map %d, error %d\n",
392 sc->sc_dev.dv_xname, i, err);
393 goto fail;
394 }
395 sc->txs[i].tx_mbuf = NULL;
396 sc->txs[i].tx_cb = sc->sc_ctrl->tx_cb + i;
397 sc->txs[i].tx_off = offsetof(struct fxp_ctrl, tx_cb[i]);
398 sc->txs[i].tx_next = &sc->txs[(i + 1) & FXP_TXCB_MASK];
399 }
400 bzero(sc->sc_ctrl, sizeof(struct fxp_ctrl));
401
402 /*
403 * Pre-allocate some receive buffers.
404 */
405 sc->sc_rxfree = 0;
406 for (i = 0; i < FXP_NRFABUFS_MIN; i++) {
407 if ((err = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1,
408 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) {
409 printf("%s: unable to create rx dma map %d, error %d\n",
410 sc->sc_dev.dv_xname, i, err);
411 goto fail;
412 }
413 sc->rx_bufs++;
414 }
415 for (i = 0; i < FXP_NRFABUFS_MIN; i++)
416 if (fxp_add_rfabuf(sc, NULL) != 0)
417 goto fail;
418
419 /*
420 * Find out how large of an SEEPROM we have.
421 */
422 fxp_autosize_eeprom(sc);
423
424 /*
425 * Get info about the primary PHY
426 */
427 fxp_read_eeprom(sc, (u_int16_t *)&data, 6, 1);
428 sc->phy_primary_addr = data & 0xff;
429 sc->phy_primary_device = (data >> 8) & 0x3f;
430 sc->phy_10Mbps_only = data >> 15;
431
432 /*
433 * Only 82558 and newer cards can do this.
434 */
435 if (sc->sc_revision >= FXP_REV_82558_A4) {
436 sc->sc_int_delay = fxp_int_delay;
437 sc->sc_bundle_max = fxp_bundle_max;
438 sc->sc_min_size_mask = fxp_min_size_mask;
439 }
440 /*
441 * Read MAC address.
442 */
443 fxp_read_eeprom(sc, (u_int16_t *)enaddr, 0, 3);
444
445 ifp = &sc->sc_arpcom.ac_if;
446 bcopy(enaddr, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN);
447 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ);
448 ifp->if_softc = sc;
449 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
450 ifp->if_ioctl = fxp_ioctl;
451 ifp->if_start = fxp_start;
452 ifp->if_watchdog = fxp_watchdog;
453 IFQ_SET_MAXLEN(&ifp->if_snd, FXP_NTXCB - 1);
454 IFQ_SET_READY(&ifp->if_snd);
455
456 ifp->if_capabilities = IFCAP_VLAN_MTU;
457
458 printf(": %s, address %s\n", intrstr,
459 ether_sprintf(sc->sc_arpcom.ac_enaddr));
460
461 if (sc->sc_flags & FXPF_DISABLE_STANDBY) {
462 fxp_read_eeprom(sc, &data, 10, 1);
463 if (data & 0x02) { /* STB enable */
464 u_int16_t cksum;
465 int i;
466
467 printf("%s: Disabling dynamic standby mode in EEPROM",
468 sc->sc_dev.dv_xname);
469 data &= ~0x02;
470 fxp_write_eeprom(sc, &data, 10, 1);
471 printf(", New ID 0x%x", data);
472 cksum = 0;
473 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) {
474 fxp_read_eeprom(sc, &data, i, 1);
475 cksum += data;
476 }
477 i = (1 << sc->eeprom_size) - 1;
478 cksum = 0xBABA - cksum;
479 fxp_read_eeprom(sc, &data, i, 1);
480 fxp_write_eeprom(sc, &cksum, i, 1);
481 printf(", cksum @ 0x%x: 0x%x -> 0x%x\n",
482 i, data, cksum);
483 }
484 }
485
486 /* Receiver lock-up workaround detection. */
487 fxp_read_eeprom(sc, &data, 3, 1);
488 if ((data & 0x03) != 0x03) {
489 sc->sc_flags |= FXPF_RECV_WORKAROUND;
490 }
491
492 /*
493 * Initialize our media structures and probe the MII.
494 */
495 sc->sc_mii.mii_ifp = ifp;
496 sc->sc_mii.mii_readreg = fxp_mdi_read;
497 sc->sc_mii.mii_writereg = fxp_mdi_write;
498 sc->sc_mii.mii_statchg = fxp_statchg;
499 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_mediachange,
500 fxp_mediastatus);
501 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
502 MII_OFFSET_ANY, MIIF_NOISOLATE);
503 /* If no phy found, just use auto mode */
504 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) {
505 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL,
506 0, NULL);
507 printf("%s: no phy found, using manual mode\n",
508 sc->sc_dev.dv_xname);
509 }
510
511 if (ifmedia_match(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0))
512 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL);
513 else if (ifmedia_match(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO, 0))
514 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
515 else
516 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_10_T);
517
518 /*
519 * Attach the interface.
520 */
521 if_attach(ifp);
522 ether_ifattach(ifp);
523
524 /*
525 * Add shutdown hook so that DMA is disabled prior to reboot. Not
526 * doing so could allow DMA to corrupt kernel memory during the
527 * reboot before the driver initializes.
528 */
529 sc->sc_sdhook = shutdownhook_establish(fxp_shutdown, sc);
530
531 /*
532 * Add suspend hook, for similiar reasons..
533 */
534 sc->sc_powerhook = powerhook_establish(fxp_power, sc);
535
536 /*
537 * Initialize timeout for statistics update.
538 */
539 timeout_set(&sc->stats_update_to, fxp_stats_update, sc);
540
541 return (0);
542
543 fail:
544 printf("%s: Failed to malloc memory\n", sc->sc_dev.dv_xname);
545 if (sc->tx_cb_map != NULL) {
546 bus_dmamap_unload(sc->sc_dmat, sc->tx_cb_map);
547 bus_dmamap_destroy(sc->sc_dmat, sc->tx_cb_map);
548 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_ctrl,
549 sizeof(struct fxp_cb_tx) * FXP_NTXCB);
550 bus_dmamem_free(sc->sc_dmat, &sc->sc_cb_seg, sc->sc_cb_nseg);
551 }
552 m = sc->rfa_headm;
553 while (m != NULL) {
554 rxmap = *((bus_dmamap_t *)m->m_ext.ext_buf);
555 bus_dmamap_unload(sc->sc_dmat, rxmap);
556 FXP_RXMAP_PUT(sc, rxmap);
557 m = m_free(m);
558 }
559 return (ENOMEM);
560 }
561
562 int
fxp_detach(sc)563 fxp_detach(sc)
564 struct fxp_softc *sc;
565 {
566 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
567
568 /* Unhook our tick handler. */
569 timeout_del(&sc->stats_update_to);
570
571 /* Detach any PHYs we might have. */
572 if (LIST_FIRST(&sc->sc_mii.mii_phys) != NULL)
573 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY);
574
575 /* Delete any remaining media. */
576 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY);
577
578 ether_ifdetach(ifp);
579 if_detach(ifp);
580
581 if (sc->sc_sdhook != NULL)
582 shutdownhook_disestablish(sc->sc_sdhook);
583 if (sc->sc_powerhook != NULL)
584 powerhook_disestablish(sc->sc_powerhook);
585
586 return (0);
587 }
588
589 /*
590 * From NetBSD:
591 *
592 * Figure out EEPROM size.
593 *
594 * 559's can have either 64-word or 256-word EEPROMs, the 558
595 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet
596 * talks about the existence of 16 to 256 word EEPROMs.
597 *
598 * The only known sizes are 64 and 256, where the 256 version is used
599 * by CardBus cards to store CIS information.
600 *
601 * The address is shifted in msb-to-lsb, and after the last
602 * address-bit the EEPROM is supposed to output a `dummy zero' bit,
603 * after which follows the actual data. We try to detect this zero, by
604 * probing the data-out bit in the EEPROM control register just after
605 * having shifted in a bit. If the bit is zero, we assume we've
606 * shifted enough address bits. The data-out should be tri-state,
607 * before this, which should translate to a logical one.
608 *
609 * Other ways to do this would be to try to read a register with known
610 * contents with a varying number of address bits, but no such
611 * register seem to be available. The high bits of register 10 are 01
612 * on the 558 and 559, but apparently not on the 557.
613 *
614 * The Linux driver computes a checksum on the EEPROM data, but the
615 * value of this checksum is not very well documented.
616 */
617 void
fxp_autosize_eeprom(sc)618 fxp_autosize_eeprom(sc)
619 struct fxp_softc *sc;
620 {
621 u_int16_t reg;
622 int x;
623
624 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
625 /*
626 * Shift in read opcode.
627 */
628 for (x = 3; x > 0; x--) {
629 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) {
630 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
631 } else {
632 reg = FXP_EEPROM_EECS;
633 }
634 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
635 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL,
636 reg | FXP_EEPROM_EESK);
637 DELAY(4);
638 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
639 DELAY(4);
640 }
641 /*
642 * Shift in address.
643 * Wait for the dummy zero following a correct address shift.
644 */
645 for (x = 1; x <= 8; x++) {
646 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
647 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL,
648 FXP_EEPROM_EECS | FXP_EEPROM_EESK);
649 DELAY(4);
650 if ((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) == 0)
651 break;
652 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
653 DELAY(4);
654 }
655 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
656 DELAY(4);
657 sc->eeprom_size = x;
658 }
659
660 /*
661 * Read from the serial EEPROM. Basically, you manually shift in
662 * the read opcode (one bit at a time) and then shift in the address,
663 * and then you shift out the data (all of this one bit at a time).
664 * The word size is 16 bits, so you have to provide the address for
665 * every 16 bits of data.
666 */
667 void
fxp_read_eeprom(sc,data,offset,words)668 fxp_read_eeprom(sc, data, offset, words)
669 struct fxp_softc *sc;
670 u_short *data;
671 int offset;
672 int words;
673 {
674 u_int16_t reg;
675 int i, x;
676
677 for (i = 0; i < words; i++) {
678 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
679 /*
680 * Shift in read opcode.
681 */
682 for (x = 3; x > 0; x--) {
683 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) {
684 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
685 } else {
686 reg = FXP_EEPROM_EECS;
687 }
688 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
689 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL,
690 reg | FXP_EEPROM_EESK);
691 DELAY(4);
692 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
693 DELAY(4);
694 }
695 /*
696 * Shift in address.
697 */
698 for (x = sc->eeprom_size; x > 0; x--) {
699 if ((i + offset) & (1 << (x - 1))) {
700 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
701 } else {
702 reg = FXP_EEPROM_EECS;
703 }
704 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
705 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL,
706 reg | FXP_EEPROM_EESK);
707 DELAY(4);
708 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
709 DELAY(4);
710 }
711 reg = FXP_EEPROM_EECS;
712 data[i] = 0;
713 /*
714 * Shift out data.
715 */
716 for (x = 16; x > 0; x--) {
717 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL,
718 reg | FXP_EEPROM_EESK);
719 DELAY(4);
720 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) &
721 FXP_EEPROM_EEDO)
722 data[i] |= (1 << (x - 1));
723 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
724 DELAY(4);
725 }
726 data[i] = letoh16(data[i]);
727 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
728 DELAY(4);
729 }
730 }
731
732 /*
733 * Start packet transmission on the interface.
734 */
735 void
fxp_start(ifp)736 fxp_start(ifp)
737 struct ifnet *ifp;
738 {
739 struct fxp_softc *sc = ifp->if_softc;
740 struct fxp_txsw *txs = sc->sc_cbt_prod;
741 struct fxp_cb_tx *txc;
742 struct mbuf *m0, *m = NULL;
743 int cnt = sc->sc_cbt_cnt, seg;
744
745 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING)
746 return;
747
748 while (1) {
749 if (cnt >= (FXP_NTXCB - 2)) {
750 ifp->if_flags |= IFF_OACTIVE;
751 break;
752 }
753
754 txs = txs->tx_next;
755
756 IFQ_POLL(&ifp->if_snd, m0);
757 if (m0 == NULL)
758 break;
759
760 if (bus_dmamap_load_mbuf(sc->sc_dmat, txs->tx_map,
761 m0, BUS_DMA_NOWAIT) != 0) {
762 MGETHDR(m, M_DONTWAIT, MT_DATA);
763 if (m == NULL)
764 break;
765 if (m0->m_pkthdr.len > MHLEN) {
766 MCLGET(m, M_DONTWAIT);
767 if (!(m->m_flags & M_EXT)) {
768 m_freem(m);
769 break;
770 }
771 }
772 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t));
773 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len;
774 if (bus_dmamap_load_mbuf(sc->sc_dmat, txs->tx_map,
775 m, BUS_DMA_NOWAIT) != 0) {
776 m_freem(m);
777 break;
778 }
779 }
780
781 IFQ_DEQUEUE(&ifp->if_snd, m0);
782 if (m != NULL) {
783 m_freem(m0);
784 m0 = m;
785 m = NULL;
786 }
787
788 txs->tx_mbuf = m0;
789
790 #if NBPFILTER > 0
791 if (ifp->if_bpf)
792 bpf_mtap(ifp->if_bpf, m0);
793 #endif
794
795 FXP_MBUF_SYNC(sc, txs->tx_map, BUS_DMASYNC_PREWRITE);
796
797 txc = txs->tx_cb;
798 txc->tbd_number = txs->tx_map->dm_nsegs;
799 txc->cb_status = 0;
800 txc->cb_command = htole16(FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF);
801 txc->tx_threshold = tx_threshold;
802 for (seg = 0; seg < txs->tx_map->dm_nsegs; seg++) {
803 txc->tbd[seg].tb_addr =
804 htole32(txs->tx_map->dm_segs[seg].ds_addr);
805 txc->tbd[seg].tb_size =
806 htole32(txs->tx_map->dm_segs[seg].ds_len);
807 }
808 FXP_TXCB_SYNC(sc, txs,
809 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
810
811 ++cnt;
812 sc->sc_cbt_prod = txs;
813 }
814
815 if (cnt != sc->sc_cbt_cnt) {
816 /* We enqueued at least one. */
817 ifp->if_timer = 5;
818
819 txs = sc->sc_cbt_prod;
820 txs = txs->tx_next;
821 sc->sc_cbt_prod = txs;
822 txs->tx_cb->cb_command =
823 htole16(FXP_CB_COMMAND_I | FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S);
824 FXP_TXCB_SYNC(sc, txs,
825 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
826
827 FXP_TXCB_SYNC(sc, sc->sc_cbt_prev,
828 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
829 sc->sc_cbt_prev->tx_cb->cb_command &=
830 htole16(~(FXP_CB_COMMAND_S | FXP_CB_COMMAND_I));
831 FXP_TXCB_SYNC(sc, sc->sc_cbt_prev,
832 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
833
834 sc->sc_cbt_prev = txs;
835
836 fxp_scb_wait(sc);
837 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
838
839 sc->sc_cbt_cnt = cnt + 1;
840 }
841 }
842
843 /*
844 * Process interface interrupts.
845 */
846 int
fxp_intr(arg)847 fxp_intr(arg)
848 void *arg;
849 {
850 struct fxp_softc *sc = arg;
851 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
852 u_int8_t statack;
853 bus_dmamap_t rxmap;
854 int claimed = 0;
855 int rnr = 0;
856
857 /*
858 * If the interface isn't running, don't try to
859 * service the interrupt.. just ack it and bail.
860 */
861 if ((ifp->if_flags & IFF_RUNNING) == 0) {
862 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK);
863 if (statack) {
864 claimed = 1;
865 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack);
866 }
867 return claimed;
868 }
869
870 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) {
871 claimed = 1;
872 rnr = (statack & (FXP_SCB_STATACK_RNR |
873 FXP_SCB_STATACK_SWI)) ? 1 : 0;
874 /*
875 * First ACK all the interrupts in this pass.
876 */
877 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack);
878
879 /*
880 * Free any finished transmit mbuf chains.
881 */
882 if (statack & (FXP_SCB_STATACK_CXTNO|FXP_SCB_STATACK_CNA)) {
883 int txcnt = sc->sc_cbt_cnt;
884 struct fxp_txsw *txs = sc->sc_cbt_cons;
885
886 FXP_TXCB_SYNC(sc, txs,
887 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
888
889 while ((txcnt > 0) &&
890 ((txs->tx_cb->cb_status & htole16(FXP_CB_STATUS_C)) ||
891 (txs->tx_cb->cb_command & htole16(FXP_CB_COMMAND_NOP)))) {
892 if (txs->tx_mbuf != NULL) {
893 FXP_MBUF_SYNC(sc, txs->tx_map,
894 BUS_DMASYNC_POSTWRITE);
895 bus_dmamap_unload(sc->sc_dmat,
896 txs->tx_map);
897 m_freem(txs->tx_mbuf);
898 txs->tx_mbuf = NULL;
899 }
900 --txcnt;
901 txs = txs->tx_next;
902 FXP_TXCB_SYNC(sc, txs,
903 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
904 }
905 sc->sc_cbt_cons = txs;
906 sc->sc_cbt_cnt = txcnt;
907 ifp->if_timer = 0;
908 ifp->if_flags &= ~IFF_OACTIVE;
909
910 if (!IFQ_IS_EMPTY(&ifp->if_snd)) {
911 /*
912 * Try to start more packets transmitting.
913 */
914 fxp_start(ifp);
915 }
916 }
917 /*
918 * Process receiver interrupts. If a Receive Unit
919 * not ready (RNR) condition exists, get whatever
920 * packets we can and re-start the receiver.
921 */
922 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR |
923 FXP_SCB_STATACK_SWI)) {
924 struct mbuf *m;
925 u_int8_t *rfap;
926 rcvloop:
927 m = sc->rfa_headm;
928 rfap = m->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE;
929 rxmap = *((bus_dmamap_t *)m->m_ext.ext_buf);
930 bus_dmamap_sync(sc->sc_dmat, rxmap,
931 0, MCLBYTES, BUS_DMASYNC_POSTREAD |
932 BUS_DMASYNC_POSTWRITE);
933
934 if (*(u_int16_t *)(rfap +
935 offsetof(struct fxp_rfa, rfa_status)) &
936 htole16(FXP_RFA_STATUS_C)) {
937 if (*(u_int16_t *)(rfap +
938 offsetof(struct fxp_rfa, rfa_status)) &
939 htole16(FXP_RFA_STATUS_RNR))
940 rnr = 1;
941
942 /*
943 * Remove first packet from the chain.
944 */
945 sc->rfa_headm = m->m_next;
946 m->m_next = NULL;
947
948 /*
949 * Add a new buffer to the receive chain.
950 * If this fails, the old buffer is recycled
951 * instead.
952 */
953 if (fxp_add_rfabuf(sc, m) == 0) {
954 u_int16_t total_len;
955
956 total_len = htole16(*(u_int16_t *)(rfap +
957 offsetof(struct fxp_rfa,
958 actual_size))) &
959 (MCLBYTES - 1);
960 if (total_len <
961 sizeof(struct ether_header)) {
962 m_freem(m);
963 goto rcvloop;
964 }
965 if (*(u_int16_t *)(rfap +
966 offsetof(struct fxp_rfa,
967 rfa_status)) &
968 htole16(FXP_RFA_STATUS_CRC)) {
969 m_freem(m);
970 goto rcvloop;
971 }
972
973 m->m_pkthdr.rcvif = ifp;
974 m->m_pkthdr.len = m->m_len =
975 total_len;
976 #if NBPFILTER > 0
977 if (ifp->if_bpf)
978 bpf_mtap(ifp->if_bpf, m);
979 #endif /* NBPFILTER > 0 */
980 ether_input_mbuf(ifp, m);
981 }
982 goto rcvloop;
983 }
984 }
985 if (rnr) {
986 rxmap = *((bus_dmamap_t *)
987 sc->rfa_headm->m_ext.ext_buf);
988 fxp_scb_wait(sc);
989 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
990 rxmap->dm_segs[0].ds_addr +
991 RFA_ALIGNMENT_FUDGE);
992 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
993
994 }
995 }
996 return (claimed);
997 }
998
999 /*
1000 * Update packet in/out/collision statistics. The i82557 doesn't
1001 * allow you to access these counters without doing a fairly
1002 * expensive DMA to get _all_ of the statistics it maintains, so
1003 * we do this operation here only once per second. The statistics
1004 * counters in the kernel are updated from the previous dump-stats
1005 * DMA and then a new dump-stats DMA is started. The on-chip
1006 * counters are zeroed when the DMA completes. If we can't start
1007 * the DMA immediately, we don't wait - we just prepare to read
1008 * them again next time.
1009 */
1010 void
fxp_stats_update(arg)1011 fxp_stats_update(arg)
1012 void *arg;
1013 {
1014 struct fxp_softc *sc = arg;
1015 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1016 struct fxp_stats *sp = &sc->sc_ctrl->stats;
1017 int s;
1018
1019 FXP_STATS_SYNC(sc, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1020 ifp->if_opackets += letoh32(sp->tx_good);
1021 ifp->if_collisions += letoh32(sp->tx_total_collisions);
1022 if (sp->rx_good) {
1023 ifp->if_ipackets += letoh32(sp->rx_good);
1024 sc->rx_idle_secs = 0;
1025 } else if (sc->sc_flags & FXPF_RECV_WORKAROUND) {
1026 sc->rx_idle_secs++;
1027 }
1028 ifp->if_ierrors +=
1029 letoh32(sp->rx_crc_errors) +
1030 letoh32(sp->rx_alignment_errors) +
1031 letoh32(sp->rx_rnr_errors) +
1032 letoh32(sp->rx_overrun_errors);
1033 /*
1034 * If any transmit underruns occurred, bump up the transmit
1035 * threshold by another 512 bytes (64 * 8).
1036 */
1037 if (sp->tx_underruns) {
1038 ifp->if_oerrors += letoh32(sp->tx_underruns);
1039 if (tx_threshold < 192)
1040 tx_threshold += 64;
1041 }
1042 s = splnet();
1043 /*
1044 * If we haven't received any packets in FXP_MAX_RX_IDLE seconds,
1045 * then assume the receiver has locked up and attempt to clear
1046 * the condition by reprogramming the multicast filter. This is
1047 * a work-around for a bug in the 82557 where the receiver locks
1048 * up if it gets certain types of garbage in the synchronization
1049 * bits prior to the packet header. This bug is supposed to only
1050 * occur in 10Mbps mode, but has been seen to occur in 100Mbps
1051 * mode as well (perhaps due to a 10/100 speed transition).
1052 */
1053 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) {
1054 sc->rx_idle_secs = 0;
1055 fxp_init(sc);
1056 splx(s);
1057 return;
1058 }
1059 /*
1060 * If there is no pending command, start another stats
1061 * dump. Otherwise punt for now.
1062 */
1063 FXP_STATS_SYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1064 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) {
1065 /*
1066 * Start another stats dump.
1067 */
1068 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET);
1069 } else {
1070 /*
1071 * A previous command is still waiting to be accepted.
1072 * Just zero our copy of the stats and wait for the
1073 * next timer event to update them.
1074 */
1075 sp->tx_good = 0;
1076 sp->tx_underruns = 0;
1077 sp->tx_total_collisions = 0;
1078
1079 sp->rx_good = 0;
1080 sp->rx_crc_errors = 0;
1081 sp->rx_alignment_errors = 0;
1082 sp->rx_rnr_errors = 0;
1083 sp->rx_overrun_errors = 0;
1084 }
1085
1086 /* Tick the MII clock. */
1087 mii_tick(&sc->sc_mii);
1088
1089 splx(s);
1090 /*
1091 * Schedule another timeout one second from now.
1092 */
1093 timeout_add(&sc->stats_update_to, hz);
1094 }
1095
1096 /*
1097 * Stop the interface. Cancels the statistics updater and resets
1098 * the interface.
1099 */
1100 void
fxp_stop(sc,drain)1101 fxp_stop(sc, drain)
1102 struct fxp_softc *sc;
1103 int drain;
1104 {
1105 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1106 int i;
1107
1108 /*
1109 * Turn down interface (done early to avoid bad interactions
1110 * between panics, shutdown hooks, and the watchdog timer)
1111 */
1112 ifp->if_timer = 0;
1113 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1114
1115 /*
1116 * Cancel stats updater.
1117 */
1118 timeout_del(&sc->stats_update_to);
1119 mii_down(&sc->sc_mii);
1120
1121 /*
1122 * Issue software reset.
1123 */
1124 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
1125 DELAY(10);
1126
1127 /*
1128 * Release any xmit buffers.
1129 */
1130 for (i = 0; i < FXP_NTXCB; i++) {
1131 if (sc->txs[i].tx_mbuf != NULL) {
1132 bus_dmamap_unload(sc->sc_dmat, sc->txs[i].tx_map);
1133 m_freem(sc->txs[i].tx_mbuf);
1134 sc->txs[i].tx_mbuf = NULL;
1135 }
1136 }
1137 sc->sc_cbt_cnt = 0;
1138
1139 if (drain) {
1140 bus_dmamap_t rxmap;
1141 struct mbuf *m;
1142
1143 /*
1144 * Free all the receive buffers then reallocate/reinitialize
1145 */
1146 m = sc->rfa_headm;
1147 while (m != NULL) {
1148 rxmap = *((bus_dmamap_t *)m->m_ext.ext_buf);
1149 bus_dmamap_unload(sc->sc_dmat, rxmap);
1150 FXP_RXMAP_PUT(sc, rxmap);
1151 m = m_free(m);
1152 sc->rx_bufs--;
1153 }
1154 sc->rfa_headm = NULL;
1155 sc->rfa_tailm = NULL;
1156 for (i = 0; i < FXP_NRFABUFS_MIN; i++) {
1157 if (fxp_add_rfabuf(sc, NULL) != 0) {
1158 /*
1159 * This "can't happen" - we're at splnet()
1160 * and we just freed all the buffers we need
1161 * above.
1162 */
1163 panic("fxp_stop: no buffers!");
1164 }
1165 sc->rx_bufs++;
1166 }
1167 }
1168 }
1169
1170 /*
1171 * Watchdog/transmission transmit timeout handler. Called when a
1172 * transmission is started on the interface, but no interrupt is
1173 * received before the timeout. This usually indicates that the
1174 * card has wedged for some reason.
1175 */
1176 void
fxp_watchdog(ifp)1177 fxp_watchdog(ifp)
1178 struct ifnet *ifp;
1179 {
1180 struct fxp_softc *sc = ifp->if_softc;
1181
1182 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname);
1183 ifp->if_oerrors++;
1184
1185 fxp_init(sc);
1186 }
1187
1188 /*
1189 * Submit a command to the i82557.
1190 */
1191 void
fxp_scb_cmd(sc,cmd)1192 fxp_scb_cmd(sc, cmd)
1193 struct fxp_softc *sc;
1194 u_int8_t cmd;
1195 {
1196 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd);
1197 }
1198
1199 void
fxp_init(xsc)1200 fxp_init(xsc)
1201 void *xsc;
1202 {
1203 struct fxp_softc *sc = xsc;
1204 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1205 struct fxp_cb_config *cbp;
1206 struct fxp_cb_ias *cb_ias;
1207 struct fxp_cb_tx *txp;
1208 bus_dmamap_t rxmap;
1209 int i, prm, save_bf, lrxen, allm, s, bufs;
1210
1211 s = splnet();
1212
1213 /*
1214 * Cancel any pending I/O
1215 */
1216 fxp_stop(sc, 0);
1217
1218 /*
1219 * Initialize base of CBL and RFA memory. Loading with zero
1220 * sets it up for regular linear addressing.
1221 */
1222 fxp_scb_wait(sc);
1223 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0);
1224 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE);
1225
1226 fxp_scb_wait(sc);
1227 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0);
1228 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE);
1229
1230 /* Once through to set flags */
1231 fxp_mc_setup(sc, 0);
1232
1233 /*
1234 * In order to support receiving 802.1Q VLAN frames, we have to
1235 * enable "save bad frames", since they are 4 bytes larger than
1236 * the normal Ethernet maximum frame length. On i82558 and later,
1237 * we have a better mechanism for this.
1238 */
1239 save_bf = 0;
1240 lrxen = 0;
1241
1242 if (sc->sc_revision >= FXP_REV_82558_A4)
1243 lrxen = 1;
1244 else
1245 save_bf = 1;
1246
1247 /*
1248 * Initialize base of dump-stats buffer.
1249 */
1250 fxp_scb_wait(sc);
1251 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1252 sc->tx_cb_map->dm_segs->ds_addr +
1253 offsetof(struct fxp_ctrl, stats));
1254 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR);
1255
1256 cbp = &sc->sc_ctrl->u.cfg;
1257 /*
1258 * This bcopy is kind of disgusting, but there are a bunch of must be
1259 * zero and must be one bits in this structure and this is the easiest
1260 * way to initialize them all to proper values.
1261 */
1262 bcopy(fxp_cb_config_template, (void *)&cbp->cb_status,
1263 sizeof(fxp_cb_config_template));
1264
1265 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0;
1266 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0;
1267
1268 #if 0
1269 cbp->cb_status = 0;
1270 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL;
1271 cbp->link_addr = 0xffffffff; /* (no) next command */
1272 cbp->byte_count = 22; /* (22) bytes to config */
1273 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */
1274 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */
1275 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */
1276 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */
1277 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */
1278 cbp->dma_bce = 0; /* (disable) dma max counters */
1279 cbp->late_scb = 0; /* (don't) defer SCB update */
1280 cbp->tno_int = 0; /* (disable) tx not okay interrupt */
1281 cbp->ci_int = 1; /* interrupt on CU idle */
1282 cbp->save_bf = save_bf ? 1 : prm; /* save bad frames */
1283 cbp->disc_short_rx = !prm; /* discard short packets */
1284 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */
1285 cbp->mediatype = !sc->phy_10Mbps_only; /* interface mode */
1286 cbp->nsai = 1; /* (don't) disable source addr insert */
1287 cbp->preamble_length = 2; /* (7 byte) preamble */
1288 cbp->loopback = 0; /* (don't) loopback */
1289 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */
1290 cbp->linear_pri_mode = 0; /* (wait after xmit only) */
1291 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */
1292 cbp->promiscuous = prm; /* promiscuous mode */
1293 cbp->bcast_disable = 0; /* (don't) disable broadcasts */
1294 cbp->crscdt = 0; /* (CRS only) */
1295 cbp->stripping = !prm; /* truncate rx packet to byte count */
1296 cbp->padding = 1; /* (do) pad short tx packets */
1297 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */
1298 cbp->long_rx = lrxen; /* (enable) long packets */
1299 cbp->force_fdx = 0; /* (don't) force full duplex */
1300 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */
1301 cbp->multi_ia = 0; /* (don't) accept multiple IAs */
1302 cbp->mc_all = allm;
1303 #else
1304 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL);
1305 if (allm)
1306 cbp->mc_all |= 0x08; /* accept all multicasts */
1307 else
1308 cbp->mc_all &= ~0x08; /* reject all multicasts */
1309
1310 if (prm) {
1311 cbp->promiscuous |= 1; /* promiscuous mode */
1312 cbp->ctrl2 &= ~0x01; /* save short packets */
1313 cbp->stripping &= ~0x01; /* don't truncate rx packets */
1314 } else {
1315 cbp->promiscuous &= ~1; /* no promiscuous mode */
1316 cbp->ctrl2 |= 0x01; /* discard short packets */
1317 cbp->stripping |= 0x01; /* truncate rx packets */
1318 }
1319
1320 if (prm || save_bf)
1321 cbp->ctrl1 |= 0x80; /* save bad frames */
1322 else
1323 cbp->ctrl1 &= ~0x80; /* discard bad frames */
1324
1325 if (sc->sc_flags & FXPF_MWI_ENABLE)
1326 cbp->ctrl0 |= 0x01; /* enable PCI MWI command */
1327
1328 if(!sc->phy_10Mbps_only) /* interface mode */
1329 cbp->mediatype |= 0x01;
1330 else
1331 cbp->mediatype &= ~0x01;
1332
1333 if(lrxen) /* long packets */
1334 cbp->stripping |= 0x08;
1335 else
1336 cbp->stripping &= ~0x08;
1337
1338 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max, dma_dce = 0 ??? */
1339 cbp->ctrl1 |= 0x08; /* ci_int = 1 */
1340 cbp->ctrl3 |= 0x08; /* nsai */
1341 cbp->fifo_limit = 0x08; /* tx and rx fifo limit */
1342 cbp->fdx_pin |= 0x80; /* Enable full duplex setting by pin */
1343 #endif
1344
1345 /*
1346 * Start the config command/DMA.
1347 */
1348 fxp_scb_wait(sc);
1349 FXP_CFG_SYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1350 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->tx_cb_map->dm_segs->ds_addr +
1351 offsetof(struct fxp_ctrl, u.cfg));
1352 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1353 /* ...and wait for it to complete. */
1354 do {
1355 DELAY(1);
1356 FXP_CFG_SYNC(sc, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1357 } while ((cbp->cb_status & htole16(FXP_CB_STATUS_C)) == 0);
1358
1359 /*
1360 * Now initialize the station address.
1361 */
1362 cb_ias = &sc->sc_ctrl->u.ias;
1363 cb_ias->cb_status = htole16(0);
1364 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL);
1365 cb_ias->link_addr = htole32(0xffffffff);
1366 bcopy(sc->sc_arpcom.ac_enaddr, (void *)cb_ias->macaddr,
1367 sizeof(sc->sc_arpcom.ac_enaddr));
1368
1369 /*
1370 * Start the IAS (Individual Address Setup) command/DMA.
1371 */
1372 fxp_scb_wait(sc);
1373 FXP_IAS_SYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1374 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->tx_cb_map->dm_segs->ds_addr +
1375 offsetof(struct fxp_ctrl, u.ias));
1376 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1377 /* ...and wait for it to complete. */
1378 do {
1379 DELAY(1);
1380 FXP_IAS_SYNC(sc, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1381 } while (!(cb_ias->cb_status & htole16(FXP_CB_STATUS_C)));
1382
1383 /* Again, this time really upload the multicast addresses */
1384 fxp_mc_setup(sc, 1);
1385
1386 /*
1387 * Initialize transmit control block (TxCB) list.
1388 */
1389 bzero(sc->sc_ctrl->tx_cb, sizeof(struct fxp_cb_tx) * FXP_NTXCB);
1390 txp = sc->sc_ctrl->tx_cb;
1391 for (i = 0; i < FXP_NTXCB; i++) {
1392 txp[i].cb_command = htole16(FXP_CB_COMMAND_NOP);
1393 txp[i].link_addr = htole32(sc->tx_cb_map->dm_segs->ds_addr +
1394 offsetof(struct fxp_ctrl, tx_cb[(i + 1) & FXP_TXCB_MASK]));
1395 txp[i].tbd_array_addr =htole32(sc->tx_cb_map->dm_segs->ds_addr +
1396 offsetof(struct fxp_ctrl, tx_cb[i].tbd[0]));
1397 }
1398 /*
1399 * Set the suspend flag on the first TxCB and start the control
1400 * unit. It will execute the NOP and then suspend.
1401 */
1402 sc->sc_cbt_prev = sc->sc_cbt_prod = sc->sc_cbt_cons = sc->txs;
1403 sc->sc_cbt_cnt = 1;
1404 sc->sc_ctrl->tx_cb[0].cb_command = htole16(FXP_CB_COMMAND_NOP |
1405 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I);
1406 bus_dmamap_sync(sc->sc_dmat, sc->tx_cb_map, 0,
1407 sc->tx_cb_map->dm_mapsize,
1408 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1409
1410 fxp_scb_wait(sc);
1411 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->tx_cb_map->dm_segs->ds_addr +
1412 offsetof(struct fxp_ctrl, tx_cb[0]));
1413 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1414
1415 /*
1416 * Initialize receiver buffer area - RFA.
1417 */
1418 if (ifp->if_flags & IFF_UP)
1419 bufs = FXP_NRFABUFS_MAX;
1420 else
1421 bufs = FXP_NRFABUFS_MIN;
1422 if (sc->rx_bufs > bufs) {
1423 while (sc->rfa_headm != NULL && sc->rx_bufs-- > bufs) {
1424 rxmap = *((bus_dmamap_t *)sc->rfa_headm->m_ext.ext_buf);
1425 bus_dmamap_unload(sc->sc_dmat, rxmap);
1426 FXP_RXMAP_PUT(sc, rxmap);
1427 sc->rfa_headm = m_free(sc->rfa_headm);
1428 }
1429 } else if (sc->rx_bufs < bufs) {
1430 int err, tmp_rx_bufs = sc->rx_bufs;
1431 for (i = sc->rx_bufs; i < bufs; i++) {
1432 if ((err = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1,
1433 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) {
1434 printf("%s: unable to create rx dma map %d, "
1435 "error %d\n", sc->sc_dev.dv_xname, i, err);
1436 break;
1437 }
1438 sc->rx_bufs++;
1439 }
1440 for (i = tmp_rx_bufs; i < sc->rx_bufs; i++)
1441 if (fxp_add_rfabuf(sc, NULL) != 0)
1442 break;
1443 }
1444 fxp_scb_wait(sc);
1445
1446 /*
1447 * Set current media.
1448 */
1449 mii_mediachg(&sc->sc_mii);
1450
1451 ifp->if_flags |= IFF_RUNNING;
1452 ifp->if_flags &= ~IFF_OACTIVE;
1453
1454 /*
1455 * Request a software generated interrupt that will be used to
1456 * (re)start the RU processing. If we direct the chip to start
1457 * receiving from the start of queue now, instead of letting the
1458 * interrupt handler first process all received packets, we run
1459 * the risk of having it overwrite mbuf clusters while they are
1460 * being processed or after they have been returned to the pool.
1461 */
1462 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTRCNTL_REQUEST_SWI);
1463 splx(s);
1464
1465 /*
1466 * Start stats updater.
1467 */
1468 timeout_add(&sc->stats_update_to, hz);
1469 }
1470
1471 /*
1472 * Change media according to request.
1473 */
1474 int
fxp_mediachange(ifp)1475 fxp_mediachange(ifp)
1476 struct ifnet *ifp;
1477 {
1478 struct fxp_softc *sc = ifp->if_softc;
1479
1480 mii_mediachg(&sc->sc_mii);
1481 return (0);
1482 }
1483
1484 /*
1485 * Notify the world which media we're using.
1486 */
1487 void
fxp_mediastatus(ifp,ifmr)1488 fxp_mediastatus(ifp, ifmr)
1489 struct ifnet *ifp;
1490 struct ifmediareq *ifmr;
1491 {
1492 struct fxp_softc *sc = ifp->if_softc;
1493
1494 mii_pollstat(&sc->sc_mii);
1495 ifmr->ifm_status = sc->sc_mii.mii_media_status;
1496 ifmr->ifm_active = sc->sc_mii.mii_media_active;
1497 }
1498
1499 /*
1500 * Add a buffer to the end of the RFA buffer list.
1501 * Return 0 if successful, 1 for failure. A failure results in
1502 * adding the 'oldm' (if non-NULL) on to the end of the list -
1503 * tossing out its old contents and recycling it.
1504 * The RFA struct is stuck at the beginning of mbuf cluster and the
1505 * data pointer is fixed up to point just past it.
1506 */
1507 int
fxp_add_rfabuf(sc,oldm)1508 fxp_add_rfabuf(sc, oldm)
1509 struct fxp_softc *sc;
1510 struct mbuf *oldm;
1511 {
1512 u_int32_t v;
1513 struct mbuf *m;
1514 u_int8_t *rfap;
1515 bus_dmamap_t rxmap = NULL;
1516
1517 MGETHDR(m, M_DONTWAIT, MT_DATA);
1518 if (m != NULL) {
1519 MCLGET(m, M_DONTWAIT);
1520 if ((m->m_flags & M_EXT) == 0) {
1521 m_freem(m);
1522 if (oldm == NULL)
1523 return 1;
1524 m = oldm;
1525 m->m_data = m->m_ext.ext_buf;
1526 }
1527 if (oldm == NULL) {
1528 rxmap = FXP_RXMAP_GET(sc);
1529 *((bus_dmamap_t *)m->m_ext.ext_buf) = rxmap;
1530 bus_dmamap_load(sc->sc_dmat, rxmap,
1531 m->m_ext.ext_buf, m->m_ext.ext_size, NULL,
1532 BUS_DMA_NOWAIT);
1533 } else if (oldm == m)
1534 rxmap = *((bus_dmamap_t *)oldm->m_ext.ext_buf);
1535 else {
1536 rxmap = *((bus_dmamap_t *)oldm->m_ext.ext_buf);
1537 bus_dmamap_unload(sc->sc_dmat, rxmap);
1538 bus_dmamap_load(sc->sc_dmat, rxmap,
1539 m->m_ext.ext_buf, m->m_ext.ext_size, NULL,
1540 BUS_DMA_NOWAIT);
1541 *mtod(m, bus_dmamap_t *) = rxmap;
1542 }
1543 } else {
1544 if (oldm == NULL)
1545 return 1;
1546 m = oldm;
1547 m->m_data = m->m_ext.ext_buf;
1548 rxmap = *mtod(m, bus_dmamap_t *);
1549 }
1550
1551 /*
1552 * Move the data pointer up so that the incoming data packet
1553 * will be 32-bit aligned.
1554 */
1555 m->m_data += RFA_ALIGNMENT_FUDGE;
1556
1557 /*
1558 * Get a pointer to the base of the mbuf cluster and move
1559 * data start past it.
1560 */
1561 rfap = m->m_data;
1562 m->m_data += sizeof(struct fxp_rfa);
1563 *(u_int16_t *)(rfap + offsetof(struct fxp_rfa, size)) =
1564 htole16(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE);
1565
1566 /*
1567 * Initialize the rest of the RFA. Note that since the RFA
1568 * is misaligned, we cannot store values directly. Instead,
1569 * we use an optimized, inline copy.
1570 */
1571 *(u_int16_t *)(rfap + offsetof(struct fxp_rfa, rfa_status)) = 0;
1572 *(u_int16_t *)(rfap + offsetof(struct fxp_rfa, rfa_control)) =
1573 htole16(FXP_RFA_CONTROL_EL);
1574 *(u_int16_t *)(rfap + offsetof(struct fxp_rfa, actual_size)) = 0;
1575
1576 v = -1;
1577 fxp_lwcopy(&v,
1578 (u_int32_t *)(rfap + offsetof(struct fxp_rfa, link_addr)));
1579 fxp_lwcopy(&v,
1580 (u_int32_t *)(rfap + offsetof(struct fxp_rfa, rbd_addr)));
1581
1582 bus_dmamap_sync(sc->sc_dmat, rxmap, 0, MCLBYTES,
1583 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1584
1585 /*
1586 * If there are other buffers already on the list, attach this
1587 * one to the end by fixing up the tail to point to this one.
1588 */
1589 if (sc->rfa_headm != NULL) {
1590 sc->rfa_tailm->m_next = m;
1591 v = htole32(rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE);
1592 rfap = sc->rfa_tailm->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE;
1593 fxp_lwcopy(&v,
1594 (u_int32_t *)(rfap + offsetof(struct fxp_rfa, link_addr)));
1595 *(u_int16_t *)(rfap + offsetof(struct fxp_rfa, rfa_control)) &=
1596 htole16((u_int16_t)~FXP_RFA_CONTROL_EL);
1597 /* XXX we only need to sync the control struct */
1598 bus_dmamap_sync(sc->sc_dmat,
1599 *((bus_dmamap_t *)sc->rfa_tailm->m_ext.ext_buf), 0,
1600 MCLBYTES, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1601 } else
1602 sc->rfa_headm = m;
1603
1604 sc->rfa_tailm = m;
1605
1606 return (m == oldm);
1607 }
1608
1609 int
fxp_mdi_read(self,phy,reg)1610 fxp_mdi_read(self, phy, reg)
1611 struct device *self;
1612 int phy;
1613 int reg;
1614 {
1615 struct fxp_softc *sc = (struct fxp_softc *)self;
1616 int count = 10000;
1617 int value;
1618
1619 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
1620 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21));
1621
1622 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0
1623 && count--)
1624 DELAY(10);
1625
1626 if (count <= 0)
1627 printf("%s: fxp_mdi_read: timed out\n", sc->sc_dev.dv_xname);
1628
1629 return (value & 0xffff);
1630 }
1631
1632 void
fxp_statchg(self)1633 fxp_statchg(self)
1634 struct device *self;
1635 {
1636 /* Nothing to do. */
1637 }
1638
1639 void
fxp_mdi_write(self,phy,reg,value)1640 fxp_mdi_write(self, phy, reg, value)
1641 struct device *self;
1642 int phy;
1643 int reg;
1644 int value;
1645 {
1646 struct fxp_softc *sc = (struct fxp_softc *)self;
1647 int count = 10000;
1648
1649 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
1650 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) |
1651 (value & 0xffff));
1652
1653 while((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 &&
1654 count--)
1655 DELAY(10);
1656
1657 if (count <= 0)
1658 printf("%s: fxp_mdi_write: timed out\n", sc->sc_dev.dv_xname);
1659 }
1660
1661 int
fxp_ioctl(ifp,command,data)1662 fxp_ioctl(ifp, command, data)
1663 struct ifnet *ifp;
1664 u_long command;
1665 caddr_t data;
1666 {
1667 struct fxp_softc *sc = ifp->if_softc;
1668 struct ifreq *ifr = (struct ifreq *)data;
1669 struct ifaddr *ifa = (struct ifaddr *)data;
1670 int s, error = 0;
1671
1672 s = splnet();
1673
1674 if ((error = ether_ioctl(ifp, &sc->sc_arpcom, command, data)) > 0) {
1675 splx(s);
1676 return (error);
1677 }
1678
1679 switch (command) {
1680 case SIOCSIFADDR:
1681 ifp->if_flags |= IFF_UP;
1682
1683 switch (ifa->ifa_addr->sa_family) {
1684 #ifdef INET
1685 case AF_INET:
1686 fxp_init(sc);
1687 arp_ifinit(&sc->sc_arpcom, ifa);
1688 break;
1689 #endif
1690 default:
1691 fxp_init(sc);
1692 break;
1693 }
1694 break;
1695
1696 case SIOCSIFMTU:
1697 if (ifr->ifr_mtu > ETHERMTU || ifr->ifr_mtu < ETHERMIN) {
1698 error = EINVAL;
1699 } else if (ifp->if_mtu != ifr->ifr_mtu) {
1700 ifp->if_mtu = ifr->ifr_mtu;
1701 }
1702 break;
1703
1704 case SIOCSIFFLAGS:
1705 /*
1706 * If interface is marked up and not running, then start it.
1707 * If it is marked down and running, stop it.
1708 * XXX If it's up then re-initialize it. This is so flags
1709 * such as IFF_PROMISC are handled.
1710 */
1711 if (ifp->if_flags & IFF_UP)
1712 fxp_init(sc);
1713 else if (ifp->if_flags & IFF_RUNNING)
1714 fxp_stop(sc, 1);
1715 break;
1716
1717 case SIOCADDMULTI:
1718 case SIOCDELMULTI:
1719 error = (command == SIOCADDMULTI) ?
1720 ether_addmulti(ifr, &sc->sc_arpcom) :
1721 ether_delmulti(ifr, &sc->sc_arpcom);
1722 if (error == ENETRESET) {
1723 /*
1724 * Multicast list has changed; set the hardware
1725 * filter accordingly.
1726 */
1727 if (ifp->if_flags & IFF_RUNNING)
1728 fxp_init(sc);
1729 error = 0;
1730 }
1731 break;
1732
1733 case SIOCSIFMEDIA:
1734 case SIOCGIFMEDIA:
1735 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command);
1736 break;
1737
1738 default:
1739 error = EINVAL;
1740 }
1741 splx(s);
1742 return (error);
1743 }
1744
1745 /*
1746 * Program the multicast filter.
1747 *
1748 * We have an artificial restriction that the multicast setup command
1749 * must be the first command in the chain, so we take steps to ensure
1750 * this. By requiring this, it allows us to keep up the performance of
1751 * the pre-initialized command ring (esp. link pointers) by not actually
1752 * inserting the mcsetup command in the ring - i.e. its link pointer
1753 * points to the TxCB ring, but the mcsetup descriptor itself is not part
1754 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it
1755 * lead into the regular TxCB ring when it completes.
1756 *
1757 * This function must be called at splnet.
1758 */
1759 void
fxp_mc_setup(sc,doit)1760 fxp_mc_setup(sc, doit)
1761 struct fxp_softc *sc;
1762 int doit;
1763 {
1764 struct fxp_cb_mcs *mcsp = &sc->sc_ctrl->u.mcs;
1765 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1766 struct ether_multistep step;
1767 struct ether_multi *enm;
1768 int nmcasts;
1769
1770 /*
1771 * Initialize multicast setup descriptor.
1772 */
1773 mcsp->cb_status = htole16(0);
1774 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL);
1775 mcsp->link_addr = htole32(-1);
1776
1777 nmcasts = 0;
1778 if (!(ifp->if_flags & IFF_ALLMULTI)) {
1779 ETHER_FIRST_MULTI(step, &sc->sc_arpcom, enm);
1780 while (enm != NULL) {
1781 if (nmcasts >= MAXMCADDR) {
1782 ifp->if_flags |= IFF_ALLMULTI;
1783 nmcasts = 0;
1784 break;
1785 }
1786
1787 /* Punt on ranges. */
1788 if (bcmp(enm->enm_addrlo, enm->enm_addrhi,
1789 sizeof(enm->enm_addrlo)) != 0) {
1790 ifp->if_flags |= IFF_ALLMULTI;
1791 nmcasts = 0;
1792 break;
1793 }
1794 bcopy(enm->enm_addrlo,
1795 (void *)&mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN);
1796 nmcasts++;
1797 ETHER_NEXT_MULTI(step, enm);
1798 }
1799 }
1800 if (doit == 0)
1801 return;
1802 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN);
1803
1804 /*
1805 * Wait until command unit is not active. This should never
1806 * be the case when nothing is queued, but make sure anyway.
1807 */
1808 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) != FXP_SCB_CUS_IDLE);
1809
1810 /*
1811 * Start the multicast setup command.
1812 */
1813 fxp_scb_wait(sc);
1814 FXP_MCS_SYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1815 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->tx_cb_map->dm_segs->ds_addr +
1816 offsetof(struct fxp_ctrl, u.mcs));
1817 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1818
1819 do {
1820 DELAY(1);
1821 FXP_MCS_SYNC(sc, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1822 } while (!(mcsp->cb_status & htole16(FXP_CB_STATUS_C)));
1823 }
1824