1 /* $OpenBSD: elink3.c,v 1.62 2004/05/12 06:35:10 tedu Exp $ */
2 /* $NetBSD: elink3.c,v 1.32 1997/05/14 00:22:00 thorpej Exp $ */
3
4 /*
5 * Copyright (c) 1996, 1997 Jonathan Stone <jonathan@NetBSD.org>
6 * Copyright (c) 1994 Herb Peyerl <hpeyerl@beer.org>
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by Herb Peyerl.
20 * 4. The name of Herb Peyerl may not be used to endorse or promote products
21 * derived from this software without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35 #include "bpfilter.h"
36
37 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/mbuf.h>
40 #include <sys/socket.h>
41 #include <sys/ioctl.h>
42 #include <sys/errno.h>
43 #include <sys/syslog.h>
44 #include <sys/select.h>
45 #include <sys/device.h>
46
47 #include <net/if.h>
48 #include <net/if_dl.h>
49 #include <net/if_types.h>
50 #include <net/netisr.h>
51 #include <net/if_media.h>
52
53 #ifdef INET
54 #include <netinet/in.h>
55 #include <netinet/in_systm.h>
56 #include <netinet/in_var.h>
57 #include <netinet/ip.h>
58 #include <netinet/if_ether.h>
59 #endif
60
61 #if NBPFILTER > 0
62 #include <net/bpf.h>
63 #endif
64
65 #include <machine/cpu.h>
66 #include <machine/bus.h>
67
68 #include <dev/mii/mii.h>
69 #include <dev/mii/miivar.h>
70
71 #include <dev/ic/elink3var.h>
72 #include <dev/ic/elink3reg.h>
73
74 /*
75 * Structure to map media-present bits in boards to
76 * ifmedia codes and printable media names. Used for table-driven
77 * ifmedia initialization.
78 */
79 struct ep_media {
80 int epm_eeprom_data; /* bitmask for eeprom config */
81 int epm_conn; /* sc->ep_connectors code for medium */
82 char *epm_name; /* name of medium */
83 int epm_ifmedia; /* ifmedia word for medium */
84 int epm_ifdata;
85 };
86
87 /*
88 * ep_media table for Vortex/Demon/Boomerang:
89 * map from media-present bits in register RESET_OPTIONS+2
90 * to ifmedia "media words" and printable names.
91 *
92 * XXX indexed directly by INTERNAL_CONFIG default_media field,
93 * (i.e., EPMEDIA_ constants) forcing order of entries.
94 * Note that 3 is reserved.
95 */
96 const struct ep_media ep_vortex_media[8] = {
97 { EP_PCI_UTP, EPC_UTP, "utp", IFM_ETHER|IFM_10_T,
98 EPMEDIA_10BASE_T },
99 { EP_PCI_AUI, EPC_AUI, "aui", IFM_ETHER|IFM_10_5,
100 EPMEDIA_AUI },
101 { 0, 0, "reserved", IFM_NONE, EPMEDIA_RESV1 },
102 { EP_PCI_BNC, EPC_BNC, "bnc", IFM_ETHER|IFM_10_2,
103 EPMEDIA_10BASE_2 },
104 { EP_PCI_100BASE_TX, EPC_100TX, "100-TX", IFM_ETHER|IFM_100_TX,
105 EPMEDIA_100BASE_TX },
106 { EP_PCI_100BASE_FX, EPC_100FX, "100-FX", IFM_ETHER|IFM_100_FX,
107 EPMEDIA_100BASE_FX },
108 { EP_PCI_100BASE_MII,EPC_MII, "mii", IFM_ETHER|IFM_100_TX,
109 EPMEDIA_MII },
110 { EP_PCI_100BASE_T4, EPC_100T4, "100-T4", IFM_ETHER|IFM_100_T4,
111 EPMEDIA_100BASE_T4 }
112 };
113
114 /*
115 * ep_media table for 3c509/3c509b/3c579/3c589:
116 * map from media-present bits in register CNFG_CNTRL
117 * (window 0, offset ?) to ifmedia "media words" and printable names.
118 */
119 struct ep_media ep_isa_media[3] = {
120 { EP_W0_CC_UTP, EPC_UTP, "utp", IFM_ETHER|IFM_10_T, EPMEDIA_10BASE_T },
121 { EP_W0_CC_AUI, EPC_AUI, "aui", IFM_ETHER|IFM_10_5, EPMEDIA_AUI },
122 { EP_W0_CC_BNC, EPC_BNC, "bnc", IFM_ETHER|IFM_10_2, EPMEDIA_10BASE_2 },
123 };
124
125 /* Map vortex reset_options bits to if_media codes. */
126 const u_int ep_default_to_media[8] = {
127 IFM_ETHER | IFM_10_T,
128 IFM_ETHER | IFM_10_5,
129 0, /* reserved by 3Com */
130 IFM_ETHER | IFM_10_2,
131 IFM_ETHER | IFM_100_TX,
132 IFM_ETHER | IFM_100_FX,
133 IFM_ETHER | IFM_100_TX, /* XXX really MII: need to talk to PHY */
134 IFM_ETHER | IFM_100_T4,
135 };
136
137 struct cfdriver ep_cd = {
138 NULL, "ep", DV_IFNET
139 };
140
141 void ep_vortex_probemedia(struct ep_softc *sc);
142 void ep_isa_probemedia(struct ep_softc *sc);
143
144 void eptxstat(struct ep_softc *);
145 int epstatus(struct ep_softc *);
146 int epioctl(struct ifnet *, u_long, caddr_t);
147 void epstart(struct ifnet *);
148 void epwatchdog(struct ifnet *);
149 void epreset(struct ep_softc *);
150 void epread(struct ep_softc *);
151 struct mbuf *epget(struct ep_softc *, int);
152 void epmbuffill(void *);
153 void epmbufempty(struct ep_softc *);
154 void epsetfilter(struct ep_softc *);
155 void ep_roadrunner_mii_enable(struct ep_softc *);
156 int epsetmedia(struct ep_softc *, int);
157
158 /* ifmedia callbacks */
159 int ep_media_change(struct ifnet *);
160 void ep_media_status(struct ifnet *, struct ifmediareq *);
161
162 /* MII callbacks */
163 int ep_mii_readreg(struct device *, int, int);
164 void ep_mii_writereg(struct device *, int, int, int);
165 void ep_statchg(struct device *);
166
167 void ep_mii_setbit(struct ep_softc *, u_int16_t);
168 void ep_mii_clrbit(struct ep_softc *, u_int16_t);
169 u_int16_t ep_mii_readbit(struct ep_softc *, u_int16_t);
170 void ep_mii_sync(struct ep_softc *);
171 void ep_mii_sendbits(struct ep_softc *, u_int32_t, int);
172
173 int epbusyeeprom(struct ep_softc *);
174 u_int16_t ep_read_eeprom(struct ep_softc *, u_int16_t);
175
176 static inline void ep_reset_cmd(struct ep_softc *sc, u_int cmd,u_int arg);
177 static inline void ep_finish_reset(bus_space_tag_t, bus_space_handle_t);
178 static inline void ep_discard_rxtop(bus_space_tag_t, bus_space_handle_t);
179 static __inline int ep_w1_reg(struct ep_softc *, int);
180
181 /*
182 * Issue a (reset) command, and be sure it has completed.
183 * Used for global reset, TX_RESET, RX_RESET.
184 */
185 static inline void
ep_reset_cmd(sc,cmd,arg)186 ep_reset_cmd(sc, cmd, arg)
187 struct ep_softc *sc;
188 u_int cmd, arg;
189 {
190 bus_space_tag_t iot = sc->sc_iot;
191 bus_space_handle_t ioh = sc->sc_ioh;
192
193 bus_space_write_2(iot, ioh, cmd, arg);
194 ep_finish_reset(iot, ioh);
195 }
196
197 /*
198 * Wait for any pending reset to complete.
199 */
200 static inline void
ep_finish_reset(iot,ioh)201 ep_finish_reset(iot, ioh)
202 bus_space_tag_t iot;
203 bus_space_handle_t ioh;
204 {
205 int i;
206
207 for (i = 0; i < 10000; i++) {
208 if ((bus_space_read_2(iot, ioh, EP_STATUS) &
209 S_COMMAND_IN_PROGRESS) == 0)
210 break;
211 DELAY(10);
212 }
213 }
214
215 static inline void
ep_discard_rxtop(iot,ioh)216 ep_discard_rxtop(iot, ioh)
217 bus_space_tag_t iot;
218 bus_space_handle_t ioh;
219 {
220 int i;
221
222 bus_space_write_2(iot, ioh, EP_COMMAND, RX_DISCARD_TOP_PACK);
223
224 /*
225 * Spin for about 1 msec, to avoid forcing a DELAY() between
226 * every received packet (adding latency and limiting pkt-recv rate).
227 * On PCI, at 4 30-nsec PCI bus cycles for a read, 8000 iterations
228 * is about right.
229 */
230 for (i = 0; i < 8000; i++) {
231 if ((bus_space_read_2(iot, ioh, EP_STATUS) &
232 S_COMMAND_IN_PROGRESS) == 0)
233 return;
234 }
235
236 /* not fast enough, do DELAY()s */
237 ep_finish_reset(iot, ioh);
238 }
239
240 /*
241 * Some chips (i.e., 3c574 RoadRunner) have Window 1 registers offset.
242 */
243 static __inline int
ep_w1_reg(sc,reg)244 ep_w1_reg(sc, reg)
245 struct ep_softc *sc;
246 int reg;
247 {
248 switch (sc->ep_chipset) {
249 case EP_CHIPSET_ROADRUNNER:
250 switch (reg) {
251 case EP_W1_FREE_TX:
252 case EP_W1_RUNNER_RDCTL:
253 case EP_W1_RUNNER_WRCTL:
254 return (reg);
255 }
256 return (reg + 0x10);
257 }
258 return (reg);
259 }
260
261 /*
262 * Back-end attach and configure.
263 */
264 void
epconfig(sc,chipset,enaddr)265 epconfig(sc, chipset, enaddr)
266 struct ep_softc *sc;
267 u_short chipset;
268 u_int8_t *enaddr;
269 {
270 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
271 bus_space_tag_t iot = sc->sc_iot;
272 bus_space_handle_t ioh = sc->sc_ioh;
273 u_int16_t i;
274
275 sc->ep_chipset = chipset;
276
277 /*
278 * We could have been groveling around in other register
279 * windows in the front-end; make sure we're in window 0
280 * to read the EEPROM.
281 */
282 GO_WINDOW(0);
283
284 if (enaddr == NULL) {
285 /*
286 * Read the station address from the eeprom.
287 */
288 for (i = 0; i < 3; i++) {
289 u_int16_t x = ep_read_eeprom(sc, i);
290
291 sc->sc_arpcom.ac_enaddr[(i << 1)] = x >> 8;
292 sc->sc_arpcom.ac_enaddr[(i << 1) + 1] = x;
293 }
294 } else {
295 bcopy(enaddr, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN);
296 }
297
298 printf(" address %s", ether_sprintf(sc->sc_arpcom.ac_enaddr));
299 if (sc->ep_flags & EP_FLAGS_MII)
300 printf("\n");
301 else
302 printf(", ");
303
304 /*
305 * Vortex-based (3c59x pci,eisa) cards allow FDDI-sized (4500) byte
306 * packets. Commands only take an 11-bit parameter, and 11 bits
307 * isn't enough to hold a full-size packet length.
308 * Commands to these cards implicitly upshift a packet size
309 * or threshold by 2 bits.
310 * To detect cards with large-packet support, we probe by setting
311 * the transmit threshold register, then change windows and
312 * read back the threshold register directly, and see if the
313 * threshold value was shifted or not.
314 */
315 bus_space_write_2(iot, ioh, EP_COMMAND,
316 SET_TX_AVAIL_THRESH | EP_LARGEWIN_PROBE );
317 GO_WINDOW(5);
318 i = bus_space_read_2(iot, ioh, EP_W5_TX_AVAIL_THRESH);
319 GO_WINDOW(1);
320 switch (i) {
321 case EP_LARGEWIN_PROBE:
322 case (EP_LARGEWIN_PROBE & EP_LARGEWIN_MASK):
323 sc->txashift = 0;
324 break;
325
326 case (EP_LARGEWIN_PROBE << 2):
327 sc->txashift = 2;
328 /* XXX does the 3c515 support Vortex-style RESET_OPTIONS? */
329 break;
330
331 default:
332 printf("wrote %x to TX_AVAIL_THRESH, read back %x. "
333 "Interface disabled\n", EP_THRESH_DISABLE, (int) i);
334 return;
335 }
336
337 timeout_set(&sc->sc_epmbuffill_tmo, epmbuffill, sc);
338
339 /*
340 * Ensure Tx-available interrupts are enabled for
341 * start the interface.
342 * XXX should be in epinit()?
343 */
344 bus_space_write_2(iot, ioh, EP_COMMAND,
345 SET_TX_AVAIL_THRESH | (1600 >> sc->txashift));
346
347 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ);
348 ifp->if_softc = sc;
349 ifp->if_start = epstart;
350 ifp->if_ioctl = epioctl;
351 ifp->if_watchdog = epwatchdog;
352 ifp->if_flags =
353 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST;
354 IFQ_SET_READY(&ifp->if_snd);
355
356 if_attach(ifp);
357 ether_ifattach(ifp);
358
359 /*
360 * Finish configuration:
361 * determine chipset if the front-end couldn't do so,
362 * show board details, set media.
363 */
364
365 GO_WINDOW(0);
366
367 ifmedia_init(&sc->sc_mii.mii_media, 0, ep_media_change,
368 ep_media_status);
369 sc->sc_mii.mii_ifp = ifp;
370 sc->sc_mii.mii_readreg = ep_mii_readreg;
371 sc->sc_mii.mii_writereg = ep_mii_writereg;
372 sc->sc_mii.mii_statchg = ep_statchg;
373
374 /*
375 * If we've got an indirect (ISA, PCMCIA?) board, the chipset
376 * is unknown. If the board has large-packet support, it's a
377 * Vortex/Boomerang, otherwise it's a 3c509.
378 * XXX use eeprom capability word instead?
379 */
380 if (sc->ep_chipset == EP_CHIPSET_UNKNOWN && sc->txashift) {
381 printf("warning: unknown chipset, possibly 3c515?\n");
382 #ifdef notyet
383 sc->sc_chipset = EP_CHIPSET_VORTEX;
384 #endif /* notyet */
385 }
386
387 /*
388 * Ascertain which media types are present and inform ifmedia.
389 */
390 switch (sc->ep_chipset) {
391 case EP_CHIPSET_ROADRUNNER:
392 if (sc->ep_flags & EP_FLAGS_MII) {
393 ep_roadrunner_mii_enable(sc);
394 GO_WINDOW(0);
395 }
396 /* FALLTHROUGH */
397
398 case EP_CHIPSET_BOOMERANG:
399 /*
400 * If the device has MII, probe it. We won't be using
401 * any `native' media in this case, only PHYs. If
402 * we don't, just treat the Boomerang like the Vortex.
403 */
404 if (sc->ep_flags & EP_FLAGS_MII) {
405 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff,
406 MII_PHY_ANY, MII_OFFSET_ANY, 0);
407 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) {
408 ifmedia_add(&sc->sc_mii.mii_media,
409 IFM_ETHER|IFM_NONE, 0, NULL);
410 ifmedia_set(&sc->sc_mii.mii_media,
411 IFM_ETHER|IFM_NONE);
412 } else {
413 ifmedia_set(&sc->sc_mii.mii_media,
414 IFM_ETHER|IFM_AUTO);
415 }
416 break;
417 }
418 /* FALLTHROUGH */
419
420 /* on a direct bus, the attach routine can tell, but check anyway. */
421 case EP_CHIPSET_VORTEX:
422 case EP_CHIPSET_BOOMERANG2:
423 ep_vortex_probemedia(sc);
424 break;
425
426 /* on ISA we can't yet tell 3c509 from 3c515. Assume the former. */
427 case EP_CHIPSET_3C509:
428 default:
429 ep_isa_probemedia(sc);
430 break;
431 }
432
433 GO_WINDOW(1); /* Window 1 is operating window */
434
435 sc->tx_start_thresh = 20; /* probably a good starting point. */
436
437 ep_reset_cmd(sc, EP_COMMAND, RX_RESET);
438 ep_reset_cmd(sc, EP_COMMAND, TX_RESET);
439 }
440
441 int
ep_detach(self)442 ep_detach(self)
443 struct device *self;
444 {
445 struct ep_softc *sc = (struct ep_softc *)self;
446 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
447
448 if (sc->ep_flags & EP_FLAGS_MII)
449 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY);
450
451 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY);
452
453 ether_ifdetach(ifp);
454 if_detach(ifp);
455
456 return (0);
457 }
458
459 /*
460 * Find supported media on 3c509-generation hardware that doesn't have
461 * a "reset_options" register in window 3.
462 * Use the config_cntrl register in window 0 instead.
463 * Used on original, 10Mbit ISA (3c509), 3c509B, and pre-Demon EISA cards
464 * that implement CONFIG_CTRL. We don't have a good way to set the
465 * default active medium; punt to ifconfig instead.
466 *
467 * XXX what about 3c515, pcmcia 10/100?
468 */
469 void
ep_isa_probemedia(sc)470 ep_isa_probemedia(sc)
471 struct ep_softc *sc;
472 {
473 bus_space_tag_t iot = sc->sc_iot;
474 bus_space_handle_t ioh = sc->sc_ioh;
475 struct ifmedia *ifm = &sc->sc_mii.mii_media;
476 int conn, i;
477 u_int16_t ep_w0_config, port;
478
479 conn = 0;
480 GO_WINDOW(0);
481 ep_w0_config = bus_space_read_2(iot, ioh, EP_W0_CONFIG_CTRL);
482 for (i = 0; i < 3; i++) {
483 struct ep_media * epm = ep_isa_media + i;
484
485 if ((ep_w0_config & epm->epm_eeprom_data) != 0) {
486 ifmedia_add(ifm, epm->epm_ifmedia, epm->epm_ifdata, 0);
487 if (conn)
488 printf("/");
489 printf("%s", epm->epm_name);
490 conn |= epm->epm_conn;
491 }
492 }
493 sc->ep_connectors = conn;
494
495 /* get default medium from EEPROM */
496 if (epbusyeeprom(sc))
497 return; /* XXX why is eeprom busy? */
498 bus_space_write_2(iot, ioh, EP_W0_EEPROM_COMMAND,
499 READ_EEPROM | EEPROM_ADDR_CFG);
500 if (epbusyeeprom(sc))
501 return; /* XXX why is eeprom busy? */
502 port = bus_space_read_2(iot, ioh, EP_W0_EEPROM_DATA);
503 port = port >> 14;
504
505 printf(" (default %s)\n", ep_vortex_media[port].epm_name);
506
507 /* tell ifconfig what currently-active media is. */
508 ifmedia_set(ifm, ep_default_to_media[port]);
509
510 /* XXX autoselect not yet implemented */
511 }
512
513
514 /*
515 * Find media present on large-packet-capable elink3 devices.
516 * Show onboard configuration of large-packet-capable elink3 devices
517 * (Demon, Vortex, Boomerang), which do not implement CONFIG_CTRL in window 0.
518 * Use media and card-version info in window 3 instead.
519 *
520 * XXX how much of this works with 3c515, pcmcia 10/100?
521 */
522 void
ep_vortex_probemedia(sc)523 ep_vortex_probemedia(sc)
524 struct ep_softc *sc;
525 {
526 bus_space_tag_t iot = sc->sc_iot;
527 bus_space_handle_t ioh = sc->sc_ioh;
528 struct ifmedia *ifm = &sc->sc_mii.mii_media;
529 u_int config1, conn;
530 int reset_options;
531 int default_media; /* 3-bit encoding of default (EEPROM) media */
532 int autoselect; /* boolean: should default to autoselect */
533 const char *medium_name;
534 register int i;
535
536 GO_WINDOW(3);
537 config1 = (u_int)bus_space_read_2(iot, ioh, EP_W3_INTERNAL_CONFIG + 2);
538 reset_options = (int)bus_space_read_1(iot, ioh, EP_W3_RESET_OPTIONS);
539 GO_WINDOW(0);
540
541 default_media = (config1 & CONFIG_MEDIAMASK) >> CONFIG_MEDIAMASK_SHIFT;
542 autoselect = (config1 & CONFIG_AUTOSELECT) >> CONFIG_AUTOSELECT_SHIFT;
543
544 /* set available media options */
545 conn = 0;
546 for (i = 0; i < 8; i++) {
547 const struct ep_media *epm = ep_vortex_media + i;
548
549 if ((reset_options & epm->epm_eeprom_data) != 0) {
550 if (conn)
551 printf("/");
552 printf("%s", epm->epm_name);
553 conn |= epm->epm_conn;
554 ifmedia_add(ifm, epm->epm_ifmedia, epm->epm_ifdata, 0);
555 }
556 }
557
558 sc->ep_connectors = conn;
559
560 /* Show eeprom's idea of default media. */
561 medium_name = (default_media > 8)
562 ? "(unknown/impossible media)"
563 : ep_vortex_media[default_media].epm_name;
564 printf(" default %s%s",
565 medium_name, (autoselect) ? "/autoselect" : "");
566 /* sc->sc_media = ep_vortex_media[default_media].epm_ifdata;*/
567
568 #ifdef notyet
569 /*
570 * Set default: either the active interface the card
571 * reads from the EEPROM, or if autoselect is true,
572 * whatever we find is actually connected.
573 *
574 * XXX autoselect not yet implemented.
575 */
576 #endif /* notyet */
577
578 /* tell ifconfig what currently-active media is. */
579 ifmedia_set(ifm, ep_default_to_media[default_media]);
580 }
581
582 /*
583 * Bring device up.
584 *
585 * The order in here seems important. Otherwise we may not receive
586 * interrupts. ?!
587 */
588 void
epinit(sc)589 epinit(sc)
590 register struct ep_softc *sc;
591 {
592 register struct ifnet *ifp = &sc->sc_arpcom.ac_if;
593 bus_space_tag_t iot = sc->sc_iot;
594 bus_space_handle_t ioh = sc->sc_ioh;
595 int i;
596
597 /* make sure any pending reset has completed before touching board */
598 ep_finish_reset(iot, ioh);
599
600 /* cancel any pending I/O */
601 epstop(sc);
602
603 if (sc->bustype != EP_BUS_PCI) {
604 GO_WINDOW(0);
605 bus_space_write_2(iot, ioh, EP_W0_CONFIG_CTRL, 0);
606 bus_space_write_2(iot, ioh, EP_W0_CONFIG_CTRL, ENABLE_DRQ_IRQ);
607 }
608
609 if (sc->bustype == EP_BUS_PCMCIA) {
610 bus_space_write_2(iot, ioh, EP_W0_RESOURCE_CFG, 0x3f00);
611 }
612
613 GO_WINDOW(2);
614 for (i = 0; i < 6; i++) /* Reload the ether_addr. */
615 bus_space_write_1(iot, ioh, EP_W2_ADDR_0 + i,
616 sc->sc_arpcom.ac_enaddr[i]);
617
618 if (sc->bustype == EP_BUS_PCI || sc->bustype == EP_BUS_EISA)
619 /*
620 * Reset the station-address receive filter.
621 * A bug workaround for busmastering (Vortex, Demon) cards.
622 */
623 for (i = 0; i < 6; i++)
624 bus_space_write_1(iot, ioh, EP_W2_RECVMASK_0 + i, 0);
625
626 ep_reset_cmd(sc, EP_COMMAND, RX_RESET);
627 ep_reset_cmd(sc, EP_COMMAND, TX_RESET);
628
629 GO_WINDOW(1); /* Window 1 is operating window */
630 for (i = 0; i < 31; i++)
631 bus_space_read_1(iot, ioh, ep_w1_reg(sc, EP_W1_TX_STATUS));
632
633 /* Set threshold for for Tx-space available interrupt. */
634 bus_space_write_2(iot, ioh, EP_COMMAND,
635 SET_TX_AVAIL_THRESH | (1600 >> sc->txashift));
636
637 if (sc->ep_chipset == EP_CHIPSET_ROADRUNNER) {
638 /* Enable options in the PCMCIA LAN COR register, via
639 * RoadRunner Window 1.
640 *
641 * XXX MAGIC CONSTANTS!
642 */
643 u_int16_t cor;
644
645 bus_space_write_2(iot, ioh, EP_W1_RUNNER_RDCTL, (1 << 11));
646
647 cor = bus_space_read_2(iot, ioh, 0) & ~0x30;
648 bus_space_write_2(iot, ioh, 0, cor);
649
650 bus_space_write_2(iot, ioh, EP_W1_RUNNER_WRCTL, 0);
651 bus_space_write_2(iot, ioh, EP_W1_RUNNER_RDCTL, 0);
652
653 if (sc->ep_flags & EP_FLAGS_MII) {
654 ep_roadrunner_mii_enable(sc);
655 GO_WINDOW(1);
656 }
657 }
658
659 /* Enable interrupts. */
660 bus_space_write_2(iot, ioh, EP_COMMAND, SET_RD_0_MASK |
661 S_CARD_FAILURE | S_RX_COMPLETE | S_TX_COMPLETE | S_TX_AVAIL);
662 bus_space_write_2(iot, ioh, EP_COMMAND, SET_INTR_MASK |
663 S_CARD_FAILURE | S_RX_COMPLETE | S_TX_COMPLETE | S_TX_AVAIL);
664
665 /*
666 * Attempt to get rid of any stray interrupts that occurred during
667 * configuration. On the i386 this isn't possible because one may
668 * already be queued. However, a single stray interrupt is
669 * unimportant.
670 */
671 bus_space_write_2(iot, ioh, EP_COMMAND, ACK_INTR | 0xff);
672
673 epsetfilter(sc);
674 epsetmedia(sc, sc->sc_mii.mii_media.ifm_cur->ifm_data);
675
676 bus_space_write_2(iot, ioh, EP_COMMAND, RX_ENABLE);
677 bus_space_write_2(iot, ioh, EP_COMMAND, TX_ENABLE);
678
679 epmbuffill(sc);
680
681 /* Interface is now `running', with no output active. */
682 ifp->if_flags |= IFF_RUNNING;
683 ifp->if_flags &= ~IFF_OACTIVE;
684
685 /* Attempt to start output, if any. */
686 epstart(ifp);
687 }
688
689 /*
690 * Set multicast receive filter.
691 * elink3 hardware has no selective multicast filter in hardware.
692 * Enable reception of all multicasts and filter in software.
693 */
694 void
epsetfilter(sc)695 epsetfilter(sc)
696 register struct ep_softc *sc;
697 {
698 register struct ifnet *ifp = &sc->sc_arpcom.ac_if;
699
700 GO_WINDOW(1); /* Window 1 is operating window */
701 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_COMMAND, SET_RX_FILTER |
702 FIL_INDIVIDUAL | FIL_BRDCST |
703 ((ifp->if_flags & IFF_MULTICAST) ? FIL_MULTICAST : 0 ) |
704 ((ifp->if_flags & IFF_PROMISC) ? FIL_PROMISC : 0 ));
705 }
706
707
708 int
ep_media_change(ifp)709 ep_media_change(ifp)
710 struct ifnet *ifp;
711 {
712 register struct ep_softc *sc = ifp->if_softc;
713
714 return epsetmedia(sc, sc->sc_mii.mii_media.ifm_cur->ifm_data);
715 }
716
717 /*
718 * Reset and enable the MII on the RoadRunner.
719 */
720 void
ep_roadrunner_mii_enable(sc)721 ep_roadrunner_mii_enable(sc)
722 struct ep_softc *sc;
723 {
724 bus_space_tag_t iot = sc->sc_iot;
725 bus_space_handle_t ioh = sc->sc_ioh;
726
727 GO_WINDOW(3);
728 bus_space_write_2(iot, ioh, EP_W3_RESET_OPTIONS,
729 EP_PCI_100BASE_MII|EP_RUNNER_ENABLE_MII);
730 delay(1000);
731 bus_space_write_2(iot, ioh, EP_W3_RESET_OPTIONS,
732 EP_PCI_100BASE_MII|EP_RUNNER_MII_RESET|EP_RUNNER_ENABLE_MII);
733 ep_reset_cmd(sc, EP_COMMAND, TX_RESET);
734 ep_reset_cmd(sc, EP_COMMAND, RX_RESET);
735 delay(1000);
736 bus_space_write_2(iot, ioh, EP_W3_RESET_OPTIONS,
737 EP_PCI_100BASE_MII|EP_RUNNER_ENABLE_MII);
738 }
739
740 /*
741 * Set active media to a specific given EPMEDIA_<> value.
742 * For vortex/demon/boomerang cards, update media field in w3_internal_config,
743 * and power on selected transceiver.
744 * For 3c509-generation cards (3c509/3c579/3c589/3c509B),
745 * update media field in w0_address_config, and power on selected xcvr.
746 */
747 int
epsetmedia(sc,medium)748 epsetmedia(sc, medium)
749 struct ep_softc *sc;
750 int medium;
751 {
752 bus_space_tag_t iot = sc->sc_iot;
753 bus_space_handle_t ioh = sc->sc_ioh;
754 int w4_media;
755 int config0, config1;
756
757 /*
758 * you can `ifconfig (link0|-link0) ep0' to get the following
759 * behaviour:
760 * -link0 disable AUI/UTP. enable BNC.
761 * link0 disable BNC. enable AUI.
762 * link1 if the card has a UTP connector, and link0 is
763 * set too, then you get the UTP port.
764 */
765
766 /*
767 * First, change the media-control bits in EP_W4_MEDIA_TYPE.
768 */
769
770 /* Turn everything off. First turn off linkbeat and UTP. */
771 GO_WINDOW(4);
772 w4_media = bus_space_read_2(iot, ioh, EP_W4_MEDIA_TYPE);
773 w4_media = w4_media & ~(ENABLE_UTP|SQE_ENABLE);
774 bus_space_write_2(iot, ioh, EP_W4_MEDIA_TYPE, w4_media);
775
776 /* Turn off coax */
777 bus_space_write_2(iot, ioh, EP_COMMAND, STOP_TRANSCEIVER);
778 delay(1000);
779
780 /* If the device has MII, select it, and then tell the
781 * PHY which media to use.
782 */
783 if (sc->ep_flags & EP_FLAGS_MII) {
784 int config0, config1;
785
786 GO_WINDOW(3);
787
788 if (sc->ep_chipset == EP_CHIPSET_ROADRUNNER) {
789 int resopt;
790
791 resopt = bus_space_read_2(iot, ioh,
792 EP_W3_RESET_OPTIONS);
793 bus_space_write_2(iot, ioh, EP_W3_RESET_OPTIONS,
794 resopt | EP_RUNNER_ENABLE_MII);
795 }
796
797 config0 = (u_int)bus_space_read_2(iot, ioh,
798 EP_W3_INTERNAL_CONFIG);
799 config1 = (u_int)bus_space_read_2(iot, ioh,
800 EP_W3_INTERNAL_CONFIG + 2);
801
802 config1 = config1 & ~CONFIG_MEDIAMASK;
803 config1 |= (EPMEDIA_MII << CONFIG_MEDIAMASK_SHIFT);
804
805 bus_space_write_2(iot, ioh, EP_W3_INTERNAL_CONFIG, config0);
806 bus_space_write_2(iot, ioh, EP_W3_INTERNAL_CONFIG + 2, config1);
807 GO_WINDOW(1); /* back to operating window */
808
809 mii_mediachg(&sc->sc_mii);
810 return (0);
811 }
812
813 /*
814 * Now turn on the selected media/transceiver.
815 */
816 GO_WINDOW(4);
817 switch (medium) {
818 case EPMEDIA_10BASE_T:
819 bus_space_write_2(iot, ioh, EP_W4_MEDIA_TYPE, (ENABLE_UTP |
820 (sc->bustype == EP_BUS_PCMCIA ? MEDIA_LED : 0)));
821 break;
822
823 case EPMEDIA_10BASE_2:
824 bus_space_write_2(iot, ioh, EP_COMMAND, START_TRANSCEIVER);
825 DELAY(1000); /* 50ms not enough? */
826 break;
827
828 /* XXX following only for new-generation cards */
829 case EPMEDIA_100BASE_TX:
830 case EPMEDIA_100BASE_FX:
831 case EPMEDIA_100BASE_T4: /* XXX check documentation */
832 bus_space_write_2(iot, ioh, EP_W4_MEDIA_TYPE,
833 w4_media | LINKBEAT_ENABLE);
834 DELAY(1000); /* not strictly necessary? */
835 break;
836
837 case EPMEDIA_AUI:
838 bus_space_write_2(iot, ioh, EP_W4_MEDIA_TYPE,
839 w4_media | SQE_ENABLE);
840 DELAY(1000); /* not strictly necessary? */
841 break;
842 case EPMEDIA_MII:
843 break;
844 default:
845 #if defined(EP_DEBUG)
846 printf("%s unknown media 0x%x\n", sc->sc_dev.dv_xname, medium);
847 #endif
848 break;
849
850 }
851
852 /*
853 * Tell the chip which PHY [sic] to use.
854 */
855 switch (sc->ep_chipset) {
856 case EP_CHIPSET_VORTEX:
857 case EP_CHIPSET_BOOMERANG2:
858 GO_WINDOW(3);
859 config0 = (u_int)bus_space_read_2(iot, ioh,
860 EP_W3_INTERNAL_CONFIG);
861 config1 = (u_int)bus_space_read_2(iot, ioh,
862 EP_W3_INTERNAL_CONFIG + 2);
863
864 #if defined(EP_DEBUG)
865 printf("%s: read 0x%x, 0x%x from EP_W3_CONFIG register\n",
866 sc->sc_dev.dv_xname, config0, config1);
867 #endif
868 config1 = config1 & ~CONFIG_MEDIAMASK;
869 config1 |= (medium << CONFIG_MEDIAMASK_SHIFT);
870
871 #if defined(EP_DEBUG)
872 printf("epsetmedia: %s: medium 0x%x, 0x%x to EP_W3_CONFIG\n",
873 sc->sc_dev.dv_xname, medium, config1);
874 #endif
875 bus_space_write_2(iot, ioh, EP_W3_INTERNAL_CONFIG, config0);
876 bus_space_write_2(iot, ioh, EP_W3_INTERNAL_CONFIG + 2, config1);
877 break;
878
879 default:
880 GO_WINDOW(0);
881 config0 = bus_space_read_2(iot, ioh, EP_W0_ADDRESS_CFG);
882 config0 &= 0x3fff;
883 bus_space_write_2(iot, ioh, EP_W0_ADDRESS_CFG,
884 config0 | (medium << 14));
885 DELAY(1000);
886 break;
887 }
888
889 GO_WINDOW(1); /* Window 1 is operating window */
890 return (0);
891 }
892
893
894 /*
895 * Get currently-selected media from card.
896 * (if_media callback, may be called before interface is brought up).
897 */
898 void
ep_media_status(ifp,req)899 ep_media_status(ifp, req)
900 struct ifnet *ifp;
901 struct ifmediareq *req;
902 {
903 register struct ep_softc *sc = ifp->if_softc;
904 bus_space_tag_t iot = sc->sc_iot;
905 bus_space_handle_t ioh = sc->sc_ioh;
906 u_int config1;
907 u_int ep_mediastatus;
908
909 /*
910 * If we have MII, go ask the PHY what's going on.
911 */
912 if (sc->ep_flags & EP_FLAGS_MII) {
913 mii_pollstat(&sc->sc_mii);
914 req->ifm_active = sc->sc_mii.mii_media_active;
915 req->ifm_status = sc->sc_mii.mii_media_status;
916 return;
917 }
918
919 /* XXX read from softc when we start autosensing media */
920 req->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media;
921
922 switch (sc->ep_chipset) {
923 case EP_CHIPSET_VORTEX:
924 case EP_CHIPSET_BOOMERANG:
925 GO_WINDOW(3);
926 delay(5000);
927
928 config1 = bus_space_read_2(iot, ioh, EP_W3_INTERNAL_CONFIG + 2);
929 GO_WINDOW(1);
930
931 config1 =
932 (config1 & CONFIG_MEDIAMASK) >> CONFIG_MEDIAMASK_SHIFT;
933 req->ifm_active = ep_default_to_media[config1];
934
935 /* XXX check full-duplex bits? */
936
937 GO_WINDOW(4);
938 req->ifm_status = IFM_AVALID; /* XXX */
939 ep_mediastatus = bus_space_read_2(iot, ioh, EP_W4_MEDIA_TYPE);
940 if (ep_mediastatus & LINKBEAT_DETECT)
941 req->ifm_status |= IFM_ACTIVE; /* XXX automedia */
942
943 break;
944
945 case EP_CHIPSET_UNKNOWN:
946 case EP_CHIPSET_3C509:
947 req->ifm_status = 0; /* XXX */
948 break;
949
950 default:
951 printf("%s: media_status on unknown chipset 0x%x\n",
952 ifp->if_xname, sc->ep_chipset);
953 break;
954 }
955
956 /* XXX look for softc heartbeat for other chips or media */
957
958 GO_WINDOW(1);
959 return;
960 }
961
962
963
964 /*
965 * Start outputting on the interface.
966 * Always called as splnet().
967 */
968 void
epstart(ifp)969 epstart(ifp)
970 struct ifnet *ifp;
971 {
972 register struct ep_softc *sc = ifp->if_softc;
973 bus_space_tag_t iot = sc->sc_iot;
974 bus_space_handle_t ioh = sc->sc_ioh;
975 struct mbuf *m, *m0;
976 int sh, len, pad;
977 bus_addr_t txreg;
978
979 /* Don't transmit if interface is busy or not running */
980 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
981 return;
982
983 startagain:
984 /* Sneak a peek at the next packet */
985 IFQ_POLL(&ifp->if_snd, m0);
986 if (m0 == 0)
987 return;
988
989 /* We need to use m->m_pkthdr.len, so require the header */
990 if ((m0->m_flags & M_PKTHDR) == 0)
991 panic("epstart: no header mbuf");
992 len = m0->m_pkthdr.len;
993
994 pad = (4 - len) & 3;
995
996 /*
997 * The 3c509 automatically pads short packets to minimum ethernet
998 * length, but we drop packets that are too large. Perhaps we should
999 * truncate them instead?
1000 */
1001 if (len + pad > ETHER_MAX_LEN) {
1002 /* packet is obviously too large: toss it */
1003 ++ifp->if_oerrors;
1004 IFQ_DEQUEUE(&ifp->if_snd, m0);
1005 m_freem(m0);
1006 goto readcheck;
1007 }
1008
1009 if (bus_space_read_2(iot, ioh, ep_w1_reg(sc, EP_W1_FREE_TX)) <
1010 len + pad + 4) {
1011 bus_space_write_2(iot, ioh, EP_COMMAND,
1012 SET_TX_AVAIL_THRESH | ((len + pad + 4) >> sc->txashift));
1013 /* not enough room in FIFO */
1014 ifp->if_flags |= IFF_OACTIVE;
1015 return;
1016 } else {
1017 bus_space_write_2(iot, ioh, EP_COMMAND,
1018 SET_TX_AVAIL_THRESH | EP_THRESH_DISABLE);
1019 }
1020 IFQ_DEQUEUE(&ifp->if_snd, m0);
1021 if (m0 == 0) /* not really needed */
1022 return;
1023
1024 bus_space_write_2(iot, ioh, EP_COMMAND, SET_TX_START_THRESH |
1025 ((len / 4 + sc->tx_start_thresh) /*>> sc->txashift*/));
1026
1027 #if NBPFILTER > 0
1028 if (ifp->if_bpf)
1029 bpf_mtap(ifp->if_bpf, m0);
1030 #endif
1031
1032 /*
1033 * Do the output at splhigh() so that an interrupt from another device
1034 * won't cause a FIFO underrun.
1035 */
1036 sh = splhigh();
1037
1038 txreg = ep_w1_reg(sc, EP_W1_TX_PIO_WR_1);
1039
1040 bus_space_write_2(iot, ioh, txreg, len);
1041 bus_space_write_2(iot, ioh, txreg, 0xffff); /* Second is meaningless */
1042 if (EP_IS_BUS_32(sc->bustype)) {
1043 for (m = m0; m; ) {
1044 if (m->m_len > 3)
1045 bus_space_write_raw_multi_4(iot, ioh, txreg,
1046 mtod(m, u_int8_t *), m->m_len & ~3);
1047 if (m->m_len & 3)
1048 bus_space_write_multi_1(iot, ioh, txreg,
1049 mtod(m, u_int8_t *) + (m->m_len & ~3),
1050 m->m_len & 3);
1051 MFREE(m, m0);
1052 m = m0;
1053 }
1054 } else {
1055 for (m = m0; m; ) {
1056 if (m->m_len > 1)
1057 bus_space_write_raw_multi_2(iot, ioh, txreg,
1058 mtod(m, u_int8_t *), m->m_len & ~1);
1059 if (m->m_len & 1)
1060 bus_space_write_1(iot, ioh, txreg,
1061 *(mtod(m, u_int8_t *) + m->m_len - 1));
1062 MFREE(m, m0);
1063 m = m0;
1064 }
1065 }
1066 while (pad--)
1067 bus_space_write_1(iot, ioh, txreg, 0);
1068
1069 splx(sh);
1070
1071 ++ifp->if_opackets;
1072
1073 readcheck:
1074 if ((bus_space_read_2(iot, ioh, ep_w1_reg(sc, EP_W1_RX_STATUS)) &
1075 ERR_INCOMPLETE) == 0) {
1076 /* We received a complete packet. */
1077 u_int16_t status = bus_space_read_2(iot, ioh, EP_STATUS);
1078
1079 if ((status & S_INTR_LATCH) == 0) {
1080 /*
1081 * No interrupt, read the packet and continue
1082 * Is this supposed to happen? Is my motherboard
1083 * completely busted?
1084 */
1085 epread(sc);
1086 } else
1087 /* Got an interrupt, return to get it serviced. */
1088 return;
1089 } else {
1090 /* Check if we are stuck and reset [see XXX comment] */
1091 if (epstatus(sc)) {
1092 #ifdef EP_DEBUG
1093 if (ifp->if_flags & IFF_DEBUG)
1094 printf("%s: adapter reset\n",
1095 sc->sc_dev.dv_xname);
1096 #endif
1097 epreset(sc);
1098 }
1099 }
1100
1101 goto startagain;
1102 }
1103
1104
1105 /*
1106 * XXX: The 3c509 card can get in a mode where both the fifo status bit
1107 * FIFOS_RX_OVERRUN and the status bit ERR_INCOMPLETE are set
1108 * We detect this situation and we reset the adapter.
1109 * It happens at times when there is a lot of broadcast traffic
1110 * on the cable (once in a blue moon).
1111 */
1112 int
epstatus(sc)1113 epstatus(sc)
1114 register struct ep_softc *sc;
1115 {
1116 bus_space_tag_t iot = sc->sc_iot;
1117 bus_space_handle_t ioh = sc->sc_ioh;
1118 u_int16_t fifost;
1119
1120 /*
1121 * Check the FIFO status and act accordingly
1122 */
1123 GO_WINDOW(4);
1124 fifost = bus_space_read_2(iot, ioh, EP_W4_FIFO_DIAG);
1125 GO_WINDOW(1);
1126
1127 if (fifost & FIFOS_RX_UNDERRUN) {
1128 #ifdef EP_DEBUG
1129 if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG)
1130 printf("%s: RX underrun\n", sc->sc_dev.dv_xname);
1131 #endif
1132 epreset(sc);
1133 return 0;
1134 }
1135
1136 if (fifost & FIFOS_RX_STATUS_OVERRUN) {
1137 #ifdef EP_DEBUG
1138 if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG)
1139 printf("%s: RX Status overrun\n", sc->sc_dev.dv_xname);
1140 #endif
1141 return 1;
1142 }
1143
1144 if (fifost & FIFOS_RX_OVERRUN) {
1145 #ifdef EP_DEBUG
1146 if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG)
1147 printf("%s: RX overrun\n", sc->sc_dev.dv_xname);
1148 #endif
1149 return 1;
1150 }
1151
1152 if (fifost & FIFOS_TX_OVERRUN) {
1153 #ifdef EP_DEBUG
1154 if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG)
1155 printf("%s: TX overrun\n", sc->sc_dev.dv_xname);
1156 #endif
1157 epreset(sc);
1158 return 0;
1159 }
1160
1161 return 0;
1162 }
1163
1164
1165 void
eptxstat(sc)1166 eptxstat(sc)
1167 register struct ep_softc *sc;
1168 {
1169 bus_space_tag_t iot = sc->sc_iot;
1170 bus_space_handle_t ioh = sc->sc_ioh;
1171 int i;
1172
1173 /*
1174 * We need to read+write TX_STATUS until we get a 0 status
1175 * in order to turn off the interrupt flag.
1176 */
1177 while ((i = bus_space_read_1(iot, ioh,
1178 ep_w1_reg(sc, EP_W1_TX_STATUS))) & TXS_COMPLETE) {
1179 bus_space_write_1(iot, ioh, ep_w1_reg(sc, EP_W1_TX_STATUS),
1180 0x0);
1181
1182 if (i & TXS_JABBER) {
1183 ++sc->sc_arpcom.ac_if.if_oerrors;
1184 #ifdef EP_DEBUG
1185 if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG)
1186 printf("%s: jabber (%x)\n",
1187 sc->sc_dev.dv_xname, i);
1188 #endif
1189 epreset(sc);
1190 } else if (i & TXS_UNDERRUN) {
1191 ++sc->sc_arpcom.ac_if.if_oerrors;
1192 #ifdef EP_DEBUG
1193 if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG)
1194 printf("%s: fifo underrun (%x) @%d\n",
1195 sc->sc_dev.dv_xname, i,
1196 sc->tx_start_thresh);
1197 #endif
1198 if (sc->tx_succ_ok < 100)
1199 sc->tx_start_thresh = min(ETHER_MAX_LEN,
1200 sc->tx_start_thresh + 20);
1201 sc->tx_succ_ok = 0;
1202 epreset(sc);
1203 } else if (i & TXS_MAX_COLLISION) {
1204 ++sc->sc_arpcom.ac_if.if_collisions;
1205 bus_space_write_2(iot, ioh, EP_COMMAND, TX_ENABLE);
1206 sc->sc_arpcom.ac_if.if_flags &= ~IFF_OACTIVE;
1207 } else
1208 sc->tx_succ_ok = (sc->tx_succ_ok+1) & 127;
1209 }
1210 }
1211
1212 int
epintr(arg)1213 epintr(arg)
1214 void *arg;
1215 {
1216 register struct ep_softc *sc = arg;
1217 bus_space_tag_t iot = sc->sc_iot;
1218 bus_space_handle_t ioh = sc->sc_ioh;
1219 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1220 u_int16_t status;
1221 int ret = 0;
1222
1223 for (;;) {
1224 bus_space_write_2(iot, ioh, EP_COMMAND, C_INTR_LATCH);
1225
1226 status = bus_space_read_2(iot, ioh, EP_STATUS);
1227
1228 if ((status & (S_TX_COMPLETE | S_TX_AVAIL |
1229 S_RX_COMPLETE | S_CARD_FAILURE)) == 0)
1230 break;
1231
1232 ret = 1;
1233
1234 /*
1235 * Acknowledge any interrupts. It's important that we do this
1236 * first, since there would otherwise be a race condition.
1237 * Due to the i386 interrupt queueing, we may get spurious
1238 * interrupts occasionally.
1239 */
1240 bus_space_write_2(iot, ioh, EP_COMMAND, ACK_INTR | status);
1241
1242 if (status & S_RX_COMPLETE)
1243 epread(sc);
1244 if (status & S_TX_AVAIL) {
1245 ifp->if_flags &= ~IFF_OACTIVE;
1246 epstart(ifp);
1247 }
1248 if (status & S_CARD_FAILURE) {
1249 epreset(sc);
1250 return (1);
1251 }
1252 if (status & S_TX_COMPLETE) {
1253 eptxstat(sc);
1254 epstart(ifp);
1255 }
1256 }
1257
1258 /* no more interrupts */
1259 return (ret);
1260 }
1261
1262 void
epread(sc)1263 epread(sc)
1264 register struct ep_softc *sc;
1265 {
1266 bus_space_tag_t iot = sc->sc_iot;
1267 bus_space_handle_t ioh = sc->sc_ioh;
1268 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1269 struct mbuf *m;
1270 int len;
1271
1272 len = bus_space_read_2(iot, ioh, ep_w1_reg(sc, EP_W1_RX_STATUS));
1273
1274 again:
1275 #ifdef EP_DEBUG
1276 if (ifp->if_flags & IFF_DEBUG) {
1277 int err = len & ERR_MASK;
1278 char *s = NULL;
1279
1280 if (len & ERR_INCOMPLETE)
1281 s = "incomplete packet";
1282 else if (err == ERR_OVERRUN)
1283 s = "packet overrun";
1284 else if (err == ERR_RUNT)
1285 s = "runt packet";
1286 else if (err == ERR_ALIGNMENT)
1287 s = "bad alignment";
1288 else if (err == ERR_CRC)
1289 s = "bad crc";
1290 else if (err == ERR_OVERSIZE)
1291 s = "oversized packet";
1292 else if (err == ERR_DRIBBLE)
1293 s = "dribble bits";
1294
1295 if (s)
1296 printf("%s: %s\n", sc->sc_dev.dv_xname, s);
1297 }
1298 #endif
1299
1300 if (len & ERR_INCOMPLETE)
1301 return;
1302
1303 if (len & ERR_RX) {
1304 ++ifp->if_ierrors;
1305 goto abort;
1306 }
1307
1308 len &= RX_BYTES_MASK; /* Lower 11 bits = RX bytes. */
1309
1310 /* Pull packet off interface. */
1311 m = epget(sc, len);
1312 if (m == 0) {
1313 ifp->if_ierrors++;
1314 goto abort;
1315 }
1316
1317 ++ifp->if_ipackets;
1318
1319 #if NBPFILTER > 0
1320 /*
1321 * Check if there's a BPF listener on this interface.
1322 * If so, hand off the raw packet to BPF.
1323 */
1324 if (ifp->if_bpf)
1325 bpf_mtap(ifp->if_bpf, m);
1326 #endif
1327
1328 ether_input_mbuf(ifp, m);
1329
1330 /*
1331 * In periods of high traffic we can actually receive enough
1332 * packets so that the fifo overrun bit will be set at this point,
1333 * even though we just read a packet. In this case we
1334 * are not going to receive any more interrupts. We check for
1335 * this condition and read again until the fifo is not full.
1336 * We could simplify this test by not using epstatus(), but
1337 * rechecking the RX_STATUS register directly. This test could
1338 * result in unnecessary looping in cases where there is a new
1339 * packet but the fifo is not full, but it will not fix the
1340 * stuck behavior.
1341 *
1342 * Even with this improvement, we still get packet overrun errors
1343 * which are hurting performance. Maybe when I get some more time
1344 * I'll modify epread() so that it can handle RX_EARLY interrupts.
1345 */
1346 if (epstatus(sc)) {
1347 len = bus_space_read_2(iot, ioh,
1348 ep_w1_reg(sc, EP_W1_RX_STATUS));
1349 /* Check if we are stuck and reset [see XXX comment] */
1350 if (len & ERR_INCOMPLETE) {
1351 #ifdef EP_DEBUG
1352 if (ifp->if_flags & IFF_DEBUG)
1353 printf("%s: adapter reset\n",
1354 sc->sc_dev.dv_xname);
1355 #endif
1356 epreset(sc);
1357 return;
1358 }
1359 goto again;
1360 }
1361
1362 return;
1363
1364 abort:
1365 ep_discard_rxtop(iot, ioh);
1366 }
1367
1368 struct mbuf *
epget(sc,totlen)1369 epget(sc, totlen)
1370 struct ep_softc *sc;
1371 int totlen;
1372 {
1373 bus_space_tag_t iot = sc->sc_iot;
1374 bus_space_handle_t ioh = sc->sc_ioh;
1375 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1376 struct mbuf *top, **mp, *m;
1377 int len, pad;
1378 int sh;
1379 bus_addr_t rxreg;
1380
1381 m = sc->mb[sc->next_mb];
1382 sc->mb[sc->next_mb] = 0;
1383 if (m == 0) {
1384 MGETHDR(m, M_DONTWAIT, MT_DATA);
1385 if (m == 0)
1386 return 0;
1387 } else {
1388 /* If the queue is no longer full, refill. */
1389 if (sc->last_mb == sc->next_mb)
1390 timeout_add(&sc->sc_epmbuffill_tmo, 1);
1391 /* Convert one of our saved mbuf's. */
1392 sc->next_mb = (sc->next_mb + 1) % MAX_MBS;
1393 m->m_data = m->m_pktdat;
1394 m->m_flags = M_PKTHDR;
1395 m_tag_init(m);
1396 m->m_pkthdr.csum = 0;
1397 }
1398 m->m_pkthdr.rcvif = ifp;
1399 m->m_pkthdr.len = totlen;
1400 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header);
1401 len = MHLEN;
1402 if (totlen >= MINCLSIZE) {
1403 MCLGET(m, M_DONTWAIT);
1404 if (m->m_flags & M_EXT)
1405 len = MCLBYTES;
1406 }
1407 m->m_data += pad;
1408 len -= pad;
1409 top = 0;
1410 mp = ⊤
1411
1412 /*
1413 * We read the packet at splhigh() so that an interrupt from another
1414 * device doesn't cause the card's buffer to overflow while we're
1415 * reading it. We may still lose packets at other times.
1416 */
1417 sh = splhigh();
1418
1419 rxreg = ep_w1_reg(sc, EP_W1_RX_PIO_RD_1);
1420
1421 while (totlen > 0) {
1422 if (top) {
1423 m = sc->mb[sc->next_mb];
1424 sc->mb[sc->next_mb] = 0;
1425 if (m == 0) {
1426 MGET(m, M_DONTWAIT, MT_DATA);
1427 if (m == 0) {
1428 splx(sh);
1429 m_freem(top);
1430 return 0;
1431 }
1432 } else {
1433 sc->next_mb = (sc->next_mb + 1) % MAX_MBS;
1434 }
1435 len = MLEN;
1436 }
1437 if (top && totlen >= MINCLSIZE) {
1438 MCLGET(m, M_DONTWAIT);
1439 if (m->m_flags & M_EXT)
1440 len = MCLBYTES;
1441 }
1442 len = min(totlen, len);
1443 if (EP_IS_BUS_32(sc->bustype)) {
1444 if (len > 3) {
1445 len &= ~3;
1446 bus_space_read_raw_multi_4(iot, ioh, rxreg,
1447 mtod(m, u_int8_t *), len);
1448 } else
1449 bus_space_read_multi_1(iot, ioh, rxreg,
1450 mtod(m, u_int8_t *), len);
1451 } else {
1452 if (len > 1) {
1453 len &= ~1;
1454 bus_space_read_raw_multi_2(iot, ioh, rxreg,
1455 mtod(m, u_int8_t *), len);
1456 } else
1457 *(mtod(m, u_int8_t *)) =
1458 bus_space_read_1(iot, ioh, rxreg);
1459 }
1460 m->m_len = len;
1461 totlen -= len;
1462 *mp = m;
1463 mp = &m->m_next;
1464 }
1465
1466 ep_discard_rxtop(iot, ioh);
1467
1468 splx(sh);
1469
1470 return top;
1471 }
1472
1473 int
epioctl(ifp,cmd,data)1474 epioctl(ifp, cmd, data)
1475 register struct ifnet *ifp;
1476 u_long cmd;
1477 caddr_t data;
1478 {
1479 struct ep_softc *sc = ifp->if_softc;
1480 struct ifaddr *ifa = (struct ifaddr *)data;
1481 struct ifreq *ifr = (struct ifreq *)data;
1482 int s, error = 0;
1483
1484 s = splnet();
1485
1486 if ((error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data)) > 0) {
1487 splx(s);
1488 return error;
1489 }
1490
1491 switch (cmd) {
1492
1493 case SIOCSIFADDR:
1494 ifp->if_flags |= IFF_UP;
1495
1496 switch (ifa->ifa_addr->sa_family) {
1497 #ifdef INET
1498 case AF_INET:
1499 epinit(sc);
1500 arp_ifinit(&sc->sc_arpcom, ifa);
1501 break;
1502 #endif
1503 default:
1504 epinit(sc);
1505 break;
1506 }
1507 break;
1508
1509 case SIOCSIFMEDIA:
1510 case SIOCGIFMEDIA:
1511 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd);
1512 break;
1513
1514 case SIOCSIFMTU:
1515 if (ifr->ifr_mtu > ETHERMTU || ifr->ifr_mtu < ETHERMIN) {
1516 error = EINVAL;
1517 } else if (ifp->if_mtu != ifr->ifr_mtu) {
1518 ifp->if_mtu = ifr->ifr_mtu;
1519 }
1520 break;
1521
1522 case SIOCSIFFLAGS:
1523 if ((ifp->if_flags & IFF_UP) == 0 &&
1524 (ifp->if_flags & IFF_RUNNING) != 0) {
1525 /*
1526 * If interface is marked down and it is running, then
1527 * stop it.
1528 */
1529 epstop(sc);
1530 ifp->if_flags &= ~IFF_RUNNING;
1531 } else if ((ifp->if_flags & IFF_UP) != 0 &&
1532 (ifp->if_flags & IFF_RUNNING) == 0) {
1533 /*
1534 * If interface is marked up and it is stopped, then
1535 * start it.
1536 */
1537 epinit(sc);
1538 } else if ((ifp->if_flags & IFF_UP) != 0) {
1539 /*
1540 * Reset the interface to pick up changes in any other
1541 * flags that affect hardware registers.
1542 */
1543 epinit(sc);
1544 }
1545 break;
1546
1547 case SIOCADDMULTI:
1548 case SIOCDELMULTI:
1549 error = (cmd == SIOCADDMULTI) ?
1550 ether_addmulti(ifr, &sc->sc_arpcom) :
1551 ether_delmulti(ifr, &sc->sc_arpcom);
1552
1553 if (error == ENETRESET) {
1554 /*
1555 * Multicast list has changed; set the hardware filter
1556 * accordingly.
1557 */
1558 epreset(sc);
1559 error = 0;
1560 }
1561 break;
1562
1563 default:
1564 error = EINVAL;
1565 break;
1566 }
1567
1568 splx(s);
1569 return (error);
1570 }
1571
1572 void
epreset(sc)1573 epreset(sc)
1574 struct ep_softc *sc;
1575 {
1576 int s;
1577
1578 s = splnet();
1579 epinit(sc);
1580 splx(s);
1581 }
1582
1583 void
epwatchdog(ifp)1584 epwatchdog(ifp)
1585 struct ifnet *ifp;
1586 {
1587 struct ep_softc *sc = ifp->if_softc;
1588
1589 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname);
1590 ++sc->sc_arpcom.ac_if.if_oerrors;
1591
1592 epreset(sc);
1593 }
1594
1595 void
epstop(sc)1596 epstop(sc)
1597 register struct ep_softc *sc;
1598 {
1599 bus_space_tag_t iot = sc->sc_iot;
1600 bus_space_handle_t ioh = sc->sc_ioh;
1601
1602 if (sc->ep_flags & EP_FLAGS_MII) {
1603 mii_down(&sc->sc_mii);
1604 }
1605
1606 if (sc->ep_chipset == EP_CHIPSET_ROADRUNNER) {
1607 /* Clear the FIFO buffer count, thus halting
1608 * any currently-running transactions.
1609 */
1610 GO_WINDOW(1); /* sanity */
1611 bus_space_write_2(iot, ioh, EP_W1_RUNNER_WRCTL, 0);
1612 bus_space_write_2(iot, ioh, EP_W1_RUNNER_RDCTL, 0);
1613 }
1614
1615 bus_space_write_2(iot, ioh, EP_COMMAND, RX_DISABLE);
1616 ep_discard_rxtop(iot, ioh);
1617
1618 bus_space_write_2(iot, ioh, EP_COMMAND, TX_DISABLE);
1619 bus_space_write_2(iot, ioh, EP_COMMAND, STOP_TRANSCEIVER);
1620
1621 ep_reset_cmd(sc, EP_COMMAND, RX_RESET);
1622 ep_reset_cmd(sc, EP_COMMAND, TX_RESET);
1623
1624 bus_space_write_2(iot, ioh, EP_COMMAND, C_INTR_LATCH);
1625 bus_space_write_2(iot, ioh, EP_COMMAND, SET_RD_0_MASK);
1626 bus_space_write_2(iot, ioh, EP_COMMAND, SET_INTR_MASK);
1627 bus_space_write_2(iot, ioh, EP_COMMAND, SET_RX_FILTER);
1628
1629 epmbufempty(sc);
1630 }
1631
1632 /*
1633 * We get eeprom data from the id_port given an offset into the
1634 * eeprom. Basically; after the ID_sequence is sent to all of
1635 * the cards; they enter the ID_CMD state where they will accept
1636 * command requests. 0x80-0xbf loads the eeprom data. We then
1637 * read the port 16 times and with every read; the cards check
1638 * for contention (ie: if one card writes a 0 bit and another
1639 * writes a 1 bit then the host sees a 0. At the end of the cycle;
1640 * each card compares the data on the bus; if there is a difference
1641 * then that card goes into ID_WAIT state again). In the meantime;
1642 * one bit of data is returned in the AX register which is conveniently
1643 * returned to us by bus_space_read_1(). Hence; we read 16 times getting one
1644 * bit of data with each read.
1645 *
1646 * NOTE: the caller must provide an i/o handle for ELINK_ID_PORT!
1647 */
1648 u_int16_t
epreadeeprom(iot,ioh,offset)1649 epreadeeprom(iot, ioh, offset)
1650 bus_space_tag_t iot;
1651 bus_space_handle_t ioh;
1652 int offset;
1653 {
1654 u_int16_t data = 0;
1655 int i;
1656
1657 bus_space_write_1(iot, ioh, 0, 0x80 + offset);
1658 delay(1000);
1659 for (i = 0; i < 16; i++)
1660 data = (data << 1) | (bus_space_read_2(iot, ioh, 0) & 1);
1661 return (data);
1662 }
1663
1664 int
epbusyeeprom(sc)1665 epbusyeeprom(sc)
1666 struct ep_softc *sc;
1667 {
1668 bus_space_tag_t iot = sc->sc_iot;
1669 bus_space_handle_t ioh = sc->sc_ioh;
1670 int i = 100, j;
1671
1672 while (i--) {
1673 j = bus_space_read_2(iot, ioh, EP_W0_EEPROM_COMMAND);
1674 if (j & EEPROM_BUSY)
1675 delay(100);
1676 else
1677 break;
1678 }
1679 if (!i) {
1680 printf("\n%s: eeprom failed to come ready\n",
1681 sc->sc_dev.dv_xname);
1682 return (1);
1683 }
1684 if (sc->bustype != EP_BUS_PCMCIA && sc->bustype != EP_BUS_PCI &&
1685 (j & EEPROM_TST_MODE)) {
1686 printf("\n%s: erase pencil mark, or disable PnP mode!\n",
1687 sc->sc_dev.dv_xname);
1688 return (1);
1689 }
1690 return (0);
1691 }
1692
1693 u_int16_t
ep_read_eeprom(sc,offset)1694 ep_read_eeprom(sc, offset)
1695 struct ep_softc *sc;
1696 u_int16_t offset;
1697 {
1698 u_int16_t readcmd;
1699
1700 /*
1701 * RoadRunner has a larger EEPROM, so a different read command
1702 * is required.
1703 */
1704 if (sc->ep_chipset == EP_CHIPSET_ROADRUNNER)
1705 readcmd = READ_EEPROM_RR;
1706 else
1707 readcmd = READ_EEPROM;
1708
1709 if (epbusyeeprom(sc))
1710 return (0); /* XXX why is eeprom busy? */
1711 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_W0_EEPROM_COMMAND,
1712 readcmd | offset);
1713 if (epbusyeeprom(sc))
1714 return (0); /* XXX why is eeprom busy? */
1715
1716 return (bus_space_read_2(sc->sc_iot, sc->sc_ioh, EP_W0_EEPROM_DATA));
1717 }
1718
1719 void
epmbuffill(v)1720 epmbuffill(v)
1721 void *v;
1722 {
1723 struct ep_softc *sc = v;
1724 int s, i;
1725
1726 s = splnet();
1727 i = sc->last_mb;
1728 do {
1729 if (sc->mb[i] == NULL)
1730 MGET(sc->mb[i], M_DONTWAIT, MT_DATA);
1731 if (sc->mb[i] == NULL)
1732 break;
1733 i = (i + 1) % MAX_MBS;
1734 } while (i != sc->next_mb);
1735 sc->last_mb = i;
1736 /* If the queue was not filled, try again. */
1737 if (sc->last_mb != sc->next_mb)
1738 timeout_add(&sc->sc_epmbuffill_tmo, 1);
1739 splx(s);
1740 }
1741
1742 void
epmbufempty(sc)1743 epmbufempty(sc)
1744 struct ep_softc *sc;
1745 {
1746 int s, i;
1747
1748 s = splnet();
1749 for (i = 0; i<MAX_MBS; i++) {
1750 if (sc->mb[i]) {
1751 m_freem(sc->mb[i]);
1752 sc->mb[i] = NULL;
1753 }
1754 }
1755 sc->last_mb = sc->next_mb = 0;
1756 timeout_del(&sc->sc_epmbuffill_tmo);
1757 splx(s);
1758 }
1759
1760 void
ep_mii_setbit(sc,bit)1761 ep_mii_setbit(sc, bit)
1762 struct ep_softc *sc;
1763 u_int16_t bit;
1764 {
1765 u_int16_t val;
1766
1767 /* We assume we're already in Window 4 */
1768 val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT);
1769 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT,
1770 val | bit);
1771 }
1772
1773 void
ep_mii_clrbit(sc,bit)1774 ep_mii_clrbit(sc, bit)
1775 struct ep_softc *sc;
1776 u_int16_t bit;
1777 {
1778 u_int16_t val;
1779
1780 /* We assume we're already in Window 4 */
1781 val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT);
1782 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT,
1783 val & ~bit);
1784 }
1785
1786 u_int16_t
ep_mii_readbit(sc,bit)1787 ep_mii_readbit(sc, bit)
1788 struct ep_softc *sc;
1789 u_int16_t bit;
1790 {
1791
1792 /* We assume we're already in Window 4 */
1793 return (bus_space_read_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT) &
1794 bit);
1795 }
1796
1797 void
ep_mii_sync(sc)1798 ep_mii_sync(sc)
1799 struct ep_softc *sc;
1800 {
1801 int i;
1802
1803 /* We assume we're already in Window 4 */
1804 ep_mii_clrbit(sc, PHYSMGMT_DIR);
1805 for (i = 0; i < 32; i++) {
1806 ep_mii_clrbit(sc, PHYSMGMT_CLK);
1807 ep_mii_setbit(sc, PHYSMGMT_CLK);
1808 }
1809 }
1810
1811 void
ep_mii_sendbits(sc,data,nbits)1812 ep_mii_sendbits(sc, data, nbits)
1813 struct ep_softc *sc;
1814 u_int32_t data;
1815 int nbits;
1816 {
1817 int i;
1818
1819 /* We assume we're already in Window 4 */
1820 ep_mii_setbit(sc, PHYSMGMT_DIR);
1821 for (i = 1 << (nbits - 1); i; i = i >> 1) {
1822 ep_mii_clrbit(sc, PHYSMGMT_CLK);
1823 ep_mii_readbit(sc, PHYSMGMT_CLK);
1824 if (data & i)
1825 ep_mii_setbit(sc, PHYSMGMT_DATA);
1826 else
1827 ep_mii_clrbit(sc, PHYSMGMT_DATA);
1828 ep_mii_setbit(sc, PHYSMGMT_CLK);
1829 ep_mii_readbit(sc, PHYSMGMT_CLK);
1830 }
1831 }
1832
1833 int
ep_mii_readreg(self,phy,reg)1834 ep_mii_readreg(self, phy, reg)
1835 struct device *self;
1836 int phy, reg;
1837 {
1838 struct ep_softc *sc = (struct ep_softc *)self;
1839 int val = 0, i, err;
1840
1841 /*
1842 * Read the PHY register by manually driving the MII control lines.
1843 */
1844
1845 GO_WINDOW(4);
1846
1847 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT, 0);
1848
1849 ep_mii_sync(sc);
1850 ep_mii_sendbits(sc, MII_COMMAND_START, 2);
1851 ep_mii_sendbits(sc, MII_COMMAND_READ, 2);
1852 ep_mii_sendbits(sc, phy, 5);
1853 ep_mii_sendbits(sc, reg, 5);
1854
1855 ep_mii_clrbit(sc, PHYSMGMT_DIR);
1856 ep_mii_clrbit(sc, PHYSMGMT_CLK);
1857 ep_mii_setbit(sc, PHYSMGMT_CLK);
1858 ep_mii_clrbit(sc, PHYSMGMT_CLK);
1859
1860 err = ep_mii_readbit(sc, PHYSMGMT_DATA);
1861 ep_mii_setbit(sc, PHYSMGMT_CLK);
1862
1863 /* Even if an error occurs, must still clock out the cycle. */
1864 for (i = 0; i < 16; i++) {
1865 val <<= 1;
1866 ep_mii_clrbit(sc, PHYSMGMT_CLK);
1867 if (err == 0 && ep_mii_readbit(sc, PHYSMGMT_DATA))
1868 val |= 1;
1869 ep_mii_setbit(sc, PHYSMGMT_CLK);
1870 }
1871 ep_mii_clrbit(sc, PHYSMGMT_CLK);
1872 ep_mii_setbit(sc, PHYSMGMT_CLK);
1873
1874 GO_WINDOW(1); /* back to operating window */
1875
1876 return (err ? 0 : val);
1877 }
1878
1879 void
ep_mii_writereg(self,phy,reg,val)1880 ep_mii_writereg(self, phy, reg, val)
1881 struct device *self;
1882 int phy, reg, val;
1883 {
1884 struct ep_softc *sc = (struct ep_softc *)self;
1885
1886 /*
1887 * Write the PHY register by manually driving the MII control lines.
1888 */
1889
1890 GO_WINDOW(4);
1891
1892 ep_mii_sync(sc);
1893 ep_mii_sendbits(sc, MII_COMMAND_START, 2);
1894 ep_mii_sendbits(sc, MII_COMMAND_WRITE, 2);
1895 ep_mii_sendbits(sc, phy, 5);
1896 ep_mii_sendbits(sc, reg, 5);
1897 ep_mii_sendbits(sc, MII_COMMAND_ACK, 2);
1898 ep_mii_sendbits(sc, val, 16);
1899
1900 ep_mii_clrbit(sc, PHYSMGMT_CLK);
1901 ep_mii_setbit(sc, PHYSMGMT_CLK);
1902
1903 GO_WINDOW(1); /* back to operating window */
1904 }
1905
1906 void
ep_statchg(self)1907 ep_statchg(self)
1908 struct device *self;
1909 {
1910 struct ep_softc *sc = (struct ep_softc *)self;
1911 bus_space_tag_t iot = sc->sc_iot;
1912 bus_space_handle_t ioh = sc->sc_ioh;
1913 int mctl;
1914
1915 /* XXX Update ifp->if_baudrate */
1916
1917 GO_WINDOW(3);
1918 mctl = bus_space_read_2(iot, ioh, EP_W3_MAC_CONTROL);
1919 if (sc->sc_mii.mii_media_active & IFM_FDX)
1920 mctl |= MAC_CONTROL_FDX;
1921 else
1922 mctl &= ~MAC_CONTROL_FDX;
1923 bus_space_write_2(iot, ioh, EP_W3_MAC_CONTROL, mctl);
1924 GO_WINDOW(1); /* back to operating window */
1925 }
1926