1 /* $OpenBSD: dc21040reg.h,v 1.12 2003/10/21 18:58:49 jmc Exp $ */ 2 /* $NetBSD: dc21040reg.h,v 1.11 1997/06/08 18:44:02 thorpej Exp $ */ 3 4 /*- 5 * Copyright (c) 1994, 1995, 1996 Matt Thomas <matt@3am-software.com> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. The name of the author may not be used to endorse or promote products 14 * derived from this software without specific prior written permission 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 * Id: dc21040reg.h,v 1.24 1997/05/16 19:47:09 thomas Exp 28 */ 29 30 #if !defined(_DC21040_H) 31 #define _DC21040_H 32 33 /* XXX The following only works with 21x4x chips which have 34 * the descriptor swap bit. 21040 chips need to have the 35 * descriptor in LE order regardles............. 36 */ 37 #if defined(BYTE_ORDER) && BYTE_ORDER == BIG_ENDIAN 38 #define TULIP_BITFIELD2(a, b) b, a 39 #define TULIP_BITFIELD3(a, b, c) c, b, a 40 #define TULIP_BITFIELD4(a, b, c, d) d, c, b, a 41 #else 42 #define TULIP_BITFIELD2(a, b) a, b 43 #define TULIP_BITFIELD3(a, b, c) a, b, c 44 #define TULIP_BITFIELD4(a, b, c, d) a, b, c, d 45 #endif 46 47 typedef union { 48 struct { 49 u_int32_t TULIP_BITFIELD3(bd_length1 : 11, 50 bd_length2 : 11, 51 bd_flag : 10); 52 }s; 53 u_int32_t f; 54 } tulip_desc_bitfield_t; 55 #define bd_length1 s.bd_length1 56 #define bd_length2 s.bd_length2 57 #define bd_flag s.bd_flag 58 typedef struct { 59 u_int32_t d_status; 60 tulip_desc_bitfield_t u; 61 u_int32_t d_addr1; 62 u_int32_t d_addr2; 63 #ifdef PPC_MPC106_BUG 64 u_int32_t fill[4]; /* Make descr. 32 bytes avoiding MPC106 bug! */ 65 #endif 66 } tulip_desc_t; 67 68 #define TULIP_DSTS_OWNER 0x80000000 /* Owner (1 = 21040) */ 69 #define TULIP_DSTS_ERRSUM 0x00008000 /* Error Summary */ 70 /* 71 * Transmit Status 72 */ 73 #define TULIP_DSTS_TxBABBLE 0x00004000 /* Transmitter Babbled */ 74 #define TULIP_DSTS_TxCARRLOSS 0x00000800 /* Carrier Loss */ 75 #define TULIP_DSTS_TxNOCARR 0x00000400 /* No Carrier */ 76 #define TULIP_DSTS_TxLATECOLL 0x00000200 /* Late Collision */ 77 #define TULIP_DSTS_TxEXCCOLL 0x00000100 /* Excessive Collisions */ 78 #define TULIP_DSTS_TxNOHRTBT 0x00000080 /* No Heartbeat */ 79 #define TULIP_DSTS_TxCOLLMASK 0x00000078 /* Collision Count (mask) */ 80 #define TULIP_DSTS_V_TxCOLLCNT 0x00000003 /* Collision Count (bit) */ 81 #define TULIP_DSTS_TxLINKFAIL 0x00000004 /* Link Failure */ 82 #define TULIP_DSTS_TxUNDERFLOW 0x00000002 /* Underflow Error */ 83 #define TULIP_DSTS_TxDEFERRED 0x00000001 /* Initially Deferred */ 84 /* 85 * Receive Status 86 */ 87 #define TULIP_DSTS_RxBADLENGTH 0x00004000 /* Length Error */ 88 #define TULIP_DSTS_RxDATATYPE 0x00003000 /* Data Type */ 89 #define TULIP_DSTS_RxRUNT 0x00000800 /* Runt Frame */ 90 #define TULIP_DSTS_RxMULTICAST 0x00000400 /* Multicast Frame */ 91 #define TULIP_DSTS_RxFIRSTDESC 0x00000200 /* First Descriptor */ 92 #define TULIP_DSTS_RxLASTDESC 0x00000100 /* Last Descriptor */ 93 #define TULIP_DSTS_RxTOOLONG 0x00000080 /* Frame Too Long */ 94 #define TULIP_DSTS_RxCOLLSEEN 0x00000040 /* Collision Seen */ 95 #define TULIP_DSTS_RxFRAMETYPE 0x00000020 /* Frame Type */ 96 #define TULIP_DSTS_RxWATCHDOG 0x00000010 /* Receive Watchdog */ 97 #define TULIP_DSTS_RxDRBBLBIT 0x00000004 /* Dribble Bit */ 98 #define TULIP_DSTS_RxBADCRC 0x00000002 /* CRC Error */ 99 #define TULIP_DSTS_RxOVERFLOW 0x00000001 /* Overflow */ 100 101 102 #define TULIP_DFLAG_ENDRING 0x0008 /* End of Transmit Ring */ 103 #define TULIP_DFLAG_CHAIN 0x0004 /* Chain using d_addr2 */ 104 105 #define TULIP_DFLAG_TxWANTINTR 0x0200 /* Signal Interrupt on Completion */ 106 #define TULIP_DFLAG_TxLASTSEG 0x0100 /* Last Segment */ 107 #define TULIP_DFLAG_TxFIRSTSEG 0x0080 /* First Segment */ 108 #define TULIP_DFLAG_TxINVRSFILT 0x0040 /* Inverse Filtering */ 109 #define TULIP_DFLAG_TxSETUPPKT 0x0020 /* Setup Packet */ 110 #define TULIP_DFLAG_TxHASCRC 0x0010 /* Don't Append the CRC */ 111 #define TULIP_DFLAG_TxNOPADDING 0x0002 /* Don't AutoPad */ 112 #define TULIP_DFLAG_TxHASHFILT 0x0001 /* Hash/Perfect Filtering */ 113 114 /* 115 * The 21040 Registers (IO Space Addresses) 116 */ 117 #define TULIP_REG_BUSMODE 0x00 /* CSR0 -- Bus Mode */ 118 #define TULIP_REG_TXPOLL 0x08 /* CSR1 -- Transmit Poll Demand */ 119 #define TULIP_REG_RXPOLL 0x10 /* CSR2 -- Receive Poll Demand */ 120 #define TULIP_REG_RXLIST 0x18 /* CSR3 -- Receive List Base Addr */ 121 #define TULIP_REG_TXLIST 0x20 /* CSR4 -- Transmit List Base Addr */ 122 #define TULIP_REG_STATUS 0x28 /* CSR5 -- Status */ 123 #define TULIP_REG_CMD 0x30 /* CSR6 -- Command */ 124 #define TULIP_REG_INTR 0x38 /* CSR7 -- Interrupt Control */ 125 #define TULIP_REG_MISSES 0x40 /* CSR8 -- Missed Frame Counter */ 126 #define TULIP_REG_ADDRROM 0x48 /* CSR9 -- ENET ROM Register */ 127 #define TULIP_REG_RSRVD 0x50 /* CSR10 -- Reserved */ 128 #define TULIP_REG_FULL_DUPLEX 0x58 /* CSR11 -- Full Duplex */ 129 #define TULIP_REG_SIA_STATUS 0x60 /* CSR12 -- SIA Status */ 130 #define TULIP_REG_SIA_CONN 0x68 /* CSR13 -- SIA Connectivity */ 131 #define TULIP_REG_SIA_TXRX 0x70 /* CSR14 -- SIA Tx Rx */ 132 #define TULIP_REG_SIA_GEN 0x78 /* CSR15 -- SIA General */ 133 134 /* 135 * CSR5 -- Status Register 136 * CSR7 -- Interrupt Control 137 */ 138 #define TULIP_STS_ERRORMASK 0x03800000L /* ( R) Error Bits (Valid when SYSERROR is set) */ 139 #define TULIP_STS_ERR_PARITY 0x00000000L /* 000 - Parity Error (Perform Reset) */ 140 #define TULIP_STS_ERR_MASTER 0x00800000L /* 001 - Master Abort */ 141 #define TULIP_STS_ERR_TARGET 0x01000000L /* 010 - Target Abort */ 142 #define TULIP_STS_ERR_SHIFT 23 143 #define TULIP_STS_TXSTATEMASK 0x00700000L /* ( R) Transmission Process State */ 144 #define TULIP_STS_TXS_RESET 0x00000000L /* 000 - Rset or transmit jabber expired */ 145 #define TULIP_STS_TXS_FETCH 0x00100000L /* 001 - Fetching transmit descriptor */ 146 #define TULIP_STS_TXS_WAITEND 0x00200000L /* 010 - Wait for end of transmission */ 147 #define TULIP_STS_TXS_READING 0x00300000L /* 011 - Read buffer and enqueue data */ 148 #define TULIP_STS_TXS_RSRVD 0x00400000L /* 100 - Reserved */ 149 #define TULIP_STS_TXS_SETUP 0x00500000L /* 101 - Setup Packet */ 150 #define TULIP_STS_TXS_SUSPEND 0x00600000L /* 110 - Transmit FIFO underflow or an 151 unavailable transmit descriptor */ 152 #define TULIP_STS_TXS_CLOSE 0x00700000L /* 111 - Close transmit descriptor */ 153 #define TULIP_STS_RXSTATEMASK 0x000E0000L /* ( R) Receive Process State*/ 154 #define TULIP_STS_RXS_STOPPED 0x00000000L /* 000 - Stopped */ 155 #define TULIP_STS_RXS_FETCH 0x00020000L /* 001 - Running -- Fetch receive descriptor */ 156 #define TULIP_STS_RXS_ENDCHECK 0x00040000L /* 010 - Running -- Check for end of receive 157 packet before prefetch of next descriptor */ 158 #define TULIP_STS_RXS_WAIT 0x00060000L /* 011 - Running -- Wait for receive packet */ 159 #define TULIP_STS_RXS_SUSPEND 0x00080000L /* 100 - Suspended -- As a result of 160 unavailable receive buffers */ 161 #define TULIP_STS_RXS_CLOSE 0x000A0000L /* 101 - Running -- Close receive descriptor */ 162 #define TULIP_STS_RXS_FLUSH 0x000C0000L /* 110 - Running -- Flush the current frame 163 from the receive FIFO as a result of 164 an unavailable receive buffer */ 165 #define TULIP_STS_RXS_DEQUEUE 0x000E0000L /* 111 - Running -- Dequeue the receive frame 166 from the receive FIFO into the receive 167 buffer. */ 168 #define TULIP_STS_NORMALINTR 0x00010000L /* (RW) Normal Interrupt */ 169 #define TULIP_STS_ABNRMLINTR 0x00008000L /* (RW) Abnormal Interrupt */ 170 #define TULIP_STS_SYSERROR 0x00002000L /* (RW) System Error */ 171 #define TULIP_STS_LINKFAIL 0x00001000L /* (RW) Link Failure (21040) */ 172 #define TULIP_STS_FULDPLXSHRT 0x00000800L /* (RW) Full Duplex Short Fram Rcvd (21040) */ 173 #define TULIP_STS_GPTIMEOUT 0x00000800L /* (RW) General Purpose Timeout (21140) */ 174 #define TULIP_STS_AUI 0x00000400L /* (RW) AUI/TP Switch (21040) */ 175 #define TULIP_STS_RXTIMEOUT 0x00000200L /* (RW) Receive Watchdog Timeout */ 176 #define TULIP_STS_RXSTOPPED 0x00000100L /* (RW) Receive Process Stopped */ 177 #define TULIP_STS_RXNOBUF 0x00000080L /* (RW) Receive Buffer Unavailable */ 178 #define TULIP_STS_RXINTR 0x00000040L /* (RW) Receive Interrupt */ 179 #define TULIP_STS_TXUNDERFLOW 0x00000020L /* (RW) Transmit Underflow */ 180 #define TULIP_STS_LINKPASS 0x00000010L /* (RW) LinkPass (21041) */ 181 #define TULIP_STS_TXBABBLE 0x00000008L /* (RW) Transmit Jabber Timeout */ 182 #define TULIP_STS_TXNOBUF 0x00000004L /* (RW) Transmit Buffer Unavailable */ 183 #define TULIP_STS_TXSTOPPED 0x00000002L /* (RW) Transmit Process Stopped */ 184 #define TULIP_STS_TXINTR 0x00000001L /* (RW) Transmit Interrupt */ 185 186 /* 187 * CSR6 -- Command (Operation Mode) Register 188 */ 189 #define TULIP_CMD_MUSTBEONE 0x02000000L /* (RW) Must Be One (21140) */ 190 #define TULIP_CMD_SCRAMBLER 0x01000000L /* (RW) Scrambler Mode (21140) */ 191 #define TULIP_CMD_PCSFUNCTION 0x00800000L /* (RW) PCS Function (21140) */ 192 #define TULIP_CMD_TXTHRSHLDCTL 0x00400000L /* (RW) Transmit Threshold Mode (21140) */ 193 #define TULIP_CMD_STOREFWD 0x00200000L /* (RW) Store and Forward (21140) */ 194 #define TULIP_CMD_NOHEARTBEAT 0x00080000L /* (RW) No Heartbeat (21140) */ 195 #define TULIP_CMD_PORTSELECT 0x00040000L /* (RW) Post Select (100Mb) (21140) */ 196 #define TULIP_CMD_ENHCAPTEFFCT 0x00040000L /* (RW) Enhanced Capture Effect (21041) */ 197 #define TULIP_CMD_CAPTREFFCT 0x00020000L /* (RW) Capture Effect (!802.3) */ 198 #define TULIP_CMD_BACKPRESSURE 0x00010000L /* (RW) Back Pressure (!802.3) (21040) */ 199 #define TULIP_CMD_THRESHOLDCTL 0x0000C000L /* (RW) Threshold Control */ 200 #define TULIP_CMD_THRSHLD72 0x00000000L /* 00 - 72 Bytes */ 201 #define TULIP_CMD_THRSHLD96 0x00004000L /* 01 - 96 Bytes */ 202 #define TULIP_CMD_THRSHLD128 0x00008000L /* 10 - 128 bytes */ 203 #define TULIP_CMD_THRSHLD160 0x0000C000L /* 11 - 160 Bytes */ 204 #define TULIP_CMD_TXRUN 0x00002000L /* (RW) Start/Stop Transmitter */ 205 #define TULIP_CMD_FORCECOLL 0x00001000L /* (RW) Force Collisions */ 206 #define TULIP_CMD_OPERMODE 0x00000C00L /* (RW) Operating Mode */ 207 #define TULIP_CMD_FULLDUPLEX 0x00000200L /* (RW) Full Duplex Mode */ 208 #define TULIP_CMD_FLAKYOSCDIS 0x00000100L /* (RW) Flakey Oscillator Disable */ 209 #define TULIP_CMD_ALLMULTI 0x00000080L /* (RW) Pass All Multicasts */ 210 #define TULIP_CMD_PROMISCUOUS 0x00000040L /* (RW) Promiscuous Mode */ 211 #define TULIP_CMD_BACKOFFCTR 0x00000020L /* (RW) Start/Stop Backoff Counter (!802.3) */ 212 #define TULIP_CMD_INVFILTER 0x00000010L /* (R ) Inverse Filtering */ 213 #define TULIP_CMD_PASSBADPKT 0x00000008L /* (RW) Pass Bad Frames */ 214 #define TULIP_CMD_HASHONLYFLTR 0x00000004L /* (R ) Hash Only Filtering */ 215 #define TULIP_CMD_RXRUN 0x00000002L /* (RW) Start/Stop Receive Filtering */ 216 #define TULIP_CMD_HASHPRFCTFLTR 0x00000001L /* (R ) Hash/Perfect Receive Filtering */ 217 218 #define TULIP_SIASTS_OTHERRXACTIVITY 0x00000200L 219 #define TULIP_SIASTS_RXACTIVITY 0x00000100L 220 #define TULIP_SIASTS_LINKFAIL 0x00000004L 221 #define TULIP_SIASTS_LINK100FAIL 0x00000002L 222 #define TULIP_SIACONN_RESET 0x00000000L 223 224 /* 225 * 21040 SIA definitions 226 */ 227 #define TULIP_21040_PROBE_10BASET_TIMEOUT 2500 228 #define TULIP_21040_PROBE_AUIBNC_TIMEOUT 300 229 #define TULIP_21040_PROBE_EXTSIA_TIMEOUT 300 230 231 #define TULIP_21040_SIACONN_10BASET 0x00008F01L 232 #define TULIP_21040_SIATXRX_10BASET 0x0000FFFFL 233 #define TULIP_21040_SIAGEN_10BASET 0x00000000L 234 235 #define TULIP_21040_SIACONN_10BASET_FD 0x00008F01L 236 #define TULIP_21040_SIATXRX_10BASET_FD 0x0000FFFDL 237 #define TULIP_21040_SIAGEN_10BASET_FD 0x00000000L 238 239 #define TULIP_21040_SIACONN_AUIBNC 0x00008F09L 240 #define TULIP_21040_SIATXRX_AUIBNC 0x00000705L 241 #define TULIP_21040_SIAGEN_AUIBNC 0x00000006L 242 243 #define TULIP_21040_SIACONN_EXTSIA 0x00003041L 244 #define TULIP_21040_SIATXRX_EXTSIA 0x00000000L 245 #define TULIP_21040_SIAGEN_EXTSIA 0x00000006L 246 247 /* 248 * 21041 SIA definitions 249 */ 250 251 #define TULIP_21041_PROBE_10BASET_TIMEOUT 2500 252 #define TULIP_21041_PROBE_AUIBNC_TIMEOUT 300 253 254 #define TULIP_21041_SIACONN_10BASET 0x0000EF01L 255 #define TULIP_21041_SIATXRX_10BASET 0x0000FF3FL 256 #define TULIP_21041_SIAGEN_10BASET 0x00000000L 257 258 #define TULIP_21041P2_SIACONN_10BASET 0x0000EF01L 259 #define TULIP_21041P2_SIATXRX_10BASET 0x0000FFFFL 260 #define TULIP_21041P2_SIAGEN_10BASET 0x00000000L 261 262 #define TULIP_21041_SIACONN_10BASET_FD 0x0000EF01L 263 #define TULIP_21041_SIATXRX_10BASET_FD 0x0000FF3DL 264 #define TULIP_21041_SIAGEN_10BASET_FD 0x00000000L 265 266 #define TULIP_21041P2_SIACONN_10BASET_FD 0x0000EF01L 267 #define TULIP_21041P2_SIATXRX_10BASET_FD 0x0000FFFFL 268 #define TULIP_21041P2_SIAGEN_10BASET_FD 0x00000000L 269 270 #define TULIP_21041_SIACONN_AUI 0x0000EF09L 271 #define TULIP_21041_SIATXRX_AUI 0x0000F73DL 272 #define TULIP_21041_SIAGEN_AUI 0x0000000EL 273 274 #define TULIP_21041P2_SIACONN_AUI 0x0000EF09L 275 #define TULIP_21041P2_SIATXRX_AUI 0x0000F7FDL 276 #define TULIP_21041P2_SIAGEN_AUI 0x0000000EL 277 278 #define TULIP_21041_SIACONN_BNC 0x0000EF09L 279 #define TULIP_21041_SIATXRX_BNC 0x0000F73DL 280 #define TULIP_21041_SIAGEN_BNC 0x00000006L 281 282 #define TULIP_21041P2_SIACONN_BNC 0x0000EF09L 283 #define TULIP_21041P2_SIATXRX_BNC 0x0000F7FDL 284 #define TULIP_21041P2_SIAGEN_BNC 0x00000006L 285 286 /* 287 * 21142 SIA definitions 288 */ 289 290 #define TULIP_21142_PROBE_10BASET_TIMEOUT 2500 291 #define TULIP_21142_PROBE_AUIBNC_TIMEOUT 300 292 293 #define TULIP_21142_SIACONN_10BASET 0x00000001L 294 #define TULIP_21142_SIATXRX_10BASET 0x00007F3FL 295 #define TULIP_21142_SIAGEN_10BASET 0x00000008L 296 297 #define TULIP_21142_SIACONN_10BASET_FD 0x00000001L 298 #define TULIP_21142_SIATXRX_10BASET_FD 0x00007F3DL 299 #define TULIP_21142_SIAGEN_10BASET_FD 0x00000008L 300 301 #define TULIP_21142_SIACONN_AUI 0x00000009L 302 #define TULIP_21142_SIATXRX_AUI 0x00000705L 303 #define TULIP_21142_SIAGEN_AUI 0x0000000EL 304 305 #define TULIP_21142_SIACONN_BNC 0x00000009L 306 #define TULIP_21142_SIATXRX_BNC 0x00000705L 307 #define TULIP_21142_SIAGEN_BNC 0x00000006L 308 309 310 311 312 #define TULIP_WATCHDOG_TXDISABLE 0x00000001L 313 #define TULIP_WATCHDOG_RXDISABLE 0x00000010L 314 315 #define TULIP_BUSMODE_SWRESET 0x00000001L 316 #define TULIP_BUSMODE_DESCSKIPLEN_MASK 0x0000007CL 317 #define TULIP_BUSMODE_BIGENDIAN 0x00000080L 318 #define TULIP_BUSMODE_BURSTLEN_MASK 0x00003F00L 319 #define TULIP_BUSMODE_BURSTLEN_DEFAULT 0x00000000L 320 #define TULIP_BUSMODE_BURSTLEN_1LW 0x00000100L 321 #define TULIP_BUSMODE_BURSTLEN_2LW 0x00000200L 322 #define TULIP_BUSMODE_BURSTLEN_4LW 0x00000400L 323 #define TULIP_BUSMODE_BURSTLEN_8LW 0x00000800L 324 #define TULIP_BUSMODE_BURSTLEN_16LW 0x00001000L 325 #define TULIP_BUSMODE_BURSTLEN_32LW 0x00002000L 326 #define TULIP_BUSMODE_CACHE_NOALIGN 0x00000000L 327 #define TULIP_BUSMODE_CACHE_ALIGN8 0x00004000L 328 #define TULIP_BUSMODE_CACHE_ALIGN16 0x00008000L 329 #define TULIP_BUSMODE_CACHE_ALIGN32 0x0000C000L 330 #define TULIP_BUSMODE_TXPOLL_NEVER 0x00000000L 331 #define TULIP_BUSMODE_TXPOLL_200000ns 0x00020000L 332 #define TULIP_BUSMODE_TXPOLL_800000ns 0x00040000L 333 #define TULIP_BUSMODE_TXPOLL_1600000ns 0x00060000L 334 #define TULIP_BUSMODE_TXPOLL_12800ns 0x00080000L /* 21041 only */ 335 #define TULIP_BUSMODE_TXPOLL_25600ns 0x000A0000L /* 21041 only */ 336 #define TULIP_BUSMODE_TXPOLL_51200ns 0x000C0000L /* 21041 only */ 337 #define TULIP_BUSMODE_TXPOLL_102400ns 0x000E0000L /* 21041 only */ 338 #define TULIP_BUSMODE_DESC_BIGENDIAN 0x00100000L /* 21041 only */ 339 #define TULIP_BUSMODE_READMULTIPLE 0x00200000L /* */ 340 341 #define TULIP_REG_CFDA 0x40 342 #define TULIP_CFDA_SLEEP 0x80000000L 343 #define TULIP_CFDA_SNOOZE 0x40000000L 344 345 #define TULIP_GP_PINSET 0x00000100L 346 /* 347 * These are the definitions used for the DEC 21140 348 * evaluation board. 349 */ 350 #define TULIP_GP_EB_PINS 0x0000001F /* General Purpose Pin directions */ 351 #define TULIP_GP_EB_OK10 0x00000080 /* 10 Mb/sec Signal Detect gep<7> */ 352 #define TULIP_GP_EB_OK100 0x00000040 /* 100 Mb/sec Signal Detect gep<6> */ 353 #define TULIP_GP_EB_INIT 0x0000000B /* No loopback --- point-to-point */ 354 355 /* 356 * These are the definitions used for the SMC9332 (21140) board. 357 */ 358 #define TULIP_GP_SMC_9332_PINS 0x0000003F /* General Purpose Pin directions */ 359 #define TULIP_GP_SMC_9332_OK10 0x00000080 /* 10 Mb/sec Signal Detect gep<7> */ 360 #define TULIP_GP_SMC_9332_OK100 0x00000040 /* 100 Mb/sec Signal Detect gep<6> */ 361 #define TULIP_GP_SMC_9332_INIT 0x00000009 /* No loopback --- point-to-point */ 362 363 #define TULIP_OUI_SMC_0 0x00 364 #define TULIP_OUI_SMC_1 0x00 365 #define TULIP_OUI_SMC_2 0xC0 366 367 /* 368 * There are the definitions used for the DEC DE500 369 * 10/100 family of boards 370 */ 371 #define TULIP_GP_DE500_PINS 0x0000001FL 372 #define TULIP_GP_DE500_LINK_PASS 0x00000080L 373 #define TULIP_GP_DE500_SYM_LINK 0x00000040L 374 #define TULIP_GP_DE500_SIGNAL_DETECT 0x00000020L 375 #define TULIP_GP_DE500_PHY_RESET 0x00000010L 376 #define TULIP_GP_DE500_HALFDUPLEX 0x00000008L 377 #define TULIP_GP_DE500_PHY_LOOPBACK 0x00000004L 378 #define TULIP_GP_DE500_FORCE_LED 0x00000002L 379 #define TULIP_GP_DE500_FORCE_100 0x00000001L 380 381 /* 382 * These are the definitions used for the Cogent EM100 383 * 21140 board. 384 */ 385 #define TULIP_GP_EM100_PINS 0x0000003F /* General Purpose Pin directions */ 386 #define TULIP_GP_EM100_INIT 0x00000009 /* No loopback --- point-to-point */ 387 #define TULIP_OUI_COGENT_0 0x00 388 #define TULIP_OUI_COGENT_1 0x00 389 #define TULIP_OUI_COGENT_2 0x92 390 #define TULIP_COGENT_EM100TX_ID 0x12 391 #define TULIP_COGENT_EM100FX_ID 0x15 392 393 394 /* 395 * These are the definitions used for the Znyx ZX342 396 * 10/100 board 397 */ 398 #define TULIP_OUI_ZNYX_0 0x00 399 #define TULIP_OUI_ZNYX_1 0xC0 400 #define TULIP_OUI_ZNYX_2 0x95 401 402 #define TULIP_ZNYX_ID_ZX312 0x0602 403 #define TULIP_ZNYX_ID_ZX312T 0x0622 404 #define TULIP_ZNYX_ID_ZX314_INTA 0x0701 405 #define TULIP_ZNYX_ID_ZX314 0x0711 406 #define TULIP_ZNYX_ID_ZX315_INTA 0x0801 407 #define TULIP_ZNYX_ID_ZX315 0x0811 408 #define TULIP_ZNYX_ID_ZX342 0x0901 409 #define TULIP_ZNYX_ID_ZX342B 0x0921 410 #define TULIP_ZNYX_ID_ZX342_X3 0x0902 411 #define TULIP_ZNYX_ID_ZX342_X4 0x0903 412 #define TULIP_ZNYX_ID_ZX344 0x0A01 413 #define TULIP_ZNYX_ID_ZX351 0x0B01 414 #define TULIP_ZNYX_ID_ZX345 0x0C01 415 #define TULIP_ZNYX_ID_ZX311 0x0D01 416 #define TULIP_ZNYX_ID_ZX346 0x0E01 417 418 #define TULIP_GP_ZX34X_PINS 0x0000001F /* General Purpose Pin directions */ 419 #define TULIP_GP_ZX344_PINS 0x0000000B /* General Purpose Pin directions */ 420 #define TULIP_GP_ZX345_PINS 0x00000003 /* General Purpose Pin directions */ 421 #define TULIP_GP_ZX346_PINS 0x00000043 /* General Purpose Pin directions */ 422 #define TULIP_GP_ZX34X_LNKFAIL 0x00000080 /* 10Mb/s Link Failure */ 423 #define TULIP_GP_ZX34X_SYMDET 0x00000040 /* 100Mb/s Symbol Detect */ 424 #define TULIP_GP_ZX345_PHYACT 0x00000040 /* PHY Activity */ 425 #define TULIP_GP_ZX34X_SIGDET 0x00000020 /* 100Mb/s Signal Detect */ 426 #define TULIP_GP_ZX346_AUTONEG_ENABLED 0x00000020 /* 802.3u autoneg enabled */ 427 #define TULIP_GP_ZX342_COLENA 0x00000008 /* 10t Ext LB */ 428 #define TULIP_GP_ZX344_ROTINT 0x00000008 /* PPB IRQ rotation */ 429 #define TULIP_GP_ZX345_SPEED10 0x00000008 /* 10Mb speed detect */ 430 #define TULIP_GP_ZX346_SPEED100 0x00000008 /* 100Mb speed detect */ 431 #define TULIP_GP_ZX34X_NCOLENA 0x00000004 /* 10t Int LB */ 432 #define TULIP_GP_ZX34X_RXMATCH 0x00000004 /* RX Match */ 433 #define TULIP_GP_ZX346_FULLDUPLEX 0x00000004 /* Full Duplex Sensed */ 434 #define TULIP_GP_ZX34X_LB102 0x00000002 /* 100tx twister LB */ 435 #define TULIP_GP_ZX34X_NLB101 0x00000001 /* PDT/PDR LB */ 436 #define TULIP_GP_ZX34X_INIT 0x00000009 437 438 /* 439 * Compex's OUI. We need to twiddle a bit on their 21041 card. 440 */ 441 #define TULIP_OUI_COMPEX_0 0x00 442 #define TULIP_OUI_COMPEX_1 0x80 443 #define TULIP_OUI_COMPEX_2 0x48 444 #define TULIP_21041_COMPEX_XREGDATA 1 445 446 /* 447 * Asante's OUI and stuff... 448 */ 449 #define TULIP_OUI_ASANTE_0 0x00 450 #define TULIP_OUI_ASANTE_1 0x00 451 #define TULIP_OUI_ASANTE_2 0x94 452 #define TULIP_GP_ASANTE_PINS 0x000000bf /* GP pin config */ 453 #define TULIP_GP_ASANTE_PHYRESET 0x00000008 /* Reset PHY */ 454 455 /* 456 * ACCTON EN1207 specialties 457 */ 458 459 #define TULIP_OUI_EN1207_0 0x00 460 #define TULIP_OUI_EN1207_1 0x00 461 #define TULIP_OUI_EN1207_2 0xE8 462 463 #define TULIP_CSR8_EN1207 0x08 464 #define TULIP_CSR9_EN1207 0x00 465 #define TULIP_CSR10_EN1207 0x03 466 #define TULIP_CSR11_EN1207 0x1F 467 468 #define TULIP_GP_EN1207_BNC_INIT 0x0000011B 469 #define TULIP_GP_EN1207_UTP_INIT 0x9E00000B 470 #define TULIP_GP_EN1207_100_INIT 0x6D00031B 471 472 /* 473 * SROM definitions for the 21140 and 21041. 474 */ 475 #define SROMXREG 0x0400 476 #define SROMSEL 0x0800 477 #define SROMRD 0x4000 478 #define SROMWR 0x2000 479 #define SROMDIN 0x0008 480 #define SROMDOUT 0x0004 481 #define SROMDOUTON 0x0004 482 #define SROMDOUTOFF 0x0004 483 #define SROMCLKON 0x0002 484 #define SROMCLKOFF 0x0002 485 #define SROMCSON 0x0001 486 #define SROMCSOFF 0x0001 487 #define SROMCS 0x0001 488 489 #define SROMCMD_MODE 4 490 #define SROMCMD_WR 5 491 #define SROMCMD_RD 6 492 493 #define SROM_BITWIDTH 6 494 495 /* 496 * MII Definitions for the 21041 and 21140/21140A/21142 497 */ 498 #define MII_PREAMBLE (~0) 499 #define MII_TEST 0xAAAAAAAA 500 #define MII_RDCMD 0xF6 /* 1111.0110 */ 501 #define MII_WRCMD 0xF5 /* 1111.0101 */ 502 #define MII_DIN 0x00080000 503 #define MII_RD 0x00040000 504 #define MII_WR 0x00000000 505 #define MII_DOUT 0x00020000 506 #define MII_CLK 0x00010000 507 #define MII_CLKON MII_CLK 508 #define MII_CLKOFF MII_CLK 509 510 #define PHYREG_CONTROL 0 511 #define PHYREG_STATUS 1 512 #define PHYREG_IDLOW 2 513 #define PHYREG_IDHIGH 3 514 #define PHYREG_AUTONEG_ADVERTISEMENT 4 515 #define PHYREG_AUTONEG_ABILITIES 5 516 #define PHYREG_AUTONEG_EXPANSION 6 517 #define PHYREG_AUTONEG_NEXTPAGE 7 518 519 #define PHYSTS_100BASET4 0x8000 520 #define PHYSTS_100BASETX_FD 0x4000 521 #define PHYSTS_100BASETX 0x2000 522 #define PHYSTS_10BASET_FD 0x1000 523 #define PHYSTS_10BASET 0x0800 524 #define PHYSTS_AUTONEG_DONE 0x0020 525 #define PHYSTS_REMOTE_FAULT 0x0010 526 #define PHYSTS_CAN_AUTONEG 0x0008 527 #define PHYSTS_LINK_UP 0x0004 528 #define PHYSTS_JABBER_DETECT 0x0002 529 #define PHYSTS_EXTENDED_REGS 0x0001 530 531 #define PHYCTL_RESET 0x8000 532 #define PHYCTL_SELECT_100MB 0x2000 533 #define PHYCTL_AUTONEG_ENABLE 0x1000 534 #define PHYCTL_ISOLATE 0x0400 535 #define PHYCTL_AUTONEG_RESTART 0x0200 536 #define PHYCTL_FULL_DUPLEX 0x0100 537 538 539 #define MII_RD 0x00040000 540 #define MII_WR 0x00000000 541 #define MII_DIN 0x00080000 542 #define MII_DOUT 0x00020000 543 #define MII_DOUTON MII_DOUT 544 #define MII_DOUTOFF MII_DOUT 545 #define MII_CLK 0x00010000 546 #define MII_CLKON MII_CLK 547 #define MII_CLKOFF MII_CLK 548 549 /* 550 * Definitions for the DE425. 551 */ 552 #define DE425_CFID 0x08 /* Configuration Id */ 553 #define DE425_CFCS 0x0C /* Configuration Command-Status */ 554 #define DE425_CFRV 0x18 /* Configuration Revision */ 555 #define DE425_CFLT 0x1C /* Configuration Latency Timer */ 556 #define DE425_CBIO 0x28 /* Configuration Base IO Address */ 557 #define DE425_CFDA 0x2C /* Configuration Driver Area */ 558 #define DE425_ENETROM_OFFSET 0xC90 /* Offset in I/O space for ENETROM */ 559 #define DE425_CFG0 0xC88 /* IRQ register */ 560 #define DE425_EISAID 0x10a34250 /* EISA device id */ 561 #define DE425_EISA_IOSIZE 0x100 562 563 #define DEC_VENDORID 0x1011 564 #define CHIPID_21040 0x0002 565 #define CHIPID_21140 0x0009 566 #define CHIPID_21041 0x0014 567 #define CHIPID_21142 0x0019 568 #define PCI_VENDORID(x) ((x) & 0xFFFF) 569 #define PCI_CHIPID(x) (((x) >> 16) & 0xFFFF) 570 571 /* 572 * Generic SROM Format 573 * 574 * 575 */ 576 577 typedef struct { 578 u_int8_t sh_idbuf[18]; 579 u_int8_t sh_version; 580 u_int8_t sh_adapter_count; 581 u_int8_t sh_ieee802_address[6]; 582 } tulip_srom_header_t; 583 584 typedef struct { 585 u_int8_t sai_device; 586 u_int8_t sai_leaf_offset_lowbyte; 587 u_int8_t sai_leaf_offset_highbyte; 588 } tulip_srom_adapter_info_t; 589 590 typedef enum { 591 TULIP_SROM_CONNTYPE_10BASET =0x0000, 592 TULIP_SROM_CONNTYPE_BNC =0x0001, 593 TULIP_SROM_CONNTYPE_AUI =0x0002, 594 TULIP_SROM_CONNTYPE_100BASETX =0x0003, 595 TULIP_SROM_CONNTYPE_100BASET4 =0x0006, 596 TULIP_SROM_CONNTYPE_100BASEFX =0x0007, 597 TULIP_SROM_CONNTYPE_MII_10BASET =0x0009, 598 TULIP_SROM_CONNTYPE_MII_100BASETX =0x000D, 599 TULIP_SROM_CONNTYPE_MII_100BASET4 =0x000F, 600 TULIP_SROM_CONNTYPE_MII_100BASEFX =0x0010, 601 TULIP_SROM_CONNTYPE_10BASET_NWAY =0x0100, 602 TULIP_SROM_CONNTYPE_10BASET_FD =0x0204, 603 TULIP_SROM_CONNTYPE_MII_10BASET_FD =0x020A, 604 TULIP_SROM_CONNTYPE_100BASETX_FD =0x020E, 605 TULIP_SROM_CONNTYPE_MII_100BASETX_FD =0x0211, 606 TULIP_SROM_CONNTYPE_10BASET_NOLINKPASS =0x0400, 607 TULIP_SROM_CONNTYPE_AUTOSENSE =0x0800, 608 TULIP_SROM_CONNTYPE_AUTOSENSE_POWERUP =0x8800, 609 TULIP_SROM_CONNTYPE_AUTOSENSE_NWAY =0x9000, 610 TULIP_SROM_CONNTYPE_NOT_USED =0xFFFF 611 } tulip_srom_connection_t; 612 613 typedef enum { 614 TULIP_SROM_MEDIA_10BASET =0x0000, 615 TULIP_SROM_MEDIA_BNC =0x0001, 616 TULIP_SROM_MEDIA_AUI =0x0002, 617 TULIP_SROM_MEDIA_100BASETX =0x0003, 618 TULIP_SROM_MEDIA_10BASET_FD =0x0004, 619 TULIP_SROM_MEDIA_100BASETX_FD =0x0005, 620 TULIP_SROM_MEDIA_100BASET4 =0x0006, 621 TULIP_SROM_MEDIA_100BASEFX =0x0007, 622 TULIP_SROM_MEDIA_100BASEFX_FD =0x0008 623 } tulip_srom_media_t; 624 625 #define TULIP_SROM_21041_EXTENDED 0x40 626 627 #define TULIP_SROM_2114X_NOINDICATOR 0x8000 628 #define TULIP_SROM_2114X_DEFAULT 0x4000 629 #define TULIP_SROM_2114X_POLARITY 0x0080 630 #define TULIP_SROM_2114X_CMDBITS(n) (((n) & 0x0071) << 18) 631 #define TULIP_SROM_2114X_BITPOS(b) (1 << (((b) & 0x0E) >> 1)) 632 633 634 635 #endif /* !defined(_DC21040_H) */ 636