1 /* $OpenBSD: dc.c,v 1.88 2005/06/25 23:27:43 brad Exp $ */
2
3 /*
4 * Copyright (c) 1997, 1998, 1999
5 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 * $FreeBSD: src/sys/pci/if_dc.c,v 1.43 2001/01/19 23:55:07 wpaul Exp $
35 */
36
37 /*
38 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143
39 * series chips and several workalikes including the following:
40 *
41 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com)
42 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com)
43 * Lite-On 82c168/82c169 PNIC (www.litecom.com)
44 * ASIX Electronics AX88140A (www.asix.com.tw)
45 * ASIX Electronics AX88141 (www.asix.com.tw)
46 * ADMtek AL981 (www.admtek.com.tw)
47 * ADMtek AN983 (www.admtek.com.tw)
48 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com)
49 * Accton EN1217, EN2242 (www.accton.com)
50 * Xircom X3201 (www.xircom.com)
51 *
52 * Datasheets for the 21143 are available at developer.intel.com.
53 * Datasheets for the clone parts can be found at their respective sites.
54 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.)
55 * The PNIC II is essentially a Macronix 98715A chip; the only difference
56 * worth noting is that its multicast hash table is only 128 bits wide
57 * instead of 512.
58 *
59 * Written by Bill Paul <wpaul@ee.columbia.edu>
60 * Electrical Engineering Department
61 * Columbia University, New York City
62 */
63
64 /*
65 * The Intel 21143 is the successor to the DEC 21140. It is basically
66 * the same as the 21140 but with a few new features. The 21143 supports
67 * three kinds of media attachments:
68 *
69 * o MII port, for 10Mbps and 100Mbps support and NWAY
70 * autonegotiation provided by an external PHY.
71 * o SYM port, for symbol mode 100Mbps support.
72 * o 10baseT port.
73 * o AUI/BNC port.
74 *
75 * The 100Mbps SYM port and 10baseT port can be used together in
76 * combination with the internal NWAY support to create a 10/100
77 * autosensing configuration.
78 *
79 * Note that not all tulip workalikes are handled in this driver: we only
80 * deal with those which are relatively well behaved. The Winbond is
81 * handled separately due to its different register offsets and the
82 * special handling needed for its various bugs. The PNIC is handled
83 * here, but I'm not thrilled about it.
84 *
85 * All of the workalike chips use some form of MII transceiver support
86 * with the exception of the Macronix chips, which also have a SYM port.
87 * The ASIX AX88140A is also documented to have a SYM port, but all
88 * the cards I've seen use an MII transceiver, probably because the
89 * AX88140A doesn't support internal NWAY.
90 */
91
92 #include "bpfilter.h"
93
94 #include <sys/param.h>
95 #include <sys/systm.h>
96 #include <sys/mbuf.h>
97 #include <sys/protosw.h>
98 #include <sys/socket.h>
99 #include <sys/ioctl.h>
100 #include <sys/errno.h>
101 #include <sys/malloc.h>
102 #include <sys/kernel.h>
103 #include <sys/device.h>
104 #include <sys/timeout.h>
105
106 #include <net/if.h>
107 #include <net/if_dl.h>
108 #include <net/if_types.h>
109
110 #ifdef INET
111 #include <netinet/in.h>
112 #include <netinet/in_systm.h>
113 #include <netinet/in_var.h>
114 #include <netinet/ip.h>
115 #include <netinet/if_ether.h>
116 #endif
117
118 #include <net/if_media.h>
119
120 #if NBPFILTER > 0
121 #include <net/bpf.h>
122 #endif
123
124 #include <dev/mii/mii.h>
125 #include <dev/mii/miivar.h>
126
127 #include <machine/bus.h>
128 #include <dev/pci/pcidevs.h>
129
130 #include <dev/ic/dcreg.h>
131
132 int dc_intr(void *);
133 void dc_shutdown(void *);
134 void dc_power(int, void *);
135 struct dc_type *dc_devtype(void *);
136 int dc_newbuf(struct dc_softc *, int, struct mbuf *);
137 int dc_encap(struct dc_softc *, struct mbuf *, u_int32_t *);
138 int dc_coal(struct dc_softc *, struct mbuf **);
139
140 void dc_pnic_rx_bug_war(struct dc_softc *, int);
141 int dc_rx_resync(struct dc_softc *);
142 void dc_rxeof(struct dc_softc *);
143 void dc_txeof(struct dc_softc *);
144 void dc_tick(void *);
145 void dc_tx_underrun(struct dc_softc *);
146 void dc_start(struct ifnet *);
147 int dc_ioctl(struct ifnet *, u_long, caddr_t);
148 void dc_init(void *);
149 void dc_stop(struct dc_softc *);
150 void dc_watchdog(struct ifnet *);
151 int dc_ifmedia_upd(struct ifnet *);
152 void dc_ifmedia_sts(struct ifnet *, struct ifmediareq *);
153
154 void dc_delay(struct dc_softc *);
155 void dc_eeprom_width(struct dc_softc *);
156 void dc_eeprom_idle(struct dc_softc *);
157 void dc_eeprom_putbyte(struct dc_softc *, int);
158 void dc_eeprom_getword(struct dc_softc *, int, u_int16_t *);
159 void dc_eeprom_getword_pnic(struct dc_softc *, int, u_int16_t *);
160 void dc_eeprom_getword_xircom(struct dc_softc *, int, u_int16_t *);
161 void dc_read_eeprom(struct dc_softc *, caddr_t, int, int, int);
162
163 void dc_mii_writebit(struct dc_softc *, int);
164 int dc_mii_readbit(struct dc_softc *);
165 void dc_mii_sync(struct dc_softc *);
166 void dc_mii_send(struct dc_softc *, u_int32_t, int);
167 int dc_mii_readreg(struct dc_softc *, struct dc_mii_frame *);
168 int dc_mii_writereg(struct dc_softc *, struct dc_mii_frame *);
169 int dc_miibus_readreg(struct device *, int, int);
170 void dc_miibus_writereg(struct device *, int, int, int);
171 void dc_miibus_statchg(struct device *);
172
173 void dc_setcfg(struct dc_softc *, int);
174 u_int32_t dc_crc_le(struct dc_softc *, caddr_t);
175 u_int32_t dc_crc_be(caddr_t);
176 void dc_setfilt_21143(struct dc_softc *);
177 void dc_setfilt_asix(struct dc_softc *);
178 void dc_setfilt_admtek(struct dc_softc *);
179 void dc_setfilt_xircom(struct dc_softc *);
180
181 void dc_setfilt(struct dc_softc *);
182
183 void dc_reset(struct dc_softc *);
184 int dc_list_rx_init(struct dc_softc *);
185 int dc_list_tx_init(struct dc_softc *);
186
187 void dc_read_srom(struct dc_softc *, int);
188 void dc_parse_21143_srom(struct dc_softc *);
189 void dc_decode_leaf_sia(struct dc_softc *,
190 struct dc_eblock_sia *);
191 void dc_decode_leaf_mii(struct dc_softc *,
192 struct dc_eblock_mii *);
193 void dc_decode_leaf_sym(struct dc_softc *,
194 struct dc_eblock_sym *);
195 void dc_apply_fixup(struct dc_softc *, int);
196
197 #define DC_SETBIT(sc, reg, x) \
198 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
199
200 #define DC_CLRBIT(sc, reg, x) \
201 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
202
203 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x))
204 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x))
205
206 void
dc_delay(sc)207 dc_delay(sc)
208 struct dc_softc *sc;
209 {
210 int idx;
211
212 for (idx = (300 / 33) + 1; idx > 0; idx--)
213 CSR_READ_4(sc, DC_BUSCTL);
214 }
215
216 void
dc_eeprom_width(sc)217 dc_eeprom_width(sc)
218 struct dc_softc *sc;
219 {
220 int i;
221
222 /* Force EEPROM to idle state. */
223 dc_eeprom_idle(sc);
224
225 /* Enter EEPROM access mode. */
226 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
227 dc_delay(sc);
228 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
229 dc_delay(sc);
230 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
231 dc_delay(sc);
232 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
233 dc_delay(sc);
234
235 for (i = 3; i--;) {
236 if (6 & (1 << i))
237 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
238 else
239 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
240 dc_delay(sc);
241 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
242 dc_delay(sc);
243 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
244 dc_delay(sc);
245 }
246
247 for (i = 1; i <= 12; i++) {
248 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
249 dc_delay(sc);
250 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) {
251 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
252 dc_delay(sc);
253 break;
254 }
255 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
256 dc_delay(sc);
257 }
258
259 /* Turn off EEPROM access mode. */
260 dc_eeprom_idle(sc);
261
262 if (i < 4 || i > 12)
263 sc->dc_romwidth = 6;
264 else
265 sc->dc_romwidth = i;
266
267 /* Enter EEPROM access mode. */
268 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
269 dc_delay(sc);
270 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
271 dc_delay(sc);
272 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
273 dc_delay(sc);
274 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
275 dc_delay(sc);
276
277 /* Turn off EEPROM access mode. */
278 dc_eeprom_idle(sc);
279 }
280
281 void
dc_eeprom_idle(sc)282 dc_eeprom_idle(sc)
283 struct dc_softc *sc;
284 {
285 int i;
286
287 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
288 dc_delay(sc);
289 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
290 dc_delay(sc);
291 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
292 dc_delay(sc);
293 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
294 dc_delay(sc);
295
296 for (i = 0; i < 25; i++) {
297 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
298 dc_delay(sc);
299 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
300 dc_delay(sc);
301 }
302
303 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
304 dc_delay(sc);
305 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS);
306 dc_delay(sc);
307 CSR_WRITE_4(sc, DC_SIO, 0x00000000);
308 }
309
310 /*
311 * Send a read command and address to the EEPROM, check for ACK.
312 */
313 void
dc_eeprom_putbyte(sc,addr)314 dc_eeprom_putbyte(sc, addr)
315 struct dc_softc *sc;
316 int addr;
317 {
318 int d, i;
319
320 d = DC_EECMD_READ >> 6;
321
322 for (i = 3; i--; ) {
323 if (d & (1 << i))
324 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
325 else
326 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
327 dc_delay(sc);
328 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
329 dc_delay(sc);
330 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
331 dc_delay(sc);
332 }
333
334 /*
335 * Feed in each bit and strobe the clock.
336 */
337 for (i = sc->dc_romwidth; i--;) {
338 if (addr & (1 << i)) {
339 SIO_SET(DC_SIO_EE_DATAIN);
340 } else {
341 SIO_CLR(DC_SIO_EE_DATAIN);
342 }
343 dc_delay(sc);
344 SIO_SET(DC_SIO_EE_CLK);
345 dc_delay(sc);
346 SIO_CLR(DC_SIO_EE_CLK);
347 dc_delay(sc);
348 }
349 }
350
351 /*
352 * Read a word of data stored in the EEPROM at address 'addr.'
353 * The PNIC 82c168/82c169 has its own non-standard way to read
354 * the EEPROM.
355 */
356 void
dc_eeprom_getword_pnic(sc,addr,dest)357 dc_eeprom_getword_pnic(sc, addr, dest)
358 struct dc_softc *sc;
359 int addr;
360 u_int16_t *dest;
361 {
362 int i;
363 u_int32_t r;
364
365 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr);
366
367 for (i = 0; i < DC_TIMEOUT; i++) {
368 DELAY(1);
369 r = CSR_READ_4(sc, DC_SIO);
370 if (!(r & DC_PN_SIOCTL_BUSY)) {
371 *dest = (u_int16_t)(r & 0xFFFF);
372 return;
373 }
374 }
375 }
376
377 /*
378 * Read a word of data stored in the EEPROM at address 'addr.'
379 * The Xircom X3201 has its own non-standard way to read
380 * the EEPROM, too.
381 */
382 void
dc_eeprom_getword_xircom(struct dc_softc * sc,int addr,u_int16_t * dest)383 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest)
384 {
385 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ);
386
387 addr *= 2;
388 CSR_WRITE_4(sc, DC_ROM, addr | 0x160);
389 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff;
390 addr += 1;
391 CSR_WRITE_4(sc, DC_ROM, addr | 0x160);
392 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8;
393
394 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ);
395 }
396
397 /*
398 * Read a word of data stored in the EEPROM at address 'addr.'
399 */
400 void
dc_eeprom_getword(sc,addr,dest)401 dc_eeprom_getword(sc, addr, dest)
402 struct dc_softc *sc;
403 int addr;
404 u_int16_t *dest;
405 {
406 int i;
407 u_int16_t word = 0;
408
409 /* Force EEPROM to idle state. */
410 dc_eeprom_idle(sc);
411
412 /* Enter EEPROM access mode. */
413 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
414 dc_delay(sc);
415 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
416 dc_delay(sc);
417 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
418 dc_delay(sc);
419 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
420 dc_delay(sc);
421
422 /*
423 * Send address of word we want to read.
424 */
425 dc_eeprom_putbyte(sc, addr);
426
427 /*
428 * Start reading bits from EEPROM.
429 */
430 for (i = 0x8000; i; i >>= 1) {
431 SIO_SET(DC_SIO_EE_CLK);
432 dc_delay(sc);
433 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)
434 word |= i;
435 dc_delay(sc);
436 SIO_CLR(DC_SIO_EE_CLK);
437 dc_delay(sc);
438 }
439
440 /* Turn off EEPROM access mode. */
441 dc_eeprom_idle(sc);
442
443 *dest = word;
444 }
445
446 /*
447 * Read a sequence of words from the EEPROM.
448 */
dc_read_eeprom(sc,dest,off,cnt,swap)449 void dc_read_eeprom(sc, dest, off, cnt, swap)
450 struct dc_softc *sc;
451 caddr_t dest;
452 int off, cnt, swap;
453 {
454 int i;
455 u_int16_t word = 0, *ptr;
456
457 for (i = 0; i < cnt; i++) {
458 if (DC_IS_PNIC(sc))
459 dc_eeprom_getword_pnic(sc, off + i, &word);
460 else if (DC_IS_XIRCOM(sc))
461 dc_eeprom_getword_xircom(sc, off + i, &word);
462 else
463 dc_eeprom_getword(sc, off + i, &word);
464 ptr = (u_int16_t *)(dest + (i * 2));
465 if (swap)
466 *ptr = betoh16(word);
467 else
468 *ptr = letoh16(word);
469 }
470 }
471
472 /*
473 * The following two routines are taken from the Macronix 98713
474 * Application Notes pp.19-21.
475 */
476 /*
477 * Write a bit to the MII bus.
478 */
479 void
dc_mii_writebit(sc,bit)480 dc_mii_writebit(sc, bit)
481 struct dc_softc *sc;
482 int bit;
483 {
484 if (bit)
485 CSR_WRITE_4(sc, DC_SIO,
486 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT);
487 else
488 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
489
490 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK);
491 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK);
492 }
493
494 /*
495 * Read a bit from the MII bus.
496 */
497 int
dc_mii_readbit(sc)498 dc_mii_readbit(sc)
499 struct dc_softc *sc;
500 {
501 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR);
502 CSR_READ_4(sc, DC_SIO);
503 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK);
504 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK);
505 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN)
506 return (1);
507 return (0);
508 }
509
510 /*
511 * Sync the PHYs by setting data bit and strobing the clock 32 times.
512 */
513 void
dc_mii_sync(sc)514 dc_mii_sync(sc)
515 struct dc_softc *sc;
516 {
517 int i;
518
519 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
520
521 for (i = 0; i < 32; i++)
522 dc_mii_writebit(sc, 1);
523 }
524
525 /*
526 * Clock a series of bits through the MII.
527 */
528 void
dc_mii_send(sc,bits,cnt)529 dc_mii_send(sc, bits, cnt)
530 struct dc_softc *sc;
531 u_int32_t bits;
532 int cnt;
533 {
534 int i;
535
536 for (i = (0x1 << (cnt - 1)); i; i >>= 1)
537 dc_mii_writebit(sc, bits & i);
538 }
539
540 /*
541 * Read an PHY register through the MII.
542 */
543 int
dc_mii_readreg(sc,frame)544 dc_mii_readreg(sc, frame)
545 struct dc_softc *sc;
546 struct dc_mii_frame *frame;
547 {
548 int i, ack, s;
549
550 s = splimp();
551
552 /*
553 * Set up frame for RX.
554 */
555 frame->mii_stdelim = DC_MII_STARTDELIM;
556 frame->mii_opcode = DC_MII_READOP;
557 frame->mii_turnaround = 0;
558 frame->mii_data = 0;
559
560 /*
561 * Sync the PHYs.
562 */
563 dc_mii_sync(sc);
564
565 /*
566 * Send command/address info.
567 */
568 dc_mii_send(sc, frame->mii_stdelim, 2);
569 dc_mii_send(sc, frame->mii_opcode, 2);
570 dc_mii_send(sc, frame->mii_phyaddr, 5);
571 dc_mii_send(sc, frame->mii_regaddr, 5);
572
573 #ifdef notdef
574 /* Idle bit */
575 dc_mii_writebit(sc, 1);
576 dc_mii_writebit(sc, 0);
577 #endif
578
579 /* Check for ack */
580 ack = dc_mii_readbit(sc);
581
582 /*
583 * Now try reading data bits. If the ack failed, we still
584 * need to clock through 16 cycles to keep the PHY(s) in sync.
585 */
586 if (ack) {
587 for(i = 0; i < 16; i++) {
588 dc_mii_readbit(sc);
589 }
590 goto fail;
591 }
592
593 for (i = 0x8000; i; i >>= 1) {
594 if (!ack) {
595 if (dc_mii_readbit(sc))
596 frame->mii_data |= i;
597 }
598 }
599
600 fail:
601
602 dc_mii_writebit(sc, 0);
603 dc_mii_writebit(sc, 0);
604
605 splx(s);
606
607 if (ack)
608 return (1);
609 return (0);
610 }
611
612 /*
613 * Write to a PHY register through the MII.
614 */
615 int
dc_mii_writereg(sc,frame)616 dc_mii_writereg(sc, frame)
617 struct dc_softc *sc;
618 struct dc_mii_frame *frame;
619 {
620 int s;
621
622 s = splimp();
623 /*
624 * Set up frame for TX.
625 */
626
627 frame->mii_stdelim = DC_MII_STARTDELIM;
628 frame->mii_opcode = DC_MII_WRITEOP;
629 frame->mii_turnaround = DC_MII_TURNAROUND;
630
631 /*
632 * Sync the PHYs.
633 */
634 dc_mii_sync(sc);
635
636 dc_mii_send(sc, frame->mii_stdelim, 2);
637 dc_mii_send(sc, frame->mii_opcode, 2);
638 dc_mii_send(sc, frame->mii_phyaddr, 5);
639 dc_mii_send(sc, frame->mii_regaddr, 5);
640 dc_mii_send(sc, frame->mii_turnaround, 2);
641 dc_mii_send(sc, frame->mii_data, 16);
642
643 /* Idle bit. */
644 dc_mii_writebit(sc, 0);
645 dc_mii_writebit(sc, 0);
646
647 splx(s);
648 return (0);
649 }
650
651 int
dc_miibus_readreg(self,phy,reg)652 dc_miibus_readreg(self, phy, reg)
653 struct device *self;
654 int phy, reg;
655 {
656 struct dc_mii_frame frame;
657 struct dc_softc *sc = (struct dc_softc *)self;
658 int i, rval, phy_reg;
659
660 /*
661 * Note: both the AL981 and AN983 have internal PHYs,
662 * however the AL981 provides direct access to the PHY
663 * registers while the AN983 uses a serial MII interface.
664 * The AN983's MII interface is also buggy in that you
665 * can read from any MII address (0 to 31), but only address 1
666 * behaves normally. To deal with both cases, we pretend
667 * that the PHY is at MII address 1.
668 */
669 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
670 return (0);
671
672 /*
673 * Note: the ukphy probs of the RS7112 report a PHY at
674 * MII address 0 (possibly HomePNA?) and 1 (ethernet)
675 * so we only respond to correct one.
676 */
677 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
678 return (0);
679
680 if (sc->dc_pmode != DC_PMODE_MII) {
681 if (phy == (MII_NPHY - 1)) {
682 switch(reg) {
683 case MII_BMSR:
684 /*
685 * Fake something to make the probe
686 * code think there's a PHY here.
687 */
688 return (BMSR_MEDIAMASK);
689 break;
690 case MII_PHYIDR1:
691 if (DC_IS_PNIC(sc))
692 return (PCI_VENDOR_LITEON);
693 return (PCI_VENDOR_DEC);
694 break;
695 case MII_PHYIDR2:
696 if (DC_IS_PNIC(sc))
697 return (PCI_PRODUCT_LITEON_PNIC);
698 return (PCI_PRODUCT_DEC_21142);
699 break;
700 default:
701 return (0);
702 break;
703 }
704 } else
705 return (0);
706 }
707
708 if (DC_IS_PNIC(sc)) {
709 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ |
710 (phy << 23) | (reg << 18));
711 for (i = 0; i < DC_TIMEOUT; i++) {
712 DELAY(1);
713 rval = CSR_READ_4(sc, DC_PN_MII);
714 if (!(rval & DC_PN_MII_BUSY)) {
715 rval &= 0xFFFF;
716 return (rval == 0xFFFF ? 0 : rval);
717 }
718 }
719 return (0);
720 }
721
722 if (DC_IS_COMET(sc)) {
723 switch(reg) {
724 case MII_BMCR:
725 phy_reg = DC_AL_BMCR;
726 break;
727 case MII_BMSR:
728 phy_reg = DC_AL_BMSR;
729 break;
730 case MII_PHYIDR1:
731 phy_reg = DC_AL_VENID;
732 break;
733 case MII_PHYIDR2:
734 phy_reg = DC_AL_DEVID;
735 break;
736 case MII_ANAR:
737 phy_reg = DC_AL_ANAR;
738 break;
739 case MII_ANLPAR:
740 phy_reg = DC_AL_LPAR;
741 break;
742 case MII_ANER:
743 phy_reg = DC_AL_ANER;
744 break;
745 default:
746 printf("%s: phy_read: bad phy register %x\n",
747 sc->sc_dev.dv_xname, reg);
748 return (0);
749 break;
750 }
751
752 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF;
753
754 if (rval == 0xFFFF)
755 return (0);
756 return (rval);
757 }
758
759 bzero(&frame, sizeof(frame));
760
761 frame.mii_phyaddr = phy;
762 frame.mii_regaddr = reg;
763 if (sc->dc_type == DC_TYPE_98713) {
764 phy_reg = CSR_READ_4(sc, DC_NETCFG);
765 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
766 }
767 dc_mii_readreg(sc, &frame);
768 if (sc->dc_type == DC_TYPE_98713)
769 CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
770
771 return (frame.mii_data);
772 }
773
774 void
dc_miibus_writereg(self,phy,reg,data)775 dc_miibus_writereg(self, phy, reg, data)
776 struct device *self;
777 int phy, reg, data;
778 {
779 struct dc_softc *sc = (struct dc_softc *)self;
780 struct dc_mii_frame frame;
781 int i, phy_reg;
782
783 bzero((char *)&frame, sizeof(frame));
784
785 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
786 return;
787 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
788 return;
789
790 if (DC_IS_PNIC(sc)) {
791 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE |
792 (phy << 23) | (reg << 10) | data);
793 for (i = 0; i < DC_TIMEOUT; i++) {
794 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY))
795 break;
796 }
797 return;
798 }
799
800 if (DC_IS_COMET(sc)) {
801 switch(reg) {
802 case MII_BMCR:
803 phy_reg = DC_AL_BMCR;
804 break;
805 case MII_BMSR:
806 phy_reg = DC_AL_BMSR;
807 break;
808 case MII_PHYIDR1:
809 phy_reg = DC_AL_VENID;
810 break;
811 case MII_PHYIDR2:
812 phy_reg = DC_AL_DEVID;
813 break;
814 case MII_ANAR:
815 phy_reg = DC_AL_ANAR;
816 break;
817 case MII_ANLPAR:
818 phy_reg = DC_AL_LPAR;
819 break;
820 case MII_ANER:
821 phy_reg = DC_AL_ANER;
822 break;
823 default:
824 printf("%s: phy_write: bad phy register %x\n",
825 sc->sc_dev.dv_xname, reg);
826 return;
827 break;
828 }
829
830 CSR_WRITE_4(sc, phy_reg, data);
831 return;
832 }
833
834 frame.mii_phyaddr = phy;
835 frame.mii_regaddr = reg;
836 frame.mii_data = data;
837
838 if (sc->dc_type == DC_TYPE_98713) {
839 phy_reg = CSR_READ_4(sc, DC_NETCFG);
840 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
841 }
842 dc_mii_writereg(sc, &frame);
843 if (sc->dc_type == DC_TYPE_98713)
844 CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
845 }
846
847 void
dc_miibus_statchg(self)848 dc_miibus_statchg(self)
849 struct device *self;
850 {
851 struct dc_softc *sc = (struct dc_softc *)self;
852 struct mii_data *mii;
853 struct ifmedia *ifm;
854
855 if (DC_IS_ADMTEK(sc))
856 return;
857
858 mii = &sc->sc_mii;
859 ifm = &mii->mii_media;
860 if (DC_IS_DAVICOM(sc) && IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) {
861 dc_setcfg(sc, ifm->ifm_media);
862 sc->dc_if_media = ifm->ifm_media;
863 } else {
864 dc_setcfg(sc, mii->mii_media_active);
865 sc->dc_if_media = mii->mii_media_active;
866 }
867 }
868
869 #define DC_BITS_512 9
870 #define DC_BITS_128 7
871 #define DC_BITS_64 6
872
873 u_int32_t
dc_crc_le(sc,addr)874 dc_crc_le(sc, addr)
875 struct dc_softc *sc;
876 caddr_t addr;
877 {
878 u_int32_t crc;
879
880 /* Compute CRC for the address value. */
881 crc = ether_crc32_le(addr, ETHER_ADDR_LEN);
882
883 /*
884 * The hash table on the PNIC II and the MX98715AEC-C/D/E
885 * chips is only 128 bits wide.
886 */
887 if (sc->dc_flags & DC_128BIT_HASH)
888 return (crc & ((1 << DC_BITS_128) - 1));
889
890 /* The hash table on the MX98715BEC is only 64 bits wide. */
891 if (sc->dc_flags & DC_64BIT_HASH)
892 return (crc & ((1 << DC_BITS_64) - 1));
893
894 /* Xircom's hash filtering table is different (read: weird) */
895 /* Xircom uses the LEAST significant bits */
896 if (DC_IS_XIRCOM(sc)) {
897 if ((crc & 0x180) == 0x180)
898 return (crc & 0x0F) + (crc & 0x70)*3 + (14 << 4);
899 else
900 return (crc & 0x1F) + ((crc>>1) & 0xF0)*3 + (12 << 4);
901 }
902
903 return (crc & ((1 << DC_BITS_512) - 1));
904 }
905
906 /*
907 * Calculate CRC of a multicast group address, return the lower 6 bits.
908 */
909 #define dc_crc_be(addr) ((ether_crc32_be(addr,ETHER_ADDR_LEN) >> 26) \
910 & 0x0000003F)
911
912 /*
913 * 21143-style RX filter setup routine. Filter programming is done by
914 * downloading a special setup frame into the TX engine. 21143, Macronix,
915 * PNIC, PNIC II and Davicom chips are programmed this way.
916 *
917 * We always program the chip using 'hash perfect' mode, i.e. one perfect
918 * address (our node address) and a 512-bit hash filter for multicast
919 * frames. We also sneak the broadcast address into the hash filter since
920 * we need that too.
921 */
922 void
dc_setfilt_21143(sc)923 dc_setfilt_21143(sc)
924 struct dc_softc *sc;
925 {
926 struct dc_desc *sframe;
927 u_int32_t h, *sp;
928 struct arpcom *ac = &sc->sc_arpcom;
929 struct ether_multi *enm;
930 struct ether_multistep step;
931 struct ifnet *ifp;
932 int i;
933
934 ifp = &sc->sc_arpcom.ac_if;
935
936 i = sc->dc_cdata.dc_tx_prod;
937 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
938 sc->dc_cdata.dc_tx_cnt++;
939 sframe = &sc->dc_ldata->dc_tx_list[i];
940 sp = &sc->dc_ldata->dc_sbuf[0];
941 bzero((char *)sp, DC_SFRAME_LEN);
942
943 sframe->dc_data = htole32(sc->sc_listmap->dm_segs[0].ds_addr +
944 offsetof(struct dc_list_data, dc_sbuf));
945 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP |
946 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT);
947
948 sc->dc_cdata.dc_tx_chain[i].sd_mbuf =
949 (struct mbuf *)&sc->dc_ldata->dc_sbuf[0];
950
951 /* If we want promiscuous mode, set the allframes bit. */
952 if (ifp->if_flags & IFF_PROMISC)
953 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
954 else
955 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
956
957 allmulti:
958 if (ifp->if_flags & IFF_ALLMULTI)
959 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
960 else {
961 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
962
963 ETHER_FIRST_MULTI(step, ac, enm);
964 while (enm != NULL) {
965 if (bcmp(enm->enm_addrlo, enm->enm_addrhi,
966 ETHER_ADDR_LEN)) {
967 ifp->if_flags |= IFF_ALLMULTI;
968 goto allmulti;
969 }
970
971 h = dc_crc_le(sc, enm->enm_addrlo);
972 sp[h >> 4] |= htole32(1 << (h & 0xF));
973 ETHER_NEXT_MULTI(step, enm);
974 }
975 }
976
977 if (ifp->if_flags & IFF_BROADCAST) {
978 h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr);
979 sp[h >> 4] |= htole32(1 << (h & 0xF));
980 }
981
982 /* Set our MAC address */
983 sp[39] = DC_SP_FIELD(sc->sc_arpcom.ac_enaddr, 0);
984 sp[40] = DC_SP_FIELD(sc->sc_arpcom.ac_enaddr, 1);
985 sp[41] = DC_SP_FIELD(sc->sc_arpcom.ac_enaddr, 2);
986
987 bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap,
988 offsetof(struct dc_list_data, dc_sbuf[0]),
989 sizeof(struct dc_list_data) -
990 offsetof(struct dc_list_data, dc_sbuf[0]),
991 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
992
993 sframe->dc_status = htole32(DC_TXSTAT_OWN);
994
995 bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap,
996 offsetof(struct dc_list_data, dc_tx_list[i]),
997 sizeof(struct dc_desc), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
998
999 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1000
1001 /*
1002 * The PNIC takes an exceedingly long time to process its
1003 * setup frame; wait 10ms after posting the setup frame
1004 * before proceeding, just so it has time to swallow its
1005 * medicine.
1006 */
1007 DELAY(10000);
1008
1009 ifp->if_timer = 5;
1010 }
1011
1012 void
dc_setfilt_admtek(sc)1013 dc_setfilt_admtek(sc)
1014 struct dc_softc *sc;
1015 {
1016 struct ifnet *ifp;
1017 struct arpcom *ac = &sc->sc_arpcom;
1018 struct ether_multi *enm;
1019 struct ether_multistep step;
1020 int h = 0;
1021 u_int32_t hashes[2] = { 0, 0 };
1022
1023 ifp = &sc->sc_arpcom.ac_if;
1024
1025 /* Init our MAC address */
1026 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->sc_arpcom.ac_enaddr[0]));
1027 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->sc_arpcom.ac_enaddr[4]));
1028
1029 /* If we want promiscuous mode, set the allframes bit. */
1030 if (ifp->if_flags & IFF_PROMISC)
1031 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1032 else
1033 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1034
1035 allmulti:
1036 if (ifp->if_flags & IFF_ALLMULTI)
1037 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1038 else
1039 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1040
1041 /* first, zot all the existing hash bits */
1042 CSR_WRITE_4(sc, DC_AL_MAR0, 0);
1043 CSR_WRITE_4(sc, DC_AL_MAR1, 0);
1044
1045 /*
1046 * If we're already in promisc or allmulti mode, we
1047 * don't have to bother programming the multicast filter.
1048 */
1049 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI))
1050 return;
1051
1052 /* now program new ones */
1053 ETHER_FIRST_MULTI(step, ac, enm);
1054 while (enm != NULL) {
1055 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
1056 ifp->if_flags |= IFF_ALLMULTI;
1057 goto allmulti;
1058 }
1059
1060 if (DC_IS_CENTAUR(sc))
1061 h = dc_crc_le(sc, enm->enm_addrlo);
1062 else
1063 h = dc_crc_be(enm->enm_addrlo);
1064 if (h < 32)
1065 hashes[0] |= (1 << h);
1066 else
1067 hashes[1] |= (1 << (h - 32));
1068 ETHER_NEXT_MULTI(step, enm);
1069 }
1070
1071 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]);
1072 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]);
1073 }
1074
1075 void
dc_setfilt_asix(sc)1076 dc_setfilt_asix(sc)
1077 struct dc_softc *sc;
1078 {
1079 struct ifnet *ifp;
1080 struct arpcom *ac = &sc->sc_arpcom;
1081 struct ether_multi *enm;
1082 struct ether_multistep step;
1083 int h = 0;
1084 u_int32_t hashes[2] = { 0, 0 };
1085
1086 ifp = &sc->sc_arpcom.ac_if;
1087
1088 /* Init our MAC address */
1089 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0);
1090 CSR_WRITE_4(sc, DC_AX_FILTDATA,
1091 *(u_int32_t *)(&sc->sc_arpcom.ac_enaddr[0]));
1092 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1);
1093 CSR_WRITE_4(sc, DC_AX_FILTDATA,
1094 *(u_int32_t *)(&sc->sc_arpcom.ac_enaddr[4]));
1095
1096 /* If we want promiscuous mode, set the allframes bit. */
1097 if (ifp->if_flags & IFF_PROMISC)
1098 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1099 else
1100 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1101
1102 if (ifp->if_flags & IFF_ALLMULTI)
1103 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1104 else
1105 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1106
1107 /*
1108 * The ASIX chip has a special bit to enable reception
1109 * of broadcast frames.
1110 */
1111 if (ifp->if_flags & IFF_BROADCAST)
1112 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1113 else
1114 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1115
1116 /* first, zot all the existing hash bits */
1117 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1118 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1119 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1120 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1121
1122 /*
1123 * If we're already in promisc or allmulti mode, we
1124 * don't have to bother programming the multicast filter.
1125 */
1126 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI))
1127 return;
1128
1129 /* now program new ones */
1130 ETHER_FIRST_MULTI(step, ac, enm);
1131 while (enm != NULL) {
1132 h = dc_crc_be(enm->enm_addrlo);
1133 if (h < 32)
1134 hashes[0] |= (1 << h);
1135 else
1136 hashes[1] |= (1 << (h - 32));
1137 ETHER_NEXT_MULTI(step, enm);
1138 }
1139
1140 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1141 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]);
1142 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1143 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]);
1144 }
1145
1146 void
dc_setfilt_xircom(sc)1147 dc_setfilt_xircom(sc)
1148 struct dc_softc *sc;
1149 {
1150 struct dc_desc *sframe;
1151 struct arpcom *ac = &sc->sc_arpcom;
1152 struct ether_multi *enm;
1153 struct ether_multistep step;
1154 u_int32_t h, *sp;
1155 struct ifnet *ifp;
1156 int i;
1157
1158 ifp = &sc->sc_arpcom.ac_if;
1159 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON));
1160
1161 i = sc->dc_cdata.dc_tx_prod;
1162 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
1163 sc->dc_cdata.dc_tx_cnt++;
1164 sframe = &sc->dc_ldata->dc_tx_list[i];
1165 sp = &sc->dc_ldata->dc_sbuf[0];
1166 bzero((char *)sp, DC_SFRAME_LEN);
1167
1168 sframe->dc_data = htole32(sc->sc_listmap->dm_segs[0].ds_addr +
1169 offsetof(struct dc_list_data, dc_sbuf));
1170 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP |
1171 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT);
1172
1173 sc->dc_cdata.dc_tx_chain[i].sd_mbuf =
1174 (struct mbuf *)&sc->dc_ldata->dc_sbuf[0];
1175
1176 /* If we want promiscuous mode, set the allframes bit. */
1177 if (ifp->if_flags & IFF_PROMISC)
1178 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1179 else
1180 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1181
1182 if (ifp->if_flags & IFF_ALLMULTI)
1183 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1184 else
1185 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1186
1187 /* now program new ones */
1188 ETHER_FIRST_MULTI(step, ac, enm);
1189 while (enm != NULL) {
1190 h = dc_crc_le(sc, enm->enm_addrlo);
1191 sp[h >> 4] |= htole32(1 << (h & 0xF));
1192 ETHER_NEXT_MULTI(step, enm);
1193 }
1194
1195 if (ifp->if_flags & IFF_BROADCAST) {
1196 h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr);
1197 sp[h >> 4] |= htole32(1 << (h & 0xF));
1198 }
1199
1200 /* Set our MAC address */
1201 sp[0] = DC_SP_FIELD(sc->sc_arpcom.ac_enaddr, 0);
1202 sp[1] = DC_SP_FIELD(sc->sc_arpcom.ac_enaddr, 1);
1203 sp[2] = DC_SP_FIELD(sc->sc_arpcom.ac_enaddr, 2);
1204
1205 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
1206 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
1207 ifp->if_flags |= IFF_RUNNING;
1208 sframe->dc_status = htole32(DC_TXSTAT_OWN);
1209 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1210
1211 /*
1212 * wait some time...
1213 */
1214 DELAY(1000);
1215
1216 ifp->if_timer = 5;
1217 }
1218
1219 void
dc_setfilt(sc)1220 dc_setfilt(sc)
1221 struct dc_softc *sc;
1222 {
1223 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) ||
1224 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc))
1225 dc_setfilt_21143(sc);
1226
1227 if (DC_IS_ASIX(sc))
1228 dc_setfilt_asix(sc);
1229
1230 if (DC_IS_ADMTEK(sc))
1231 dc_setfilt_admtek(sc);
1232
1233 if (DC_IS_XIRCOM(sc))
1234 dc_setfilt_xircom(sc);
1235 }
1236
1237 /*
1238 * In order to fiddle with the
1239 * 'full-duplex' and '100Mbps' bits in the netconfig register, we
1240 * first have to put the transmit and/or receive logic in the idle state.
1241 */
1242 void
dc_setcfg(sc,media)1243 dc_setcfg(sc, media)
1244 struct dc_softc *sc;
1245 int media;
1246 {
1247 int i, restart = 0;
1248 u_int32_t isr;
1249
1250 if (IFM_SUBTYPE(media) == IFM_NONE)
1251 return;
1252
1253 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) {
1254 restart = 1;
1255 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON));
1256
1257 for (i = 0; i < DC_TIMEOUT; i++) {
1258 isr = CSR_READ_4(sc, DC_ISR);
1259 if (isr & DC_ISR_TX_IDLE &&
1260 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED ||
1261 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT))
1262 break;
1263 DELAY(10);
1264 }
1265
1266 if (i == DC_TIMEOUT)
1267 printf("%s: failed to force tx and "
1268 "rx to idle state\n", sc->sc_dev.dv_xname);
1269 }
1270
1271 if (IFM_SUBTYPE(media) == IFM_100_TX) {
1272 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1273 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1274 if (sc->dc_pmode == DC_PMODE_MII) {
1275 int watchdogreg;
1276
1277 if (DC_IS_INTEL(sc)) {
1278 /* there's a write enable bit here that reads as 1 */
1279 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1280 watchdogreg &= ~DC_WDOG_CTLWREN;
1281 watchdogreg |= DC_WDOG_JABBERDIS;
1282 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1283 } else {
1284 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1285 }
1286 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS|
1287 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER));
1288 if (sc->dc_type == DC_TYPE_98713)
1289 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS|
1290 DC_NETCFG_SCRAMBLER));
1291 if (!DC_IS_DAVICOM(sc))
1292 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1293 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1294 if (DC_IS_INTEL(sc))
1295 dc_apply_fixup(sc, IFM_AUTO);
1296 } else {
1297 if (DC_IS_PNIC(sc)) {
1298 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL);
1299 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1300 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1301 }
1302 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1303 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1304 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1305 if (DC_IS_INTEL(sc))
1306 dc_apply_fixup(sc,
1307 (media & IFM_GMASK) == IFM_FDX ?
1308 IFM_100_TX|IFM_FDX : IFM_100_TX);
1309 }
1310 }
1311
1312 if (IFM_SUBTYPE(media) == IFM_10_T) {
1313 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1314 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1315 if (sc->dc_pmode == DC_PMODE_MII) {
1316 int watchdogreg;
1317
1318 if (DC_IS_INTEL(sc)) {
1319 /* there's a write enable bit here that reads as 1 */
1320 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1321 watchdogreg &= ~DC_WDOG_CTLWREN;
1322 watchdogreg |= DC_WDOG_JABBERDIS;
1323 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1324 } else {
1325 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1326 }
1327 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS|
1328 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER));
1329 if (sc->dc_type == DC_TYPE_98713)
1330 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1331 if (!DC_IS_DAVICOM(sc))
1332 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1333 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1334 if (DC_IS_INTEL(sc))
1335 dc_apply_fixup(sc, IFM_AUTO);
1336 } else {
1337 if (DC_IS_PNIC(sc)) {
1338 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL);
1339 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1340 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1341 }
1342 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1343 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1344 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1345 if (DC_IS_INTEL(sc)) {
1346 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET);
1347 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1348 if ((media & IFM_GMASK) == IFM_FDX)
1349 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D);
1350 else
1351 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F);
1352 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1353 DC_CLRBIT(sc, DC_10BTCTRL,
1354 DC_TCTL_AUTONEGENBL);
1355 dc_apply_fixup(sc,
1356 (media & IFM_GMASK) == IFM_FDX ?
1357 IFM_10_T|IFM_FDX : IFM_10_T);
1358 DELAY(20000);
1359 }
1360 }
1361 }
1362
1363 /*
1364 * If this is a Davicom DM9102A card with a DM9801 HomePNA
1365 * PHY and we want HomePNA mode, set the portsel bit to turn
1366 * on the external MII port.
1367 */
1368 if (DC_IS_DAVICOM(sc)) {
1369 if (IFM_SUBTYPE(media) == IFM_HPNA_1) {
1370 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1371 sc->dc_link = 1;
1372 } else {
1373 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1374 }
1375 }
1376
1377 if ((media & IFM_GMASK) == IFM_FDX) {
1378 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1379 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1380 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1381 } else {
1382 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1383 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1384 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1385 }
1386
1387 if (restart)
1388 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON);
1389 }
1390
1391 void
dc_reset(sc)1392 dc_reset(sc)
1393 struct dc_softc *sc;
1394 {
1395 int i;
1396
1397 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1398
1399 for (i = 0; i < DC_TIMEOUT; i++) {
1400 DELAY(10);
1401 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET))
1402 break;
1403 }
1404
1405 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_XIRCOM(sc) ||
1406 DC_IS_INTEL(sc) || DC_IS_CONEXANT(sc)) {
1407 DELAY(10000);
1408 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1409 i = 0;
1410 }
1411
1412 if (i == DC_TIMEOUT)
1413 printf("%s: reset never completed!\n", sc->sc_dev.dv_xname);
1414
1415 /* Wait a little while for the chip to get its brains in order. */
1416 DELAY(1000);
1417
1418 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
1419 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000);
1420 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000);
1421
1422 /*
1423 * Bring the SIA out of reset. In some cases, it looks
1424 * like failing to unreset the SIA soon enough gets it
1425 * into a state where it will never come out of reset
1426 * until we reset the whole chip again.
1427 */
1428 if (DC_IS_INTEL(sc)) {
1429 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1430 CSR_WRITE_4(sc, DC_10BTCTRL, 0);
1431 CSR_WRITE_4(sc, DC_WATCHDOG, 0);
1432 }
1433
1434 if (sc->dc_type == DC_TYPE_21145)
1435 dc_setcfg(sc, IFM_10_T);
1436 }
1437
1438 void
dc_apply_fixup(sc,media)1439 dc_apply_fixup(sc, media)
1440 struct dc_softc *sc;
1441 int media;
1442 {
1443 struct dc_mediainfo *m;
1444 u_int8_t *p;
1445 int i;
1446 u_int32_t reg;
1447
1448 m = sc->dc_mi;
1449
1450 while (m != NULL) {
1451 if (m->dc_media == media)
1452 break;
1453 m = m->dc_next;
1454 }
1455
1456 if (m == NULL)
1457 return;
1458
1459 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) {
1460 reg = (p[0] | (p[1] << 8)) << 16;
1461 CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1462 }
1463
1464 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) {
1465 reg = (p[0] | (p[1] << 8)) << 16;
1466 CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1467 }
1468 }
1469
1470 void
dc_decode_leaf_sia(sc,l)1471 dc_decode_leaf_sia(sc, l)
1472 struct dc_softc *sc;
1473 struct dc_eblock_sia *l;
1474 {
1475 struct dc_mediainfo *m;
1476
1477 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT);
1478 if (m == NULL)
1479 return;
1480 bzero(m, sizeof(struct dc_mediainfo));
1481 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) {
1482 case DC_SIA_CODE_10BT:
1483 m->dc_media = IFM_10_T;
1484 break;
1485 case DC_SIA_CODE_10BT_FDX:
1486 m->dc_media = IFM_10_T|IFM_FDX;
1487 break;
1488 case DC_SIA_CODE_10B2:
1489 m->dc_media = IFM_10_2;
1490 break;
1491 case DC_SIA_CODE_10B5:
1492 m->dc_media = IFM_10_5;
1493 break;
1494 default:
1495 break;
1496 }
1497
1498 /*
1499 * We need to ignore CSR13, CSR14, CSR15 for SIA mode.
1500 * Things apparently already work for cards that do
1501 * supply Media Specific Data.
1502 */
1503 if (l->dc_sia_code & DC_SIA_CODE_EXT) {
1504 m->dc_gp_len = 2;
1505 m->dc_gp_ptr =
1506 (u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl;
1507 } else {
1508 m->dc_gp_len = 2;
1509 m->dc_gp_ptr =
1510 (u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl;
1511 }
1512
1513 m->dc_next = sc->dc_mi;
1514 sc->dc_mi = m;
1515
1516 sc->dc_pmode = DC_PMODE_SIA;
1517 }
1518
1519 void
dc_decode_leaf_sym(sc,l)1520 dc_decode_leaf_sym(sc, l)
1521 struct dc_softc *sc;
1522 struct dc_eblock_sym *l;
1523 {
1524 struct dc_mediainfo *m;
1525
1526 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT);
1527 if (m == NULL)
1528 return;
1529 bzero(m, sizeof(struct dc_mediainfo));
1530 if (l->dc_sym_code == DC_SYM_CODE_100BT)
1531 m->dc_media = IFM_100_TX;
1532
1533 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX)
1534 m->dc_media = IFM_100_TX|IFM_FDX;
1535
1536 m->dc_gp_len = 2;
1537 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl;
1538
1539 m->dc_next = sc->dc_mi;
1540 sc->dc_mi = m;
1541
1542 sc->dc_pmode = DC_PMODE_SYM;
1543 }
1544
1545 void
dc_decode_leaf_mii(sc,l)1546 dc_decode_leaf_mii(sc, l)
1547 struct dc_softc *sc;
1548 struct dc_eblock_mii *l;
1549 {
1550 u_int8_t *p;
1551 struct dc_mediainfo *m;
1552
1553 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT);
1554 if (m == NULL)
1555 return;
1556 bzero(m, sizeof(struct dc_mediainfo));
1557 /* We abuse IFM_AUTO to represent MII. */
1558 m->dc_media = IFM_AUTO;
1559 m->dc_gp_len = l->dc_gpr_len;
1560
1561 p = (u_int8_t *)l;
1562 p += sizeof(struct dc_eblock_mii);
1563 m->dc_gp_ptr = p;
1564 p += 2 * l->dc_gpr_len;
1565 m->dc_reset_len = *p;
1566 p++;
1567 m->dc_reset_ptr = p;
1568
1569 m->dc_next = sc->dc_mi;
1570 sc->dc_mi = m;
1571 }
1572
1573 void
dc_read_srom(sc,bits)1574 dc_read_srom(sc, bits)
1575 struct dc_softc *sc;
1576 int bits;
1577 {
1578 int size;
1579
1580 size = 2 << bits;
1581 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT);
1582 if (sc->dc_srom == NULL)
1583 return;
1584 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0);
1585 }
1586
1587 void
dc_parse_21143_srom(sc)1588 dc_parse_21143_srom(sc)
1589 struct dc_softc *sc;
1590 {
1591 struct dc_leaf_hdr *lhdr;
1592 struct dc_eblock_hdr *hdr;
1593 int have_mii, i, loff;
1594 char *ptr;
1595
1596 have_mii = 0;
1597 loff = sc->dc_srom[27];
1598 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]);
1599
1600 ptr = (char *)lhdr;
1601 ptr += sizeof(struct dc_leaf_hdr) - 1;
1602 /*
1603 * Look if we got a MII media block.
1604 */
1605 for (i = 0; i < lhdr->dc_mcnt; i++) {
1606 hdr = (struct dc_eblock_hdr *)ptr;
1607 if (hdr->dc_type == DC_EBLOCK_MII)
1608 have_mii++;
1609
1610 ptr += (hdr->dc_len & 0x7F);
1611 ptr++;
1612 }
1613
1614 /*
1615 * Do the same thing again. Only use SIA and SYM media
1616 * blocks if no MII media block is available.
1617 */
1618 ptr = (char *)lhdr;
1619 ptr += sizeof(struct dc_leaf_hdr) - 1;
1620 for (i = 0; i < lhdr->dc_mcnt; i++) {
1621 hdr = (struct dc_eblock_hdr *)ptr;
1622 switch(hdr->dc_type) {
1623 case DC_EBLOCK_MII:
1624 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr);
1625 break;
1626 case DC_EBLOCK_SIA:
1627 if (! have_mii)
1628 dc_decode_leaf_sia(sc,
1629 (struct dc_eblock_sia *)hdr);
1630 break;
1631 case DC_EBLOCK_SYM:
1632 if (! have_mii)
1633 dc_decode_leaf_sym(sc,
1634 (struct dc_eblock_sym *)hdr);
1635 break;
1636 default:
1637 /* Don't care. Yet. */
1638 break;
1639 }
1640 ptr += (hdr->dc_len & 0x7F);
1641 ptr++;
1642 }
1643 }
1644
1645 /*
1646 * Attach the interface. Allocate softc structures, do ifmedia
1647 * setup and ethernet/BPF attach.
1648 */
1649 void
dc_attach(sc)1650 dc_attach(sc)
1651 struct dc_softc *sc;
1652 {
1653 struct ifnet *ifp;
1654 int mac_offset, tmp, i;
1655
1656 /*
1657 * Get station address from the EEPROM.
1658 */
1659 if (sc->sc_hasmac)
1660 goto hasmac;
1661
1662 switch(sc->dc_type) {
1663 case DC_TYPE_98713:
1664 case DC_TYPE_98713A:
1665 case DC_TYPE_987x5:
1666 case DC_TYPE_PNICII:
1667 dc_read_eeprom(sc, (caddr_t)&mac_offset,
1668 (DC_EE_NODEADDR_OFFSET / 2), 1, 0);
1669 dc_read_eeprom(sc, (caddr_t)&sc->sc_arpcom.ac_enaddr,
1670 (mac_offset / 2), 3, 0);
1671 break;
1672 case DC_TYPE_PNIC:
1673 dc_read_eeprom(sc, (caddr_t)&sc->sc_arpcom.ac_enaddr, 0, 3, 1);
1674 break;
1675 case DC_TYPE_DM9102:
1676 case DC_TYPE_21143:
1677 case DC_TYPE_21145:
1678 case DC_TYPE_ASIX:
1679 dc_read_eeprom(sc, (caddr_t)&sc->sc_arpcom.ac_enaddr,
1680 DC_EE_NODEADDR, 3, 0);
1681 break;
1682 case DC_TYPE_AL981:
1683 case DC_TYPE_AN983:
1684 *(u_int32_t *)(&sc->sc_arpcom.ac_enaddr[0]) =
1685 CSR_READ_4(sc, DC_AL_PAR0);
1686 *(u_int16_t *)(&sc->sc_arpcom.ac_enaddr[4]) =
1687 CSR_READ_4(sc, DC_AL_PAR1);
1688 break;
1689 case DC_TYPE_CONEXANT:
1690 bcopy(&sc->dc_srom + DC_CONEXANT_EE_NODEADDR,
1691 &sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN);
1692 break;
1693 case DC_TYPE_XIRCOM:
1694 break;
1695 default:
1696 dc_read_eeprom(sc, (caddr_t)&sc->sc_arpcom.ac_enaddr,
1697 DC_EE_NODEADDR, 3, 0);
1698 break;
1699 }
1700 hasmac:
1701
1702 if (bus_dmamem_alloc(sc->sc_dmat, sizeof(struct dc_list_data),
1703 PAGE_SIZE, 0, sc->sc_listseg, 1, &sc->sc_listnseg,
1704 BUS_DMA_NOWAIT) != 0) {
1705 printf(": can't alloc list mem\n");
1706 goto fail;
1707 }
1708 if (bus_dmamem_map(sc->sc_dmat, sc->sc_listseg, sc->sc_listnseg,
1709 sizeof(struct dc_list_data), &sc->sc_listkva,
1710 BUS_DMA_NOWAIT) != 0) {
1711 printf(": can't map list mem\n");
1712 goto fail;
1713 }
1714 if (bus_dmamap_create(sc->sc_dmat, sizeof(struct dc_list_data), 1,
1715 sizeof(struct dc_list_data), 0, BUS_DMA_NOWAIT,
1716 &sc->sc_listmap) != 0) {
1717 printf(": can't alloc list map\n");
1718 goto fail;
1719 }
1720 if (bus_dmamap_load(sc->sc_dmat, sc->sc_listmap, sc->sc_listkva,
1721 sizeof(struct dc_list_data), NULL, BUS_DMA_NOWAIT) != 0) {
1722 printf(": can't load list map\n");
1723 goto fail;
1724 }
1725 sc->dc_ldata = (struct dc_list_data *)sc->sc_listkva;
1726 bzero(sc->dc_ldata, sizeof(struct dc_list_data));
1727
1728 for (i = 0; i < DC_RX_LIST_CNT; i++) {
1729 if (bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES,
1730 0, BUS_DMA_NOWAIT,
1731 &sc->dc_cdata.dc_rx_chain[i].sd_map) != 0) {
1732 printf(": can't create rx map\n");
1733 return;
1734 }
1735 }
1736 if (bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0,
1737 BUS_DMA_NOWAIT, &sc->sc_rx_sparemap) != 0) {
1738 printf(": can't create rx spare map\n");
1739 return;
1740 }
1741
1742 for (i = 0; i < DC_TX_LIST_CNT; i++) {
1743 if (bus_dmamap_create(sc->sc_dmat, MCLBYTES,
1744 DC_TX_LIST_CNT - 5, MCLBYTES, 0, BUS_DMA_NOWAIT,
1745 &sc->dc_cdata.dc_tx_chain[i].sd_map) != 0) {
1746 printf(": can't create tx map\n");
1747 return;
1748 }
1749 }
1750 if (bus_dmamap_create(sc->sc_dmat, MCLBYTES, DC_TX_LIST_CNT - 5,
1751 MCLBYTES, 0, BUS_DMA_NOWAIT, &sc->sc_tx_sparemap) != 0) {
1752 printf(": can't create tx spare map\n");
1753 return;
1754 }
1755
1756 /*
1757 * A 21143 or clone chip was detected. Inform the world.
1758 */
1759 printf(" address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr));
1760
1761 ifp = &sc->sc_arpcom.ac_if;
1762 ifp->if_softc = sc;
1763 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1764 ifp->if_ioctl = dc_ioctl;
1765 ifp->if_start = dc_start;
1766 ifp->if_watchdog = dc_watchdog;
1767 ifp->if_baudrate = 10000000;
1768 IFQ_SET_MAXLEN(&ifp->if_snd, DC_TX_LIST_CNT - 1);
1769 IFQ_SET_READY(&ifp->if_snd);
1770 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ);
1771
1772 ifp->if_capabilities = IFCAP_VLAN_MTU;
1773
1774 /* Do MII setup. If this is a 21143, check for a PHY on the
1775 * MII bus after applying any necessary fixups to twiddle the
1776 * GPIO bits. If we don't end up finding a PHY, restore the
1777 * old selection (SIA only or SIA/SYM) and attach the dcphy
1778 * driver instead.
1779 */
1780 if (DC_IS_INTEL(sc)) {
1781 dc_apply_fixup(sc, IFM_AUTO);
1782 tmp = sc->dc_pmode;
1783 sc->dc_pmode = DC_PMODE_MII;
1784 }
1785
1786 /*
1787 * Setup General Purpose port mode and data so the tulip can talk
1788 * to the MII. This needs to be done before mii_attach so that
1789 * we can actually see them.
1790 */
1791 if (DC_IS_XIRCOM(sc)) {
1792 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN |
1793 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
1794 DELAY(10);
1795 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN |
1796 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
1797 DELAY(10);
1798 }
1799
1800 sc->sc_mii.mii_ifp = ifp;
1801 sc->sc_mii.mii_readreg = dc_miibus_readreg;
1802 sc->sc_mii.mii_writereg = dc_miibus_writereg;
1803 sc->sc_mii.mii_statchg = dc_miibus_statchg;
1804 ifmedia_init(&sc->sc_mii.mii_media, 0, dc_ifmedia_upd, dc_ifmedia_sts);
1805 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
1806 MII_OFFSET_ANY, 0);
1807
1808 if (DC_IS_INTEL(sc)) {
1809 if (LIST_EMPTY(&sc->sc_mii.mii_phys)) {
1810 sc->dc_pmode = tmp;
1811 if (sc->dc_pmode != DC_PMODE_SIA)
1812 sc->dc_pmode = DC_PMODE_SYM;
1813 sc->dc_flags |= DC_21143_NWAY;
1814 if (sc->dc_flags & DC_MOMENCO_BOTCH)
1815 sc->dc_pmode = DC_PMODE_MII;
1816 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff,
1817 MII_PHY_ANY, MII_OFFSET_ANY, 0);
1818 } else {
1819 /* we have a PHY, so we must clear this bit */
1820 sc->dc_flags &= ~DC_TULIP_LEDS;
1821 }
1822 }
1823
1824 if (LIST_EMPTY(&sc->sc_mii.mii_phys)) {
1825 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL);
1826 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE);
1827 printf("%s: MII without any PHY!\n", sc->sc_dev.dv_xname);
1828 } else if (sc->dc_type == DC_TYPE_21145) {
1829 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_10_T);
1830 } else
1831 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
1832
1833 if (DC_IS_DAVICOM(sc) && sc->dc_revision >= DC_REVISION_DM9102A)
1834 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_HPNA_1,0,NULL);
1835
1836 if (DC_IS_ADMTEK(sc)) {
1837 /*
1838 * Set automatic TX underrun recovery for the ADMtek chips
1839 */
1840 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR);
1841 }
1842
1843 /*
1844 * Call MI attach routines.
1845 */
1846 if_attach(ifp);
1847 ether_ifattach(ifp);
1848
1849 sc->sc_dhook = shutdownhook_establish(dc_shutdown, sc);
1850 sc->sc_pwrhook = powerhook_establish(dc_power, sc);
1851
1852 fail:
1853 return;
1854 }
1855
1856 int
dc_detach(sc)1857 dc_detach(sc)
1858 struct dc_softc *sc;
1859 {
1860 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1861
1862 if (LIST_FIRST(&sc->sc_mii.mii_phys) != NULL)
1863 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY);
1864
1865 if (sc->dc_srom)
1866 free(sc->dc_srom, M_DEVBUF);
1867
1868 timeout_del(&sc->dc_tick_tmo);
1869
1870 ether_ifdetach(ifp);
1871 if_detach(ifp);
1872
1873 shutdownhook_disestablish(sc->sc_dhook);
1874 powerhook_disestablish(sc->sc_pwrhook);
1875
1876 return (0);
1877 }
1878
1879 /*
1880 * Initialize the transmit descriptors.
1881 */
1882 int
dc_list_tx_init(sc)1883 dc_list_tx_init(sc)
1884 struct dc_softc *sc;
1885 {
1886 struct dc_chain_data *cd;
1887 struct dc_list_data *ld;
1888 int i;
1889 bus_addr_t next;
1890
1891 cd = &sc->dc_cdata;
1892 ld = sc->dc_ldata;
1893 for (i = 0; i < DC_TX_LIST_CNT; i++) {
1894 next = sc->sc_listmap->dm_segs[0].ds_addr;
1895 if (i == (DC_TX_LIST_CNT - 1))
1896 next +=
1897 offsetof(struct dc_list_data, dc_tx_list[0]);
1898 else
1899 next +=
1900 offsetof(struct dc_list_data, dc_tx_list[i + 1]);
1901 cd->dc_tx_chain[i].sd_mbuf = NULL;
1902 ld->dc_tx_list[i].dc_data = htole32(0);
1903 ld->dc_tx_list[i].dc_ctl = htole32(0);
1904 ld->dc_tx_list[i].dc_next = htole32(next);
1905 }
1906
1907 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0;
1908
1909 return (0);
1910 }
1911
1912
1913 /*
1914 * Initialize the RX descriptors and allocate mbufs for them. Note that
1915 * we arrange the descriptors in a closed ring, so that the last descriptor
1916 * points back to the first.
1917 */
1918 int
dc_list_rx_init(sc)1919 dc_list_rx_init(sc)
1920 struct dc_softc *sc;
1921 {
1922 struct dc_chain_data *cd;
1923 struct dc_list_data *ld;
1924 int i;
1925 bus_addr_t next;
1926
1927 cd = &sc->dc_cdata;
1928 ld = sc->dc_ldata;
1929
1930 for (i = 0; i < DC_RX_LIST_CNT; i++) {
1931 if (dc_newbuf(sc, i, NULL) == ENOBUFS)
1932 return (ENOBUFS);
1933 next = sc->sc_listmap->dm_segs[0].ds_addr;
1934 if (i == (DC_RX_LIST_CNT - 1))
1935 next +=
1936 offsetof(struct dc_list_data, dc_rx_list[0]);
1937 else
1938 next +=
1939 offsetof(struct dc_list_data, dc_rx_list[i + 1]);
1940 ld->dc_rx_list[i].dc_next = htole32(next);
1941 }
1942
1943 cd->dc_rx_prod = 0;
1944
1945 return (0);
1946 }
1947
1948 /*
1949 * Initialize an RX descriptor and attach an MBUF cluster.
1950 */
1951 int
dc_newbuf(sc,i,m)1952 dc_newbuf(sc, i, m)
1953 struct dc_softc *sc;
1954 int i;
1955 struct mbuf *m;
1956 {
1957 struct mbuf *m_new = NULL;
1958 struct dc_desc *c;
1959 bus_dmamap_t map;
1960
1961 c = &sc->dc_ldata->dc_rx_list[i];
1962
1963 if (m == NULL) {
1964 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1965 if (m_new == NULL) {
1966 printf("%s: no memory for rx list "
1967 "-- packet dropped!\n", sc->sc_dev.dv_xname);
1968 return (ENOBUFS);
1969 }
1970
1971 MCLGET(m_new, M_DONTWAIT);
1972 if (!(m_new->m_flags & M_EXT)) {
1973 printf("%s: no memory for rx list "
1974 "-- packet dropped!\n", sc->sc_dev.dv_xname);
1975 m_freem(m_new);
1976 return (ENOBUFS);
1977 }
1978 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1979 if (bus_dmamap_load_mbuf(sc->sc_dmat, sc->sc_rx_sparemap,
1980 m_new, BUS_DMA_NOWAIT) != 0) {
1981 printf("%s: rx load failed\n", sc->sc_dev.dv_xname);
1982 m_freem(m_new);
1983 return (ENOBUFS);
1984 }
1985 map = sc->dc_cdata.dc_rx_chain[i].sd_map;
1986 sc->dc_cdata.dc_rx_chain[i].sd_map = sc->sc_rx_sparemap;
1987 sc->sc_rx_sparemap = map;
1988 } else {
1989 m_new = m;
1990 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1991 m_new->m_data = m_new->m_ext.ext_buf;
1992 }
1993
1994 m_adj(m_new, sizeof(u_int64_t));
1995
1996 /*
1997 * If this is a PNIC chip, zero the buffer. This is part
1998 * of the workaround for the receive bug in the 82c168 and
1999 * 82c169 chips.
2000 */
2001 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR)
2002 bzero((char *)mtod(m_new, char *), m_new->m_len);
2003
2004 bus_dmamap_sync(sc->sc_dmat, sc->dc_cdata.dc_rx_chain[i].sd_map, 0,
2005 sc->dc_cdata.dc_rx_chain[i].sd_map->dm_mapsize,
2006 BUS_DMASYNC_PREREAD);
2007
2008 sc->dc_cdata.dc_rx_chain[i].sd_mbuf = m_new;
2009 c->dc_data = htole32(
2010 sc->dc_cdata.dc_rx_chain[i].sd_map->dm_segs[0].ds_addr +
2011 sizeof(u_int64_t));
2012 c->dc_ctl = htole32(DC_RXCTL_RLINK | ETHER_MAX_DIX_LEN);
2013 c->dc_status = htole32(DC_RXSTAT_OWN);
2014
2015 bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap,
2016 offsetof(struct dc_list_data, dc_rx_list[i]),
2017 sizeof(struct dc_desc),
2018 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2019
2020 return (0);
2021 }
2022
2023 /*
2024 * Grrrrr.
2025 * The PNIC chip has a terrible bug in it that manifests itself during
2026 * periods of heavy activity. The exact mode of failure if difficult to
2027 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it
2028 * will happen on slow machines. The bug is that sometimes instead of
2029 * uploading one complete frame during reception, it uploads what looks
2030 * like the entire contents of its FIFO memory. The frame we want is at
2031 * the end of the whole mess, but we never know exactly how much data has
2032 * been uploaded, so salvaging the frame is hard.
2033 *
2034 * There is only one way to do it reliably, and it's disgusting.
2035 * Here's what we know:
2036 *
2037 * - We know there will always be somewhere between one and three extra
2038 * descriptors uploaded.
2039 *
2040 * - We know the desired received frame will always be at the end of the
2041 * total data upload.
2042 *
2043 * - We know the size of the desired received frame because it will be
2044 * provided in the length field of the status word in the last descriptor.
2045 *
2046 * Here's what we do:
2047 *
2048 * - When we allocate buffers for the receive ring, we bzero() them.
2049 * This means that we know that the buffer contents should be all
2050 * zeros, except for data uploaded by the chip.
2051 *
2052 * - We also force the PNIC chip to upload frames that include the
2053 * ethernet CRC at the end.
2054 *
2055 * - We gather all of the bogus frame data into a single buffer.
2056 *
2057 * - We then position a pointer at the end of this buffer and scan
2058 * backwards until we encounter the first non-zero byte of data.
2059 * This is the end of the received frame. We know we will encounter
2060 * some data at the end of the frame because the CRC will always be
2061 * there, so even if the sender transmits a packet of all zeros,
2062 * we won't be fooled.
2063 *
2064 * - We know the size of the actual received frame, so we subtract
2065 * that value from the current pointer location. This brings us
2066 * to the start of the actual received packet.
2067 *
2068 * - We copy this into an mbuf and pass it on, along with the actual
2069 * frame length.
2070 *
2071 * The performance hit is tremendous, but it beats dropping frames all
2072 * the time.
2073 */
2074
2075 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG)
2076 void
dc_pnic_rx_bug_war(sc,idx)2077 dc_pnic_rx_bug_war(sc, idx)
2078 struct dc_softc *sc;
2079 int idx;
2080 {
2081 struct dc_desc *cur_rx;
2082 struct dc_desc *c = NULL;
2083 struct mbuf *m = NULL;
2084 unsigned char *ptr;
2085 int i, total_len;
2086 u_int32_t rxstat = 0;
2087
2088 i = sc->dc_pnic_rx_bug_save;
2089 cur_rx = &sc->dc_ldata->dc_rx_list[idx];
2090 ptr = sc->dc_pnic_rx_buf;
2091 bzero(ptr, ETHER_MAX_DIX_LEN * 5);
2092
2093 /* Copy all the bytes from the bogus buffers. */
2094 while (1) {
2095 c = &sc->dc_ldata->dc_rx_list[i];
2096 rxstat = letoh32(c->dc_status);
2097 m = sc->dc_cdata.dc_rx_chain[i].sd_mbuf;
2098 bcopy(mtod(m, char *), ptr, ETHER_MAX_DIX_LEN);
2099 ptr += ETHER_MAX_DIX_LEN;
2100 /* If this is the last buffer, break out. */
2101 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG)
2102 break;
2103 dc_newbuf(sc, i, m);
2104 DC_INC(i, DC_RX_LIST_CNT);
2105 }
2106
2107 /* Find the length of the actual receive frame. */
2108 total_len = DC_RXBYTES(rxstat);
2109
2110 /* Scan backwards until we hit a non-zero byte. */
2111 while(*ptr == 0x00)
2112 ptr--;
2113
2114 /* Round off. */
2115 if ((unsigned long)(ptr) & 0x3)
2116 ptr -= 1;
2117
2118 /* Now find the start of the frame. */
2119 ptr -= total_len;
2120 if (ptr < sc->dc_pnic_rx_buf)
2121 ptr = sc->dc_pnic_rx_buf;
2122
2123 /*
2124 * Now copy the salvaged frame to the last mbuf and fake up
2125 * the status word to make it look like a successful
2126 * frame reception.
2127 */
2128 dc_newbuf(sc, i, m);
2129 bcopy(ptr, mtod(m, char *), total_len);
2130 cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG);
2131 }
2132
2133 /*
2134 * This routine searches the RX ring for dirty descriptors in the
2135 * event that the rxeof routine falls out of sync with the chip's
2136 * current descriptor pointer. This may happen sometimes as a result
2137 * of a "no RX buffer available" condition that happens when the chip
2138 * consumes all of the RX buffers before the driver has a chance to
2139 * process the RX ring. This routine may need to be called more than
2140 * once to bring the driver back in sync with the chip, however we
2141 * should still be getting RX DONE interrupts to drive the search
2142 * for new packets in the RX ring, so we should catch up eventually.
2143 */
2144 int
dc_rx_resync(sc)2145 dc_rx_resync(sc)
2146 struct dc_softc *sc;
2147 {
2148 u_int32_t stat;
2149 int i, pos, offset;
2150
2151 pos = sc->dc_cdata.dc_rx_prod;
2152
2153 for (i = 0; i < DC_RX_LIST_CNT; i++) {
2154
2155 offset = offsetof(struct dc_list_data, dc_rx_list[pos]);
2156 bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap,
2157 offset, sizeof(struct dc_desc),
2158 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2159
2160 stat = sc->dc_ldata->dc_rx_list[pos].dc_status;
2161 if (!(stat & htole32(DC_RXSTAT_OWN)))
2162 break;
2163 DC_INC(pos, DC_RX_LIST_CNT);
2164 }
2165
2166 /* If the ring really is empty, then just return. */
2167 if (i == DC_RX_LIST_CNT)
2168 return (0);
2169
2170 /* We've fallen behind the chip: catch it. */
2171 sc->dc_cdata.dc_rx_prod = pos;
2172
2173 return (EAGAIN);
2174 }
2175
2176 /*
2177 * A frame has been uploaded: pass the resulting mbuf chain up to
2178 * the higher level protocols.
2179 */
2180 void
dc_rxeof(sc)2181 dc_rxeof(sc)
2182 struct dc_softc *sc;
2183 {
2184 struct mbuf *m;
2185 struct ifnet *ifp;
2186 struct dc_desc *cur_rx;
2187 int i, offset, total_len = 0;
2188 u_int32_t rxstat;
2189
2190 ifp = &sc->sc_arpcom.ac_if;
2191 i = sc->dc_cdata.dc_rx_prod;
2192
2193 for(;;) {
2194 struct mbuf *m0 = NULL;
2195
2196 offset = offsetof(struct dc_list_data, dc_rx_list[i]);
2197 bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap,
2198 offset, sizeof(struct dc_desc),
2199 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2200
2201 cur_rx = &sc->dc_ldata->dc_rx_list[i];
2202 rxstat = letoh32(cur_rx->dc_status);
2203 if (rxstat & DC_RXSTAT_OWN)
2204 break;
2205
2206 m = sc->dc_cdata.dc_rx_chain[i].sd_mbuf;
2207 total_len = DC_RXBYTES(rxstat);
2208
2209 bus_dmamap_sync(sc->sc_dmat, sc->dc_cdata.dc_rx_chain[i].sd_map,
2210 0, sc->dc_cdata.dc_rx_chain[i].sd_map->dm_mapsize,
2211 BUS_DMASYNC_POSTREAD);
2212
2213 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) {
2214 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) {
2215 if (rxstat & DC_RXSTAT_FIRSTFRAG)
2216 sc->dc_pnic_rx_bug_save = i;
2217 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) {
2218 DC_INC(i, DC_RX_LIST_CNT);
2219 continue;
2220 }
2221 dc_pnic_rx_bug_war(sc, i);
2222 rxstat = letoh32(cur_rx->dc_status);
2223 total_len = DC_RXBYTES(rxstat);
2224 }
2225 }
2226
2227 sc->dc_cdata.dc_rx_chain[i].sd_mbuf = NULL;
2228
2229 /*
2230 * If an error occurs, update stats, clear the
2231 * status word and leave the mbuf cluster in place:
2232 * it should simply get re-used next time this descriptor
2233 * comes up in the ring. However, don't report long
2234 * frames as errors since they could be VLANs.
2235 */
2236 if ((rxstat & DC_RXSTAT_RXERR)) {
2237 if (!(rxstat & DC_RXSTAT_GIANT) ||
2238 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE |
2239 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN |
2240 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) {
2241 ifp->if_ierrors++;
2242 if (rxstat & DC_RXSTAT_COLLSEEN)
2243 ifp->if_collisions++;
2244 dc_newbuf(sc, i, m);
2245 if (rxstat & DC_RXSTAT_CRCERR) {
2246 DC_INC(i, DC_RX_LIST_CNT);
2247 continue;
2248 } else {
2249 dc_init(sc);
2250 return;
2251 }
2252 }
2253 }
2254
2255 /* No errors; receive the packet. */
2256 total_len -= ETHER_CRC_LEN;
2257
2258 m->m_pkthdr.rcvif = ifp;
2259 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
2260 total_len + ETHER_ALIGN, 0, ifp, NULL);
2261 dc_newbuf(sc, i, m);
2262 DC_INC(i, DC_RX_LIST_CNT);
2263 if (m0 == NULL) {
2264 ifp->if_ierrors++;
2265 continue;
2266 }
2267 m_adj(m0, ETHER_ALIGN);
2268 m = m0;
2269
2270 ifp->if_ipackets++;
2271 #if NBPFILTER > 0
2272 if (ifp->if_bpf)
2273 bpf_mtap(ifp->if_bpf, m);
2274 #endif
2275 ether_input_mbuf(ifp, m);
2276 }
2277
2278 sc->dc_cdata.dc_rx_prod = i;
2279 }
2280
2281 /*
2282 * A frame was downloaded to the chip. It's safe for us to clean up
2283 * the list buffers.
2284 */
2285
2286 void
dc_txeof(sc)2287 dc_txeof(sc)
2288 struct dc_softc *sc;
2289 {
2290 struct dc_desc *cur_tx = NULL;
2291 struct ifnet *ifp;
2292 int idx, offset;
2293
2294 ifp = &sc->sc_arpcom.ac_if;
2295
2296 /*
2297 * Go through our tx list and free mbufs for those
2298 * frames that have been transmitted.
2299 */
2300 idx = sc->dc_cdata.dc_tx_cons;
2301 while(idx != sc->dc_cdata.dc_tx_prod) {
2302 u_int32_t txstat;
2303
2304 offset = offsetof(struct dc_list_data, dc_tx_list[idx]);
2305 bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap,
2306 offset, sizeof(struct dc_desc),
2307 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2308
2309 cur_tx = &sc->dc_ldata->dc_tx_list[idx];
2310 txstat = letoh32(cur_tx->dc_status);
2311
2312 if (txstat & DC_TXSTAT_OWN)
2313 break;
2314
2315 if (!(cur_tx->dc_ctl & htole32(DC_TXCTL_LASTFRAG)) ||
2316 cur_tx->dc_ctl & htole32(DC_TXCTL_SETUP)) {
2317 if (cur_tx->dc_ctl & htole32(DC_TXCTL_SETUP)) {
2318 /*
2319 * Yes, the PNIC is so brain damaged
2320 * that it will sometimes generate a TX
2321 * underrun error while DMAing the RX
2322 * filter setup frame. If we detect this,
2323 * we have to send the setup frame again,
2324 * or else the filter won't be programmed
2325 * correctly.
2326 */
2327 if (DC_IS_PNIC(sc)) {
2328 if (txstat & DC_TXSTAT_ERRSUM)
2329 dc_setfilt(sc);
2330 }
2331 sc->dc_cdata.dc_tx_chain[idx].sd_mbuf = NULL;
2332 }
2333 sc->dc_cdata.dc_tx_cnt--;
2334 DC_INC(idx, DC_TX_LIST_CNT);
2335 continue;
2336 }
2337
2338 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) {
2339 /*
2340 * XXX: Why does my Xircom taunt me so?
2341 * For some reason it likes setting the CARRLOST flag
2342 * even when the carrier is there. wtf?!
2343 * Who knows, but Conexant chips have the
2344 * same problem. Maybe they took lessons
2345 * from Xircom.
2346 */
2347 if (/*sc->dc_type == DC_TYPE_21143 &&*/
2348 sc->dc_pmode == DC_PMODE_MII &&
2349 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM|
2350 DC_TXSTAT_NOCARRIER)))
2351 txstat &= ~DC_TXSTAT_ERRSUM;
2352 } else {
2353 if (/*sc->dc_type == DC_TYPE_21143 &&*/
2354 sc->dc_pmode == DC_PMODE_MII &&
2355 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM|
2356 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST)))
2357 txstat &= ~DC_TXSTAT_ERRSUM;
2358 }
2359
2360 if (txstat & DC_TXSTAT_ERRSUM) {
2361 ifp->if_oerrors++;
2362 if (txstat & DC_TXSTAT_EXCESSCOLL)
2363 ifp->if_collisions++;
2364 if (txstat & DC_TXSTAT_LATECOLL)
2365 ifp->if_collisions++;
2366 if (!(txstat & DC_TXSTAT_UNDERRUN)) {
2367 dc_init(sc);
2368 return;
2369 }
2370 }
2371
2372 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3;
2373
2374 ifp->if_opackets++;
2375 if (sc->dc_cdata.dc_tx_chain[idx].sd_map->dm_nsegs != 0) {
2376 bus_dmamap_t map = sc->dc_cdata.dc_tx_chain[idx].sd_map;
2377
2378 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
2379 BUS_DMASYNC_POSTWRITE);
2380 bus_dmamap_unload(sc->sc_dmat, map);
2381 }
2382 if (sc->dc_cdata.dc_tx_chain[idx].sd_mbuf != NULL) {
2383 m_freem(sc->dc_cdata.dc_tx_chain[idx].sd_mbuf);
2384 sc->dc_cdata.dc_tx_chain[idx].sd_mbuf = NULL;
2385 }
2386
2387 bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap,
2388 offset, sizeof(struct dc_desc),
2389 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2390
2391 sc->dc_cdata.dc_tx_cnt--;
2392 DC_INC(idx, DC_TX_LIST_CNT);
2393 }
2394
2395 if (idx != sc->dc_cdata.dc_tx_cons) {
2396 /* some buffers have been freed */
2397 sc->dc_cdata.dc_tx_cons = idx;
2398 ifp->if_flags &= ~IFF_OACTIVE;
2399 }
2400 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5;
2401 }
2402
2403 void
dc_tick(xsc)2404 dc_tick(xsc)
2405 void *xsc;
2406 {
2407 struct dc_softc *sc = (struct dc_softc *)xsc;
2408 struct mii_data *mii;
2409 struct ifnet *ifp;
2410 int s;
2411 u_int32_t r;
2412
2413 s = splimp();
2414
2415 ifp = &sc->sc_arpcom.ac_if;
2416 mii = &sc->sc_mii;
2417
2418 if (sc->dc_flags & DC_REDUCED_MII_POLL) {
2419 if (sc->dc_flags & DC_21143_NWAY) {
2420 r = CSR_READ_4(sc, DC_10BTSTAT);
2421 if (IFM_SUBTYPE(mii->mii_media_active) ==
2422 IFM_100_TX && (r & DC_TSTAT_LS100)) {
2423 sc->dc_link = 0;
2424 mii_mediachg(mii);
2425 }
2426 if (IFM_SUBTYPE(mii->mii_media_active) ==
2427 IFM_10_T && (r & DC_TSTAT_LS10)) {
2428 sc->dc_link = 0;
2429 mii_mediachg(mii);
2430 }
2431 if (sc->dc_link == 0)
2432 mii_tick(mii);
2433 } else {
2434 r = CSR_READ_4(sc, DC_ISR);
2435 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT &&
2436 sc->dc_cdata.dc_tx_cnt == 0 && !DC_IS_ASIX(sc)) {
2437 mii_tick(mii);
2438 if (!(mii->mii_media_status & IFM_ACTIVE))
2439 sc->dc_link = 0;
2440 }
2441 }
2442 } else
2443 mii_tick(mii);
2444
2445 /*
2446 * When the init routine completes, we expect to be able to send
2447 * packets right away, and in fact the network code will send a
2448 * gratuitous ARP the moment the init routine marks the interface
2449 * as running. However, even though the MAC may have been initialized,
2450 * there may be a delay of a few seconds before the PHY completes
2451 * autonegotiation and the link is brought up. Any transmissions
2452 * made during that delay will be lost. Dealing with this is tricky:
2453 * we can't just pause in the init routine while waiting for the
2454 * PHY to come ready since that would bring the whole system to
2455 * a screeching halt for several seconds.
2456 *
2457 * What we do here is prevent the TX start routine from sending
2458 * any packets until a link has been established. After the
2459 * interface has been initialized, the tick routine will poll
2460 * the state of the PHY until the IFM_ACTIVE flag is set. Until
2461 * that time, packets will stay in the send queue, and once the
2462 * link comes up, they will be flushed out to the wire.
2463 */
2464 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE &&
2465 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2466 sc->dc_link++;
2467 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0)
2468 dc_start(ifp);
2469 }
2470
2471 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link)
2472 timeout_add(&sc->dc_tick_tmo, hz / 10);
2473 else
2474 timeout_add(&sc->dc_tick_tmo, hz);
2475
2476 splx(s);
2477 }
2478
2479 /* A transmit underrun has occurred. Back off the transmit threshold,
2480 * or switch to store and forward mode if we have to.
2481 */
2482 void
dc_tx_underrun(sc)2483 dc_tx_underrun(sc)
2484 struct dc_softc *sc;
2485 {
2486 u_int32_t isr;
2487 int i;
2488
2489 if (DC_IS_DAVICOM(sc))
2490 dc_init(sc);
2491
2492 if (DC_IS_INTEL(sc)) {
2493 /*
2494 * The real 21143 requires that the transmitter be idle
2495 * in order to change the transmit threshold or store
2496 * and forward state.
2497 */
2498 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2499
2500 for (i = 0; i < DC_TIMEOUT; i++) {
2501 isr = CSR_READ_4(sc, DC_ISR);
2502 if (isr & DC_ISR_TX_IDLE)
2503 break;
2504 DELAY(10);
2505 }
2506 if (i == DC_TIMEOUT) {
2507 printf("%s: failed to force tx to idle state\n",
2508 sc->sc_dev.dv_xname);
2509 dc_init(sc);
2510 }
2511 }
2512
2513 sc->dc_txthresh += DC_TXTHRESH_INC;
2514 if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
2515 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
2516 } else {
2517 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
2518 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
2519 }
2520
2521 if (DC_IS_INTEL(sc))
2522 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2523
2524 return;
2525 }
2526
2527 int
dc_intr(arg)2528 dc_intr(arg)
2529 void *arg;
2530 {
2531 struct dc_softc *sc;
2532 struct ifnet *ifp;
2533 u_int32_t status;
2534 int claimed = 0;
2535
2536 sc = arg;
2537
2538 ifp = &sc->sc_arpcom.ac_if;
2539
2540 /* Suppress unwanted interrupts */
2541 if (!(ifp->if_flags & IFF_UP)) {
2542 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS)
2543 dc_stop(sc);
2544 return (claimed);
2545 }
2546
2547 /* Disable interrupts. */
2548 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
2549
2550 while(((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) &&
2551 status != 0xFFFFFFFF) {
2552
2553 claimed = 1;
2554 CSR_WRITE_4(sc, DC_ISR, status);
2555
2556 if (status & DC_ISR_RX_OK) {
2557 int curpkts;
2558 curpkts = ifp->if_ipackets;
2559 dc_rxeof(sc);
2560 if (curpkts == ifp->if_ipackets) {
2561 while(dc_rx_resync(sc))
2562 dc_rxeof(sc);
2563 }
2564 }
2565
2566 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF))
2567 dc_txeof(sc);
2568
2569 if (status & DC_ISR_TX_IDLE) {
2570 dc_txeof(sc);
2571 if (sc->dc_cdata.dc_tx_cnt) {
2572 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2573 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
2574 }
2575 }
2576
2577 if (status & DC_ISR_TX_UNDERRUN)
2578 dc_tx_underrun(sc);
2579
2580 if ((status & DC_ISR_RX_WATDOGTIMEO)
2581 || (status & DC_ISR_RX_NOBUF)) {
2582 int curpkts;
2583 curpkts = ifp->if_ipackets;
2584 dc_rxeof(sc);
2585 if (curpkts == ifp->if_ipackets) {
2586 while(dc_rx_resync(sc))
2587 dc_rxeof(sc);
2588 }
2589 }
2590
2591 if (status & DC_ISR_BUS_ERR) {
2592 dc_reset(sc);
2593 dc_init(sc);
2594 }
2595 }
2596
2597 /* Re-enable interrupts. */
2598 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
2599
2600 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0)
2601 dc_start(ifp);
2602
2603 return (claimed);
2604 }
2605
2606 /*
2607 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
2608 * pointers to the fragment pointers.
2609 */
2610 int
dc_encap(sc,m_head,txidx)2611 dc_encap(sc, m_head, txidx)
2612 struct dc_softc *sc;
2613 struct mbuf *m_head;
2614 u_int32_t *txidx;
2615 {
2616 struct dc_desc *f = NULL;
2617 int frag, cur, cnt = 0, i;
2618 bus_dmamap_t map;
2619
2620 /*
2621 * Start packing the mbufs in this chain into
2622 * the fragment pointers. Stop when we run out
2623 * of fragments or hit the end of the mbuf chain.
2624 */
2625 map = sc->sc_tx_sparemap;
2626
2627 if (bus_dmamap_load_mbuf(sc->sc_dmat, map,
2628 m_head, BUS_DMA_NOWAIT) != 0)
2629 return (ENOBUFS);
2630
2631 cur = frag = *txidx;
2632
2633 for (i = 0; i < map->dm_nsegs; i++) {
2634 if (sc->dc_flags & DC_TX_ADMTEK_WAR) {
2635 if (*txidx != sc->dc_cdata.dc_tx_prod &&
2636 frag == (DC_TX_LIST_CNT - 1)) {
2637 bus_dmamap_unload(sc->sc_dmat, map);
2638 return (ENOBUFS);
2639 }
2640 }
2641 if ((DC_TX_LIST_CNT -
2642 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5) {
2643 bus_dmamap_unload(sc->sc_dmat, map);
2644 return (ENOBUFS);
2645 }
2646
2647 f = &sc->dc_ldata->dc_tx_list[frag];
2648 f->dc_ctl = htole32(DC_TXCTL_TLINK | map->dm_segs[i].ds_len);
2649 if (cnt == 0) {
2650 f->dc_status = htole32(0);
2651 f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG);
2652 } else
2653 f->dc_status = htole32(DC_TXSTAT_OWN);
2654 f->dc_data = htole32(map->dm_segs[i].ds_addr);
2655 cur = frag;
2656 DC_INC(frag, DC_TX_LIST_CNT);
2657 cnt++;
2658 }
2659
2660 sc->dc_cdata.dc_tx_cnt += cnt;
2661 sc->dc_cdata.dc_tx_chain[cur].sd_mbuf = m_head;
2662 sc->sc_tx_sparemap = sc->dc_cdata.dc_tx_chain[cur].sd_map;
2663 sc->dc_cdata.dc_tx_chain[cur].sd_map = map;
2664 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG);
2665 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG)
2666 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |=
2667 htole32(DC_TXCTL_FINT);
2668 if (sc->dc_flags & DC_TX_INTR_ALWAYS)
2669 sc->dc_ldata->dc_tx_list[cur].dc_ctl |=
2670 htole32(DC_TXCTL_FINT);
2671 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64)
2672 sc->dc_ldata->dc_tx_list[cur].dc_ctl |=
2673 htole32(DC_TXCTL_FINT);
2674 else if ((sc->dc_flags & DC_TX_USE_TX_INTR) &&
2675 TBR_IS_ENABLED(&sc->sc_arpcom.ac_if.if_snd))
2676 sc->dc_ldata->dc_tx_list[cur].dc_ctl |=
2677 htole32(DC_TXCTL_FINT);
2678 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
2679 BUS_DMASYNC_PREWRITE);
2680
2681 sc->dc_ldata->dc_tx_list[*txidx].dc_status = htole32(DC_TXSTAT_OWN);
2682
2683 bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap,
2684 offsetof(struct dc_list_data, dc_tx_list[*txidx]),
2685 sizeof(struct dc_desc) * cnt,
2686 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2687
2688 *txidx = frag;
2689
2690 return (0);
2691 }
2692
2693 /*
2694 * Coalesce an mbuf chain into a single mbuf cluster buffer.
2695 * Needed for some really badly behaved chips that just can't
2696 * do scatter/gather correctly.
2697 */
2698 int
dc_coal(sc,m_head)2699 dc_coal(sc, m_head)
2700 struct dc_softc *sc;
2701 struct mbuf **m_head;
2702 {
2703 struct mbuf *m_new, *m;
2704
2705 m = *m_head;
2706 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
2707 if (m_new == NULL) {
2708 printf("%s: no memory for tx list", sc->sc_dev.dv_xname);
2709 return (ENOBUFS);
2710 }
2711 if (m->m_pkthdr.len > MHLEN) {
2712 MCLGET(m_new, M_DONTWAIT);
2713 if (!(m_new->m_flags & M_EXT)) {
2714 m_freem(m_new);
2715 printf("%s: no memory for tx list",
2716 sc->sc_dev.dv_xname);
2717 return (ENOBUFS);
2718 }
2719 }
2720 m_copydata(m, 0, m->m_pkthdr.len, mtod(m_new, caddr_t));
2721 m_new->m_pkthdr.len = m_new->m_len = m->m_pkthdr.len;
2722 m_freem(m);
2723 *m_head = m_new;
2724
2725 return (0);
2726 }
2727
2728 /*
2729 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2730 * to the mbuf data regions directly in the transmit lists. We also save a
2731 * copy of the pointers since the transmit list fragment pointers are
2732 * physical addresses.
2733 */
2734
2735 void
dc_start(ifp)2736 dc_start(ifp)
2737 struct ifnet *ifp;
2738 {
2739 struct dc_softc *sc;
2740 struct mbuf *m_head = NULL;
2741 int idx;
2742
2743 sc = ifp->if_softc;
2744
2745 if (!sc->dc_link && ifp->if_snd.ifq_len < 10)
2746 return;
2747
2748 if (ifp->if_flags & IFF_OACTIVE)
2749 return;
2750
2751 idx = sc->dc_cdata.dc_tx_prod;
2752
2753 while(sc->dc_cdata.dc_tx_chain[idx].sd_mbuf == NULL) {
2754 IFQ_POLL(&ifp->if_snd, m_head);
2755 if (m_head == NULL)
2756 break;
2757
2758 if (sc->dc_flags & DC_TX_COALESCE &&
2759 (m_head->m_next != NULL ||
2760 sc->dc_flags & DC_TX_ALIGN)) {
2761 /* note: dc_coal breaks the poll-and-dequeue rule.
2762 * if dc_coal fails, we lose the packet.
2763 */
2764 IFQ_DEQUEUE(&ifp->if_snd, m_head);
2765 if (dc_coal(sc, &m_head)) {
2766 ifp->if_flags |= IFF_OACTIVE;
2767 break;
2768 }
2769 }
2770
2771 if (dc_encap(sc, m_head, &idx)) {
2772 ifp->if_flags |= IFF_OACTIVE;
2773 break;
2774 }
2775
2776 /* now we are committed to transmit the packet */
2777 if (sc->dc_flags & DC_TX_COALESCE) {
2778 /* if mbuf is coalesced, it is already dequeued */
2779 } else
2780 IFQ_DEQUEUE(&ifp->if_snd, m_head);
2781
2782 /*
2783 * If there's a BPF listener, bounce a copy of this frame
2784 * to him.
2785 */
2786 #if NBPFILTER > 0
2787 if (ifp->if_bpf)
2788 bpf_mtap(ifp->if_bpf, m_head);
2789 #endif
2790 if (sc->dc_flags & DC_TX_ONE) {
2791 ifp->if_flags |= IFF_OACTIVE;
2792 break;
2793 }
2794 }
2795 if (idx == sc->dc_cdata.dc_tx_prod)
2796 return;
2797
2798 /* Transmit */
2799 sc->dc_cdata.dc_tx_prod = idx;
2800 if (!(sc->dc_flags & DC_TX_POLL))
2801 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
2802
2803 /*
2804 * Set a timeout in case the chip goes out to lunch.
2805 */
2806 ifp->if_timer = 5;
2807 }
2808
2809 void
dc_init(xsc)2810 dc_init(xsc)
2811 void *xsc;
2812 {
2813 struct dc_softc *sc = xsc;
2814 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
2815 struct mii_data *mii;
2816 int s;
2817
2818 s = splimp();
2819
2820 mii = &sc->sc_mii;
2821
2822 /*
2823 * Cancel pending I/O and free all RX/TX buffers.
2824 */
2825 dc_stop(sc);
2826 dc_reset(sc);
2827
2828 /*
2829 * Set cache alignment and burst length.
2830 */
2831 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc))
2832 CSR_WRITE_4(sc, DC_BUSCTL, 0);
2833 else
2834 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE);
2835 /*
2836 * Evenly share the bus between receive and transmit process.
2837 */
2838 if (DC_IS_INTEL(sc))
2839 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION);
2840 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) {
2841 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA);
2842 } else {
2843 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG);
2844 }
2845 if (sc->dc_flags & DC_TX_POLL)
2846 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1);
2847 switch(sc->dc_cachesize) {
2848 case 32:
2849 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG);
2850 break;
2851 case 16:
2852 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG);
2853 break;
2854 case 8:
2855 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG);
2856 break;
2857 case 0:
2858 default:
2859 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE);
2860 break;
2861 }
2862
2863 if (sc->dc_flags & DC_TX_STORENFWD)
2864 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
2865 else {
2866 if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
2867 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
2868 } else {
2869 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
2870 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
2871 }
2872 }
2873
2874 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC);
2875 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF);
2876
2877 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
2878 /*
2879 * The app notes for the 98713 and 98715A say that
2880 * in order to have the chips operate properly, a magic
2881 * number must be written to CSR16. Macronix does not
2882 * document the meaning of these bits so there's no way
2883 * to know exactly what they do. The 98713 has a magic
2884 * number all its own; the rest all use a different one.
2885 */
2886 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000);
2887 if (sc->dc_type == DC_TYPE_98713)
2888 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713);
2889 else
2890 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715);
2891 }
2892
2893 if (DC_IS_XIRCOM(sc)) {
2894 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN |
2895 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
2896 DELAY(10);
2897 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN |
2898 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
2899 DELAY(10);
2900 }
2901
2902 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
2903 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN);
2904
2905 /* Init circular RX list. */
2906 if (dc_list_rx_init(sc) == ENOBUFS) {
2907 printf("%s: initialization failed: no "
2908 "memory for rx buffers\n", sc->sc_dev.dv_xname);
2909 dc_stop(sc);
2910 splx(s);
2911 return;
2912 }
2913
2914 /*
2915 * Init tx descriptors.
2916 */
2917 dc_list_tx_init(sc);
2918
2919 /*
2920 * Sync down both lists initialized.
2921 */
2922 bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap,
2923 0, sc->sc_listmap->dm_mapsize,
2924 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2925
2926 /*
2927 * Load the address of the RX list.
2928 */
2929 CSR_WRITE_4(sc, DC_RXADDR, sc->sc_listmap->dm_segs[0].ds_addr +
2930 offsetof(struct dc_list_data, dc_rx_list[0]));
2931 CSR_WRITE_4(sc, DC_TXADDR, sc->sc_listmap->dm_segs[0].ds_addr +
2932 offsetof(struct dc_list_data, dc_tx_list[0]));
2933
2934 /*
2935 * Enable interrupts.
2936 */
2937 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
2938 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF);
2939
2940 /* Enable transmitter. */
2941 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2942
2943 /*
2944 * If this is an Intel 21143 and we're not using the
2945 * MII port, program the LED control pins so we get
2946 * link and activity indications.
2947 */
2948 if (sc->dc_flags & DC_TULIP_LEDS) {
2949 CSR_WRITE_4(sc, DC_WATCHDOG,
2950 DC_WDOG_CTLWREN|DC_WDOG_LINK|DC_WDOG_ACTIVITY);
2951 CSR_WRITE_4(sc, DC_WATCHDOG, 0);
2952 }
2953
2954 /*
2955 * Load the RX/multicast filter. We do this sort of late
2956 * because the filter programming scheme on the 21143 and
2957 * some clones requires DMAing a setup frame via the TX
2958 * engine, and we need the transmitter enabled for that.
2959 */
2960 dc_setfilt(sc);
2961
2962 /* Enable receiver. */
2963 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
2964 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF);
2965
2966 mii_mediachg(mii);
2967 dc_setcfg(sc, sc->dc_if_media);
2968
2969 ifp->if_flags |= IFF_RUNNING;
2970 ifp->if_flags &= ~IFF_OACTIVE;
2971
2972 splx(s);
2973
2974 timeout_set(&sc->dc_tick_tmo, dc_tick, sc);
2975
2976 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1)
2977 sc->dc_link = 1;
2978 else {
2979 if (sc->dc_flags & DC_21143_NWAY)
2980 timeout_add(&sc->dc_tick_tmo, hz / 10);
2981 else
2982 timeout_add(&sc->dc_tick_tmo, hz);
2983 }
2984
2985 #ifdef SRM_MEDIA
2986 if(sc->dc_srm_media) {
2987 struct ifreq ifr;
2988
2989 ifr.ifr_media = sc->dc_srm_media;
2990 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA);
2991 sc->dc_srm_media = 0;
2992 }
2993 #endif
2994 }
2995
2996 /*
2997 * Set media options.
2998 */
2999 int
dc_ifmedia_upd(ifp)3000 dc_ifmedia_upd(ifp)
3001 struct ifnet *ifp;
3002 {
3003 struct dc_softc *sc;
3004 struct mii_data *mii;
3005 struct ifmedia *ifm;
3006
3007 sc = ifp->if_softc;
3008 mii = &sc->sc_mii;
3009 mii_mediachg(mii);
3010
3011 ifm = &mii->mii_media;
3012
3013 if (DC_IS_DAVICOM(sc) &&
3014 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1)
3015 dc_setcfg(sc, ifm->ifm_media);
3016 else
3017 sc->dc_link = 0;
3018
3019 return (0);
3020 }
3021
3022 /*
3023 * Report current media status.
3024 */
3025 void
dc_ifmedia_sts(ifp,ifmr)3026 dc_ifmedia_sts(ifp, ifmr)
3027 struct ifnet *ifp;
3028 struct ifmediareq *ifmr;
3029 {
3030 struct dc_softc *sc;
3031 struct mii_data *mii;
3032 struct ifmedia *ifm;
3033
3034 sc = ifp->if_softc;
3035 mii = &sc->sc_mii;
3036 mii_pollstat(mii);
3037 ifm = &mii->mii_media;
3038 if (DC_IS_DAVICOM(sc)) {
3039 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) {
3040 ifmr->ifm_active = ifm->ifm_media;
3041 ifmr->ifm_status = 0;
3042 return;
3043 }
3044 }
3045 ifmr->ifm_active = mii->mii_media_active;
3046 ifmr->ifm_status = mii->mii_media_status;
3047 }
3048
3049 int
dc_ioctl(ifp,command,data)3050 dc_ioctl(ifp, command, data)
3051 struct ifnet *ifp;
3052 u_long command;
3053 caddr_t data;
3054 {
3055 struct dc_softc *sc = ifp->if_softc;
3056 struct ifreq *ifr = (struct ifreq *) data;
3057 struct ifaddr *ifa = (struct ifaddr *)data;
3058 struct mii_data *mii;
3059 int s, error = 0;
3060
3061 s = splimp();
3062
3063 if ((error = ether_ioctl(ifp, &sc->sc_arpcom, command, data)) > 0) {
3064 splx(s);
3065 return (error);
3066 }
3067
3068 switch(command) {
3069 case SIOCSIFADDR:
3070 ifp->if_flags |= IFF_UP;
3071 switch (ifa->ifa_addr->sa_family) {
3072 case AF_INET:
3073 dc_init(sc);
3074 arp_ifinit(&sc->sc_arpcom, ifa);
3075 break;
3076 default:
3077 dc_init(sc);
3078 break;
3079 }
3080 break;
3081 case SIOCSIFFLAGS:
3082 if (ifp->if_flags & IFF_UP) {
3083 if (ifp->if_flags & IFF_RUNNING &&
3084 ifp->if_flags & IFF_PROMISC &&
3085 !(sc->dc_if_flags & IFF_PROMISC)) {
3086 dc_setfilt(sc);
3087 } else if (ifp->if_flags & IFF_RUNNING &&
3088 !(ifp->if_flags & IFF_PROMISC) &&
3089 sc->dc_if_flags & IFF_PROMISC) {
3090 dc_setfilt(sc);
3091 } else if (!(ifp->if_flags & IFF_RUNNING)) {
3092 sc->dc_txthresh = 0;
3093 dc_init(sc);
3094 }
3095 } else {
3096 if (ifp->if_flags & IFF_RUNNING)
3097 dc_stop(sc);
3098 }
3099 sc->dc_if_flags = ifp->if_flags;
3100 error = 0;
3101 break;
3102 case SIOCSIFMTU:
3103 if (ifr->ifr_mtu > ETHERMTU || ifr->ifr_mtu < ETHERMIN) {
3104 error = EINVAL;
3105 } else if (ifp->if_mtu != ifr->ifr_mtu) {
3106 ifp->if_mtu = ifr->ifr_mtu;
3107 }
3108 break;
3109 case SIOCADDMULTI:
3110 case SIOCDELMULTI:
3111 error = (command == SIOCADDMULTI) ?
3112 ether_addmulti(ifr, &sc->sc_arpcom) :
3113 ether_delmulti(ifr, &sc->sc_arpcom);
3114
3115 if (error == ENETRESET) {
3116 /*
3117 * Multicast list has changed; set the hardware
3118 * filter accordingly.
3119 */
3120 if (ifp->if_flags & IFF_RUNNING)
3121 dc_setfilt(sc);
3122 error = 0;
3123 }
3124 break;
3125 case SIOCGIFMEDIA:
3126 case SIOCSIFMEDIA:
3127 mii = &sc->sc_mii;
3128 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
3129 #ifdef SRM_MEDIA
3130 if (sc->dc_srm_media)
3131 sc->dc_srm_media = 0;
3132 #endif
3133 break;
3134 default:
3135 error = EINVAL;
3136 break;
3137 }
3138
3139 splx(s);
3140
3141 return (error);
3142 }
3143
3144 void
dc_watchdog(ifp)3145 dc_watchdog(ifp)
3146 struct ifnet *ifp;
3147 {
3148 struct dc_softc *sc;
3149
3150 sc = ifp->if_softc;
3151
3152 ifp->if_oerrors++;
3153 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname);
3154
3155 dc_stop(sc);
3156 dc_reset(sc);
3157 dc_init(sc);
3158
3159 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0)
3160 dc_start(ifp);
3161 }
3162
3163 /*
3164 * Stop the adapter and free any mbufs allocated to the
3165 * RX and TX lists.
3166 */
3167 void
dc_stop(sc)3168 dc_stop(sc)
3169 struct dc_softc *sc;
3170 {
3171 struct ifnet *ifp;
3172 int i;
3173
3174 ifp = &sc->sc_arpcom.ac_if;
3175 ifp->if_timer = 0;
3176
3177 timeout_del(&sc->dc_tick_tmo);
3178
3179 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3180
3181 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON));
3182 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3183 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000);
3184 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000);
3185 sc->dc_link = 0;
3186
3187 /*
3188 * Free data in the RX lists.
3189 */
3190 for (i = 0; i < DC_RX_LIST_CNT; i++) {
3191 if (sc->dc_cdata.dc_rx_chain[i].sd_map->dm_nsegs != 0) {
3192 bus_dmamap_t map = sc->dc_cdata.dc_rx_chain[i].sd_map;
3193
3194 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
3195 BUS_DMASYNC_POSTREAD);
3196 bus_dmamap_unload(sc->sc_dmat, map);
3197 }
3198 if (sc->dc_cdata.dc_rx_chain[i].sd_mbuf != NULL) {
3199 m_freem(sc->dc_cdata.dc_rx_chain[i].sd_mbuf);
3200 sc->dc_cdata.dc_rx_chain[i].sd_mbuf = NULL;
3201 }
3202 }
3203 bzero((char *)&sc->dc_ldata->dc_rx_list,
3204 sizeof(sc->dc_ldata->dc_rx_list));
3205
3206 /*
3207 * Free the TX list buffers.
3208 */
3209 for (i = 0; i < DC_TX_LIST_CNT; i++) {
3210 if (sc->dc_cdata.dc_tx_chain[i].sd_map->dm_nsegs != 0) {
3211 bus_dmamap_t map = sc->dc_cdata.dc_tx_chain[i].sd_map;
3212
3213 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
3214 BUS_DMASYNC_POSTWRITE);
3215 bus_dmamap_unload(sc->sc_dmat, map);
3216 }
3217 if (sc->dc_cdata.dc_tx_chain[i].sd_mbuf != NULL) {
3218 if (sc->dc_ldata->dc_tx_list[i].dc_ctl &
3219 htole32(DC_TXCTL_SETUP)) {
3220 sc->dc_cdata.dc_tx_chain[i].sd_mbuf = NULL;
3221 continue;
3222 }
3223 m_freem(sc->dc_cdata.dc_tx_chain[i].sd_mbuf);
3224 sc->dc_cdata.dc_tx_chain[i].sd_mbuf = NULL;
3225 }
3226 }
3227 bzero((char *)&sc->dc_ldata->dc_tx_list,
3228 sizeof(sc->dc_ldata->dc_tx_list));
3229
3230 bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap,
3231 0, sc->sc_listmap->dm_mapsize,
3232 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3233 }
3234
3235 /*
3236 * Stop all chip I/O so that the kernel's probe routines don't
3237 * get confused by errant DMAs when rebooting.
3238 */
3239 void
dc_shutdown(v)3240 dc_shutdown(v)
3241 void *v;
3242 {
3243 struct dc_softc *sc = (struct dc_softc *)v;
3244
3245 dc_stop(sc);
3246 }
3247
3248 void
dc_power(why,arg)3249 dc_power(why, arg)
3250 int why;
3251 void *arg;
3252 {
3253 struct dc_softc *sc = arg;
3254 struct ifnet *ifp;
3255 int s;
3256
3257 s = splimp();
3258 if (why != PWR_RESUME)
3259 dc_stop(sc);
3260 else {
3261 ifp = &sc->sc_arpcom.ac_if;
3262 if (ifp->if_flags & IFF_UP)
3263 dc_init(sc);
3264 }
3265 splx(s);
3266 }
3267
3268 struct cfdriver dc_cd = {
3269 0, "dc", DV_IFNET
3270 };
3271