1 /* $OpenBSD: anreg.h,v 1.9 2003/10/21 18:58:48 jmc Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: src/sys/dev/an/if_anreg.h,v 1.9 2001/07/27 16:05:21 brooks Exp $ 35 */ 36 37 #pragma pack(1) 38 39 #define AN_TIMEOUT 65536 40 41 /* Default network name: empty string */ 42 #define AN_DEFAULT_NETNAME "" 43 44 /* The nodename must be less than 16 bytes */ 45 #define AN_DEFAULT_NODENAME "OpenBSD" 46 47 #define AN_DEFAULT_IBSS "OpenBSD IBSS" 48 49 /* 50 * register space access macros 51 */ 52 #define CSR_WRITE_2(sc, reg, val) \ 53 bus_space_write_2(sc->an_btag, sc->an_bhandle, reg, val) 54 55 #define CSR_READ_2(sc, reg) \ 56 bus_space_read_2(sc->an_btag, sc->an_bhandle, reg) 57 58 #define CSR_WRITE_1(sc, reg, val) \ 59 bus_space_write_1(sc->an_btag, sc->an_bhandle, reg, val) 60 61 #define CSR_READ_1(sc, reg) \ 62 bus_space_read_1(sc->an_btag, sc->an_bhandle, reg) 63 64 /* 65 * Size of Aironet I/O space. 66 */ 67 #define AN_IOSIZ 0x40 68 69 /* 70 * Hermes register definitions and what little I know about them. 71 */ 72 73 /* Hermes command/status registers. */ 74 #define AN_COMMAND 0x00 75 #define AN_PARAM0 0x02 76 #define AN_PARAM1 0x04 77 #define AN_PARAM2 0x06 78 #define AN_STATUS 0x08 79 #define AN_RESP0 0x0A 80 #define AN_RESP1 0x0C 81 #define AN_RESP2 0x0E 82 #define AN_LINKSTAT 0x10 83 84 /* Command register */ 85 #define AN_CMD_BUSY 0x8000 /* busy bit */ 86 #define AN_CMD_NO_ACK 0x0080 /* don't acknowledge command */ 87 #define AN_CMD_CODE_MASK 0x003F 88 #define AN_CMD_QUAL_MASK 0x7F00 89 90 /* Command codes */ 91 #define AN_CMD_NOOP 0x0000 /* no-op */ 92 #define AN_CMD_ENABLE 0x0001 /* enable */ 93 #define AN_CMD_DISABLE 0x0002 /* disable */ 94 #define AN_CMD_FORCE_SYNCLOSS 0x0003 /* force loss of sync */ 95 #define AN_CMD_FW_RESTART 0x0004 /* firmware resrart */ 96 #define AN_CMD_HOST_SLEEP 0x0005 97 #define AN_CMD_MAGIC_PKT 0x0006 98 #define AN_CMD_READCFG 0x0008 99 #define AN_CMD_SET_MODE 0x0009 100 #define AN_CMD_ALLOC_MEM 0x000A /* allocate NIC memory */ 101 #define AN_CMD_TX 0x000B /* transmit */ 102 #define AN_CMD_DEALLOC_MEM 0x000C 103 #define AN_CMD_NOOP2 0x0010 104 #define AN_CMD_ACCESS 0x0021 105 #define AN_CMD_ALLOC_BUF 0x0028 106 #define AN_CMD_PSP_NODES 0x0030 107 #define AN_CMD_SET_PHYREG 0x003E 108 #define AN_CMD_TX_TEST 0x003F 109 #define AN_CMD_SLEEP 0x0085 110 #define AN_CMD_SAVECFG 0x0108 111 112 /* 113 * Reclaim qualifier bit, applicable to the 114 * TX command. 115 */ 116 #define AN_RECLAIM 0x0100 /* reclaim NIC memory */ 117 118 /* 119 * ACCESS command qualifier bits. 120 */ 121 #define AN_ACCESS_READ 0x0000 122 #define AN_ACCESS_WRITE 0x0100 123 124 /* 125 * PROGRAM command qualifier bits. 126 */ 127 #define AN_PROGRAM_DISABLE 0x0000 128 #define AN_PROGRAM_ENABLE_RAM 0x0100 129 #define AN_PROGRAM_ENABLE_NVRAM 0x0200 130 #define AN_PROGRAM_NVRAM 0x0300 131 132 /* Status register values */ 133 #define AN_STAT_CMD_CODE 0x003F 134 #define AN_STAT_CMD_RESULT 0x7F00 135 136 /* Linkstat register */ 137 #define AN_LINKSTAT_ASSOCIATED 0x0400 138 #define AN_LINKSTAT_AUTHFAIL 0x0300 139 #define AN_LINKSTAT_ASSOC_FAIL 0x8400 140 #define AN_LINKSTAT_DISASSOC 0x8200 141 #define AN_LINKSTAT_DEAUTH 0x8100 142 #define AN_LINKSTAT_SYNCLOST_TSF 0x8004 143 #define AN_LINKSTAT_SYNCLOST_HOSTREQ 0x8003 144 #define AN_LINKSTAT_SYNCLOST_AVGRETRY 0x8002 145 #define AN_LINKSTAT_SYNCLOST_MAXRETRY 0x8001 146 #define AN_LINKSTAT_SYNCLOST_MISSBEACON 0x8000 147 148 /* memory handle management registers */ 149 #define AN_RX_FID 0x20 150 #define AN_ALLOC_FID 0x22 151 #define AN_TX_CMP_FID 0x24 152 153 /* 154 * Buffer Access Path (BAP) registers. 155 * These are I/O channels. I believe you can use each one for 156 * any desired purpose independently of the other. In general 157 * though, we use BAP1 for reading and writing LTV records and 158 * reading received data frames, and BAP0 for writing transmit 159 * frames. This is a convention though, not a rule. 160 */ 161 #define AN_SEL0 0x18 162 #define AN_SEL1 0x1A 163 #define AN_OFF0 0x1C 164 #define AN_OFF1 0x1E 165 #define AN_DATA0 0x36 166 #define AN_DATA1 0x38 167 #define AN_BAP0 AN_DATA0 168 #define AN_BAP1 AN_DATA1 169 170 #define AN_OFF_BUSY 0x8000 171 #define AN_OFF_ERR 0x4000 172 #define AN_OFF_DONE 0x2000 173 #define AN_OFF_DATAOFF 0x0FFF 174 175 /* Event registers */ 176 #define AN_EVENT_STAT 0x30 /* Event status */ 177 #define AN_INT_EN 0x32 /* Interrupt enable/disable */ 178 #define AN_EVENT_ACK 0x34 /* Ack event */ 179 180 /* Events */ 181 #define AN_EV_CLR_STUCK_BUSY 0x4000 /* clear stuck busy bit */ 182 #define AN_EV_WAKEREQUEST 0x2000 /* awaken from PSP mode */ 183 #define AN_EV_AWAKE 0x0100 /* station woke up from PSP mode*/ 184 #define AN_EV_LINKSTAT 0x0080 /* link status available */ 185 #define AN_EV_CMD 0x0010 /* command completed */ 186 #define AN_EV_ALLOC 0x0008 /* async alloc/reclaim completed */ 187 #define AN_EV_TX_EXC 0x0004 /* async xmit completed with failure */ 188 #define AN_EV_TX 0x0002 /* async xmit completed successfully */ 189 #define AN_EV_RX 0x0001 /* async rx completed */ 190 191 #define AN_INTRS \ 192 (AN_EV_RX|AN_EV_TX|AN_EV_TX_EXC|AN_EV_ALLOC|AN_EV_LINKSTAT) 193 194 /* Host software registers */ 195 #define AN_SW0 0x28 196 #define AN_SW1 0x2A 197 #define AN_SW2 0x2C 198 #define AN_SW3 0x2E 199 200 #define AN_CNTL 0x14 201 202 #define AN_CNTL_AUX_ENA 0xC000 203 #define AN_CNTL_AUX_ENA_STAT 0xC000 204 #define AN_CNTL_AUX_DIS_STAT 0x0000 205 #define AN_CNTL_AUX_ENA_CNTL 0x8000 206 #define AN_CNTL_AUX_DIS_CNTL 0x4000 207 208 #define AN_AUX_PAGE 0x3A 209 #define AN_AUX_OFFSET 0x3C 210 #define AN_AUX_DATA 0x3E 211 212 /* 213 * Length, Type, Value (LTV) record definitions and RID values. 214 */ 215 struct an_ltv_gen { 216 u_int16_t an_len; 217 u_int16_t an_type; 218 u_int16_t an_val[1]; 219 }; 220 221 #define AN_OPMODE_IBSS_ADHOC 0x0000 222 #define AN_OPMODE_INFRASTRUCTURE_STATION 0x0001 223 #define AN_OPMODE_AP 0x0002 224 #define AN_OPMODE_AP_REPEATER 0x0003 225 #define AN_OPMODE_UNMODIFIED_PAYLOAD 0x0100 226 #define AN_OPMODE_AIRONET_EXTENSIONS 0x0200 227 #define AN_OPMODE_AP_EXTENSIONS 0x0400 228 229 #define AN_RXMODE_BC_MC_ADDR 0x0000 230 #define AN_RXMODE_BC_ADDR 0x0001 231 #define AN_RXMODE_ADDR 0x0002 232 #define AN_RXMODE_80211_MONITOR_CURBSS 0x0003 233 #define AN_RXMODE_80211_MONITOR_ANYBSS 0x0004 234 #define AN_RXMODE_LAN_MONITOR_CURBSS 0x0005 235 #define AN_RXMODE_NO_8023_HEADER 0x0100 236 237 #define AN_RATE_1MBPS 0x0002 238 #define AN_RATE_2MBPS 0x0004 239 #define AN_RATE_5_5MBPS 0x000B 240 #define AN_RATE_11MBPS 0x0016 241 242 #define AN_DEVTYPE_PC4500 0x0065 243 #define AN_DEVTYPE_PC4800 0x006D 244 245 #define AN_SCANMODE_ACTIVE 0x0000 246 #define AN_SCANMODE_PASSIVE 0x0001 247 #define AN_SCANMODE_AIRONET_ACTIVE 0x0002 248 249 #define AN_AUTHTYPE_NONE 0x0000 250 #define AN_AUTHTYPE_OPEN 0x0001 251 #define AN_AUTHTYPE_SHAREDKEY 0x0002 252 #define AN_AUTHTYPE_PRIVACY_IN_USE 0x0100 253 #define AN_AUTHTYPE_ALLOW_UNENCRYPTED 0x0200 254 255 #define AN_PSAVE_NONE 0x0000 256 #define AN_PSAVE_CAM 0x0001 257 #define AN_PSAVE_PSP 0x0002 258 #define AN_PSAVE_PSP_CAM 0x0003 259 260 #define AN_RADIOTYPE_80211_FH 0x0001 261 #define AN_RADIOTYPE_80211_DS 0x0002 262 #define AN_RADIOTYPE_LM2000_DS 0x0004 263 264 #define AN_DIVERSITY_FACTORY_DEFAULT 0x0000 265 #define AN_DIVERSITY_ANTENNA_1_ONLY 0x0001 266 #define AN_DIVERSITY_ANTENNA_2_ONLY 0x0002 267 #define AN_DIVERSITY_ANTENNA_1_AND_2 0x0003 268 269 #define AN_TXPOWER_FACTORY_DEFAULT 0x0000 270 #define AN_TXPOWER_50MW 50 271 #define AN_TXPOWER_100MW 100 272 #define AN_TXPOWER_250MW 250 273 274 #define AN_DEF_SSID_LEN 7 275 #define AN_DEF_SSID "tsunami" 276 277 278 #define AN_ENCAP_ACTION_RX 0x0001 279 #define AN_ENCAP_ACTION_TX 0x0002 280 281 #define AN_RXENCAP_NONE 0x0000 282 #define AN_RXENCAP_RFC1024 0x0001 283 284 #define AN_TXENCAP_RFC1024 0x0000 285 #define AN_TXENCAP_80211 0x0002 286 287 #define AN_STATUS_OPMODE_CONFIGURED 0x0001 288 #define AN_STATUS_OPMODE_MAC_ENABLED 0x0002 289 #define AN_STATUS_OPMODE_RX_ENABLED 0x0004 290 #define AN_STATUS_OPMODE_IN_SYNC 0x0010 291 #define AN_STATUS_OPMODE_ASSOCIATED 0x0020 292 #define AN_STATUS_OPMODE_ERROR 0x8000 293 294 295 /* 296 * Statistics 297 */ 298 #define AN_RID_16BITS_CUM 0xFF60 /* Cumulative 16-bit stats counters */ 299 #define AN_RID_16BITS_DELTA 0xFF61 /* 16-bit stats (since last clear) */ 300 #define AN_RID_16BITS_DELTACLR 0xFF62 /* 16-bit stats, clear on read */ 301 #define AN_RID_32BITS_CUM 0xFF68 /* Cumulative 32-bit stats counters */ 302 #define AN_RID_32BITS_DELTA 0xFF69 /* 32-bit stats (since last clear) */ 303 #define AN_RID_32BITS_DELTACLR 0xFF6A /* 32-bit stats, clear on read */ 304 305 /* 306 * Receive frame structure. 307 */ 308 struct an_rxframe { 309 u_int32_t an_rx_time; /* 0x00 */ 310 u_int16_t an_rx_status; /* 0x04 */ 311 u_int16_t an_rx_payload_len; /* 0x06 */ 312 u_int8_t an_rsvd0; /* 0x08 */ 313 u_int8_t an_rx_signal_strength; /* 0x09 */ 314 u_int8_t an_rx_rate; /* 0x0A */ 315 u_int8_t an_rx_chan; /* 0x0B */ 316 u_int8_t an_rx_assoc_cnt; /* 0x0C */ 317 u_int8_t an_rsvd1[3]; /* 0x0D */ 318 u_int8_t an_plcp_hdr[4]; /* 0x10 */ 319 u_int16_t an_frame_ctl; /* 0x14 */ 320 u_int16_t an_duration; /* 0x16 */ 321 u_int8_t an_addr1[6]; /* 0x18 */ 322 u_int8_t an_addr2[6]; /* 0x1E */ 323 u_int8_t an_addr3[6]; /* 0x24 */ 324 u_int16_t an_seq_ctl; /* 0x2A */ 325 u_int8_t an_addr4[6]; /* 0x2C */ 326 u_int16_t an_gaplen; /* 0x32 */ 327 }; 328 329 #define AN_RXGAP_MAX 8 330 331 /* 332 * Transmit frame structure. 333 */ 334 struct an_txframe { 335 u_int32_t an_tx_sw; /* 0x00 */ 336 u_int16_t an_tx_status; /* 0x04 */ 337 u_int16_t an_tx_payload_len; /* 0x06 */ 338 u_int16_t an_tx_ctl; /* 0x08 */ 339 u_int16_t an_tx_assoc_id; /* 0x0A */ 340 u_int16_t an_tx_retry; /* 0x0C */ 341 u_int8_t an_tx_assoc_cnt; /* 0x0E */ 342 u_int8_t an_tx_rate; /* 0x0F */ 343 u_int8_t an_tx_max_long_retries; /* 0x10 */ 344 u_int8_t an_tx_max_short_retries; /*0x11 */ 345 u_int8_t an_rsvd0[2]; /* 0x12 */ 346 u_int16_t an_frame_ctl; /* 0x14 */ 347 u_int16_t an_duration; /* 0x16 */ 348 u_int8_t an_addr1[6]; /* 0x18 */ 349 u_int8_t an_addr2[6]; /* 0x1E */ 350 u_int8_t an_addr3[6]; /* 0x24 */ 351 u_int16_t an_seq_ctl; /* 0x2A */ 352 u_int8_t an_addr4[6]; /* 0x2C */ 353 u_int16_t an_gaplen; /* 0x32 */ 354 }; 355 356 struct an_rxframe_802_3 { 357 u_int16_t an_rx_802_3_status; /* 0x34 */ 358 u_int16_t an_rx_802_3_payload_len;/* 0x36 */ 359 u_int8_t an_rx_dst_addr[6]; /* 0x38 */ 360 u_int8_t an_rx_src_addr[6]; /* 0x3E */ 361 }; 362 #define AN_RXGAP_MAX 8 363 364 365 /* 366 * Transmit 802.3 header structure. 367 */ 368 struct an_txframe_802_3 { 369 u_int16_t an_tx_802_3_status; /* 0x34 */ 370 u_int16_t an_tx_802_3_payload_len;/* 0x36 */ 371 u_int8_t an_tx_dst_addr[6]; /* 0x38 */ 372 u_int8_t an_tx_src_addr[6]; /* 0x3E */ 373 }; 374 375 #define AN_TXSTAT_EXCESS_RETRY 0x0002 376 #define AN_TXSTAT_LIFE_EXCEEDED 0x0004 377 #define AN_TXSTAT_AID_FAIL 0x0008 378 #define AN_TXSTAT_MAC_DISABLED 0x0010 379 #define AN_TXSTAT_ASSOC_LOST 0x0020 380 381 #define AN_TXCTL_RSVD 0x0001 382 #define AN_TXCTL_TXOK_INTR 0x0002 383 #define AN_TXCTL_TXERR_INTR 0x0004 384 #define AN_TXCTL_HEADER_TYPE 0x0008 385 #define AN_TXCTL_PAYLOAD_TYPE 0x0010 386 #define AN_TXCTL_NORELEASE 0x0020 387 #define AN_TXCTL_NORETRIES 0x0040 388 #define AN_TXCTL_CLEAR_AID 0x0080 389 #define AN_TXCTL_STRICT_ORDER 0x0100 390 #define AN_TXCTL_USE_RTS 0x0200 391 392 #define AN_HEADERTYPE_8023 0x0000 393 #define AN_HEADERTYPE_80211 0x0008 394 395 #define AN_PAYLOADTYPE_ETHER 0x0000 396 #define AN_PAYLOADTYPE_LLC 0x0010 397 398 #define AN_TXCTL_80211 \ 399 (AN_TXCTL_TXOK_INTR|AN_TXCTL_TXERR_INTR|AN_HEADERTYPE_80211| \ 400 AN_PAYLOADTYPE_LLC|AN_TXCTL_NORELEASE) 401 402 #define AN_TXCTL_8023 \ 403 (AN_TXCTL_TXOK_INTR|AN_TXCTL_TXERR_INTR|AN_HEADERTYPE_8023| \ 404 AN_PAYLOADTYPE_ETHER|AN_TXCTL_NORELEASE) 405 406 #define AN_TXGAP_80211 0 407 #define AN_TXGAP_8023 0 408 409 struct an_802_3_hdr { 410 u_int16_t an_8023_status; 411 u_int16_t an_8023_payload_len; 412 u_int8_t an_8023_dst_addr[6]; 413 u_int8_t an_8023_src_addr[6]; 414 u_int16_t an_8023_dat[3]; /* SNAP header */ 415 u_int16_t an_8023_type; 416 }; 417 418 struct an_snap_hdr { 419 u_int16_t an_snap_dat[3]; /* SNAP header */ 420 u_int16_t an_snap_type; 421 }; 422 423 #define AN_INC(x, y) (x) = (x + 1) % y 424 425 #define AN_802_3_OFFSET 0x2E 426 #define AN_802_11_OFFSET 0x44 427 #define AN_802_11_OFFSET_RAW 0x3C 428 429 #define AN_STAT_BADCRC 0x0001 430 #define AN_STAT_UNDECRYPTABLE 0x0002 431 #define AN_STAT_ERRSTAT 0x0003 432 #define AN_STAT_MAC_PORT 0x0700 433 #define AN_STAT_1042 0x2000 /* RFC1042 encoded */ 434 #define AN_STAT_TUNNEL 0x4000 /* Bridge-tunnel encoded */ 435 #define AN_STAT_WMP_MSG 0x6000 /* WaveLAN-II management protocol */ 436 #define AN_RXSTAT_MSG_TYPE 0xE000 437 438 #define AN_ENC_TX_802_3 0x00 439 #define AN_ENC_TX_802_11 0x11 440 #define AN_ENC_TX_E_II 0x0E 441 442 #define AN_ENC_TX_1042 0x00 443 #define AN_ENC_TX_TUNNEL 0xF8 444 445 #define AN_TXCNTL_MACPORT 0x00FF 446 #define AN_TXCNTL_STRUCTTYPE 0xFF00 447 448 #define AN_RID_WEP_TEMP 0xFF15 449 #define AN_RID_WEP_PERM 0xFF16 450 451 /* 452 * SNAP (sub-network access protocol) constants for transmission 453 * of IP datagrams over IEEE 802 networks, taken from RFC1042. 454 * We need these for the LLC/SNAP header fields in the TX/RX frame 455 * structure. 456 */ 457 #define AN_SNAP_K1 0xaa /* assigned global SAP for SNAP */ 458 #define AN_SNAP_K2 0x00 459 #define AN_SNAP_CONTROL 0x03 /* unnumbered information format */ 460 #define AN_SNAP_WORD0 (AN_SNAP_K1 | (AN_SNAP_K1 << 8)) 461 #define AN_SNAP_WORD1 (AN_SNAP_K2 | (AN_SNAP_CONTROL << 8)) 462 #define AN_SNAPHDR_LEN 0x6 463 464 465 466 #pragma pack() 467