1 /* $MirOS: src/sys/dev/ic/adwlib.c,v 1.2 2005/03/06 21:27:37 tg Exp $ */
2 /* $OpenBSD: adwlib.c,v 1.19 2004/01/09 21:32:23 brad Exp $ */
3 /* $NetBSD: adwlib.c,v 1.20 2000/07/04 04:17:03 itojun Exp $ */
4
5 /*
6 * Low level routines for the Advanced Systems Inc. SCSI controllers chips
7 *
8 * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc.
9 * All rights reserved.
10 *
11 * Author: Baldassare Dante Profeta <dante@mclink.it>
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
21 * 3. All advertising materials mentioning features or use of this software
22 * must display the following acknowledgement:
23 * This product includes software developed by the NetBSD
24 * Foundation, Inc. and its contributors.
25 * 4. Neither the name of The NetBSD Foundation nor the names of its
26 * contributors may be used to endorse or promote products derived
27 * from this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
31 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
32 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
33 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
34 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
37 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
39 * POSSIBILITY OF SUCH DAMAGE.
40 */
41 /*
42 * Ported from:
43 */
44 /*
45 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
46 *
47 * Copyright (c) 1995-2000 Advanced System Products, Inc.
48 * All Rights Reserved.
49 *
50 * Redistribution and use in source and binary forms, with or without
51 * modification, are permitted provided that redistributions of source
52 * code retain the above copyright notice and this comment without
53 * modification.
54 */
55
56 #include <sys/types.h>
57 #include <sys/param.h>
58 #include <sys/systm.h>
59 #include <sys/malloc.h>
60 #include <sys/kernel.h>
61 #include <sys/queue.h>
62 #include <sys/device.h>
63
64 #include <machine/bus.h>
65 #include <machine/intr.h>
66
67 #include <scsi/scsi_all.h>
68 #include <scsi/scsiconf.h>
69
70 #include <dev/pci/pcidevs.h>
71
72 #include <dev/ic/adwlib.h>
73 #include <dev/microcode/adw/adwmcode.h>
74 #include <dev/ic/adw.h>
75
76
77 int AdwRamSelfTest(bus_space_tag_t, bus_space_handle_t, u_int8_t);
78 int AdwLoadMCode(bus_space_tag_t, bus_space_handle_t, u_int16_t *,
79 u_int8_t);
80 int AdwASC3550Cabling(bus_space_tag_t, bus_space_handle_t, ADW_DVC_CFG *);
81 int AdwASC38C0800Cabling(bus_space_tag_t, bus_space_handle_t,
82 ADW_DVC_CFG *);
83 int AdwASC38C1600Cabling(bus_space_tag_t, bus_space_handle_t,
84 ADW_DVC_CFG *);
85
86 u_int16_t AdwGetEEPROMConfig(bus_space_tag_t, bus_space_handle_t,
87 ADW_EEPROM *);
88 void AdwSetEEPROMConfig(bus_space_tag_t, bus_space_handle_t,
89 ADW_EEPROM *);
90 u_int16_t AdwReadEEPWord(bus_space_tag_t, bus_space_handle_t, int);
91 void AdwWaitEEPCmd(bus_space_tag_t, bus_space_handle_t);
92
93 void AdwInquiryHandling(ADW_SOFTC *, ADW_SCSI_REQ_Q *);
94
95 void AdwSleepMilliSecond(u_int32_t);
96 void AdwDelayMicroSecond(u_int32_t);
97
98
99 /*
100 * EEPROM Configuration.
101 *
102 * All drivers should use this structure to set the default EEPROM
103 * configuration. The BIOS now uses this structure when it is built.
104 * Additional structure information can be found in adwlib.h where
105 * the structure is defined.
106 */
107 const static ADW_EEPROM adw_3550_Default_EEPROM = {
108 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
109 0x0000, /* 01 cfg_msw */
110 0xFFFF, /* 02 disc_enable */
111 0xFFFF, /* 03 wdtr_able */
112 { 0xFFFF }, /* 04 sdtr_able */
113 0xFFFF, /* 05 start_motor */
114 0xFFFF, /* 06 tagqng_able */
115 0xFFFF, /* 07 bios_scan */
116 0, /* 08 scam_tolerant */
117 7, /* 09 adapter_scsi_id */
118 0, /* bios_boot_delay */
119 3, /* 10 scsi_reset_delay */
120 0, /* bios_id_lun */
121 0, /* 11 termination */
122 0, /* reserved1 */
123 0xFFE7, /* 12 bios_ctrl */
124 { 0xFFFF }, /* 13 ultra_able */
125 { 0 }, /* 14 reserved2 */
126 ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
127 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */
128 0, /* 16 dvc_cntl */
129 { 0 }, /* 17 bug_fix */
130 { 0,0,0 }, /* 18-20 serial_number[3] */
131 0, /* 21 check_sum */
132 { /* 22-29 oem_name[16] */
133 0,0,0,0,0,0,0,0,
134 0,0,0,0,0,0,0,0
135 },
136 0, /* 30 dvc_err_code */
137 0, /* 31 adw_err_code */
138 0, /* 32 adw_err_addr */
139 0, /* 33 saved_dvc_err_code */
140 0, /* 34 saved_adw_err_code */
141 0 /* 35 saved_adw_err_addr */
142 };
143
144 const static ADW_EEPROM adw_38C0800_Default_EEPROM = {
145 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
146 0x0000, /* 01 cfg_msw */
147 0xFFFF, /* 02 disc_enable */
148 0xFFFF, /* 03 wdtr_able */
149 { 0x4444 }, /* 04 sdtr_speed1 */
150 0xFFFF, /* 05 start_motor */
151 0xFFFF, /* 06 tagqng_able */
152 0xFFFF, /* 07 bios_scan */
153 0, /* 08 scam_tolerant */
154 7, /* 09 adapter_scsi_id */
155 0, /* bios_boot_delay */
156 3, /* 10 scsi_reset_delay */
157 0, /* bios_id_lun */
158 0, /* 11 termination_se */
159 0, /* termination_lvd */
160 0xFFE7, /* 12 bios_ctrl */
161 { 0x4444 }, /* 13 sdtr_speed2 */
162 { 0x4444 }, /* 14 sdtr_speed3 */
163 ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
164 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */
165 0, /* 16 dvc_cntl */
166 { 0x4444 }, /* 17 sdtr_speed4 */
167 { 0,0,0 }, /* 18-20 serial_number[3] */
168 0, /* 21 check_sum */
169 { /* 22-29 oem_name[16] */
170 0,0,0,0,0,0,0,0,
171 0,0,0,0,0,0,0,0
172 },
173 0, /* 30 dvc_err_code */
174 0, /* 31 adw_err_code */
175 0, /* 32 adw_err_addr */
176 0, /* 33 saved_dvc_err_code */
177 0, /* 34 saved_adw_err_code */
178 0, /* 35 saved_adw_err_addr */
179 { /* 36-55 reserved1[16] */
180 0,0,0,0,0,0,0,0,0,0,
181 0,0,0,0,0,0,0,0,0,0
182 },
183 0, /* 56 cisptr_lsw */
184 0, /* 57 cisprt_msw */
185 PCI_VENDOR_ADVSYS, /* 58 subsysvid */
186 PCI_PRODUCT_ADVSYS_U2W, /* 59 subsysid */
187 { 0,0,0,0 } /* 60-63 reserved2[4] */
188 };
189
190 const static ADW_EEPROM adw_38C1600_Default_EEPROM = {
191 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
192 0x0000, /* 01 cfg_msw */
193 0xFFFF, /* 02 disc_enable */
194 0xFFFF, /* 03 wdtr_able */
195 { 0x5555 }, /* 04 sdtr_speed1 */
196 0xFFFF, /* 05 start_motor */
197 0xFFFF, /* 06 tagqng_able */
198 0xFFFF, /* 07 bios_scan */
199 0, /* 08 scam_tolerant */
200 7, /* 09 adapter_scsi_id */
201 0, /* bios_boot_delay */
202 3, /* 10 scsi_reset_delay */
203 0, /* bios_id_lun */
204 0, /* 11 termination_se */
205 0, /* termination_lvd */
206 0xFFE7, /* 12 bios_ctrl */
207 { 0x5555 }, /* 13 sdtr_speed2 */
208 { 0x5555 }, /* 14 sdtr_speed3 */
209 ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
210 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */
211 0, /* 16 dvc_cntl */
212 { 0x5555 }, /* 17 sdtr_speed4 */
213 { 0,0,0 }, /* 18-20 serial_number[3] */
214 0, /* 21 check_sum */
215 { /* 22-29 oem_name[16] */
216 0,0,0,0,0,0,0,0,
217 0,0,0,0,0,0,0,0
218 },
219 0, /* 30 dvc_err_code */
220 0, /* 31 adw_err_code */
221 0, /* 32 adw_err_addr */
222 0, /* 33 saved_dvc_err_code */
223 0, /* 34 saved_adw_err_code */
224 0, /* 35 saved_adw_err_addr */
225 { /* 36-55 reserved1[16] */
226 0,0,0,0,0,0,0,0,0,0,
227 0,0,0,0,0,0,0,0,0,0
228 },
229 0, /* 56 cisptr_lsw */
230 0, /* 57 cisprt_msw */
231 PCI_VENDOR_ADVSYS, /* 58 subsysvid */
232 PCI_PRODUCT_ADVSYS_U3W, /* 59 subsysid */
233 { 0,0,0,0 } /* 60-63 reserved2[4] */
234 };
235
236
237 /*
238 * Read the board's EEPROM configuration. Set fields in ADW_SOFTC and
239 * ADW_DVC_CFG based on the EEPROM settings. The chip is stopped while
240 * all of this is done.
241 *
242 * For a non-fatal error return a warning code. If there are no warnings
243 * then 0 is returned.
244 *
245 * Note: Chip is stopped on entry.
246 */
247 int
AdwInitFromEEPROM(sc)248 AdwInitFromEEPROM(sc)
249 ADW_SOFTC *sc;
250 {
251 bus_space_tag_t iot = sc->sc_iot;
252 bus_space_handle_t ioh = sc->sc_ioh;
253 ADW_EEPROM eep_config;
254 u_int16_t warn_code;
255 u_int16_t sdtr_speed = 0;
256 u_int8_t tid, termination;
257 int i, j;
258
259
260 warn_code = 0;
261
262 /*
263 * Read the board's EEPROM configuration.
264 *
265 * Set default values if a bad checksum is found.
266 *
267 * XXX - Don't handle big-endian access to EEPROM yet.
268 */
269 if (AdwGetEEPROMConfig(iot, ioh, &eep_config) != eep_config.check_sum) {
270 warn_code |= ADW_WARN_EEPROM_CHKSUM;
271
272 /*
273 * Set EEPROM default values.
274 */
275 switch(sc->chip_type) {
276 case ADW_CHIP_ASC3550:
277 eep_config = adw_3550_Default_EEPROM;
278 break;
279 case ADW_CHIP_ASC38C0800:
280 eep_config = adw_38C0800_Default_EEPROM;
281 break;
282 case ADW_CHIP_ASC38C1600:
283 eep_config = adw_38C1600_Default_EEPROM;
284
285 // XXX TODO!!! if (ASC_PCI_ID2FUNC(sc->cfg.pci_slot_info) != 0) {
286 if (sc->cfg.pci_slot_info != 0) {
287 u_int8_t lsw_msb;
288
289 lsw_msb = eep_config.cfg_lsw >> 8;
290 /*
291 * Set Function 1 EEPROM Word 0 MSB
292 *
293 * Clear the BIOS_ENABLE (bit 14) and
294 * INTAB (bit 11) EEPROM bits.
295 *
296 * Disable Bit 14 (BIOS_ENABLE) to fix
297 * SPARC Ultra 60 and old Mac system booting
298 * problem. The Expansion ROM must
299 * be disabled in Function 1 for these systems.
300 */
301 lsw_msb &= ~(((ADW_EEPROM_BIOS_ENABLE |
302 ADW_EEPROM_INTAB) >> 8) & 0xFF);
303 /*
304 * Set the INTAB (bit 11) if the GPIO 0 input
305 * indicates the Function 1 interrupt line is
306 * wired to INTA.
307 *
308 * Set/Clear Bit 11 (INTAB) from
309 * the GPIO bit 0 input:
310 * 1 - Function 1 intr line wired to INT A.
311 * 0 - Function 1 intr line wired to INT B.
312 *
313 * Note: Adapter boards always have Function 0
314 * wired to INTA.
315 * Put all 5 GPIO bits in input mode and then
316 * read their input values.
317 */
318 ADW_WRITE_BYTE_REGISTER(iot, ioh,
319 IOPB_GPIO_CNTL, 0);
320 if (ADW_READ_BYTE_REGISTER(iot, ioh,
321 IOPB_GPIO_DATA) & 0x01) {
322 /*
323 * Function 1 interrupt wired to INTA;
324 * Set EEPROM bit.
325 */
326 lsw_msb |= (ADW_EEPROM_INTAB >> 8)
327 & 0xFF;
328 }
329 eep_config.cfg_lsw &= 0x00FF;
330 eep_config.cfg_lsw |= lsw_msb << 8;
331 }
332 break;
333 }
334
335 /*
336 * Assume the 6 byte board serial number that was read
337 * from EEPROM is correct even if the EEPROM checksum
338 * failed.
339 */
340 for (i=2, j=1; i>=0; i--, j++) {
341 eep_config.serial_number[i] =
342 AdwReadEEPWord(iot, ioh, ADW_EEP_DVC_CFG_END - j);
343 }
344
345 AdwSetEEPROMConfig(iot, ioh, &eep_config);
346 }
347 /*
348 * Set sc and sc->cfg variables from the EEPROM configuration
349 * that was read.
350 *
351 * This is the mapping of EEPROM fields to Adw Library fields.
352 */
353 sc->wdtr_able = eep_config.wdtr_able;
354 if (sc->chip_type == ADW_CHIP_ASC3550) {
355 sc->sdtr_able = eep_config.sdtr1.sdtr_able;
356 sc->ultra_able = eep_config.sdtr2.ultra_able;
357 } else {
358 sc->sdtr_speed1 = eep_config.sdtr1.sdtr_speed1;
359 sc->sdtr_speed2 = eep_config.sdtr2.sdtr_speed2;
360 sc->sdtr_speed3 = eep_config.sdtr3.sdtr_speed3;
361 sc->sdtr_speed4 = eep_config.sdtr4.sdtr_speed4;
362 }
363 sc->ppr_able = 0;
364 sc->tagqng_able = eep_config.tagqng_able;
365 sc->cfg.disc_enable = eep_config.disc_enable;
366 sc->max_host_qng = eep_config.max_host_qng;
367 sc->max_dvc_qng = eep_config.max_dvc_qng;
368 sc->chip_scsi_id = (eep_config.adapter_scsi_id & ADW_MAX_TID);
369 sc->start_motor = eep_config.start_motor;
370 sc->scsi_reset_wait = eep_config.scsi_reset_delay;
371 sc->bios_ctrl = eep_config.bios_ctrl;
372 sc->no_scam = eep_config.scam_tolerant;
373 sc->cfg.serial1 = eep_config.serial_number[0];
374 sc->cfg.serial2 = eep_config.serial_number[1];
375 sc->cfg.serial3 = eep_config.serial_number[2];
376
377 if (sc->chip_type == ADW_CHIP_ASC38C0800 ||
378 sc->chip_type == ADW_CHIP_ASC38C1600) {
379 sc->sdtr_able = 0;
380 for (tid = 0; tid <= ADW_MAX_TID; tid++) {
381 if (tid == 0) {
382 sdtr_speed = sc->sdtr_speed1;
383 } else if (tid == 4) {
384 sdtr_speed = sc->sdtr_speed2;
385 } else if (tid == 8) {
386 sdtr_speed = sc->sdtr_speed3;
387 } else if (tid == 12) {
388 sdtr_speed = sc->sdtr_speed4;
389 }
390 if (sdtr_speed & ADW_MAX_TID) {
391 sc->sdtr_able |= (1 << tid);
392 }
393 sdtr_speed >>= 4;
394 }
395 }
396
397 /*
398 * Set the host maximum queuing (max. 253, min. 16) and the per device
399 * maximum queuing (max. 63, min. 4).
400 */
401 if (eep_config.max_host_qng > ADW_DEF_MAX_HOST_QNG) {
402 eep_config.max_host_qng = ADW_DEF_MAX_HOST_QNG;
403 } else if (eep_config.max_host_qng < ADW_DEF_MIN_HOST_QNG)
404 {
405 /* If the value is zero, assume it is uninitialized. */
406 if (eep_config.max_host_qng == 0) {
407 eep_config.max_host_qng = ADW_DEF_MAX_HOST_QNG;
408 } else {
409 eep_config.max_host_qng = ADW_DEF_MIN_HOST_QNG;
410 }
411 }
412
413 if (eep_config.max_dvc_qng > ADW_DEF_MAX_DVC_QNG) {
414 eep_config.max_dvc_qng = ADW_DEF_MAX_DVC_QNG;
415 } else if (eep_config.max_dvc_qng < ADW_DEF_MIN_DVC_QNG) {
416 /* If the value is zero, assume it is uninitialized. */
417 if (eep_config.max_dvc_qng == 0) {
418 eep_config.max_dvc_qng = ADW_DEF_MAX_DVC_QNG;
419 } else {
420 eep_config.max_dvc_qng = ADW_DEF_MIN_DVC_QNG;
421 }
422 }
423
424 /*
425 * If 'max_dvc_qng' is greater than 'max_host_qng', then
426 * set 'max_dvc_qng' to 'max_host_qng'.
427 */
428 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
429 eep_config.max_dvc_qng = eep_config.max_host_qng;
430 }
431
432 /*
433 * Set ADW_SOFTC 'max_host_qng' and 'max_dvc_qng'
434 * values based on possibly adjusted EEPROM values.
435 */
436 sc->max_host_qng = eep_config.max_host_qng;
437 sc->max_dvc_qng = eep_config.max_dvc_qng;
438
439
440 /*
441 * If the EEPROM 'termination' field is set to automatic (0), then set
442 * the ADW_SOFTC.cfg 'termination' field to automatic also.
443 *
444 * If the termination is specified with a non-zero 'termination'
445 * value check that a legal value is set and set the ADW_SOFTC.cfg
446 * 'termination' field appropriately.
447 */
448
449 switch(sc->chip_type) {
450 case ADW_CHIP_ASC3550:
451 sc->cfg.termination = 0; /* auto termination */
452 switch(eep_config.termination_se) {
453 case 3:
454 /* Enable manual control with low on / high on. */
455 sc->cfg.termination |= ADW_TERM_CTL_L;
456 case 2:
457 /* Enable manual control with low off / high on. */
458 sc->cfg.termination |= ADW_TERM_CTL_H;
459 case 1:
460 /* Enable manual control with low off / high off. */
461 sc->cfg.termination |= ADW_TERM_CTL_SEL;
462 case 0:
463 break;
464 default:
465 warn_code |= ADW_WARN_EEPROM_TERMINATION;
466 }
467 break;
468
469 case ADW_CHIP_ASC38C0800:
470 case ADW_CHIP_ASC38C1600:
471 switch(eep_config.termination_se) {
472 case 0:
473 /* auto termination for SE */
474 termination = 0;
475 break;
476 case 1:
477 /* Enable manual control with low off / high off. */
478 termination = 0;
479 break;
480 case 2:
481 /* Enable manual control with low off / high on. */
482 termination = ADW_TERM_SE_HI;
483 break;
484 case 3:
485 /* Enable manual control with low on / high on. */
486 termination = ADW_TERM_SE;
487 break;
488 default:
489 /*
490 * The EEPROM 'termination_se' field contains a
491 * bad value. Use automatic termination instead.
492 */
493 termination = 0;
494 warn_code |= ADW_WARN_EEPROM_TERMINATION;
495 }
496
497 switch(eep_config.termination_lvd) {
498 case 0:
499 /* auto termination for LVD */
500 sc->cfg.termination = termination;
501 break;
502 case 1:
503 /* Enable manual control with low off / high off. */
504 sc->cfg.termination = termination;
505 break;
506 case 2:
507 /* Enable manual control with low off / high on. */
508 sc->cfg.termination = termination | ADW_TERM_LVD_HI;
509 break;
510 case 3:
511 /* Enable manual control with low on / high on. */
512 sc->cfg.termination = termination | ADW_TERM_LVD;
513 break;
514 default:
515 /*
516 * The EEPROM 'termination_lvd' field contains a
517 * bad value. Use automatic termination instead.
518 */
519 sc->cfg.termination = termination;
520 warn_code |= ADW_WARN_EEPROM_TERMINATION;
521 }
522 break;
523 }
524
525 return warn_code;
526 }
527
528
529 /*
530 * Initialize the ASC-3550/ASC-38C0800/ASC-38C1600.
531 *
532 * On failure return the error code.
533 */
534 int
AdwInitDriver(sc)535 AdwInitDriver(sc)
536 ADW_SOFTC *sc;
537 {
538 bus_space_tag_t iot = sc->sc_iot;
539 bus_space_handle_t ioh = sc->sc_ioh;
540 u_int16_t error_code;
541 int word;
542 int i;
543 u_int16_t bios_mem[ADW_MC_BIOSLEN/2]; /* BIOS RISC Memory
544 0x40-0x8F. */
545 u_int16_t wdtr_able = 0, sdtr_able, ppr_able, tagqng_able;
546 u_int8_t max_cmd[ADW_MAX_TID + 1];
547 u_int8_t tid;
548
549
550 error_code = 0;
551
552 /*
553 * Save the RISC memory BIOS region before writing the microcode.
554 * The BIOS may already be loaded and using its RISC LRAM region
555 * so its region must be saved and restored.
556 *
557 * Note: This code makes the assumption, which is currently true,
558 * that a chip reset does not clear RISC LRAM.
559 */
560 for (i = 0; i < ADW_MC_BIOSLEN/2; i++) {
561 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_BIOSMEM+(2*i), bios_mem[i]);
562 }
563
564 /*
565 * Save current per TID negotiated values.
566 */
567 switch (sc->chip_type) {
568 case ADW_CHIP_ASC3550:
569 if (bios_mem[(ADW_MC_BIOS_SIGNATURE-ADW_MC_BIOSMEM)/2]==0x55AA){
570
571 u_int16_t bios_version, major, minor;
572
573 bios_version = bios_mem[(ADW_MC_BIOS_VERSION -
574 ADW_MC_BIOSMEM) / 2];
575 major = (bios_version >> 12) & 0xF;
576 minor = (bios_version >> 8) & 0xF;
577 if (major < 3 || (major == 3 && minor == 1)) {
578 /*
579 * BIOS 3.1 and earlier location of
580 * 'wdtr_able' variable.
581 */
582 ADW_READ_WORD_LRAM(iot, ioh, 0x120, wdtr_able);
583 } else {
584 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE,
585 wdtr_able);
586 }
587 }
588 break;
589
590 case ADW_CHIP_ASC38C1600:
591 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, ppr_able);
592 /* FALLTHROUGH */
593 case ADW_CHIP_ASC38C0800:
594 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, wdtr_able);
595 break;
596 }
597 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able);
598 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, tagqng_able);
599 for (tid = 0; tid <= ADW_MAX_TID; tid++) {
600 ADW_READ_BYTE_LRAM(iot, ioh, ADW_MC_NUMBER_OF_MAX_CMD + tid,
601 max_cmd[tid]);
602 }
603
604 /*
605 * Perform a RAM Built-In Self Test
606 */
607 if((error_code = AdwRamSelfTest(iot, ioh, sc->chip_type))) {
608 return error_code;
609 }
610
611 /*
612 * Load the Microcode
613 */
614 ;
615 if((error_code = AdwLoadMCode(iot, ioh, bios_mem, sc->chip_type))) {
616 return error_code;
617 }
618
619 /*
620 * Read microcode version and date.
621 */
622 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_VERSION_DATE, sc->cfg.mcode_date);
623 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_VERSION_NUM, sc->cfg.mcode_version);
624
625 /*
626 * If the PCI Configuration Command Register "Parity Error Response
627 * Control" Bit was clear (0), then set the microcode variable
628 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
629 * to ignore DMA parity errors.
630 */
631 if (sc->cfg.control_flag & CONTROL_FLAG_IGNORE_PERR) {
632 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, word);
633 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG,
634 word | CONTROL_FLAG_IGNORE_PERR);
635 }
636
637 switch (sc->chip_type) {
638 case ADW_CHIP_ASC3550:
639 /*
640 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a
641 * FIFO threshold of 128 bytes.
642 * This register is only accessible to the host.
643 */
644 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0,
645 START_CTL_EMFU | READ_CMD_MRM);
646 break;
647
648 case ADW_CHIP_ASC38C0800:
649 /*
650 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
651 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
652 * cable detection and then we are able to read C_DET[3:0].
653 *
654 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
655 * Microcode Default Value' section below.
656 */
657 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1,
658 ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1)
659 | ADW_DIS_TERM_DRV);
660
661 /*
662 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and
663 * START_CTL_TH [3:2] bits for the default FIFO threshold.
664 *
665 * Note: ASC-38C0800 FIFO threshold has been changed to
666 * 256 bytes.
667 *
668 * For DMA Errata #4 set the BC_THRESH_ENB bit.
669 */
670 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0,
671 BC_THRESH_ENB | FIFO_THRESH_80B
672 | START_CTL_TH | READ_CMD_MRM);
673 break;
674
675 case ADW_CHIP_ASC38C1600:
676 /*
677 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
678 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
679 * cable detection and then we are able to read C_DET[3:0].
680 *
681 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
682 * Microcode Default Value' section below.
683 */
684 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1,
685 ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1)
686 | ADW_DIS_TERM_DRV);
687
688 /*
689 * If the BIOS control flag AIPP (Asynchronous Information
690 * Phase Protection) disable bit is not set, then set the
691 * firmware 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to
692 * enable AIPP checking and encoding.
693 */
694 if ((sc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0) {
695 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, word);
696 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG,
697 word | CONTROL_FLAG_ENABLE_AIPP);
698 }
699
700 /*
701 * For ASC-38C1600 use DMA_CFG0 default values:
702 * FIFO_THRESH_80B [6:4], and START_CTL_TH [3:2].
703 */
704 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0,
705 FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM);
706 break;
707 }
708
709 /*
710 * Microcode operating variables for WDTR, SDTR, and command tag
711 * queuing will be set in AdwInquiryHandling() based on what a
712 * device reports it is capable of in Inquiry byte 7.
713 *
714 * If SCSI Bus Resets have been disabled, then directly set
715 * SDTR and WDTR from the EEPROM configuration. This will allow
716 * the BIOS and warm boot to work without a SCSI bus hang on
717 * the Inquiry caused by host and target mismatched DTR values.
718 * Without the SCSI Bus Reset, before an Inquiry a device can't
719 * be assumed to be in Asynchronous, Narrow mode.
720 */
721 if ((sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
722 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, sc->wdtr_able);
723 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sc->sdtr_able);
724 }
725
726 /*
727 * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2,
728 * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID
729 * bitmask. These values determine the maximum SDTR speed negotiated
730 * with a device.
731 *
732 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
733 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
734 * without determining here whether the device supports SDTR.
735 */
736 switch (sc->chip_type) {
737 case ADW_CHIP_ASC3550:
738 word = 0;
739 for (tid = 0; tid <= ADW_MAX_TID; tid++) {
740 if (ADW_TID_TO_TIDMASK(tid) & sc->ultra_able) {
741 /* Set Ultra speed for TID 'tid'. */
742 word |= (0x3 << (4 * (tid % 4)));
743 } else {
744 /* Set Fast speed for TID 'tid'. */
745 word |= (0x2 << (4 * (tid % 4)));
746 }
747 /* Check if done with sdtr_speed1. */
748 if (tid == 3) {
749 ADW_WRITE_WORD_LRAM(iot, ioh,
750 ADW_MC_SDTR_SPEED1, word);
751 word = 0;
752 /* Check if done with sdtr_speed2. */
753 } else if (tid == 7) {
754 ADW_WRITE_WORD_LRAM(iot, ioh,
755 ADW_MC_SDTR_SPEED2, word);
756 word = 0;
757 /* Check if done with sdtr_speed3. */
758 } else if (tid == 11) {
759 ADW_WRITE_WORD_LRAM(iot, ioh,
760 ADW_MC_SDTR_SPEED3, word);
761 word = 0;
762 /* Check if done with sdtr_speed4. */
763 } else if (tid == 15) {
764 ADW_WRITE_WORD_LRAM(iot, ioh,
765 ADW_MC_SDTR_SPEED4, word);
766 /* End of loop. */
767 }
768 }
769
770 /*
771 * Set microcode operating variable for the
772 * disconnect per TID bitmask.
773 */
774 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DISC_ENABLE,
775 sc->cfg.disc_enable);
776 break;
777
778 case ADW_CHIP_ASC38C0800:
779 /* FALLTHROUGH */
780 case ADW_CHIP_ASC38C1600:
781 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DISC_ENABLE,
782 sc->cfg.disc_enable);
783 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED1,
784 sc->sdtr_speed1);
785 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED2,
786 sc->sdtr_speed2);
787 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED3,
788 sc->sdtr_speed3);
789 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED4,
790 sc->sdtr_speed4);
791 break;
792 }
793
794
795 /*
796 * Set SCSI_CFG0 Microcode Default Value.
797 *
798 * The microcode will set the SCSI_CFG0 register using this value
799 * after it is started below.
800 */
801 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG0,
802 ADW_PARITY_EN | ADW_QUEUE_128 | ADW_SEL_TMO_LONG |
803 ADW_OUR_ID_EN | sc->chip_scsi_id);
804
805
806 switch(sc->chip_type) {
807 case ADW_CHIP_ASC3550:
808 error_code = AdwASC3550Cabling(iot, ioh, &sc->cfg);
809 break;
810
811 case ADW_CHIP_ASC38C0800:
812 error_code = AdwASC38C0800Cabling(iot, ioh, &sc->cfg);
813 break;
814
815 case ADW_CHIP_ASC38C1600:
816 error_code = AdwASC38C1600Cabling(iot, ioh, &sc->cfg);
817 break;
818 }
819 if(error_code) {
820 return error_code;
821 }
822
823 /*
824 * Set SEL_MASK Microcode Default Value
825 *
826 * The microcode will set the SEL_MASK register using this value
827 * after it is started below.
828 */
829 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SEL_MASK,
830 ADW_TID_TO_TIDMASK(sc->chip_scsi_id));
831
832 /*
833 * Create and Initialize Host->RISC Carrier lists
834 */
835 sc->carr_freelist = AdwInitCarriers(sc->sc_dmamap_carrier,
836 sc->sc_control->carriers);
837
838 /*
839 * Set-up the Host->RISC Initiator Command Queue (ICQ).
840 */
841
842 if ((sc->icq_sp = sc->carr_freelist) == NULL) {
843 return ADW_IERR_NO_CARRIER;
844 }
845 sc->carr_freelist = ADW_CARRIER_VADDR(sc,
846 ADW_GET_CARRP(sc->icq_sp->next_ba));
847
848 /*
849 * The first command issued will be placed in the stopper carrier.
850 */
851 sc->icq_sp->next_ba = ADW_CQ_STOPPER;
852
853 /*
854 * Set RISC ICQ physical address start value.
855 */
856 ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_ICQ, sc->icq_sp->carr_ba);
857
858 /*
859 * Initialize the COMMA register to the same value otherwise
860 * the RISC will prematurely detect a command is available.
861 */
862 if(sc->chip_type == ADW_CHIP_ASC38C1600) {
863 ADW_WRITE_DWORD_REGISTER(iot, ioh, IOPDW_COMMA,
864 sc->icq_sp->carr_ba);
865 }
866
867 /*
868 * Set-up the RISC->Host Initiator Response Queue (IRQ).
869 */
870 if ((sc->irq_sp = sc->carr_freelist) == NULL) {
871 return ADW_IERR_NO_CARRIER;
872 }
873 sc->carr_freelist = ADW_CARRIER_VADDR(sc,
874 ADW_GET_CARRP(sc->irq_sp->next_ba));
875
876 /*
877 * The first command completed by the RISC will be placed in
878 * the stopper.
879 *
880 * Note: Set 'next_ba' to ADW_CQ_STOPPER. When the request is
881 * completed the RISC will set the ADW_RQ_DONE bit.
882 */
883 sc->irq_sp->next_ba = ADW_CQ_STOPPER;
884
885 /*
886 * Set RISC IRQ physical address start value.
887 */
888 ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_IRQ, sc->irq_sp->carr_ba);
889 sc->carr_pending_cnt = 0;
890
891 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_INTR_ENABLES,
892 (ADW_INTR_ENABLE_HOST_INTR | ADW_INTR_ENABLE_GLOBAL_INTR));
893 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_BEGIN_ADDR, word);
894 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_PC, word);
895
896 /* finally, finally, gentlemen, start your engine */
897 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RISC_CSR, ADW_RISC_CSR_RUN);
898
899 /*
900 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
901 * Resets should be performed. The RISC has to be running
902 * to issue a SCSI Bus Reset.
903 */
904 if (sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS)
905 {
906 /*
907 * If the BIOS Signature is present in memory, restore the
908 * BIOS Handshake Configuration Table and do not perform
909 * a SCSI Bus Reset.
910 */
911 if (bios_mem[(ADW_MC_BIOS_SIGNATURE - ADW_MC_BIOSMEM)/2] ==
912 0x55AA) {
913 /*
914 * Restore per TID negotiated values.
915 */
916 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE,
917 wdtr_able);
918 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE,
919 sdtr_able);
920 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE,
921 tagqng_able);
922 for (tid = 0; tid <= ADW_MAX_TID; tid++) {
923 ADW_WRITE_BYTE_LRAM(iot, ioh,
924 ADW_MC_NUMBER_OF_MAX_CMD + tid,
925 max_cmd[tid]);
926 }
927 } else {
928 if (AdwResetCCB(sc) != ADW_TRUE) {
929 error_code = ADW_WARN_BUSRESET_ERROR;
930 }
931 }
932 }
933
934 return error_code;
935 }
936
937
938 int
AdwRamSelfTest(iot,ioh,chip_type)939 AdwRamSelfTest(iot, ioh, chip_type)
940 bus_space_tag_t iot;
941 bus_space_handle_t ioh;
942 u_int8_t chip_type;
943 {
944 int i;
945 u_int8_t byte;
946
947
948 if ((chip_type == ADW_CHIP_ASC38C0800) ||
949 (chip_type == ADW_CHIP_ASC38C1600)) {
950 /*
951 * RAM BIST (RAM Built-In Self Test)
952 *
953 * Address : I/O base + offset 0x38h register (byte).
954 * Function: Bit 7-6(RW) : RAM mode
955 * Normal Mode : 0x00
956 * Pre-test Mode : 0x40
957 * RAM Test Mode : 0x80
958 * Bit 5 : unused
959 * Bit 4(RO) : Done bit
960 * Bit 3-0(RO) : Status
961 * Host Error : 0x08
962 * Int_RAM Error : 0x04
963 * RISC Error : 0x02
964 * SCSI Error : 0x01
965 * No Error : 0x00
966 *
967 * Note: RAM BIST code should be put right here, before loading
968 * the microcode and after saving the RISC memory BIOS region.
969 */
970
971 /*
972 * LRAM Pre-test
973 *
974 * Write PRE_TEST_MODE (0x40) to register and wait for
975 * 10 milliseconds.
976 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05),
977 * return an error. Reset to NORMAL_MODE (0x00) and do again.
978 * If cannot reset to NORMAL_MODE, return an error too.
979 */
980 for (i = 0; i < 2; i++) {
981 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST,
982 PRE_TEST_MODE);
983 /* Wait for 10ms before reading back. */
984 AdwSleepMilliSecond(10);
985 byte = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST);
986 if ((byte & RAM_TEST_DONE) == 0 || (byte & 0x0F) !=
987 PRE_TEST_VALUE) {
988 return ADW_IERR_BIST_PRE_TEST;
989 }
990
991 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST,
992 NORMAL_MODE);
993 /* Wait for 10ms before reading back. */
994 AdwSleepMilliSecond(10);
995 if (ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST)
996 != NORMAL_VALUE) {
997 return ADW_IERR_BIST_PRE_TEST;
998 }
999 }
1000
1001 /*
1002 * LRAM Test - It takes about 1.5 ms to run through the test.
1003 *
1004 * Write RAM_TEST_MODE (0x80) to register and wait for
1005 * 10 milliseconds.
1006 * If Done bit not set or Status not 0, save register byte,
1007 * set the err_code, and return an error.
1008 */
1009 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, RAM_TEST_MODE);
1010 /* Wait for 10ms before checking status. */
1011 AdwSleepMilliSecond(10);
1012
1013 byte = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST);
1014 if ((byte & RAM_TEST_DONE)==0 || (byte & RAM_TEST_STATUS)!=0) {
1015 /* Get here if Done bit not set or Status not 0. */
1016 return ADW_IERR_BIST_RAM_TEST;
1017 }
1018
1019 /* We need to reset back to normal mode after LRAM test passes*/
1020 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, NORMAL_MODE);
1021 }
1022
1023 return 0;
1024 }
1025
1026
1027 int
AdwLoadMCode(iot,ioh,bios_mem,chip_type)1028 AdwLoadMCode(iot, ioh, bios_mem, chip_type)
1029 bus_space_tag_t iot;
1030 bus_space_handle_t ioh;
1031 u_int16_t *bios_mem;
1032 u_int8_t chip_type;
1033 {
1034 u_int8_t *mcode_data;
1035 u_int32_t mcode_chksum;
1036 u_int16_t mcode_size;
1037 u_int32_t sum;
1038 u_int16_t code_sum;
1039 int begin_addr;
1040 int end_addr;
1041 int word;
1042 int adw_memsize;
1043 int adw_mcode_expanded_size;
1044 int i, j;
1045
1046
1047 switch(chip_type) {
1048 case ADW_CHIP_ASC3550:
1049 mcode_data = (u_int8_t *)adw_asc3550_mcode_data.mcode_data;
1050 mcode_chksum = (u_int32_t)adw_asc3550_mcode_data.mcode_chksum;
1051 mcode_size = (u_int16_t)adw_asc3550_mcode_data.mcode_size;
1052 adw_memsize = ADW_3550_MEMSIZE;
1053 break;
1054
1055 case ADW_CHIP_ASC38C0800:
1056 mcode_data = (u_int8_t *)adw_asc38C0800_mcode_data.mcode_data;
1057 mcode_chksum =(u_int32_t)adw_asc38C0800_mcode_data.mcode_chksum;
1058 mcode_size = (u_int16_t)adw_asc38C0800_mcode_data.mcode_size;
1059 adw_memsize = ADW_38C0800_MEMSIZE;
1060 break;
1061
1062 case ADW_CHIP_ASC38C1600:
1063 mcode_data = (u_int8_t *)adw_asc38C1600_mcode_data.mcode_data;
1064 mcode_chksum =(u_int32_t)adw_asc38C1600_mcode_data.mcode_chksum;
1065 mcode_size = (u_int16_t)adw_asc38C1600_mcode_data.mcode_size;
1066 adw_memsize = ADW_38C1600_MEMSIZE;
1067 break;
1068 }
1069
1070 /*
1071 * Write the microcode image to RISC memory starting at address 0.
1072 */
1073 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0);
1074
1075 /* Assume the following compressed format of the microcode buffer:
1076 *
1077 * 254 word (508 byte) table indexed by byte code followed
1078 * by the following byte codes:
1079 *
1080 * 1-Byte Code:
1081 * 00: Emit word 0 in table.
1082 * 01: Emit word 1 in table.
1083 * .
1084 * FD: Emit word 253 in table.
1085 *
1086 * Multi-Byte Code:
1087 * FE WW WW: (3 byte code) Word to emit is the next word WW WW.
1088 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
1089 */
1090 word = 0;
1091 for (i = 253 * 2; i < mcode_size; i++) {
1092 if (mcode_data[i] == 0xff) {
1093 for (j = 0; j < mcode_data[i + 1]; j++) {
1094 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh,
1095 (((u_int16_t)mcode_data[i + 3] << 8) |
1096 mcode_data[i + 2]));
1097 word++;
1098 }
1099 i += 3;
1100 } else if (mcode_data[i] == 0xfe) {
1101 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh,
1102 (((u_int16_t)mcode_data[i + 2] << 8) |
1103 mcode_data[i + 1]));
1104 i += 2;
1105 word++;
1106 } else {
1107 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, (((u_int16_t)
1108 mcode_data[(mcode_data[i] * 2) + 1] <<8) |
1109 mcode_data[mcode_data[i] * 2]));
1110 word++;
1111 }
1112 }
1113
1114 /*
1115 * Set 'word' for later use to clear the rest of memory and save
1116 * the expanded mcode size.
1117 */
1118 word *= 2;
1119 adw_mcode_expanded_size = word;
1120
1121 /*
1122 * Clear the rest of the Internal RAM.
1123 */
1124 for (; word < adw_memsize; word += 2) {
1125 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 0);
1126 }
1127
1128 /*
1129 * Verify the microcode checksum.
1130 */
1131 sum = 0;
1132 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0);
1133
1134 for (word = 0; word < adw_mcode_expanded_size; word += 2) {
1135 sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh);
1136 }
1137
1138 if (sum != mcode_chksum) {
1139 return ADW_IERR_MCODE_CHKSUM;
1140 }
1141
1142 /*
1143 * Restore the RISC memory BIOS region.
1144 */
1145 for (i = 0; i < ADW_MC_BIOSLEN/2; i++) {
1146 if(chip_type == ADW_CHIP_ASC3550) {
1147 ADW_WRITE_BYTE_LRAM(iot, ioh, ADW_MC_BIOSMEM + (2 * i),
1148 bios_mem[i]);
1149 } else {
1150 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_BIOSMEM + (2 * i),
1151 bios_mem[i]);
1152 }
1153 }
1154
1155 /*
1156 * Calculate and write the microcode code checksum to the microcode
1157 * code checksum location ADW_MC_CODE_CHK_SUM (0x2C).
1158 */
1159 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_BEGIN_ADDR, begin_addr);
1160 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_END_ADDR, end_addr);
1161 code_sum = 0;
1162 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, begin_addr);
1163 for (word = begin_addr; word < end_addr; word += 2) {
1164 code_sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh);
1165 }
1166 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CODE_CHK_SUM, code_sum);
1167
1168 /*
1169 * Set the chip type.
1170 */
1171 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CHIP_TYPE, chip_type);
1172
1173 return 0;
1174 }
1175
1176
1177 int
AdwASC3550Cabling(iot,ioh,cfg)1178 AdwASC3550Cabling(iot, ioh, cfg)
1179 bus_space_tag_t iot;
1180 bus_space_handle_t ioh;
1181 ADW_DVC_CFG *cfg;
1182 {
1183 u_int16_t scsi_cfg1;
1184
1185
1186 /*
1187 * Determine SCSI_CFG1 Microcode Default Value.
1188 *
1189 * The microcode will set the SCSI_CFG1 register using this value
1190 * after it is started below.
1191 */
1192
1193 /* Read current SCSI_CFG1 Register value. */
1194 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1);
1195
1196 /*
1197 * If all three connectors are in use in ASC3550, return an error.
1198 */
1199 if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 ||
1200 (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) {
1201 return ADW_IERR_ILLEGAL_CONNECTION;
1202 }
1203
1204 /*
1205 * If the cable is reversed all of the SCSI_CTRL register signals
1206 * will be set. Check for and return an error if this condition is
1207 * found.
1208 */
1209 if ((ADW_READ_WORD_REGISTER(iot,ioh, IOPW_SCSI_CTRL) & 0x3F07)==0x3F07){
1210 return ADW_IERR_REVERSED_CABLE;
1211 }
1212
1213 /*
1214 * If this is a differential board and a single-ended device
1215 * is attached to one of the connectors, return an error.
1216 */
1217 if ((scsi_cfg1 & ADW_DIFF_MODE) &&
1218 (scsi_cfg1 & ADW_DIFF_SENSE) == 0) {
1219 return ADW_IERR_SINGLE_END_DEVICE;
1220 }
1221
1222 /*
1223 * If automatic termination control is enabled, then set the
1224 * termination value based on a table listed in a_condor.h.
1225 *
1226 * If manual termination was specified with an EEPROM setting
1227 * then 'termination' was set-up in AdwInitFromEEPROM() and
1228 * is ready to be 'ored' into SCSI_CFG1.
1229 */
1230 if (cfg->termination == 0) {
1231 /*
1232 * The software always controls termination by setting
1233 * TERM_CTL_SEL.
1234 * If TERM_CTL_SEL were set to 0, the hardware would set
1235 * termination.
1236 */
1237 cfg->termination |= ADW_TERM_CTL_SEL;
1238
1239 switch(scsi_cfg1 & ADW_CABLE_DETECT) {
1240 /* TERM_CTL_H: on, TERM_CTL_L: on */
1241 case 0x3: case 0x7: case 0xB:
1242 case 0xD: case 0xE: case 0xF:
1243 cfg->termination |=
1244 (ADW_TERM_CTL_H | ADW_TERM_CTL_L);
1245 break;
1246
1247 /* TERM_CTL_H: on, TERM_CTL_L: off */
1248 case 0x1: case 0x5: case 0x9:
1249 case 0xA: case 0xC:
1250 cfg->termination |= ADW_TERM_CTL_H;
1251 break;
1252
1253 /* TERM_CTL_H: off, TERM_CTL_L: off */
1254 case 0x2: case 0x6:
1255 break;
1256 }
1257 }
1258
1259 /*
1260 * Clear any set TERM_CTL_H and TERM_CTL_L bits.
1261 */
1262 scsi_cfg1 &= ~ADW_TERM_CTL;
1263
1264 /*
1265 * Invert the TERM_CTL_H and TERM_CTL_L bits and then
1266 * set 'scsi_cfg1'. The TERM_POL bit does not need to be
1267 * referenced, because the hardware internally inverts
1268 * the Termination High and Low bits if TERM_POL is set.
1269 */
1270 scsi_cfg1 |= (ADW_TERM_CTL_SEL | (~cfg->termination & ADW_TERM_CTL));
1271
1272 /*
1273 * Set SCSI_CFG1 Microcode Default Value
1274 *
1275 * Set filter value and possibly modified termination control
1276 * bits in the Microcode SCSI_CFG1 Register Value.
1277 *
1278 * The microcode will set the SCSI_CFG1 register using this value
1279 * after it is started below.
1280 */
1281 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG1,
1282 ADW_FLTR_DISABLE | scsi_cfg1);
1283
1284 /*
1285 * Set MEM_CFG Microcode Default Value
1286 *
1287 * The microcode will set the MEM_CFG register using this value
1288 * after it is started below.
1289 *
1290 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
1291 * are defined.
1292 *
1293 * ASC-3550 has 8KB internal memory.
1294 */
1295 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_MEM_CFG,
1296 ADW_BIOS_EN | ADW_RAM_SZ_8KB);
1297
1298 return 0;
1299 }
1300
1301
1302 int
AdwASC38C0800Cabling(iot,ioh,cfg)1303 AdwASC38C0800Cabling(iot, ioh, cfg)
1304 bus_space_tag_t iot;
1305 bus_space_handle_t ioh;
1306 ADW_DVC_CFG *cfg;
1307 {
1308 u_int16_t scsi_cfg1;
1309
1310
1311 /*
1312 * Determine SCSI_CFG1 Microcode Default Value.
1313 *
1314 * The microcode will set the SCSI_CFG1 register using this value
1315 * after it is started below.
1316 */
1317
1318 /* Read current SCSI_CFG1 Register value. */
1319 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1);
1320
1321 /*
1322 * If the cable is reversed all of the SCSI_CTRL register signals
1323 * will be set. Check for and return an error if this condition is
1324 * found.
1325 */
1326 if ((ADW_READ_WORD_REGISTER(iot,ioh, IOPW_SCSI_CTRL) & 0x3F07)==0x3F07){
1327 return ADW_IERR_REVERSED_CABLE;
1328 }
1329
1330 /*
1331 * All kind of combinations of devices attached to one of four
1332 * connectors are acceptable except HVD device attached.
1333 * For example, LVD device can be attached to SE connector while
1334 * SE device attached to LVD connector.
1335 * If LVD device attached to SE connector, it only runs up to
1336 * Ultra speed.
1337 *
1338 * If an HVD device is attached to one of LVD connectors, return
1339 * an error.
1340 * However, there is no way to detect HVD device attached to
1341 * SE connectors.
1342 */
1343 if (scsi_cfg1 & ADW_HVD) {
1344 return ADW_IERR_HVD_DEVICE;
1345 }
1346
1347 /*
1348 * If either SE or LVD automatic termination control is enabled, then
1349 * set the termination value based on a table listed in a_condor.h.
1350 *
1351 * If manual termination was specified with an EEPROM setting then
1352 * 'termination' was set-up in AdwInitFromEEPROM() and is ready
1353 * to be 'ored' into SCSI_CFG1.
1354 */
1355 if ((cfg->termination & ADW_TERM_SE) == 0) {
1356 /* SE automatic termination control is enabled. */
1357 switch(scsi_cfg1 & ADW_C_DET_SE) {
1358 /* TERM_SE_HI: on, TERM_SE_LO: on */
1359 case 0x1: case 0x2: case 0x3:
1360 cfg->termination |= ADW_TERM_SE;
1361 break;
1362
1363 /* TERM_SE_HI: on, TERM_SE_LO: off */
1364 case 0x0:
1365 cfg->termination |= ADW_TERM_SE_HI;
1366 break;
1367 }
1368 }
1369
1370 if ((cfg->termination & ADW_TERM_LVD) == 0) {
1371 /* LVD automatic termination control is enabled. */
1372 switch(scsi_cfg1 & ADW_C_DET_LVD) {
1373 /* TERM_LVD_HI: on, TERM_LVD_LO: on */
1374 case 0x4: case 0x8: case 0xC:
1375 cfg->termination |= ADW_TERM_LVD;
1376 break;
1377
1378 /* TERM_LVD_HI: off, TERM_LVD_LO: off */
1379 case 0x0:
1380 break;
1381 }
1382 }
1383
1384 /*
1385 * Clear any set TERM_SE and TERM_LVD bits.
1386 */
1387 scsi_cfg1 &= (~ADW_TERM_SE & ~ADW_TERM_LVD);
1388
1389 /*
1390 * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'.
1391 */
1392 scsi_cfg1 |= (~cfg->termination & 0xF0);
1393
1394 /*
1395 * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and
1396 * HVD/LVD/SE bits and set possibly modified termination control bits
1397 * in the Microcode SCSI_CFG1 Register Value.
1398 */
1399 scsi_cfg1 &= (~ADW_BIG_ENDIAN & ~ADW_DIS_TERM_DRV &
1400 ~ADW_TERM_POL & ~ADW_HVD_LVD_SE);
1401
1402 /*
1403 * Set SCSI_CFG1 Microcode Default Value
1404 *
1405 * Set possibly modified termination control and reset DIS_TERM_DRV
1406 * bits in the Microcode SCSI_CFG1 Register Value.
1407 *
1408 * The microcode will set the SCSI_CFG1 register using this value
1409 * after it is started below.
1410 */
1411 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
1412
1413 /*
1414 * Set MEM_CFG Microcode Default Value
1415 *
1416 * The microcode will set the MEM_CFG register using this value
1417 * after it is started below.
1418 *
1419 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
1420 * are defined.
1421 *
1422 * ASC-38C0800 has 16KB internal memory.
1423 */
1424 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_MEM_CFG,
1425 ADW_BIOS_EN | ADW_RAM_SZ_16KB);
1426
1427 return 0;
1428 }
1429
1430
1431 int
AdwASC38C1600Cabling(iot,ioh,cfg)1432 AdwASC38C1600Cabling(iot, ioh, cfg)
1433 bus_space_tag_t iot;
1434 bus_space_handle_t ioh;
1435 ADW_DVC_CFG *cfg;
1436 {
1437 u_int16_t scsi_cfg1;
1438
1439
1440 /*
1441 * Determine SCSI_CFG1 Microcode Default Value.
1442 *
1443 * The microcode will set the SCSI_CFG1 register using this value
1444 * after it is started below.
1445 * Each ASC-38C1600 function has only two cable detect bits.
1446 * The bus mode override bits are in IOPB_SOFT_OVER_WR.
1447 */
1448
1449 /* Read current SCSI_CFG1 Register value. */
1450 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1);
1451
1452 /*
1453 * If the cable is reversed all of the SCSI_CTRL register signals
1454 * will be set. Check for and return an error if this condition is
1455 * found.
1456 */
1457 if ((ADW_READ_WORD_REGISTER(iot,ioh, IOPW_SCSI_CTRL) & 0x3F07)==0x3F07){
1458 return ADW_IERR_REVERSED_CABLE;
1459 }
1460
1461 /*
1462 * Each ASC-38C1600 function has two connectors. Only an HVD device
1463 * cannot be connected to either connector. An LVD device or SE device
1464 * may be connected to either connector. If an SE device is connected,
1465 * then at most Ultra speed (20 MHz) can be used on both connectors.
1466 *
1467 * If an HVD device is attached, return an error.
1468 */
1469 if (scsi_cfg1 & ADW_HVD) {
1470 return ADW_IERR_HVD_DEVICE;
1471 }
1472
1473 /*
1474 * Each function in the ASC-38C1600 uses only the SE cable detect and
1475 * termination because there are two connectors for each function.
1476 * Each function may use either LVD or SE mode.
1477 * Corresponding the SE automatic termination control EEPROM bits are
1478 * used for each function.
1479 * Each function has its own EEPROM. If SE automatic control is enabled
1480 * for the function, then set the termination value based on a table
1481 * listed in adwlib.h.
1482 *
1483 * If manual termination is specified in the EEPROM for the function,
1484 * then 'termination' was set-up in AdwInitFromEEPROM() and is
1485 * ready to be 'ored' into SCSI_CFG1.
1486 */
1487 if ((cfg->termination & ADW_TERM_SE) == 0) {
1488 /* SE automatic termination control is enabled. */
1489 switch(scsi_cfg1 & ADW_C_DET_SE) {
1490 /* TERM_SE_HI: on, TERM_SE_LO: on */
1491 case 0x1: case 0x2: case 0x3:
1492 cfg->termination |= ADW_TERM_SE;
1493 break;
1494
1495 case 0x0:
1496 /* !!!!TODO!!!! */
1497 // if (ASC_PCI_ID2FUNC(cfg->pci_slot_info) == 0) {
1498 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */
1499 // }
1500 // else
1501 // {
1502 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */
1503 cfg->termination |= ADW_TERM_SE_HI;
1504 // }
1505 break;
1506 }
1507 }
1508
1509 /*
1510 * Clear any set TERM_SE bits.
1511 */
1512 scsi_cfg1 &= ~ADW_TERM_SE;
1513
1514 /*
1515 * Invert the TERM_SE bits and then set 'scsi_cfg1'.
1516 */
1517 scsi_cfg1 |= (~cfg->termination & ADW_TERM_SE);
1518
1519 /*
1520 * Clear Big Endian and Terminator Polarity bits and set possibly
1521 * modified termination control bits in the Microcode SCSI_CFG1
1522 * Register Value.
1523 */
1524 scsi_cfg1 &= (~ADW_BIG_ENDIAN & ~ADW_DIS_TERM_DRV & ~ADW_TERM_POL);
1525
1526 /*
1527 * Set SCSI_CFG1 Microcode Default Value
1528 *
1529 * Set possibly modified termination control bits in the Microcode
1530 * SCSI_CFG1 Register Value.
1531 *
1532 * The microcode will set the SCSI_CFG1 register using this value
1533 * after it is started below.
1534 */
1535 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
1536
1537 /*
1538 * Set MEM_CFG Microcode Default Value
1539 *
1540 * The microcode will set the MEM_CFG register using this value
1541 * after it is started below.
1542 *
1543 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
1544 * are defined.
1545 *
1546 * ASC-38C1600 has 32KB internal memory.
1547 */
1548 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_MEM_CFG,
1549 ADW_BIOS_EN | ADW_RAM_SZ_32KB);
1550
1551 return 0;
1552 }
1553
1554
1555 /*
1556 * Read EEPROM configuration into the specified buffer.
1557 *
1558 * Return a checksum based on the EEPROM configuration read.
1559 */
1560 u_int16_t
AdwGetEEPROMConfig(iot,ioh,cfg_buf)1561 AdwGetEEPROMConfig(iot, ioh, cfg_buf)
1562 bus_space_tag_t iot;
1563 bus_space_handle_t ioh;
1564 ADW_EEPROM *cfg_buf;
1565 {
1566 u_int16_t wval, chksum;
1567 u_int16_t *wbuf;
1568 int eep_addr;
1569
1570
1571 wbuf = (u_int16_t *) cfg_buf;
1572 chksum = 0;
1573
1574 for (eep_addr = ADW_EEP_DVC_CFG_BEGIN;
1575 eep_addr < ADW_EEP_DVC_CFG_END;
1576 eep_addr++, wbuf++) {
1577 wval = AdwReadEEPWord(iot, ioh, eep_addr);
1578 chksum += wval;
1579 *wbuf = wval;
1580 }
1581
1582 *wbuf = AdwReadEEPWord(iot, ioh, eep_addr);
1583 wbuf++;
1584 for (eep_addr = ADW_EEP_DVC_CTL_BEGIN;
1585 eep_addr < ADW_EEP_MAX_WORD_ADDR;
1586 eep_addr++, wbuf++) {
1587 *wbuf = AdwReadEEPWord(iot, ioh, eep_addr);
1588 }
1589
1590 return chksum;
1591 }
1592
1593
1594 /*
1595 * Read the EEPROM from specified location
1596 */
1597 u_int16_t
AdwReadEEPWord(iot,ioh,eep_word_addr)1598 AdwReadEEPWord(iot, ioh, eep_word_addr)
1599 bus_space_tag_t iot;
1600 bus_space_handle_t ioh;
1601 int eep_word_addr;
1602 {
1603 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD,
1604 ADW_EEP_CMD_READ | eep_word_addr);
1605 AdwWaitEEPCmd(iot, ioh);
1606
1607 return ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_DATA);
1608 }
1609
1610
1611 /*
1612 * Wait for EEPROM command to complete
1613 */
1614 void
AdwWaitEEPCmd(iot,ioh)1615 AdwWaitEEPCmd(iot, ioh)
1616 bus_space_tag_t iot;
1617 bus_space_handle_t ioh;
1618 {
1619 int eep_delay_ms;
1620
1621
1622 for (eep_delay_ms = 0; eep_delay_ms < ADW_EEP_DELAY_MS; eep_delay_ms++){
1623 if (ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_CMD) &
1624 ADW_EEP_CMD_DONE) {
1625 break;
1626 }
1627 AdwSleepMilliSecond(1);
1628 }
1629
1630 ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_CMD);
1631 }
1632
1633
1634 /*
1635 * Write the EEPROM from 'cfg_buf'.
1636 */
1637 void
AdwSetEEPROMConfig(iot,ioh,cfg_buf)1638 AdwSetEEPROMConfig(iot, ioh, cfg_buf)
1639 bus_space_tag_t iot;
1640 bus_space_handle_t ioh;
1641 ADW_EEPROM *cfg_buf;
1642 {
1643 u_int16_t *wbuf;
1644 u_int16_t addr, chksum;
1645
1646
1647 wbuf = (u_int16_t *) cfg_buf;
1648 chksum = 0;
1649
1650 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, ADW_EEP_CMD_WRITE_ABLE);
1651 AdwWaitEEPCmd(iot, ioh);
1652
1653 /*
1654 * Write EEPROM from word 0 to word 20
1655 */
1656 for (addr = ADW_EEP_DVC_CFG_BEGIN;
1657 addr < ADW_EEP_DVC_CFG_END; addr++, wbuf++) {
1658 chksum += *wbuf;
1659 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf);
1660 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD,
1661 ADW_EEP_CMD_WRITE | addr);
1662 AdwWaitEEPCmd(iot, ioh);
1663 AdwSleepMilliSecond(ADW_EEP_DELAY_MS);
1664 }
1665
1666 /*
1667 * Write EEPROM checksum at word 21
1668 */
1669 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, chksum);
1670 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD,
1671 ADW_EEP_CMD_WRITE | addr);
1672 AdwWaitEEPCmd(iot, ioh);
1673 wbuf++; /* skip over check_sum */
1674
1675 /*
1676 * Write EEPROM OEM name at words 22 to 29
1677 */
1678 for (addr = ADW_EEP_DVC_CTL_BEGIN;
1679 addr < ADW_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
1680 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf);
1681 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD,
1682 ADW_EEP_CMD_WRITE | addr);
1683 AdwWaitEEPCmd(iot, ioh);
1684 }
1685
1686 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD,
1687 ADW_EEP_CMD_WRITE_DISABLE);
1688 AdwWaitEEPCmd(iot, ioh);
1689
1690 return;
1691 }
1692
1693
1694 /*
1695 * AdwExeScsiQueue() - Send a request to the RISC microcode program.
1696 *
1697 * Allocate a carrier structure, point the carrier to the ADW_SCSI_REQ_Q,
1698 * add the carrier to the ICQ (Initiator Command Queue), and tickle the
1699 * RISC to notify it a new command is ready to be executed.
1700 *
1701 * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be
1702 * set to SCSI_MAX_RETRY.
1703 *
1704 * Return:
1705 * ADW_SUCCESS(1) - The request was successfully queued.
1706 * ADW_BUSY(0) - Resource unavailable; Retry again after pending
1707 * request completes.
1708 * ADW_ERROR(-1) - Invalid ADW_SCSI_REQ_Q request structure
1709 * host IC error.
1710 */
1711 int
AdwExeScsiQueue(sc,scsiq)1712 AdwExeScsiQueue(sc, scsiq)
1713 ADW_SOFTC *sc;
1714 ADW_SCSI_REQ_Q *scsiq;
1715 {
1716 bus_space_tag_t iot = sc->sc_iot;
1717 bus_space_handle_t ioh = sc->sc_ioh;
1718 ADW_CCB *ccb;
1719 long req_size;
1720 u_int32_t req_paddr;
1721 ADW_CARRIER *new_carrp;
1722
1723 /*
1724 * The ADW_SCSI_REQ_Q 'target_id' field should never exceed ADW_MAX_TID.
1725 */
1726 if (scsiq->target_id > ADW_MAX_TID) {
1727 scsiq->host_status = QHSTA_M_INVALID_DEVICE;
1728 scsiq->done_status = QD_WITH_ERROR;
1729 return ADW_ERROR;
1730 }
1731
1732 /*
1733 * Beginning of CRITICAL SECTION: ASSUME splbio() in effect
1734 */
1735
1736 ccb = adw_ccb_phys_kv(sc, scsiq->ccb_ptr);
1737
1738 /*
1739 * Allocate a carrier and initialize fields.
1740 */
1741 if ((new_carrp = sc->carr_freelist) == NULL) {
1742 return ADW_BUSY;
1743 }
1744 sc->carr_freelist = ADW_CARRIER_VADDR(sc,
1745 ADW_GET_CARRP(new_carrp->next_ba));
1746 sc->carr_pending_cnt++;
1747
1748 /*
1749 * Set the carrier to be a stopper by setting 'next_ba'
1750 * to the stopper value. The current stopper will be changed
1751 * below to point to the new stopper.
1752 */
1753 new_carrp->next_ba = ADW_CQ_STOPPER;
1754
1755 req_size = sizeof(ADW_SCSI_REQ_Q);
1756 req_paddr = sc->sc_dmamap_control->dm_segs[0].ds_addr +
1757 ADW_CCB_OFF(ccb) + offsetof(struct adw_ccb, scsiq);
1758
1759 /* Save physical address of ADW_SCSI_REQ_Q and Carrier. */
1760 scsiq->scsiq_rptr = req_paddr;
1761
1762 /*
1763 * Every ADW_SCSI_REQ_Q.carr_ba is byte swapped to little-endian
1764 * order during initialization.
1765 */
1766 scsiq->carr_ba = sc->icq_sp->carr_ba;
1767 scsiq->carr_va = sc->icq_sp->carr_ba;
1768
1769 /*
1770 * Use the current stopper to send the ADW_SCSI_REQ_Q command to
1771 * the microcode. The newly allocated stopper will become the new
1772 * stopper.
1773 */
1774 sc->icq_sp->areq_ba = req_paddr;
1775
1776 /*
1777 * Set the 'next_ba' pointer for the old stopper to be the
1778 * physical address of the new stopper. The RISC can only
1779 * follow physical addresses.
1780 */
1781 sc->icq_sp->next_ba = new_carrp->carr_ba;
1782
1783 #if ADW_DEBUG
1784 printf("icq 0x%x, 0x%x, 0x%x, 0x%x\n",
1785 sc->icq_sp->carr_id,
1786 sc->icq_sp->carr_ba,
1787 sc->icq_sp->areq_ba,
1788 sc->icq_sp->next_ba);
1789 #endif
1790 /*
1791 * Set the host adapter stopper pointer to point to the new carrier.
1792 */
1793 sc->icq_sp = new_carrp;
1794
1795 if (sc->chip_type == ADW_CHIP_ASC3550 ||
1796 sc->chip_type == ADW_CHIP_ASC38C0800) {
1797 /*
1798 * Tickle the RISC to tell it to read its Command Queue Head
1799 * pointer.
1800 */
1801 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADW_TICKLE_A);
1802 if (sc->chip_type == ADW_CHIP_ASC3550) {
1803 /*
1804 * Clear the tickle value. In the ASC-3550 the RISC flag
1805 * command 'clr_tickle_a' does not work unless the host
1806 * value is cleared.
1807 */
1808 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE,
1809 ADW_TICKLE_NOP);
1810 }
1811 } else if (sc->chip_type == ADW_CHIP_ASC38C1600) {
1812 /*
1813 * Notify the RISC a carrier is ready by writing the physical
1814 * address of the new carrier stopper to the COMMA register.
1815 */
1816 ADW_WRITE_DWORD_REGISTER(iot, ioh, IOPDW_COMMA,
1817 new_carrp->carr_ba);
1818 }
1819
1820 /*
1821 * End of CRITICAL SECTION: Must be protected within splbio/splx pair
1822 */
1823
1824 return ADW_SUCCESS;
1825 }
1826
1827
1828 void
AdwResetChip(iot,ioh)1829 AdwResetChip(iot, ioh)
1830 bus_space_tag_t iot;
1831 bus_space_handle_t ioh;
1832 {
1833
1834 /*
1835 * Reset Chip.
1836 */
1837 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG,
1838 ADW_CTRL_REG_CMD_RESET);
1839 AdwSleepMilliSecond(100);
1840 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG,
1841 ADW_CTRL_REG_CMD_WR_IO_REG);
1842 }
1843
1844
1845 /*
1846 * Reset SCSI Bus and purge all outstanding requests.
1847 *
1848 * Return Value:
1849 * ADW_TRUE(1) - All requests are purged and SCSI Bus is reset.
1850 * ADW_FALSE(0) - Microcode command failed.
1851 * ADW_ERROR(-1) - Microcode command timed-out. Microcode or IC
1852 * may be hung which requires driver recovery.
1853 */
1854 int
AdwResetCCB(sc)1855 AdwResetCCB(sc)
1856 ADW_SOFTC *sc;
1857 {
1858 int status;
1859
1860 /*
1861 * Send the SCSI Bus Reset idle start idle command which asserts
1862 * the SCSI Bus Reset signal.
1863 */
1864 status = AdwSendIdleCmd(sc, (u_int16_t) IDLE_CMD_SCSI_RESET_START, 0L);
1865 if (status != ADW_TRUE) {
1866 return status;
1867 }
1868
1869 /*
1870 * Delay for the specified SCSI Bus Reset hold time.
1871 *
1872 * The hold time delay is done on the host because the RISC has no
1873 * microsecond accurate timer.
1874 */
1875 AdwDelayMicroSecond((u_int16_t) ADW_SCSI_RESET_HOLD_TIME_US);
1876
1877 /*
1878 * Send the SCSI Bus Reset end idle command which de-asserts
1879 * the SCSI Bus Reset signal and purges any pending requests.
1880 */
1881 status = AdwSendIdleCmd(sc, (u_int16_t) IDLE_CMD_SCSI_RESET_END, 0L);
1882 if (status != ADW_TRUE) {
1883 return status;
1884 }
1885
1886 AdwSleepMilliSecond((u_int32_t) sc->scsi_reset_wait * 1000);
1887
1888 return status;
1889 }
1890
1891
1892 /*
1893 * Reset chip and SCSI Bus.
1894 *
1895 * Return Value:
1896 * ADW_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful.
1897 * ADW_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure.
1898 */
1899 int
AdwResetSCSIBus(sc)1900 AdwResetSCSIBus(sc)
1901 ADW_SOFTC *sc;
1902 {
1903 bus_space_tag_t iot = sc->sc_iot;
1904 bus_space_handle_t ioh = sc->sc_ioh;
1905 int status;
1906 u_int16_t wdtr_able, sdtr_able, ppr_able, tagqng_able;
1907 u_int8_t tid, max_cmd[ADW_MAX_TID + 1];
1908 u_int16_t bios_sig;
1909
1910
1911 /*
1912 * Save current per TID negotiated values.
1913 */
1914 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, wdtr_able);
1915 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able);
1916 if (sc->chip_type == ADW_CHIP_ASC38C1600) {
1917 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, ppr_able);
1918 }
1919 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, tagqng_able);
1920 for (tid = 0; tid <= ADW_MAX_TID; tid++) {
1921 ADW_READ_BYTE_LRAM(iot, ioh, ADW_MC_NUMBER_OF_MAX_CMD + tid,
1922 max_cmd[tid]);
1923 }
1924
1925 /*
1926 * Force the AdwInitAscDriver() function to perform a SCSI Bus Reset
1927 * by clearing the BIOS signature word.
1928 * The initialization functions assumes a SCSI Bus Reset is not
1929 * needed if the BIOS signature word is present.
1930 */
1931 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_BIOS_SIGNATURE, bios_sig);
1932 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_BIOS_SIGNATURE, 0);
1933
1934 /*
1935 * Stop chip and reset it.
1936 */
1937 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RISC_CSR, ADW_RISC_CSR_STOP);
1938 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG,
1939 ADW_CTRL_REG_CMD_RESET);
1940 AdwSleepMilliSecond(100);
1941 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG,
1942 ADW_CTRL_REG_CMD_WR_IO_REG);
1943
1944 /*
1945 * Reset Adw Library error code, if any, and try
1946 * re-initializing the chip.
1947 * Then translate initialization return value to status value.
1948 */
1949 status = (AdwInitDriver(sc) == 0)? ADW_TRUE : ADW_FALSE;
1950
1951 /*
1952 * Restore the BIOS signature word.
1953 */
1954 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_BIOS_SIGNATURE, bios_sig);
1955
1956 /*
1957 * Restore per TID negotiated values.
1958 */
1959 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, wdtr_able);
1960 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able);
1961 if (sc->chip_type == ADW_CHIP_ASC38C1600) {
1962 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, ppr_able);
1963 }
1964 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, tagqng_able);
1965 for (tid = 0; tid <= ADW_MAX_TID; tid++) {
1966 ADW_WRITE_BYTE_LRAM(iot, ioh, ADW_MC_NUMBER_OF_MAX_CMD + tid,
1967 max_cmd[tid]);
1968 }
1969
1970 return status;
1971 }
1972
1973
1974 /*
1975 * Adw Library Interrupt Service Routine
1976 *
1977 * This function is called by a driver's interrupt service routine.
1978 * The function disables and re-enables interrupts.
1979 *
1980 * Note: AdwISR() can be called when interrupts are disabled or even
1981 * when there is no hardware interrupt condition present. It will
1982 * always check for completed idle commands and microcode requests.
1983 * This is an important feature that shouldn't be changed because it
1984 * allows commands to be completed from polling mode loops.
1985 *
1986 * Return:
1987 * ADW_TRUE(1) - interrupt was pending
1988 * ADW_FALSE(0) - no interrupt was pending
1989 */
1990 int
AdwISR(sc)1991 AdwISR(sc)
1992 ADW_SOFTC *sc;
1993 {
1994 bus_space_tag_t iot = sc->sc_iot;
1995 bus_space_handle_t ioh = sc->sc_ioh;
1996 u_int8_t int_stat;
1997 u_int16_t target_bit;
1998 ADW_CARRIER *free_carrp/*, *ccb_carr*/;
1999 u_int32_t irq_next_pa;
2000 ADW_SCSI_REQ_Q *scsiq;
2001 ADW_CCB *ccb;
2002 int s;
2003
2004
2005 s = splbio();
2006
2007 /* Reading the register clears the interrupt. */
2008 int_stat = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_INTR_STATUS_REG);
2009
2010 if ((int_stat & (ADW_INTR_STATUS_INTRA | ADW_INTR_STATUS_INTRB |
2011 ADW_INTR_STATUS_INTRC)) == 0) {
2012 splx(s);
2013 return ADW_FALSE;
2014 }
2015
2016 /*
2017 * Notify the driver of an asynchronous microcode condition by
2018 * calling the ADW_SOFTC.async_callback function. The function
2019 * is passed the microcode ADW_MC_INTRB_CODE byte value.
2020 */
2021 if (int_stat & ADW_INTR_STATUS_INTRB) {
2022 u_int8_t intrb_code;
2023
2024 ADW_READ_BYTE_LRAM(iot, ioh, ADW_MC_INTRB_CODE, intrb_code);
2025
2026 if (sc->chip_type == ADW_CHIP_ASC3550 ||
2027 sc->chip_type == ADW_CHIP_ASC38C0800) {
2028 if (intrb_code == ADW_ASYNC_CARRIER_READY_FAILURE &&
2029 sc->carr_pending_cnt != 0) {
2030 ADW_WRITE_BYTE_REGISTER(iot, ioh,
2031 IOPB_TICKLE, ADW_TICKLE_A);
2032 if (sc->chip_type == ADW_CHIP_ASC3550) {
2033 ADW_WRITE_BYTE_REGISTER(iot, ioh,
2034 IOPB_TICKLE, ADW_TICKLE_NOP);
2035 }
2036 }
2037 }
2038
2039 if (sc->async_callback != 0) {
2040 (*(ADW_ASYNC_CALLBACK)sc->async_callback)(sc, intrb_code);
2041 }
2042 }
2043
2044 /*
2045 * Check if the IRQ stopper carrier contains a completed request.
2046 */
2047 while (((irq_next_pa = sc->irq_sp->next_ba) & ADW_RQ_DONE) != 0)
2048 {
2049 #if ADW_DEBUG
2050 printf("irq 0x%x, 0x%x, 0x%x, 0x%x\n",
2051 sc->irq_sp->carr_id,
2052 sc->irq_sp->carr_ba,
2053 sc->irq_sp->areq_ba,
2054 sc->irq_sp->next_ba);
2055 #endif
2056 /*
2057 * Get a pointer to the newly completed ADW_SCSI_REQ_Q
2058 * structure.
2059 * The RISC will have set 'areq_ba' to a virtual address.
2060 *
2061 * The firmware will have copied the ADW_SCSI_REQ_Q.ccb_ptr
2062 * field to the carrier ADW_CARRIER.areq_ba field.
2063 * The conversion below complements the conversion of
2064 * ADW_SCSI_REQ_Q.ccb_ptr' in AdwExeScsiQueue().
2065 */
2066 ccb = adw_ccb_phys_kv(sc, sc->irq_sp->areq_ba);
2067 scsiq = &ccb->scsiq;
2068 scsiq->ccb_ptr = sc->irq_sp->areq_ba;
2069
2070 /*
2071 * Request finished with good status and the queue was not
2072 * DMAed to host memory by the firmware. Set all status fields
2073 * to indicate good status.
2074 */
2075 if ((irq_next_pa & ADW_RQ_GOOD) != 0) {
2076 scsiq->done_status = QD_NO_ERROR;
2077 scsiq->host_status = scsiq->scsi_status = 0;
2078 scsiq->data_cnt = 0L;
2079 }
2080
2081 /*
2082 * Advance the stopper pointer to the next carrier
2083 * ignoring the lower four bits. Free the previous
2084 * stopper carrier.
2085 */
2086 free_carrp = sc->irq_sp;
2087 sc->irq_sp = ADW_CARRIER_VADDR(sc, ADW_GET_CARRP(irq_next_pa));
2088
2089 if (sc->carr_freelist == NULL)
2090 free_carrp->next_ba = (u_int32_t)NULL;
2091 else free_carrp->next_ba = sc->carr_freelist->carr_ba;
2092 /* microcode requirement :( */
2093 sc->carr_freelist = free_carrp;
2094 sc->carr_pending_cnt--;
2095
2096 target_bit = ADW_TID_TO_TIDMASK(scsiq->target_id);
2097
2098 /*
2099 * Clear request microcode control flag.
2100 */
2101 scsiq->cntl = 0;
2102
2103 /*
2104 * Check Condition handling
2105 */
2106 /*
2107 * If the command that completed was a SCSI INQUIRY and
2108 * LUN 0 was sent the command, then process the INQUIRY
2109 * command information for the device.
2110 */
2111 if (scsiq->done_status == QD_NO_ERROR &&
2112 scsiq->cdb[0] == INQUIRY &&
2113 scsiq->target_lun == 0) {
2114 AdwInquiryHandling(sc, scsiq);
2115 }
2116
2117 /*
2118 * Notify the driver of the completed request by passing
2119 * the ADW_SCSI_REQ_Q pointer to its callback function.
2120 */
2121 (*(ADW_ISR_CALLBACK)sc->isr_callback)(sc, scsiq);
2122 /*
2123 * Note: After the driver callback function is called, 'scsiq'
2124 * can no longer be referenced.
2125 *
2126 * Fall through and continue processing other completed
2127 * requests...
2128 */
2129 }
2130
2131 splx(s);
2132
2133 return ADW_TRUE;
2134 }
2135
2136
2137 /*
2138 * Send an idle command to the chip and wait for completion.
2139 *
2140 * Command completion is polled for once per microsecond.
2141 *
2142 * The function can be called from anywhere including an interrupt handler.
2143 * But the function is not re-entrant, so it uses the splbio/splx()
2144 * functions to prevent reentrancy.
2145 *
2146 * Return Values:
2147 * ADW_TRUE - command completed successfully
2148 * ADW_FALSE - command failed
2149 * ADW_ERROR - command timed out
2150 */
2151 int
AdwSendIdleCmd(sc,idle_cmd,idle_cmd_parameter)2152 AdwSendIdleCmd(sc, idle_cmd, idle_cmd_parameter)
2153 ADW_SOFTC *sc;
2154 u_int16_t idle_cmd;
2155 u_int32_t idle_cmd_parameter;
2156 {
2157 bus_space_tag_t iot = sc->sc_iot;
2158 bus_space_handle_t ioh = sc->sc_ioh;
2159 u_int16_t result;
2160 u_int32_t i, j, s;
2161
2162 s = splbio();
2163
2164 /*
2165 * Clear the idle command status which is set by the microcode
2166 * to a non-zero value to indicate when the command is completed.
2167 */
2168 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD_STATUS, (u_int16_t) 0);
2169
2170 /*
2171 * Write the idle command value after the idle command parameter
2172 * has been written to avoid a race condition. If the order is not
2173 * followed, the microcode may process the idle command before the
2174 * parameters have been written to LRAM.
2175 */
2176 ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD_PARAMETER,
2177 idle_cmd_parameter);
2178 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD, idle_cmd);
2179
2180 /*
2181 * Tickle the RISC to tell it to process the idle command.
2182 */
2183 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADW_TICKLE_B);
2184 if (sc->chip_type == ADW_CHIP_ASC3550) {
2185 /*
2186 * Clear the tickle value. In the ASC-3550 the RISC flag
2187 * command 'clr_tickle_b' does not work unless the host
2188 * value is cleared.
2189 */
2190 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADW_TICKLE_NOP);
2191 }
2192
2193 /* Wait for up to 100 millisecond for the idle command to timeout. */
2194 for (i = 0; i < SCSI_WAIT_100_MSEC; i++) {
2195 /* Poll once each microsecond for command completion. */
2196 for (j = 0; j < SCSI_US_PER_MSEC; j++) {
2197 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD_STATUS,
2198 result);
2199 if (result != 0) {
2200 splx(s);
2201 return result;
2202 }
2203 AdwDelayMicroSecond(1);
2204 }
2205 }
2206
2207 splx(s);
2208 return ADW_ERROR;
2209 }
2210
2211
2212 /*
2213 * Inquiry Information Byte 7 Handling
2214 *
2215 * Handle SCSI Inquiry Command information for a device by setting
2216 * microcode operating variables that affect WDTR, SDTR, and Tag
2217 * Queuing.
2218 */
2219 void
AdwInquiryHandling(sc,scsiq)2220 AdwInquiryHandling(sc, scsiq)
2221 ADW_SOFTC *sc;
2222 ADW_SCSI_REQ_Q *scsiq;
2223 {
2224 #ifndef FAILSAFE
2225 bus_space_tag_t iot = sc->sc_iot;
2226 bus_space_handle_t ioh = sc->sc_ioh;
2227 u_int8_t tid;
2228 ADW_SCSI_INQUIRY *inq;
2229 u_int16_t tidmask;
2230 u_int16_t cfg_word;
2231
2232
2233 /*
2234 * AdwInquiryHandling() requires up to INQUIRY information Byte 7
2235 * to be available.
2236 *
2237 * If less than 8 bytes of INQUIRY information were requested or less
2238 * than 8 bytes were transferred, then return. cdb[4] is the request
2239 * length and the ADW_SCSI_REQ_Q 'data_cnt' field is set by the
2240 * microcode to the transfer residual count.
2241 */
2242
2243 if (scsiq->cdb[4] < 8 || (scsiq->cdb[4] - scsiq->data_cnt) < 8) {
2244 return;
2245 }
2246
2247 tid = scsiq->target_id;
2248
2249 inq = (ADW_SCSI_INQUIRY *) scsiq->vdata_addr;
2250
2251 /*
2252 * WDTR, SDTR, and Tag Queuing cannot be enabled for old devices.
2253 */
2254 if ((inq->rsp_data_fmt < 2) /*SCSI-1 | CCS*/ &&
2255 (inq->ansi_apr_ver < 2)) {
2256 return;
2257 } else {
2258 /*
2259 * INQUIRY Byte 7 Handling
2260 *
2261 * Use a device's INQUIRY byte 7 to determine whether it
2262 * supports WDTR, SDTR, and Tag Queuing. If the feature
2263 * is enabled in the EEPROM and the device supports the
2264 * feature, then enable it in the microcode.
2265 */
2266
2267 tidmask = ADW_TID_TO_TIDMASK(tid);
2268
2269 /*
2270 * Wide Transfers
2271 *
2272 * If the EEPROM enabled WDTR for the device and the device
2273 * supports wide bus (16 bit) transfers, then turn on the
2274 * device's 'wdtr_able' bit and write the new value to the
2275 * microcode.
2276 */
2277 #ifdef SCSI_ADW_WDTR_DISABLE
2278 if(!(tidmask & SCSI_ADW_WDTR_DISABLE))
2279 #endif /* SCSI_ADW_WDTR_DISABLE */
2280 if ((sc->wdtr_able & tidmask) && inq->WBus16) {
2281 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE,
2282 cfg_word);
2283 if ((cfg_word & tidmask) == 0) {
2284 cfg_word |= tidmask;
2285 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE,
2286 cfg_word);
2287
2288 /*
2289 * Clear the microcode "SDTR negotiation" and
2290 * "WDTR negotiation" done indicators for the
2291 * target to cause it to negotiate with the new
2292 * setting set above.
2293 * WDTR when accepted causes the target to enter
2294 * asynchronous mode, so SDTR must be negotiated
2295 */
2296 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE,
2297 cfg_word);
2298 cfg_word &= ~tidmask;
2299 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE,
2300 cfg_word);
2301 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_DONE,
2302 cfg_word);
2303 cfg_word &= ~tidmask;
2304 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_DONE,
2305 cfg_word);
2306 }
2307 }
2308
2309 /*
2310 * Synchronous Transfers
2311 *
2312 * If the EEPROM enabled SDTR for the device and the device
2313 * supports synchronous transfers, then turn on the device's
2314 * 'sdtr_able' bit. Write the new value to the microcode.
2315 */
2316 #ifdef SCSI_ADW_SDTR_DISABLE
2317 if(!(tidmask & SCSI_ADW_SDTR_DISABLE))
2318 #endif /* SCSI_ADW_SDTR_DISABLE */
2319 if ((sc->sdtr_able & tidmask) && inq->Sync) {
2320 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE,cfg_word);
2321 if ((cfg_word & tidmask) == 0) {
2322 cfg_word |= tidmask;
2323 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE,
2324 cfg_word);
2325
2326 /*
2327 * Clear the microcode "SDTR negotiation"
2328 * done indicator for the target to cause it
2329 * to negotiate with the new setting set above.
2330 */
2331 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE,
2332 cfg_word);
2333 cfg_word &= ~tidmask;
2334 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE,
2335 cfg_word);
2336 }
2337 }
2338 /*
2339 * If the Inquiry data included enough space for the SPI-3
2340 * Clocking field, then check if DT mode is supported.
2341 */
2342 if (sc->chip_type == ADW_CHIP_ASC38C1600 &&
2343 (scsiq->cdb[4] >= 57 ||
2344 (scsiq->cdb[4] - scsiq->data_cnt) >= 57)) {
2345 /*
2346 * PPR (Parallel Protocol Request) Capable
2347 *
2348 * If the device supports DT mode, then it must be
2349 * PPR capable.
2350 * The PPR message will be used in place of the SDTR
2351 * and WDTR messages to negotiate synchronous speed
2352 * and offset, transfer width, and protocol options.
2353 */
2354 if((inq->Clocking) & INQ_CLOCKING_DT_ONLY){
2355 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE,
2356 sc->ppr_able);
2357 sc->ppr_able |= tidmask;
2358 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE,
2359 sc->ppr_able);
2360 }
2361 }
2362
2363 /*
2364 * If the EEPROM enabled Tag Queuing for the device and the
2365 * device supports Tag Queueing, then turn on the device's
2366 * 'tagqng_enable' bit in the microcode and set the microcode
2367 * maximum command count to the ADW_SOFTC 'max_dvc_qng'
2368 * value.
2369 *
2370 * Tag Queuing is disabled for the BIOS which runs in polled
2371 * mode and would see no benefit from Tag Queuing. Also by
2372 * disabling Tag Queuing in the BIOS devices with Tag Queuing
2373 * bugs will at least work with the BIOS.
2374 */
2375 #ifdef SCSI_ADW_TAGQ_DISABLE
2376 if(!(tidmask & SCSI_ADW_TAGQ_DISABLE))
2377 #endif /* SCSI_ADW_TAGQ_DISABLE */
2378 if ((sc->tagqng_able & tidmask) && inq->CmdQue) {
2379 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE,
2380 cfg_word);
2381 cfg_word |= tidmask;
2382 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE,
2383 cfg_word);
2384
2385 ADW_WRITE_BYTE_LRAM(iot, ioh,
2386 ADW_MC_NUMBER_OF_MAX_CMD + tid,
2387 sc->max_dvc_qng);
2388 }
2389 }
2390 #endif /* FAILSAFE */
2391 }
2392
2393
2394 void
AdwSleepMilliSecond(n)2395 AdwSleepMilliSecond(n)
2396 u_int32_t n;
2397 {
2398
2399 DELAY(n * 1000);
2400 }
2401
2402
2403 void
AdwDelayMicroSecond(n)2404 AdwDelayMicroSecond(n)
2405 u_int32_t n;
2406 {
2407
2408 DELAY(n);
2409 }
2410