1 /* $MirOS: src/sys/dev/ic/adw.c,v 1.3 2005/11/23 19:24:35 tg Exp $ */
2 /* $OpenBSD: adw.c,v 1.28 2004/01/09 21:32:23 brad Exp $ */
3 /* $NetBSD: adw.c,v 1.23 2000/05/27 18:24:50 dante Exp $ */
4
5 /*
6 * Generic driver for the Advanced Systems Inc. SCSI controllers
7 *
8 * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc.
9 * All rights reserved.
10 *
11 * Author: Baldassare Dante Profeta <dante@mclink.it>
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
21 * 3. All advertising materials mentioning features or use of this software
22 * must display the following acknowledgement:
23 * This product includes software developed by the NetBSD
24 * Foundation, Inc. and its contributors.
25 * 4. Neither the name of The NetBSD Foundation nor the names of its
26 * contributors may be used to endorse or promote products derived
27 * from this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
31 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
32 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
33 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
34 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
37 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
39 * POSSIBILITY OF SUCH DAMAGE.
40 */
41
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/kernel.h>
45 #include <sys/errno.h>
46 #include <sys/ioctl.h>
47 #include <sys/device.h>
48 #include <sys/malloc.h>
49 #include <sys/buf.h>
50 #include <sys/proc.h>
51 #include <sys/user.h>
52 #include <sys/timeout.h>
53
54 #include <machine/bus.h>
55 #include <machine/intr.h>
56
57 #include <scsi/scsi_all.h>
58 #include <scsi/scsiconf.h>
59
60 #include <dev/ic/adwlib.h>
61 #include <dev/microcode/adw/adwmcode.h>
62 #include <dev/ic/adw.h>
63
64 #ifndef DDB
65 #define Debugger() panic("should call debugger here (adw.c)")
66 #endif /* ! DDB */
67
68 #ifdef __PTRDIFF_TYPE__
69 typedef __PTRDIFF_TYPE__ ptrdiff_t;
70 #endif
71
72 /******************************************************************************/
73
74
75 void adw_enqueue(ADW_SOFTC *, struct scsi_xfer *, int);
76 struct scsi_xfer *adw_dequeue(ADW_SOFTC *);
77
78 int adw_alloc_controls(ADW_SOFTC *);
79 int adw_alloc_carriers(ADW_SOFTC *);
80 int adw_create_ccbs(ADW_SOFTC *, ADW_CCB *, int);
81 void adw_free_ccb(ADW_SOFTC *, ADW_CCB *);
82 void adw_reset_ccb(ADW_CCB *);
83 int adw_init_ccb(ADW_SOFTC *, ADW_CCB *);
84 ADW_CCB *adw_get_ccb(ADW_SOFTC *, int);
85 int adw_queue_ccb(ADW_SOFTC *, ADW_CCB *, int);
86
87 int adw_scsi_cmd(struct scsi_xfer *);
88 int adw_build_req(struct scsi_xfer *, ADW_CCB *, int);
89 void adw_build_sglist(ADW_CCB *, ADW_SCSI_REQ_Q *, ADW_SG_BLOCK *);
90 void adw_minphys(struct buf *);
91 void adw_isr_callback(ADW_SOFTC *, ADW_SCSI_REQ_Q *);
92 void adw_async_callback(ADW_SOFTC *, u_int8_t);
93
94 void adw_print_info(ADW_SOFTC *, int);
95
96 int adw_poll(ADW_SOFTC *, struct scsi_xfer *, int);
97 void adw_timeout(void *);
98 void adw_reset_bus(ADW_SOFTC *);
99
100
101 /******************************************************************************/
102
103
104 struct cfdriver adw_cd = {
105 NULL, "adw", DV_DULL
106 };
107
108 /* the below structure is so we have a default dev struct for our link struct */
109 struct scsi_device adw_dev =
110 {
111 NULL, /* Use default error handler */
112 NULL, /* have a queue, served by this */
113 NULL, /* have no async handler */
114 NULL, /* Use default 'done' routine */
115 };
116
117
118 /******************************************************************************/
119 /* scsi_xfer queue routines */
120 /******************************************************************************/
121
122 /*
123 * Insert a scsi_xfer into the software queue. We overload xs->free_list
124 * to avoid having to allocate additional resources (since we're used
125 * only during resource shortages anyhow.
126 */
127 void
adw_enqueue(sc,xs,infront)128 adw_enqueue(sc, xs, infront)
129 ADW_SOFTC *sc;
130 struct scsi_xfer *xs;
131 int infront;
132 {
133
134 if (infront || sc->sc_queue.lh_first == NULL) {
135 if (sc->sc_queue.lh_first == NULL)
136 sc->sc_queuelast = xs;
137 LIST_INSERT_HEAD(&sc->sc_queue, xs, free_list);
138 return;
139 }
140 LIST_INSERT_AFTER(sc->sc_queuelast, xs, free_list);
141 sc->sc_queuelast = xs;
142 }
143
144
145 /*
146 * Pull a scsi_xfer off the front of the software queue.
147 */
148 struct scsi_xfer *
adw_dequeue(sc)149 adw_dequeue(sc)
150 ADW_SOFTC *sc;
151 {
152 struct scsi_xfer *xs;
153
154 xs = sc->sc_queue.lh_first;
155 LIST_REMOVE(xs, free_list);
156
157 if (sc->sc_queue.lh_first == NULL)
158 sc->sc_queuelast = NULL;
159
160 return (xs);
161 }
162
163 /******************************************************************************/
164 /* DMA Mapping for Control Blocks */
165 /******************************************************************************/
166
167
168 int
adw_alloc_controls(sc)169 adw_alloc_controls(sc)
170 ADW_SOFTC *sc;
171 {
172 bus_dma_segment_t seg;
173 int error, rseg;
174
175 /*
176 * Allocate the control structure.
177 */
178 if ((error = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct adw_control),
179 NBPG, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) {
180 printf("%s: unable to allocate control structures,"
181 " error = %d\n", sc->sc_dev.dv_xname, error);
182 return (error);
183 }
184 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg,
185 sizeof(struct adw_control), (caddr_t *) & sc->sc_control,
186 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) {
187 printf("%s: unable to map control structures, error = %d\n",
188 sc->sc_dev.dv_xname, error);
189 return (error);
190 }
191
192 /*
193 * Create and load the DMA map used for the control blocks.
194 */
195 if ((error = bus_dmamap_create(sc->sc_dmat, sizeof(struct adw_control),
196 1, sizeof(struct adw_control), 0, BUS_DMA_NOWAIT,
197 &sc->sc_dmamap_control)) != 0) {
198 printf("%s: unable to create control DMA map, error = %d\n",
199 sc->sc_dev.dv_xname, error);
200 return (error);
201 }
202 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_control,
203 sc->sc_control, sizeof(struct adw_control), NULL,
204 BUS_DMA_NOWAIT)) != 0) {
205 printf("%s: unable to load control DMA map, error = %d\n",
206 sc->sc_dev.dv_xname, error);
207 return (error);
208 }
209
210 return (0);
211 }
212
213
214 int
adw_alloc_carriers(sc)215 adw_alloc_carriers(sc)
216 ADW_SOFTC *sc;
217 {
218 bus_dma_segment_t seg;
219 int error, rseg;
220
221 /*
222 * Allocate the control structure.
223 */
224 sc->sc_control->carriers =
225 malloc(sizeof(ADW_CARRIER) * ADW_MAX_CARRIER, M_DEVBUF,
226 M_NOWAIT);
227 if (sc->sc_control->carriers == NULL)
228 return (ENOMEM);
229
230
231 if ((error = bus_dmamem_alloc(sc->sc_dmat,
232 sizeof(ADW_CARRIER) * ADW_MAX_CARRIER,
233 0x10, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) {
234 printf("%s: unable to allocate carrier structures,"
235 " error = %d\n", sc->sc_dev.dv_xname, error);
236 return (error);
237 }
238 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg,
239 sizeof(ADW_CARRIER) * ADW_MAX_CARRIER,
240 (caddr_t *) &sc->sc_control->carriers,
241 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) {
242 printf("%s: unable to map carrier structures,"
243 " error = %d\n", sc->sc_dev.dv_xname, error);
244 return (error);
245 }
246
247 /*
248 * Create and load the DMA map used for the control blocks.
249 */
250 if ((error = bus_dmamap_create(sc->sc_dmat,
251 sizeof(ADW_CARRIER) * ADW_MAX_CARRIER, 1,
252 sizeof(ADW_CARRIER) * ADW_MAX_CARRIER, 0,BUS_DMA_NOWAIT,
253 &sc->sc_dmamap_carrier)) != 0) {
254 printf("%s: unable to create carriers DMA map,"
255 " error = %d\n", sc->sc_dev.dv_xname, error);
256 return (error);
257 }
258 if ((error = bus_dmamap_load(sc->sc_dmat,
259 sc->sc_dmamap_carrier, sc->sc_control->carriers,
260 sizeof(ADW_CARRIER) * ADW_MAX_CARRIER, NULL,
261 BUS_DMA_NOWAIT)) != 0) {
262 printf("%s: unable to load carriers DMA map,"
263 " error = %d\n", sc->sc_dev.dv_xname, error);
264 return (error);
265 }
266
267 return (0);
268 }
269
270
271 /******************************************************************************/
272 /* Control Blocks routines */
273 /******************************************************************************/
274
275
276 /*
277 * Create a set of ccbs and add them to the free list. Called once
278 * by adw_init(). We return the number of CCBs successfully created.
279 */
280 int
adw_create_ccbs(sc,ccbstore,count)281 adw_create_ccbs(sc, ccbstore, count)
282 ADW_SOFTC *sc;
283 ADW_CCB *ccbstore;
284 int count;
285 {
286 ADW_CCB *ccb;
287 int i, error;
288
289 for (i = 0; i < count; i++) {
290 ccb = &ccbstore[i];
291 if ((error = adw_init_ccb(sc, ccb)) != 0) {
292 printf("%s: unable to initialize ccb, error = %d\n",
293 sc->sc_dev.dv_xname, error);
294 return (i);
295 }
296 TAILQ_INSERT_TAIL(&sc->sc_free_ccb, ccb, chain);
297 }
298
299 return (i);
300 }
301
302
303 /*
304 * A ccb is put onto the free list.
305 */
306 void
adw_free_ccb(sc,ccb)307 adw_free_ccb(sc, ccb)
308 ADW_SOFTC *sc;
309 ADW_CCB *ccb;
310 {
311 int s;
312
313 s = splbio();
314
315 adw_reset_ccb(ccb);
316 TAILQ_INSERT_HEAD(&sc->sc_free_ccb, ccb, chain);
317
318 /*
319 * If there were none, wake anybody waiting for one to come free,
320 * starting with queued entries.
321 */
322 if (ccb->chain.tqe_next == 0)
323 wakeup(&sc->sc_free_ccb);
324
325 splx(s);
326 }
327
328
329 void
adw_reset_ccb(ccb)330 adw_reset_ccb(ccb)
331 ADW_CCB *ccb;
332 {
333
334 ccb->flags = 0;
335 }
336
337
338 int
adw_init_ccb(sc,ccb)339 adw_init_ccb(sc, ccb)
340 ADW_SOFTC *sc;
341 ADW_CCB *ccb;
342 {
343 int hashnum, error;
344
345 /*
346 * Create the DMA map for this CCB.
347 */
348 error = bus_dmamap_create(sc->sc_dmat,
349 (ADW_MAX_SG_LIST - 1) * PAGE_SIZE,
350 ADW_MAX_SG_LIST, (ADW_MAX_SG_LIST - 1) * PAGE_SIZE,
351 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ccb->dmamap_xfer);
352 if (error) {
353 printf("%s: unable to create CCB DMA map, error = %d\n",
354 sc->sc_dev.dv_xname, error);
355 return (error);
356 }
357
358 /*
359 * put in the phystokv hash table
360 * Never gets taken out.
361 */
362 ccb->hashkey = sc->sc_dmamap_control->dm_segs[0].ds_addr +
363 ADW_CCB_OFF(ccb);
364 hashnum = CCB_HASH(ccb->hashkey);
365 ccb->nexthash = sc->sc_ccbhash[hashnum];
366 sc->sc_ccbhash[hashnum] = ccb;
367 adw_reset_ccb(ccb);
368 return (0);
369 }
370
371
372 /*
373 * Get a free ccb
374 *
375 * If there are none, see if we can allocate a new one
376 */
377 ADW_CCB *
adw_get_ccb(sc,flags)378 adw_get_ccb(sc, flags)
379 ADW_SOFTC *sc;
380 int flags;
381 {
382 ADW_CCB *ccb = 0;
383 int s;
384
385 s = splbio();
386
387 /*
388 * If we can and have to, sleep waiting for one to come free
389 * but only if we can't allocate a new one.
390 */
391 for (;;) {
392 ccb = sc->sc_free_ccb.tqh_first;
393 if (ccb) {
394 TAILQ_REMOVE(&sc->sc_free_ccb, ccb, chain);
395 break;
396 }
397 if ((flags & SCSI_NOSLEEP) != 0)
398 goto out;
399
400 tsleep(&sc->sc_free_ccb, PRIBIO, "adwccb", 0);
401 }
402
403 ccb->flags |= CCB_ALLOC;
404
405 out:
406 splx(s);
407 return (ccb);
408 }
409
410
411 /*
412 * Given a physical address, find the ccb that it corresponds to.
413 */
414 ADW_CCB *
adw_ccb_phys_kv(sc,ccb_phys)415 adw_ccb_phys_kv(sc, ccb_phys)
416 ADW_SOFTC *sc;
417 u_int32_t ccb_phys;
418 {
419 int hashnum = CCB_HASH(ccb_phys);
420 ADW_CCB *ccb = sc->sc_ccbhash[hashnum];
421
422 while (ccb) {
423 if (ccb->hashkey == ccb_phys)
424 break;
425 ccb = ccb->nexthash;
426 }
427 return (ccb);
428 }
429
430
431 /*
432 * Queue a CCB to be sent to the controller, and send it if possible.
433 */
434 int
adw_queue_ccb(sc,ccb,retry)435 adw_queue_ccb(sc, ccb, retry)
436 ADW_SOFTC *sc;
437 ADW_CCB *ccb;
438 int retry;
439 {
440 int errcode = ADW_SUCCESS;
441
442 if(!retry) {
443 TAILQ_INSERT_TAIL(&sc->sc_waiting_ccb, ccb, chain);
444 }
445
446 while ((ccb = sc->sc_waiting_ccb.tqh_first) != NULL) {
447
448 errcode = AdwExeScsiQueue(sc, &ccb->scsiq);
449 switch(errcode) {
450 case ADW_SUCCESS:
451 break;
452
453 case ADW_BUSY:
454 printf("ADW_BUSY\n");
455 return(ADW_BUSY);
456
457 case ADW_ERROR:
458 printf("ADW_ERROR\n");
459 TAILQ_REMOVE(&sc->sc_waiting_ccb, ccb, chain);
460 return(ADW_ERROR);
461 }
462
463 TAILQ_REMOVE(&sc->sc_waiting_ccb, ccb, chain);
464 TAILQ_INSERT_TAIL(&sc->sc_pending_ccb, ccb, chain);
465
466 /* ALWAYS initialize stimeout, lest it contain garbage! */
467 timeout_set(&ccb->xs->stimeout, adw_timeout, ccb);
468 if ((ccb->xs->flags & SCSI_POLL) == 0)
469 timeout_add(&ccb->xs->stimeout, (ccb->timeout * hz) / 1000);
470 }
471
472 return(errcode);
473 }
474
475
476 /******************************************************************************/
477 /* SCSI layer interfacing routines */
478 /******************************************************************************/
479
480
481 int
adw_init(sc)482 adw_init(sc)
483 ADW_SOFTC *sc;
484 {
485 u_int16_t warn_code;
486
487
488 sc->cfg.lib_version = (ADW_LIB_VERSION_MAJOR << 8) |
489 ADW_LIB_VERSION_MINOR;
490 sc->cfg.chip_version =
491 ADW_GET_CHIP_VERSION(sc->sc_iot, sc->sc_ioh, sc->bus_type);
492
493 /*
494 * Reset the chip to start and allow register writes.
495 */
496 if (ADW_FIND_SIGNATURE(sc->sc_iot, sc->sc_ioh) == 0) {
497 panic("adw_init: adw_find_signature failed");
498 } else {
499 AdwResetChip(sc->sc_iot, sc->sc_ioh);
500
501 warn_code = AdwInitFromEEPROM(sc);
502
503 if (warn_code & ADW_WARN_EEPROM_CHKSUM)
504 printf("%s: Bad checksum found. "
505 "Setting default values\n",
506 sc->sc_dev.dv_xname);
507 if (warn_code & ADW_WARN_EEPROM_TERMINATION)
508 printf("%s: Bad bus termination setting."
509 "Using automatic termination.\n",
510 sc->sc_dev.dv_xname);
511 }
512
513 sc->isr_callback = (ADW_CALLBACK) adw_isr_callback;
514 sc->async_callback = (ADW_CALLBACK) adw_async_callback;
515
516 return 0;
517 }
518
519
520 void
adw_attach(sc)521 adw_attach(sc)
522 ADW_SOFTC *sc;
523 {
524 int i, error;
525
526
527 TAILQ_INIT(&sc->sc_free_ccb);
528 TAILQ_INIT(&sc->sc_waiting_ccb);
529 TAILQ_INIT(&sc->sc_pending_ccb);
530 LIST_INIT(&sc->sc_queue);
531
532
533 /*
534 * Allocate the Control Blocks.
535 */
536 error = adw_alloc_controls(sc);
537 if (error)
538 return; /* (error) */ ;
539
540 bzero(sc->sc_control, sizeof(struct adw_control));
541
542 /*
543 * Create and initialize the Control Blocks.
544 */
545 i = adw_create_ccbs(sc, sc->sc_control->ccbs, ADW_MAX_CCB);
546 if (i == 0) {
547 printf("%s: unable to create Control Blocks\n",
548 sc->sc_dev.dv_xname);
549 return; /* (ENOMEM) */ ;
550 } else if (i != ADW_MAX_CCB) {
551 printf("%s: WARNING: only %d of %d Control Blocks"
552 " created\n",
553 sc->sc_dev.dv_xname, i, ADW_MAX_CCB);
554 }
555
556 /*
557 * Create and initialize the Carriers.
558 */
559 error = adw_alloc_carriers(sc);
560 if (error)
561 return; /* (error) */ ;
562
563 /*
564 * Zero's the freeze_device status
565 */
566 bzero(sc->sc_freeze_dev, sizeof(sc->sc_freeze_dev));
567
568 /*
569 * Initialize the adapter
570 */
571 switch (AdwInitDriver(sc)) {
572 case ADW_IERR_BIST_PRE_TEST:
573 panic("%s: BIST pre-test error",
574 sc->sc_dev.dv_xname);
575 break;
576
577 case ADW_IERR_BIST_RAM_TEST:
578 panic("%s: BIST RAM test error",
579 sc->sc_dev.dv_xname);
580 break;
581
582 case ADW_IERR_MCODE_CHKSUM:
583 panic("%s: Microcode checksum error",
584 sc->sc_dev.dv_xname);
585 break;
586
587 case ADW_IERR_ILLEGAL_CONNECTION:
588 panic("%s: All three connectors are in use",
589 sc->sc_dev.dv_xname);
590 break;
591
592 case ADW_IERR_REVERSED_CABLE:
593 panic("%s: Cable is reversed",
594 sc->sc_dev.dv_xname);
595 break;
596
597 case ADW_IERR_HVD_DEVICE:
598 panic("%s: HVD attached to LVD connector",
599 sc->sc_dev.dv_xname);
600 break;
601
602 case ADW_IERR_SINGLE_END_DEVICE:
603 panic("%s: single-ended device is attached to"
604 " one of the connectors",
605 sc->sc_dev.dv_xname);
606 break;
607
608 case ADW_IERR_NO_CARRIER:
609 panic("%s: unable to create Carriers",
610 sc->sc_dev.dv_xname);
611 break;
612
613 case ADW_WARN_BUSRESET_ERROR:
614 printf("%s: WARNING: Bus Reset Error\n",
615 sc->sc_dev.dv_xname);
616 break;
617 }
618
619 /*
620 * Fill in the adapter.
621 */
622 sc->sc_adapter.scsi_cmd = adw_scsi_cmd;
623 sc->sc_adapter.scsi_minphys = adw_minphys;
624
625 /*
626 * fill in the prototype scsi_link.
627 */
628 sc->sc_link.adapter_softc = sc;
629 sc->sc_link.adapter_target = sc->chip_scsi_id;
630 sc->sc_link.adapter = &sc->sc_adapter;
631 sc->sc_link.device = &adw_dev;
632 sc->sc_link.openings = 4;
633 sc->sc_link.adapter_buswidth = ADW_MAX_TID+1;
634
635 config_found(&sc->sc_dev, &sc->sc_link, scsiprint);
636 }
637
638
639 void
adw_minphys(bp)640 adw_minphys(bp)
641 struct buf *bp;
642 {
643
644 if (bp->b_bcount > ((ADW_MAX_SG_LIST - 1) * PAGE_SIZE))
645 bp->b_bcount = ((ADW_MAX_SG_LIST - 1) * PAGE_SIZE);
646 minphys(bp);
647 }
648
649
650 /*
651 * start a scsi operation given the command and the data address.
652 * Also needs the unit, target and lu.
653 */
654 int
adw_scsi_cmd(xs)655 adw_scsi_cmd(xs)
656 struct scsi_xfer *xs;
657 {
658 struct scsi_link *sc_link = xs->sc_link;
659 ADW_SOFTC *sc = sc_link->adapter_softc;
660 ADW_CCB *ccb;
661 int s, fromqueue = 1, dontqueue = 0, nowait = 0, retry = 0;
662 int flags;
663
664 s = splbio(); /* protect the queue */
665
666 /*
667 * If we're running the queue from adw_done(), we've been
668 * called with the first queue entry as our argument.
669 */
670 if (xs == sc->sc_queue.lh_first) {
671 if(sc->sc_freeze_dev[xs->sc_link->target]) {
672 splx(s);
673 return (TRY_AGAIN_LATER);
674 }
675 xs = adw_dequeue(sc);
676 fromqueue = 1;
677 nowait = 1;
678 } else {
679 if(sc->sc_freeze_dev[xs->sc_link->target]) {
680 splx(s);
681 xs->error = XS_DRIVER_STUFFUP;
682 return (TRY_AGAIN_LATER);
683 }
684
685 /* Polled requests can't be queued for later. */
686 dontqueue = xs->flags & SCSI_POLL;
687
688 /*
689 * If there are jobs in the queue, run them first.
690 */
691 if (sc->sc_queue.lh_first != NULL) {
692 /*
693 * If we can't queue, we have to abort, since
694 * we have to preserve order.
695 */
696 if (dontqueue) {
697 splx(s);
698 xs->error = XS_DRIVER_STUFFUP;
699 return (TRY_AGAIN_LATER);
700 }
701 /*
702 * Swap with the first queue entry.
703 */
704 adw_enqueue(sc, xs, 0);
705 xs = adw_dequeue(sc);
706 fromqueue = 1;
707 }
708 }
709
710
711 /*
712 * get a ccb to use. If the transfer
713 * is from a buf (possibly from interrupt time)
714 * then we can't allow it to sleep
715 */
716
717 flags = xs->flags;
718 if (nowait)
719 flags |= SCSI_NOSLEEP;
720 if ((ccb = adw_get_ccb(sc, flags)) == NULL) {
721 /*
722 * If we can't queue, we lose.
723 */
724 if (dontqueue) {
725 splx(s);
726 xs->error = XS_DRIVER_STUFFUP;
727 return (TRY_AGAIN_LATER);
728 }
729 /*
730 * Stuff ourselves into the queue, in front
731 * if we came off in the first place.
732 */
733 adw_enqueue(sc, xs, fromqueue);
734 splx(s);
735 return (SUCCESSFULLY_QUEUED);
736 }
737 splx(s); /* done playing with the queue */
738
739 ccb->xs = xs;
740 ccb->timeout = xs->timeout;
741
742 if (adw_build_req(xs, ccb, flags)) {
743 retryagain:
744 s = splbio();
745 retry = adw_queue_ccb(sc, ccb, retry);
746 splx(s);
747
748 switch(retry) {
749 case ADW_BUSY:
750 goto retryagain;
751
752 case ADW_ERROR:
753 xs->error = XS_DRIVER_STUFFUP;
754 return (COMPLETE);
755 }
756
757 /*
758 * Usually return SUCCESSFULLY QUEUED
759 */
760 if ((xs->flags & SCSI_POLL) == 0)
761 return (SUCCESSFULLY_QUEUED);
762
763 /*
764 * If we can't use interrupts, poll on completion
765 */
766 if (adw_poll(sc, xs, ccb->timeout)) {
767 adw_timeout(ccb);
768 if (adw_poll(sc, xs, ccb->timeout))
769 adw_timeout(ccb);
770 }
771 }
772 return (COMPLETE);
773 }
774
775
776 /*
777 * Build a request structure for the Wide Boards.
778 */
779 int
adw_build_req(xs,ccb,flags)780 adw_build_req(xs, ccb, flags)
781 struct scsi_xfer *xs;
782 ADW_CCB *ccb;
783 int flags;
784 {
785 struct scsi_link *sc_link = xs->sc_link;
786 ADW_SOFTC *sc = sc_link->adapter_softc;
787 bus_dma_tag_t dmat = sc->sc_dmat;
788 ADW_SCSI_REQ_Q *scsiqp;
789 int error;
790
791 scsiqp = &ccb->scsiq;
792 bzero(scsiqp, sizeof(ADW_SCSI_REQ_Q));
793
794 /*
795 * Set the ADW_SCSI_REQ_Q 'ccb_ptr' to point to the
796 * physical CCB structure.
797 */
798 scsiqp->ccb_ptr = ccb->hashkey;
799
800 /*
801 * Build the ADW_SCSI_REQ_Q request.
802 */
803
804 /*
805 * Set CDB length and copy it to the request structure.
806 * For wide boards a CDB length maximum of 16 bytes
807 * is supported.
808 */
809 bcopy(xs->cmd, &scsiqp->cdb, ((scsiqp->cdb_len = xs->cmdlen) <= 12)?
810 xs->cmdlen : 12 );
811 if(xs->cmdlen > 12)
812 bcopy(&(xs->cmd[12]), &scsiqp->cdb16, xs->cmdlen - 12);
813
814 scsiqp->target_id = sc_link->target;
815 scsiqp->target_lun = sc_link->lun;
816
817 scsiqp->vsense_addr = &ccb->scsi_sense;
818 scsiqp->sense_addr = sc->sc_dmamap_control->dm_segs[0].ds_addr +
819 ADW_CCB_OFF(ccb) + offsetof(struct adw_ccb, scsi_sense);
820 scsiqp->sense_len = sizeof(struct scsi_sense_data);
821
822 /*
823 * Build ADW_SCSI_REQ_Q for a scatter-gather buffer command.
824 */
825 if (xs->datalen) {
826 /*
827 * Map the DMA transfer.
828 */
829 #ifdef TFS
830 if (xs->flags & SCSI_DATA_UIO) {
831 error = bus_dmamap_load_uio(dmat,
832 ccb->dmamap_xfer, (struct uio *) xs->data,
833 (flags & SCSI_NOSLEEP) ?
834 BUS_DMA_NOWAIT : BUS_DMA_WAITOK);
835 } else
836 #endif /* TFS */
837 {
838 error = bus_dmamap_load(dmat,
839 ccb->dmamap_xfer, xs->data, xs->datalen, NULL,
840 (flags & SCSI_NOSLEEP) ?
841 BUS_DMA_NOWAIT : BUS_DMA_WAITOK);
842 }
843
844 if (error) {
845 if (error == EFBIG) {
846 printf("%s: adw_scsi_cmd, more than %d dma"
847 " segments\n",
848 sc->sc_dev.dv_xname, ADW_MAX_SG_LIST);
849 } else {
850 printf("%s: adw_scsi_cmd, error %d loading"
851 " dma map\n",
852 sc->sc_dev.dv_xname, error);
853 }
854
855 xs->error = XS_DRIVER_STUFFUP;
856 adw_free_ccb(sc, ccb);
857 return (0);
858 }
859 bus_dmamap_sync(dmat, ccb->dmamap_xfer,
860 0, ccb->dmamap_xfer->dm_mapsize,
861 (xs->flags & SCSI_DATA_IN) ?
862 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
863
864 /*
865 * Build scatter-gather list.
866 */
867 scsiqp->data_cnt = xs->datalen;
868 scsiqp->vdata_addr = xs->data;
869 scsiqp->data_addr = ccb->dmamap_xfer->dm_segs[0].ds_addr;
870 bzero(ccb->sg_block, sizeof(ADW_SG_BLOCK) * ADW_NUM_SG_BLOCK);
871 adw_build_sglist(ccb, scsiqp, ccb->sg_block);
872 } else {
873 /*
874 * No data xfer, use non S/G values.
875 */
876 scsiqp->data_cnt = 0;
877 scsiqp->vdata_addr = 0;
878 scsiqp->data_addr = 0;
879 }
880
881 return (1);
882 }
883
884
885 /*
886 * Build scatter-gather list for Wide Boards.
887 */
888 void
adw_build_sglist(ccb,scsiqp,sg_block)889 adw_build_sglist(ccb, scsiqp, sg_block)
890 ADW_CCB *ccb;
891 ADW_SCSI_REQ_Q *scsiqp;
892 ADW_SG_BLOCK *sg_block;
893 {
894 u_long sg_block_next_addr; /* block and its next */
895 ptrdiff_t sg_block_physical_addr;
896 int i; /* how many SG entries */
897 bus_dma_segment_t *sg_list = &ccb->dmamap_xfer->dm_segs[0];
898 int sg_elem_cnt = ccb->dmamap_xfer->dm_nsegs;
899
900
901 sg_block_next_addr = (u_long) sg_block; /* allow math operation */
902 sg_block_physical_addr = ccb->hashkey +
903 offsetof(struct adw_ccb, sg_block[0]);
904 scsiqp->sg_real_addr = sg_block_physical_addr;
905
906 /*
907 * If there are more than NO_OF_SG_PER_BLOCK dma segments (hw sg-list)
908 * then split the request into multiple sg-list blocks.
909 */
910
911 do {
912 for (i = 0; i < NO_OF_SG_PER_BLOCK; i++) {
913 sg_block->sg_list[i].sg_addr = sg_list->ds_addr;
914 sg_block->sg_list[i].sg_count = sg_list->ds_len;
915
916 if (--sg_elem_cnt == 0) {
917 /* last entry, get out */
918 sg_block->sg_cnt = i + 1;
919 sg_block->sg_ptr = NULL; /* next link = NULL */
920 return;
921 }
922 sg_list++;
923 }
924 sg_block_next_addr += sizeof(ADW_SG_BLOCK);
925 sg_block_physical_addr += sizeof(ADW_SG_BLOCK);
926
927 sg_block->sg_cnt = NO_OF_SG_PER_BLOCK;
928 sg_block->sg_ptr = (void *)sg_block_physical_addr;
929 sg_block = (ADW_SG_BLOCK *) sg_block_next_addr; /* virt. addr */
930 } while (1);
931 }
932
933
934 /******************************************************************************/
935 /* Interrupts and TimeOut routines */
936 /******************************************************************************/
937
938
939 int
adw_intr(arg)940 adw_intr(arg)
941 void *arg;
942 {
943 ADW_SOFTC *sc = arg;
944 struct scsi_xfer *xs;
945
946
947 if(AdwISR(sc) != ADW_FALSE) {
948 /*
949 * If there are queue entries in the software queue, try to
950 * run the first one. We should be more or less guaranteed
951 * to succeed, since we just freed a CCB.
952 *
953 * NOTE: adw_scsi_cmd() relies on our calling it with
954 * the first entry in the queue.
955 */
956 if ((xs = sc->sc_queue.lh_first) != NULL)
957 (void) adw_scsi_cmd(xs);
958
959 return (1);
960 }
961
962 return (0);
963 }
964
965
966 /*
967 * Poll a particular unit, looking for a particular xs
968 */
969 int
adw_poll(sc,xs,count)970 adw_poll(sc, xs, count)
971 ADW_SOFTC *sc;
972 struct scsi_xfer *xs;
973 int count;
974 {
975
976 /* timeouts are in msec, so we loop in 1000 usec cycles */
977 while (count > 0) {
978 adw_intr(sc);
979 if (xs->flags & ITSDONE) {
980 if ((xs->cmd->opcode == INQUIRY)
981 && (xs->sc_link->lun == 0)
982 && (xs->error == XS_NOERROR))
983 adw_print_info(sc, xs->sc_link->target);
984 return (0);
985 }
986 delay(1000); /* only happens in boot so ok */
987 count--;
988 }
989 return (1);
990 }
991
992
993 void
adw_timeout(arg)994 adw_timeout(arg)
995 void *arg;
996 {
997 ADW_CCB *ccb = arg;
998 struct scsi_xfer *xs = ccb->xs;
999 struct scsi_link *sc_link = xs->sc_link;
1000 ADW_SOFTC *sc = sc_link->adapter_softc;
1001 int s;
1002
1003 sc_print_addr(sc_link);
1004 printf("timed out");
1005
1006 s = splbio();
1007
1008 if (ccb->flags & CCB_ABORTED) {
1009 /*
1010 * Abort Timed Out
1011 *
1012 * No more opportunities. Lets try resetting the bus and
1013 * reinitialize the host adapter.
1014 */
1015 timeout_del(&xs->stimeout);
1016 printf(" AGAIN. Resetting SCSI Bus\n");
1017 adw_reset_bus(sc);
1018 splx(s);
1019 return;
1020 } else if (ccb->flags & CCB_ABORTING) {
1021 /*
1022 * Abort the operation that has timed out.
1023 *
1024 * Second opportunity.
1025 */
1026 printf("\n");
1027 xs->error = XS_TIMEOUT;
1028 ccb->flags |= CCB_ABORTED;
1029 #if 0
1030 /*
1031 * - XXX - 3.3a microcode is BROKEN!!!
1032 *
1033 * We cannot abort a CCB, so we can only hope the command
1034 * get completed before the next timeout, otherwise a
1035 * Bus Reset will arrive inexorably.
1036 */
1037 /*
1038 * ADW_ABORT_CCB() makes the board to generate an interrupt
1039 *
1040 * - XXX - The above assertion MUST be verified (and this
1041 * code changed as well [callout_*()]), when the
1042 * ADW_ABORT_CCB will be working again
1043 */
1044 ADW_ABORT_CCB(sc, ccb);
1045 #endif
1046 /*
1047 * waiting for multishot callout_reset() let's restart it
1048 * by hand so the next time a timeout event will occur
1049 * we will reset the bus.
1050 */
1051 timeout_add(&xs->stimeout, (ccb->timeout * hz) / 1000);
1052 } else {
1053 /*
1054 * Abort the operation that has timed out.
1055 *
1056 * First opportunity.
1057 */
1058 printf("\n");
1059 xs->error = XS_TIMEOUT;
1060 ccb->flags |= CCB_ABORTING;
1061 #if 0
1062 /*
1063 * - XXX - 3.3a microcode is BROKEN!!!
1064 *
1065 * We cannot abort a CCB, so we can only hope the command
1066 * get completed before the next 2 timeout, otherwise a
1067 * Bus Reset will arrive inexorably.
1068 */
1069 /*
1070 * ADW_ABORT_CCB() makes the board to generate an interrupt
1071 *
1072 * - XXX - The above assertion MUST be verified (and this
1073 * code changed as well [callout_*()]), when the
1074 * ADW_ABORT_CCB will be working again
1075 */
1076 ADW_ABORT_CCB(sc, ccb);
1077 #endif
1078 /*
1079 * waiting for multishot callout_reset() let's restart it
1080 * by hand so to give a second opportunity to the command
1081 * which timed-out.
1082 */
1083 timeout_add(&xs->stimeout, (ccb->timeout * hz) / 1000);
1084 }
1085
1086 splx(s);
1087 }
1088
1089
1090 void
adw_reset_bus(sc)1091 adw_reset_bus(sc)
1092 ADW_SOFTC *sc;
1093 {
1094 ADW_CCB *ccb;
1095 int s;
1096
1097 s = splbio();
1098 AdwResetSCSIBus(sc); /* XXX - should check return value? */
1099 while((ccb = TAILQ_LAST(&sc->sc_pending_ccb,
1100 adw_pending_ccb)) != NULL) {
1101 timeout_del(&ccb->xs->stimeout);
1102 TAILQ_REMOVE(&sc->sc_pending_ccb, ccb, chain);
1103 TAILQ_INSERT_HEAD(&sc->sc_waiting_ccb, ccb, chain);
1104 }
1105
1106 bzero(sc->sc_freeze_dev, sizeof(sc->sc_freeze_dev));
1107 adw_queue_ccb(sc, TAILQ_FIRST(&sc->sc_waiting_ccb), 1);
1108
1109 splx(s);
1110 }
1111
1112
1113 /******************************************************************************/
1114 /* Host Adapter and Peripherals Information Routines */
1115 /******************************************************************************/
1116
1117
1118 void
adw_print_info(sc,tid)1119 adw_print_info(sc, tid)
1120 ADW_SOFTC *sc;
1121 int tid;
1122 {
1123 bus_space_handle_t ioh = sc->sc_ioh;
1124 bus_space_tag_t iot = sc->sc_iot;
1125 u_int16_t hshk_cfg, able_mask, period = 0;
1126
1127 /* hshk/HSHK means 'handskake' */
1128
1129 ADW_READ_WORD_LRAM(iot, ioh,
1130 ADW_MC_DEVICE_HSHK_CFG_TABLE + (2 * tid), hshk_cfg);
1131
1132 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, able_mask);
1133 if ((able_mask & ADW_TID_TO_TIDMASK(tid)) == 0)
1134 hshk_cfg &= ~HSHK_CFG_WIDE_XFR;
1135
1136 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, able_mask);
1137 if ((able_mask & ADW_TID_TO_TIDMASK(tid)) == 0)
1138 hshk_cfg &= ~HSHK_CFG_OFFSET;
1139
1140 printf("%s: target %d using %d bit ", sc->sc_dev.dv_xname, tid,
1141 (hshk_cfg & HSHK_CFG_WIDE_XFR) ? 16 : 8);
1142
1143 if ((hshk_cfg & HSHK_CFG_OFFSET) == 0)
1144 printf("async ");
1145 else {
1146 period = (hshk_cfg & 0x1f00) >> 8;
1147 switch (period) {
1148 case 0x11:
1149 printf("80.0 ");
1150 break;
1151 case 0x10:
1152 printf("40.0 ");
1153 break;
1154 default:
1155 period = (period * 25) + 50;
1156 printf("%d.%d ", 1000/period, ADW_TENTHS(1000, period));
1157 break;
1158 }
1159 printf("MHz %d REQ/ACK offset ", hshk_cfg & HSHK_CFG_OFFSET);
1160 }
1161
1162 printf("xfers\n");
1163 }
1164
1165
1166 /******************************************************************************/
1167 /* WIDE boards Interrupt callbacks */
1168 /******************************************************************************/
1169
1170
1171 /*
1172 * adw_isr_callback() - Second Level Interrupt Handler called by AdwISR()
1173 *
1174 * Interrupt callback function for the Wide SCSI Adw Library.
1175 *
1176 * Notice:
1177 * Interrupts are disabled by the caller (AdwISR() function), and will be
1178 * enabled at the end of the caller.
1179 */
1180 void
adw_isr_callback(sc,scsiq)1181 adw_isr_callback(sc, scsiq)
1182 ADW_SOFTC *sc;
1183 ADW_SCSI_REQ_Q *scsiq;
1184 {
1185 bus_dma_tag_t dmat;
1186 ADW_CCB *ccb;
1187 struct scsi_xfer *xs;
1188 struct scsi_sense_data *s1, *s2;
1189
1190
1191 ccb = adw_ccb_phys_kv(sc, scsiq->ccb_ptr);
1192 TAILQ_REMOVE(&sc->sc_pending_ccb, ccb, chain);
1193
1194 if ((ccb->flags & CCB_ALLOC) == 0) {
1195 printf("%s: unallocated ccb found on pending list!\n",
1196 sc->sc_dev.dv_xname);
1197 Debugger();
1198 adw_free_ccb(sc, ccb);
1199 return;
1200 }
1201
1202 xs = ccb->xs;
1203 timeout_del(&xs->stimeout);
1204
1205 /*
1206 * If we were a data transfer, unload the map that described
1207 * the data buffer.
1208 */
1209 dmat = sc->sc_dmat;
1210 if (xs->datalen) {
1211 bus_dmamap_sync(dmat, ccb->dmamap_xfer,
1212 0, ccb->dmamap_xfer->dm_mapsize,
1213 ((xs->flags & SCSI_DATA_IN) ?
1214 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE));
1215 bus_dmamap_unload(dmat, ccb->dmamap_xfer);
1216 }
1217
1218 /*
1219 * 'done_status' contains the command's ending status.
1220 * 'host_status' contains the host adapter status.
1221 * 'scsi_status' contains the scsi peripheral status.
1222 */
1223
1224 sc->sc_freeze_dev[scsiq->target_id] = 0;
1225 xs->status = scsiq->scsi_status;
1226
1227 switch (scsiq->done_status) {
1228 case QD_NO_ERROR: /* (scsi_status == 0) && (host_status == 0) */
1229 NO_ERROR:
1230 xs->resid = scsiq->data_cnt;
1231 xs->error = XS_NOERROR;
1232 break;
1233
1234 case QD_WITH_ERROR:
1235 switch (scsiq->host_status) {
1236 case QHSTA_NO_ERROR:
1237 switch (scsiq->scsi_status) {
1238 case SCSI_COND_MET:
1239 case SCSI_INTERM:
1240 case SCSI_INTERM_COND_MET:
1241 /*
1242 * These non-zero status values are
1243 * not really error conditions.
1244 *
1245 * XXX - would it be too paranoid to
1246 * add SCSI_OK here in
1247 * case the docs are wrong re
1248 * QD_NO_ERROR?
1249 */
1250 goto NO_ERROR;
1251
1252 case SCSI_CHECK:
1253 case SCSI_TERMINATED:
1254 case SCSI_ACA_ACTIVE:
1255 s1 = &ccb->scsi_sense;
1256 s2 = &xs->sense;
1257 *s2 = *s1;
1258 xs->error = XS_SENSE;
1259 break;
1260
1261 case SCSI_BUSY:
1262 case SCSI_QUEUE_FULL:
1263 case SCSI_RESV_CONFLICT:
1264 sc->sc_freeze_dev[scsiq->target_id] = 1;
1265 xs->error = XS_BUSY;
1266 break;
1267
1268 default: /* scsiq->scsi_status value */
1269 printf("%s: bad scsi_status: 0x%02x.\n"
1270 ,sc->sc_dev.dv_xname
1271 ,scsiq->scsi_status);
1272 xs->error = XS_DRIVER_STUFFUP;
1273 break;
1274 }
1275 break;
1276
1277 case QHSTA_M_SEL_TIMEOUT:
1278 xs->error = XS_SELTIMEOUT;
1279 break;
1280
1281 case QHSTA_M_DIRECTION_ERR:
1282 case QHSTA_M_SXFR_OFF_UFLW:
1283 case QHSTA_M_SXFR_OFF_OFLW:
1284 case QHSTA_M_SXFR_XFR_OFLW:
1285 case QHSTA_M_QUEUE_ABORTED:
1286 case QHSTA_M_INVALID_DEVICE:
1287 case QHSTA_M_SGBACKUP_ERROR:
1288 case QHSTA_M_SXFR_DESELECTED:
1289 case QHSTA_M_SXFR_XFR_PH_ERR:
1290 case QHSTA_M_BUS_DEVICE_RESET:
1291 case QHSTA_M_NO_AUTO_REQ_SENSE:
1292 case QHSTA_M_BAD_CMPL_STATUS_IN:
1293 case QHSTA_M_SXFR_UNKNOWN_ERROR:
1294 case QHSTA_M_AUTO_REQ_SENSE_FAIL:
1295 case QHSTA_M_UNEXPECTED_BUS_FREE:
1296 printf("%s: host adapter error 0x%02x."
1297 " See adw(4).\n"
1298 ,sc->sc_dev.dv_xname, scsiq->host_status);
1299 xs->error = XS_DRIVER_STUFFUP;
1300 break;
1301
1302 case QHSTA_M_RDMA_PERR:
1303 case QHSTA_M_SXFR_WD_TMO:
1304 case QHSTA_M_WTM_TIMEOUT:
1305 case QHSTA_M_FROZEN_TIDQ:
1306 case QHSTA_M_SXFR_SDMA_ERR:
1307 case QHSTA_M_SXFR_SXFR_PERR:
1308 case QHSTA_M_SCSI_BUS_RESET:
1309 case QHSTA_M_DIRECTION_ERR_HUNG:
1310 case QHSTA_M_SCSI_BUS_RESET_UNSOL:
1311 /*
1312 * XXX - are all these cases really asking
1313 * for a card reset? _BUS_RESET and
1314 * _BUS_RESET_UNSOL added just to make
1315 * sure the pending queue is cleared out
1316 * in case card has lost track of them.
1317 */
1318 printf("%s: host adapter error 0x%02x,"
1319 " resetting bus. See adw(4).\n"
1320 ,sc->sc_dev.dv_xname, scsiq->host_status);
1321 adw_reset_bus(sc);
1322 xs->error = XS_RESET;
1323 break;
1324
1325 default: /* scsiq->host_status value */
1326 /*
1327 * XXX - is a panic really appropriate here? If
1328 * not, would it be better to make the
1329 * XS_DRIVER_STUFFUP case above the
1330 * default behaviour? Or XS_RESET?
1331 */
1332 panic("%s: bad host_status: 0x%02x"
1333 ,sc->sc_dev.dv_xname, scsiq->host_status);
1334 break;
1335 }
1336 break;
1337
1338 case QD_ABORTED_BY_HOST:
1339 xs->error = XS_DRIVER_STUFFUP;
1340 break;
1341
1342 default: /* scsiq->done_status value */
1343 /*
1344 * XXX - would QD_NO_STATUS really mean the I/O is not
1345 * done? and would that mean it should somehow be
1346 * put back as a pending I/O?
1347 */
1348 printf("%s: bad done_status: 0x%02x"
1349 " (host_status: 0x%02x, scsi_status: 0x%02x)\n"
1350 ,sc->sc_dev.dv_xname
1351 ,scsiq->done_status
1352 ,scsiq->host_status
1353 ,scsiq->scsi_status);
1354 xs->error = XS_DRIVER_STUFFUP;
1355 break;
1356 }
1357
1358 adw_free_ccb(sc, ccb);
1359
1360 xs->flags |= ITSDONE;
1361 scsi_done(xs);
1362 }
1363
1364
1365 /*
1366 * adw_async_callback() - Adw Library asynchronous event callback function.
1367 */
1368 void
adw_async_callback(sc,code)1369 adw_async_callback(sc, code)
1370 ADW_SOFTC *sc;
1371 u_int8_t code;
1372 {
1373 switch (code) {
1374 case ADW_ASYNC_SCSI_BUS_RESET_DET:
1375 /* The firmware detected a SCSI Bus reset. */
1376 printf("%s: SCSI Bus reset detected\n", sc->sc_dev.dv_xname);
1377 break;
1378
1379 case ADW_ASYNC_RDMA_FAILURE:
1380 /*
1381 * Handle RDMA failure by resetting the SCSI Bus and
1382 * possibly the chip if it is unresponsive.
1383 */
1384 printf("%s: RDMA failure. Resetting the SCSI Bus and"
1385 " the adapter\n", sc->sc_dev.dv_xname);
1386 adw_reset_bus(sc);
1387 break;
1388
1389 case ADW_HOST_SCSI_BUS_RESET:
1390 /* Host generated SCSI bus reset occurred. */
1391 printf("%s: Host generated SCSI bus reset occurred\n",
1392 sc->sc_dev.dv_xname);
1393 break;
1394
1395
1396 case ADW_ASYNC_CARRIER_READY_FAILURE:
1397 /*
1398 * Carrier Ready failure.
1399 *
1400 * A warning only - RISC too busy to realize it's been
1401 * tickled. Occurs in normal operation under heavy
1402 * load, so a message is printed only when ADW_DEBUG'ing
1403 */
1404 #ifdef ADW_DEBUG
1405 printf("%s: Carrier Ready failure!\n", sc->sc_dev.dv_xname);
1406 #endif
1407 break;
1408
1409 default:
1410 printf("%s: Unknown Async callback code (ignored): 0x%02x\n",
1411 sc->sc_dev.dv_xname, code);
1412 break;
1413 }
1414 }
1415