1 /** $MirOS: src/sys/arch/sparc/include/cpu.h,v 1.3 2006/08/21 12:26:42 tg Exp $ */ 2 /* $OpenBSD: cpu.h,v 1.20 2003/06/02 23:27:54 millert Exp $ */ 3 /* $NetBSD: cpu.h,v 1.24 1997/03/15 22:25:15 pk Exp $ */ 4 5 /* 6 * Copyright (c) 1992, 1993 7 * The Regents of the University of California. All rights reserved. 8 * 9 * This software was developed by the Computer Systems Engineering group 10 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 11 * contributed to Berkeley. 12 * 13 * All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by the University of 16 * California, Lawrence Berkeley Laboratory. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions 20 * are met: 21 * 1. Redistributions of source code must retain the above copyright 22 * notice, this list of conditions and the following disclaimer. 23 * 2. Redistributions in binary form must reproduce the above copyright 24 * notice, this list of conditions and the following disclaimer in the 25 * documentation and/or other materials provided with the distribution. 26 * 3. Neither the name of the University nor the names of its contributors 27 * may be used to endorse or promote products derived from this software 28 * without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 33 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 38 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 39 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 40 * SUCH DAMAGE. 41 * 42 * @(#)cpu.h 8.4 (Berkeley) 1/5/94 43 */ 44 45 #ifndef _SPARC_CPU_H_ 46 #define _SPARC_CPU_H_ 47 48 /* 49 * CTL_MACHDEP definitions. 50 */ 51 #define CPU_LED_BLINK 1 /* int: twiddle the power LED */ 52 /* 2 formerly int: vsyncblank */ 53 #define CPU_CPUTYPE 3 /* int: cpu type */ 54 #define CPU_V8MUL 4 55 #define CPU_CONSDEV 5 /* dev_t: console terminal device */ 56 #define CPU_MAXID 6 /* 5 valid machdep IDs */ 57 58 #define CTL_MACHDEP_NAMES { \ 59 { 0, 0 }, \ 60 { "led_blink", CTLTYPE_INT }, \ 61 { 0, 0 }, \ 62 { "cputype", CTLTYPE_INT }, \ 63 { "v8mul", CTLTYPE_INT }, \ 64 { "console_device", CTLTYPE_STRUCT }, \ 65 } 66 67 #ifdef _KERNEL 68 /* 69 * Exported definitions unique to SPARC cpu support. 70 */ 71 72 #include <machine/psl.h> 73 #include <sparc/sparc/intreg.h> 74 75 /* 76 * definitions of cpu-dependent requirements 77 * referenced in generic code 78 */ 79 #define cpu_swapin(p) /* nothing */ 80 #define cpu_swapout(p) /* nothing */ 81 #define cpu_wait(p) /* nothing */ 82 83 /* 84 * Arguments to hardclock, softclock and gatherstats encapsulate the 85 * previous machine state in an opaque clockframe. The ipl is here 86 * as well for strayintr (see locore.s:interrupt and intr.c:strayintr). 87 * Note that CLKF_INTR is valid only if CLKF_USERMODE is false. 88 */ 89 struct clockframe { 90 u_int psr; /* psr before interrupt, excluding PSR_ET */ 91 u_int pc; /* pc at interrupt */ 92 u_int npc; /* npc at interrupt */ 93 u_int ipl; /* actual interrupt priority level */ 94 u_int fp; /* %fp at interrupt */ 95 }; 96 typedef struct clockframe clockframe; 97 98 extern int eintstack[]; 99 100 #define CLKF_USERMODE(framep) (((framep)->psr & PSR_PS) == 0) 101 #define CLKF_PC(framep) ((framep)->pc) 102 #define CLKF_INTR(framep) ((framep)->fp < (u_int)eintstack) 103 104 /* 105 * Software interrupt request `register'. 106 */ 107 union sir { 108 int sir_any; 109 char sir_which[4]; 110 }; 111 extern union sir sir; 112 113 #define SIR_NET 0 114 #define SIR_CLOCK 1 115 116 #if defined(SUN4M) 117 extern void raise(int, int); 118 #if !(defined(SUN4) || defined(SUN4C)) 119 #define setsoftint() raise(0,1) 120 #else /* both defined */ 121 #define setsoftint() (cputyp == CPU_SUN4M ? raise(0,1) : ienab_bis(IE_L1)) 122 #endif /* !4,!4c */ 123 #else /* 4m not defined */ 124 #define setsoftint() ienab_bis(IE_L1) 125 #endif /* SUN4M */ 126 127 #define setsoftnet() (sir.sir_which[SIR_NET] = 1, setsoftint()) 128 #define setsoftclock() (sir.sir_which[SIR_CLOCK] = 1, setsoftint()) 129 130 /* 131 * Preempt the current process if in interrupt from user mode, 132 * or after the current trap/syscall if in system mode. 133 */ 134 extern int want_resched; /* resched() was called */ 135 #define need_resched() (want_resched = 1, want_ast = 1) 136 extern int want_ast; 137 138 /* 139 * Give a profiling tick to the current process when the user profiling 140 * buffer pages are invalid. On the sparc, request an ast to send us 141 * through trap(), marking the proc as needing a profiling tick. 142 */ 143 #define need_proftick(p) ((p)->p_flag |= P_OWEUPC, want_ast = 1) 144 145 /* 146 * Notify the current process (p) that it has a signal pending, 147 * process as soon as possible. 148 */ 149 #define signotify(p) (want_ast = 1) 150 151 #define __do_calibrate_cyclecounter(rvptr) /* nothing */ 152 153 extern int foundfpu; /* true => we have an FPU */ 154 155 /* 156 * Interrupt handler chains. Interrupt handlers should return 0 for 157 * ``not me'' or 1 (``I took care of it''). intr_establish() inserts a 158 * handler into the list. The handler is called with its (single) 159 * argument, or with a pointer to a clockframe if ih_arg is NULL. 160 * ih_ipl specifies the interrupt level that should be blocked when 161 * executing this handler. 162 */ 163 struct intrhand { 164 int (*ih_fun)(void *); 165 void *ih_arg; 166 int ih_ipl; 167 struct intrhand *ih_next; 168 }; 169 extern struct intrhand *intrhand[15]; 170 void intr_establish(int level, struct intrhand *, int); 171 void vmeintr_establish(int vec, int level, struct intrhand *, int); 172 173 /* 174 * intr_fasttrap() is a lot like intr_establish, but is used for ``fast'' 175 * interrupt vectors (vectors that are not shared and are handled in the 176 * trap window). Such functions must be written in assembly. 177 */ 178 void intr_fasttrap(int level, void (*vec)(void)); 179 180 /* auxreg.c */ 181 void led_blink(void *); 182 /* scf.c */ 183 void scfblink(void *); 184 /* disksubr.c */ 185 struct dkbad; 186 int isbad(struct dkbad *bt, int, int, int); 187 /* machdep.c */ 188 int ldcontrolb(caddr_t); 189 void dumpconf(void); 190 caddr_t reserve_dumppages(caddr_t); 191 /* clock.c */ 192 struct timeval; 193 void lo_microtime(struct timeval *); 194 int statintr(void *); 195 int clockintr(void *);/* level 10 (clock) interrupt code */ 196 int statintr(void *); /* level 14 (statclock) interrupt code */ 197 /* locore.s */ 198 struct fpstate; 199 void savefpstate(struct fpstate *); 200 void loadfpstate(struct fpstate *); 201 int probeget(caddr_t, int); 202 void write_all_windows(void); 203 void write_user_windows(void); 204 void proc_trampoline(void); 205 struct pcb; 206 void snapshot(struct pcb *); 207 struct frame *getfp(void); 208 int xldcontrolb(caddr_t, struct pcb *); 209 void copywords(const void *, void *, size_t); 210 void qcopy(const void *, void *, size_t); 211 void qzero(void *, size_t); 212 /* locore2.c */ 213 void remrunqueue(struct proc *); 214 /* trap.c */ 215 void kill_user_windows(struct proc *); 216 int rwindow_save(struct proc *); 217 /* amd7930intr.s */ 218 void amd7930_trap(void); 219 #ifdef KGDB 220 /* zs_kgdb.c */ 221 void zs_kgdb_init(void); 222 #endif 223 /* fb.c */ 224 void fb_unblank(void); 225 /* cache.c */ 226 void cache_flush(caddr_t, u_int); 227 /* kgdb_stub.c */ 228 #ifdef KGDB 229 void kgdb_attach(int (*)(void *), void (*)(void *, int), void *); 230 void kgdb_connect(int); 231 void kgdb_panic(void); 232 #endif 233 /* iommu.c */ 234 void iommu_enter(u_int, u_int); 235 void iommu_remove(u_int, u_int); 236 /* emul.c */ 237 struct trapframe; 238 int fixalign(struct proc *, struct trapframe *); 239 int emulinstr(int, struct trapframe *); 240 241 /* 242 * 243 * The SPARC has a Trap Base Register (TBR) which holds the upper 20 bits 244 * of the trap vector table. The next eight bits are supplied by the 245 * hardware when the trap occurs, and the bottom four bits are always 246 * zero (so that we can shove up to 16 bytes of executable code---exactly 247 * four instructions---into each trap vector). 248 * 249 * The hardware allocates half the trap vectors to hardware and half to 250 * software. 251 * 252 * Traps have priorities assigned (lower number => higher priority). 253 */ 254 255 struct trapvec { 256 int tv_instr[4]; /* the four instructions */ 257 }; 258 extern struct trapvec *trapbase; /* the 256 vectors */ 259 260 extern void wzero(void *, u_int); 261 extern void wcopy(const void *, void *, u_int); 262 263 #endif /* _KERNEL */ 264 #endif /* _SPARC_CPU_H_ */ 265