1 /* $OpenBSD: dmareg.h,v 1.6 2003/06/05 12:27:02 deraadt Exp $ */ 2 /* $NetBSD: dmareg.h,v 1.10 1996/11/28 09:37:34 pk Exp $ */ 3 4 /* 5 * Copyright (c) 1994 Peter Galbavy. All rights reserved. 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #define DMACSRBITS "\020\01INT\02ERR\03DR1\04DR2\05IEN\011WRITE\016ENCNT\017TC\032DMAON" 28 29 struct dma_regs { 30 volatile u_long csr; /* DMA CSR */ 31 #define D_INT_PEND 0x00000001 /* interrupt pending */ 32 #define D_ERR_PEND 0x00000002 /* error pending */ 33 #define D_DRAINING 0x0000000c /* fifo draining */ 34 #define D_INT_EN 0x00000010 /* interrupt enable */ 35 #define D_INVALIDATE 0x00000020 /* invalidate fifo */ 36 #define D_SLAVE_ERR 0x00000040 /* slave access size error */ 37 #define D_DRAIN 0x00000040 /* rev0,1,esc: drain fifo */ 38 #define D_RESET 0x00000080 /* reset scsi */ 39 #define D_WRITE 0x00000100 /* 1 = dev -> mem */ 40 #define D_EN_DMA 0x00000200 /* enable DMA requests */ 41 #define D_R_PEND 0x00000400 /* rev0,1: request pending */ 42 #define D_ESC_BURST 0x00000800 /* DMA ESC: 16 byte bursts */ 43 #define D_EN_CNT 0x00002000 /* enable byte counter */ 44 #define D_TC 0x00004000 /* terminal count */ 45 #define D_DSBL_CSR_DRN 0x00010000 /* disable fifo drain on csr */ 46 #define D_DSBL_SCSI_DRN 0x00020000 /* disable fifo drain on reg */ 47 #define D_BURST_SIZE 0x000c0000 /* sbus read/write burst size */ 48 #define D_BURST_0 0x00080000 /* no bursts (SCSI-only) */ 49 #define D_BURST_16 0x00000000 /* 16-byte bursts */ 50 #define D_BURST_32 0x00040000 /* 32-byte bursts */ 51 #define D_AUTODRAIN 0x00040000 /* DMA ESC: Auto-drain */ 52 #define D_DIAG 0x00100000 /* disable fifo drain on addr */ 53 #define D_TWO_CYCLE 0x00200000 /* 2 clocks per transfer */ 54 #define D_FASTER 0x00400000 /* 3 clocks per transfer */ 55 #define DE_AUI_TP 0x00400000 /* 1 for TP, 0 for AUI */ 56 #define D_TCI_DIS 0x00800000 /* disable intr on D_TC */ 57 #define D_EN_NEXT 0x01000000 /* enable auto next address */ 58 #define D_DMA_ON 0x02000000 /* enable dma from scsi */ 59 #define D_A_LOADED 0x04000000 /* address loaded */ 60 #define D_NA_LOADED 0x08000000 /* next address loaded */ 61 #define D_DEV_ID 0xf0000000 /* device ID */ 62 #define DMAREV_0 0x00000000 /* Sunray DMA */ 63 #define DMAREV_ESC 0x40000000 /* DMA ESC array */ 64 #define DMAREV_1 0x80000000 /* 'DMA' */ 65 #define DMAREV_PLUS 0x90000000 /* 'DMA+' */ 66 #define DMAREV_2 0xa0000000 /* 'DMA2' */ 67 #define DMAREV_HME 0xb0000000 /* 'HME' gate array */ 68 69 volatile caddr_t addr; 70 #define DMA_D_ADDR 0x01 /* DMA ADDR (in u_longs) */ 71 72 volatile u_long bcnt; /* DMA COUNT (in u_longs) */ 73 #define D_BCNT_MASK 0x00ffffff /* only 24 bits */ 74 75 volatile u_long test; /* DMA TEST (in u_longs) */ 76 #define en_testcsr addr /* enet registers overlap */ 77 #define en_cachev bcnt 78 #define en_bar test 79 80 }; 81 82 /* 83 * PROM-reported DMA burst sizes for the SBus 84 */ 85 #define SBUS_BURST_1 0x1 86 #define SBUS_BURST_2 0x2 87 #define SBUS_BURST_4 0x4 88 #define SBUS_BURST_8 0x8 89 #define SBUS_BURST_16 0x10 90 #define SBUS_BURST_32 0x20 91 #define SBUS_BURST_64 0x40 92