1 /** $MirOS: src/sys/arch/i386/pci/pcibiosvar.h,v 1.3 2005/07/21 21:52:16 tg Exp $ */ 2 /* $OpenBSD: pcibiosvar.h,v 1.14 2004/09/26 20:17:42 mickey Exp $ */ 3 /* $NetBSD: pcibios.h,v 1.2 2000/04/28 17:15:16 uch Exp $ */ 4 5 /* 6 * Copyright (c) 1999, by UCHIYAMA Yasushi 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. The name of the developer may NOT be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * Data structure definitions for the PCI BIOS interface. 32 */ 33 34 #define PCIBIOS_ADDR_FIXUP 0x0001 35 #define PCIBIOS_BUS_FIXUP 0x0002 36 #define PCIBIOS_INTR_FIXUP 0x0004 37 #define PCIBIOS_INTR_GUESS 0x0008 38 #define PCIBIOS_VERBOSE 0x0010 39 #define PCIBIOS_INTRDEBUG 0x0020 40 #define PCIBIOS_FIXUP_FORCE 0x0040 41 42 /* 43 * PCI BIOS return codes. 44 */ 45 #define PCIBIOS_SUCCESS 0x00 46 #define PCIBIOS_SERVICE_NOT_PRESENT 0x80 47 #define PCIBIOS_FUNCTION_NOT_SUPPORTED 0x81 48 #define PCIBIOS_BAD_VENDOR_ID 0x83 49 #define PCIBIOS_DEVICE_NOT_FOUND 0x86 50 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 51 #define PCIBIOS_SET_FAILED 0x88 52 #define PCIBIOS_BUFFER_TOO_SMALL 0x89 53 54 struct pcibios_softc { 55 struct device sc_dev; 56 57 int max_bus; 58 59 /* address fixup guts */ 60 struct extent *extent_mem; 61 struct extent *extent_port; 62 bus_addr_t mem_alloc_start; 63 bus_addr_t port_alloc_start; 64 int nbogus; 65 }; 66 67 /* 68 * PCI IRQ Routing Table definitions. 69 */ 70 71 /* 72 * Slot entry (per PCI 2.1) 73 */ 74 struct pcibios_linkmap { 75 u_int8_t link; 76 u_int16_t bitmap; 77 } __packed; 78 79 struct pcibios_intr_routing { 80 u_int8_t bus; 81 u_int8_t device; 82 struct pcibios_linkmap linkmap[4]; /* INT[A:D]# */ 83 u_int8_t slot; 84 u_int8_t reserved; 85 } __packed; 86 87 /* 88 * $PIR header. Reference: 89 * 90 * http://www.microsoft.com/HWDEV/busbios/PCIIRQ.htm 91 */ 92 struct pcibios_pir_header { 93 u_int32_t signature; /* $PIR */ 94 u_int16_t version; 95 u_int16_t tablesize; 96 u_int8_t router_bus; 97 u_int8_t router_devfunc; 98 u_int16_t exclusive_irq; 99 u_int32_t compat_router; /* PCI vendor/product */ 100 u_int32_t miniport; 101 u_int8_t reserved[11]; 102 u_int8_t checksum; 103 } __packed; 104 105 #define PIR_DEVFUNC_DEVICE(devfunc) (((devfunc) >> 3) & 0x1f) 106 #define PIR_DEVFUNC_FUNCTION(devfunc) ((devfunc) & 7) 107 #define PIR_DEVFUNC_COMPOSE(dev,func) ((((dev) &0x1f) << 3) | ((func) & 7)) 108 109 void pcibios_init(void); 110 111 extern struct pcibios_pir_header pcibios_pir_header; 112 extern struct pcibios_intr_routing *pcibios_pir_table; 113 extern int pcibios_pir_table_nentries; 114 115 int pcibios_flags; 116 117 typedef void *pciintr_icu_handle_t; 118 119 struct pciintr_icu { 120 int (*pi_getclink)(pciintr_icu_handle_t, int, int *); 121 int (*pi_get_intr)(pciintr_icu_handle_t, int, int *); 122 int (*pi_set_intr)(pciintr_icu_handle_t, int, int); 123 int (*pi_get_trigger)(pciintr_icu_handle_t, int, int *); 124 int (*pi_set_trigger)(pciintr_icu_handle_t, int, int); 125 }; 126 127 typedef const struct pciintr_icu *pciintr_icu_tag_t; 128 129 #define pciintr_icu_getclink(t, h, link, pirqp) \ 130 (*(t)->pi_getclink)((h), (link), (pirqp)) 131 #define pciintr_icu_get_intr(t, h, pirq, irqp) \ 132 (*(t)->pi_get_intr)((h), (pirq), (irqp)) 133 #define pciintr_icu_set_intr(t, h, pirq, irq) \ 134 (*(t)->pi_set_intr)((h), (pirq), (irq)) 135 #define pciintr_icu_get_trigger(t, h, irq, triggerp) \ 136 (*(t)->pi_get_trigger)((h), (irq), (triggerp)) 137 #define pciintr_icu_set_trigger(t, h, irq, trigger) \ 138 (*(t)->pi_set_trigger)((h), (irq), (trigger)) 139 140 #define PCIBIOS_PRINTV(arg) \ 141 do { \ 142 if (pcibios_flags & PCIBIOS_VERBOSE) \ 143 printf arg; \ 144 } while (0) 145 146 #define PCIADDR_SEARCH_IO 0 147 #define PCIADDR_SEARCH_MEM 1 148 struct extent *pciaddr_search(int, bus_addr_t *, bus_size_t); 149 150 int pci_intr_fixup(struct pcibios_softc *, pci_chipset_tag_t, bus_space_tag_t); 151 int pci_bus_fixup(pci_chipset_tag_t, int); 152 void pci_addr_fixup(struct pcibios_softc *, pci_chipset_tag_t, int); 153 void pci_device_foreach(struct pcibios_softc *, pci_chipset_tag_t, int, 154 void (*)(struct pcibios_softc *, pci_chipset_tag_t, pcitag_t)); 155 int pci_intr_header_fixup(pci_chipset_tag_t, pcitag_t, pci_intr_handle_t *); 156 int pci_intr_route_link(pci_chipset_tag_t, pci_intr_handle_t *); 157 int pci_intr_post_fixup(void); 158 159 /* 160 * Init functions for our known PCI ICUs. 161 */ 162 int piix_init(pci_chipset_tag_t, bus_space_tag_t, pcitag_t, 163 pciintr_icu_tag_t *, pciintr_icu_handle_t *); 164 int opti82c558_init(pci_chipset_tag_t, bus_space_tag_t, pcitag_t, 165 pciintr_icu_tag_t *, pciintr_icu_handle_t *); 166 int opti82c700_init(pci_chipset_tag_t, bus_space_tag_t, pcitag_t, 167 pciintr_icu_tag_t *, pciintr_icu_handle_t *); 168 int via82c586_init(pci_chipset_tag_t, bus_space_tag_t, pcitag_t, 169 pciintr_icu_tag_t *, pciintr_icu_handle_t *); 170 int via8231_init(pci_chipset_tag_t, bus_space_tag_t, pcitag_t, 171 pciintr_icu_tag_t *, pciintr_icu_handle_t *); 172 int sis85c503_init(pci_chipset_tag_t, bus_space_tag_t, pcitag_t, 173 pciintr_icu_tag_t *, pciintr_icu_handle_t *); 174 int amd756_init(pci_chipset_tag_t, bus_space_tag_t, pcitag_t, 175 pciintr_icu_tag_t *, pciintr_icu_handle_t *); 176 int ali1543_init(pci_chipset_tag_t, bus_space_tag_t, pcitag_t, 177 pciintr_icu_tag_t *, pciintr_icu_handle_t *); 178