1 /* ppc-opc.c -- PowerPC opcode list
2 Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004,
3 2005 Free Software Foundation, Inc.
4 Written by Ian Lance Taylor, Cygnus Support
5
6 This file is part of GDB, GAS, and the GNU binutils.
7
8 GDB, GAS, and the GNU binutils are free software; you can redistribute
9 them and/or modify them under the terms of the GNU General Public
10 License as published by the Free Software Foundation; either version
11 2, or (at your option) any later version.
12
13 GDB, GAS, and the GNU binutils are distributed in the hope that they
14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
16 the GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
22
23 #include <stdio.h>
24 #include "sysdep.h"
25 #include "opcode/ppc.h"
26 #include "opintl.h"
27
28 /* This file holds the PowerPC opcode table. The opcode table
29 includes almost all of the extended instruction mnemonics. This
30 permits the disassembler to use them, and simplifies the assembler
31 logic, at the cost of increasing the table size. The table is
32 strictly constant data, so the compiler should be able to put it in
33 the .text section.
34
35 This file also holds the operand table. All knowledge about
36 inserting operands into instructions and vice-versa is kept in this
37 file. */
38
39 /* Local insertion and extraction functions. */
40
41 static unsigned long insert_bat (unsigned long, long, int, const char **);
42 static long extract_bat (unsigned long, int, int *);
43 static unsigned long insert_bba (unsigned long, long, int, const char **);
44 static long extract_bba (unsigned long, int, int *);
45 static unsigned long insert_bd (unsigned long, long, int, const char **);
46 static long extract_bd (unsigned long, int, int *);
47 static unsigned long insert_bdm (unsigned long, long, int, const char **);
48 static long extract_bdm (unsigned long, int, int *);
49 static unsigned long insert_bdp (unsigned long, long, int, const char **);
50 static long extract_bdp (unsigned long, int, int *);
51 static unsigned long insert_bo (unsigned long, long, int, const char **);
52 static long extract_bo (unsigned long, int, int *);
53 static unsigned long insert_boe (unsigned long, long, int, const char **);
54 static long extract_boe (unsigned long, int, int *);
55 static unsigned long insert_dq (unsigned long, long, int, const char **);
56 static long extract_dq (unsigned long, int, int *);
57 static unsigned long insert_ds (unsigned long, long, int, const char **);
58 static long extract_ds (unsigned long, int, int *);
59 static unsigned long insert_de (unsigned long, long, int, const char **);
60 static long extract_de (unsigned long, int, int *);
61 static unsigned long insert_des (unsigned long, long, int, const char **);
62 static long extract_des (unsigned long, int, int *);
63 static unsigned long insert_fxm (unsigned long, long, int, const char **);
64 static long extract_fxm (unsigned long, int, int *);
65 static unsigned long insert_li (unsigned long, long, int, const char **);
66 static long extract_li (unsigned long, int, int *);
67 static unsigned long insert_mbe (unsigned long, long, int, const char **);
68 static long extract_mbe (unsigned long, int, int *);
69 static unsigned long insert_mb6 (unsigned long, long, int, const char **);
70 static long extract_mb6 (unsigned long, int, int *);
71 static unsigned long insert_nb (unsigned long, long, int, const char **);
72 static long extract_nb (unsigned long, int, int *);
73 static unsigned long insert_nsi (unsigned long, long, int, const char **);
74 static long extract_nsi (unsigned long, int, int *);
75 static unsigned long insert_ral (unsigned long, long, int, const char **);
76 static unsigned long insert_ram (unsigned long, long, int, const char **);
77 static unsigned long insert_raq (unsigned long, long, int, const char **);
78 static unsigned long insert_ras (unsigned long, long, int, const char **);
79 static unsigned long insert_rbs (unsigned long, long, int, const char **);
80 static long extract_rbs (unsigned long, int, int *);
81 static unsigned long insert_rsq (unsigned long, long, int, const char **);
82 static unsigned long insert_rtq (unsigned long, long, int, const char **);
83 static unsigned long insert_sh6 (unsigned long, long, int, const char **);
84 static long extract_sh6 (unsigned long, int, int *);
85 static unsigned long insert_spr (unsigned long, long, int, const char **);
86 static long extract_spr (unsigned long, int, int *);
87 static unsigned long insert_sprg (unsigned long, long, int, const char **);
88 static long extract_sprg (unsigned long, int, int *);
89 static unsigned long insert_tbr (unsigned long, long, int, const char **);
90 static long extract_tbr (unsigned long, int, int *);
91 static unsigned long insert_ev2 (unsigned long, long, int, const char **);
92 static long extract_ev2 (unsigned long, int, int *);
93 static unsigned long insert_ev4 (unsigned long, long, int, const char **);
94 static long extract_ev4 (unsigned long, int, int *);
95 static unsigned long insert_ev8 (unsigned long, long, int, const char **);
96 static long extract_ev8 (unsigned long, int, int *);
97
98 /* The operands table.
99
100 The fields are bits, shift, insert, extract, flags.
101
102 We used to put parens around the various additions, like the one
103 for BA just below. However, that caused trouble with feeble
104 compilers with a limit on depth of a parenthesized expression, like
105 (reportedly) the compiler in Microsoft Developer Studio 5. So we
106 omit the parens, since the macros are never used in a context where
107 the addition will be ambiguous. */
108
109 const struct powerpc_operand powerpc_operands[] =
110 {
111 /* The zero index is used to indicate the end of the list of
112 operands. */
113 #define UNUSED 0
114 { 0, 0, NULL, NULL, 0 },
115
116 /* The BA field in an XL form instruction. */
117 #define BA UNUSED + 1
118 #define BA_MASK (0x1f << 16)
119 { 5, 16, NULL, NULL, PPC_OPERAND_CR },
120
121 /* The BA field in an XL form instruction when it must be the same
122 as the BT field in the same instruction. */
123 #define BAT BA + 1
124 { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
125
126 /* The BB field in an XL form instruction. */
127 #define BB BAT + 1
128 #define BB_MASK (0x1f << 11)
129 { 5, 11, NULL, NULL, PPC_OPERAND_CR },
130
131 /* The BB field in an XL form instruction when it must be the same
132 as the BA field in the same instruction. */
133 #define BBA BB + 1
134 { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
135
136 /* The BD field in a B form instruction. The lower two bits are
137 forced to zero. */
138 #define BD BBA + 1
139 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
140
141 /* The BD field in a B form instruction when absolute addressing is
142 used. */
143 #define BDA BD + 1
144 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
145
146 /* The BD field in a B form instruction when the - modifier is used.
147 This sets the y bit of the BO field appropriately. */
148 #define BDM BDA + 1
149 { 16, 0, insert_bdm, extract_bdm,
150 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
151
152 /* The BD field in a B form instruction when the - modifier is used
153 and absolute address is used. */
154 #define BDMA BDM + 1
155 { 16, 0, insert_bdm, extract_bdm,
156 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
157
158 /* The BD field in a B form instruction when the + modifier is used.
159 This sets the y bit of the BO field appropriately. */
160 #define BDP BDMA + 1
161 { 16, 0, insert_bdp, extract_bdp,
162 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
163
164 /* The BD field in a B form instruction when the + modifier is used
165 and absolute addressing is used. */
166 #define BDPA BDP + 1
167 { 16, 0, insert_bdp, extract_bdp,
168 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
169
170 /* The BF field in an X or XL form instruction. */
171 #define BF BDPA + 1
172 { 3, 23, NULL, NULL, PPC_OPERAND_CR },
173
174 /* An optional BF field. This is used for comparison instructions,
175 in which an omitted BF field is taken as zero. */
176 #define OBF BF + 1
177 { 3, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
178
179 /* The BFA field in an X or XL form instruction. */
180 #define BFA OBF + 1
181 { 3, 18, NULL, NULL, PPC_OPERAND_CR },
182
183 /* The BI field in a B form or XL form instruction. */
184 #define BI BFA + 1
185 #define BI_MASK (0x1f << 16)
186 { 5, 16, NULL, NULL, PPC_OPERAND_CR },
187
188 /* The BO field in a B form instruction. Certain values are
189 illegal. */
190 #define BO BI + 1
191 #define BO_MASK (0x1f << 21)
192 { 5, 21, insert_bo, extract_bo, 0 },
193
194 /* The BO field in a B form instruction when the + or - modifier is
195 used. This is like the BO field, but it must be even. */
196 #define BOE BO + 1
197 { 5, 21, insert_boe, extract_boe, 0 },
198
199 #define BH BOE + 1
200 { 2, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
201
202 /* The BT field in an X or XL form instruction. */
203 #define BT BH + 1
204 { 5, 21, NULL, NULL, PPC_OPERAND_CR },
205
206 /* The condition register number portion of the BI field in a B form
207 or XL form instruction. This is used for the extended
208 conditional branch mnemonics, which set the lower two bits of the
209 BI field. This field is optional. */
210 #define CR BT + 1
211 { 3, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
212
213 /* The CRB field in an X form instruction. */
214 #define CRB CR + 1
215 { 5, 6, NULL, NULL, 0 },
216
217 /* The CRFD field in an X form instruction. */
218 #define CRFD CRB + 1
219 { 3, 23, NULL, NULL, PPC_OPERAND_CR },
220
221 /* The CRFS field in an X form instruction. */
222 #define CRFS CRFD + 1
223 { 3, 0, NULL, NULL, PPC_OPERAND_CR },
224
225 /* The CT field in an X form instruction. */
226 #define CT CRFS + 1
227 { 5, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
228
229 /* The D field in a D form instruction. This is a displacement off
230 a register, and implies that the next operand is a register in
231 parentheses. */
232 #define D CT + 1
233 { 16, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
234
235 /* The DE field in a DE form instruction. This is like D, but is 12
236 bits only. */
237 #define DE D + 1
238 { 14, 0, insert_de, extract_de, PPC_OPERAND_PARENS },
239
240 /* The DES field in a DES form instruction. This is like DS, but is 14
241 bits only (12 stored.) */
242 #define DES DE + 1
243 { 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
244
245 /* The DQ field in a DQ form instruction. This is like D, but the
246 lower four bits are forced to zero. */
247 #define DQ DES + 1
248 { 16, 0, insert_dq, extract_dq,
249 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
250
251 /* The DS field in a DS form instruction. This is like D, but the
252 lower two bits are forced to zero. */
253 #define DS DQ + 1
254 { 16, 0, insert_ds, extract_ds,
255 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
256
257 /* The E field in a wrteei instruction. */
258 #define E DS + 1
259 { 1, 15, NULL, NULL, 0 },
260
261 /* The FL1 field in a POWER SC form instruction. */
262 #define FL1 E + 1
263 { 4, 12, NULL, NULL, 0 },
264
265 /* The FL2 field in a POWER SC form instruction. */
266 #define FL2 FL1 + 1
267 { 3, 2, NULL, NULL, 0 },
268
269 /* The FLM field in an XFL form instruction. */
270 #define FLM FL2 + 1
271 { 8, 17, NULL, NULL, 0 },
272
273 /* The FRA field in an X or A form instruction. */
274 #define FRA FLM + 1
275 #define FRA_MASK (0x1f << 16)
276 { 5, 16, NULL, NULL, PPC_OPERAND_FPR },
277
278 /* The FRB field in an X or A form instruction. */
279 #define FRB FRA + 1
280 #define FRB_MASK (0x1f << 11)
281 { 5, 11, NULL, NULL, PPC_OPERAND_FPR },
282
283 /* The FRC field in an A form instruction. */
284 #define FRC FRB + 1
285 #define FRC_MASK (0x1f << 6)
286 { 5, 6, NULL, NULL, PPC_OPERAND_FPR },
287
288 /* The FRS field in an X form instruction or the FRT field in a D, X
289 or A form instruction. */
290 #define FRS FRC + 1
291 #define FRT FRS
292 { 5, 21, NULL, NULL, PPC_OPERAND_FPR },
293
294 /* The FXM field in an XFX instruction. */
295 #define FXM FRS + 1
296 #define FXM_MASK (0xff << 12)
297 { 8, 12, insert_fxm, extract_fxm, 0 },
298
299 /* Power4 version for mfcr. */
300 #define FXM4 FXM + 1
301 { 8, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },
302
303 /* The L field in a D or X form instruction. */
304 #define L FXM4 + 1
305 { 1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
306
307 /* The LEV field in a POWER SVC form instruction. */
308 #define SVC_LEV L + 1
309 { 7, 5, NULL, NULL, 0 },
310
311 /* The LEV field in an SC form instruction. */
312 #define LEV SVC_LEV + 1
313 { 7, 5, NULL, NULL, PPC_OPERAND_OPTIONAL },
314
315 /* The LI field in an I form instruction. The lower two bits are
316 forced to zero. */
317 #define LI LEV + 1
318 { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
319
320 /* The LI field in an I form instruction when used as an absolute
321 address. */
322 #define LIA LI + 1
323 { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
324
325 /* The LS field in an X (sync) form instruction. */
326 #define LS LIA + 1
327 { 2, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
328
329 /* The MB field in an M form instruction. */
330 #define MB LS + 1
331 #define MB_MASK (0x1f << 6)
332 { 5, 6, NULL, NULL, 0 },
333
334 /* The ME field in an M form instruction. */
335 #define ME MB + 1
336 #define ME_MASK (0x1f << 1)
337 { 5, 1, NULL, NULL, 0 },
338
339 /* The MB and ME fields in an M form instruction expressed a single
340 operand which is a bitmask indicating which bits to select. This
341 is a two operand form using PPC_OPERAND_NEXT. See the
342 description in opcode/ppc.h for what this means. */
343 #define MBE ME + 1
344 { 5, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
345 { 32, 0, insert_mbe, extract_mbe, 0 },
346
347 /* The MB or ME field in an MD or MDS form instruction. The high
348 bit is wrapped to the low end. */
349 #define MB6 MBE + 2
350 #define ME6 MB6
351 #define MB6_MASK (0x3f << 5)
352 { 6, 5, insert_mb6, extract_mb6, 0 },
353
354 /* The MO field in an mbar instruction. */
355 #define MO MB6 + 1
356 { 5, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
357
358 /* The NB field in an X form instruction. The value 32 is stored as
359 0. */
360 #define NB MO + 1
361 { 6, 11, insert_nb, extract_nb, 0 },
362
363 /* The NSI field in a D form instruction. This is the same as the
364 SI field, only negated. */
365 #define NSI NB + 1
366 { 16, 0, insert_nsi, extract_nsi,
367 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
368
369 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
370 #define RA NSI + 1
371 #define RA_MASK (0x1f << 16)
372 { 5, 16, NULL, NULL, PPC_OPERAND_GPR },
373
374 /* As above, but 0 in the RA field means zero, not r0. */
375 #define RA0 RA + 1
376 { 5, 16, NULL, NULL, PPC_OPERAND_GPR_0 },
377
378 /* The RA field in the DQ form lq instruction, which has special
379 value restrictions. */
380 #define RAQ RA0 + 1
381 { 5, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 },
382
383 /* The RA field in a D or X form instruction which is an updating
384 load, which means that the RA field may not be zero and may not
385 equal the RT field. */
386 #define RAL RAQ + 1
387 { 5, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 },
388
389 /* The RA field in an lmw instruction, which has special value
390 restrictions. */
391 #define RAM RAL + 1
392 { 5, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 },
393
394 /* The RA field in a D or X form instruction which is an updating
395 store or an updating floating point load, which means that the RA
396 field may not be zero. */
397 #define RAS RAM + 1
398 { 5, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 },
399
400 /* The RA field of the tlbwe instruction, which is optional. */
401 #define RAOPT RAS + 1
402 { 5, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
403
404 /* The RB field in an X, XO, M, or MDS form instruction. */
405 #define RB RAOPT + 1
406 #define RB_MASK (0x1f << 11)
407 { 5, 11, NULL, NULL, PPC_OPERAND_GPR },
408
409 /* The RB field in an X form instruction when it must be the same as
410 the RS field in the instruction. This is used for extended
411 mnemonics like mr. */
412 #define RBS RB + 1
413 { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
414
415 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
416 instruction or the RT field in a D, DS, X, XFX or XO form
417 instruction. */
418 #define RS RBS + 1
419 #define RT RS
420 #define RT_MASK (0x1f << 21)
421 { 5, 21, NULL, NULL, PPC_OPERAND_GPR },
422
423 /* The RS field of the DS form stq instruction, which has special
424 value restrictions. */
425 #define RSQ RS + 1
426 { 5, 21, insert_rsq, NULL, PPC_OPERAND_GPR_0 },
427
428 /* The RT field of the DQ form lq instruction, which has special
429 value restrictions. */
430 #define RTQ RSQ + 1
431 { 5, 21, insert_rtq, NULL, PPC_OPERAND_GPR_0 },
432
433 /* The RS field of the tlbwe instruction, which is optional. */
434 #define RSO RTQ + 1
435 #define RTO RSO
436 { 5, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
437
438 /* The SH field in an X or M form instruction. */
439 #define SH RSO + 1
440 #define SH_MASK (0x1f << 11)
441 { 5, 11, NULL, NULL, 0 },
442
443 /* The SH field in an MD form instruction. This is split. */
444 #define SH6 SH + 1
445 #define SH6_MASK ((0x1f << 11) | (1 << 1))
446 { 6, 1, insert_sh6, extract_sh6, 0 },
447
448 /* The SH field of the tlbwe instruction, which is optional. */
449 #define SHO SH6 + 1
450 { 5, 11,NULL, NULL, PPC_OPERAND_OPTIONAL },
451
452 /* The SI field in a D form instruction. */
453 #define SI SHO + 1
454 { 16, 0, NULL, NULL, PPC_OPERAND_SIGNED },
455
456 /* The SI field in a D form instruction when we accept a wide range
457 of positive values. */
458 #define SISIGNOPT SI + 1
459 { 16, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
460
461 /* The SPR field in an XFX form instruction. This is flipped--the
462 lower 5 bits are stored in the upper 5 and vice- versa. */
463 #define SPR SISIGNOPT + 1
464 #define PMR SPR
465 #define SPR_MASK (0x3ff << 11)
466 { 10, 11, insert_spr, extract_spr, 0 },
467
468 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
469 #define SPRBAT SPR + 1
470 #define SPRBAT_MASK (0x3 << 17)
471 { 2, 17, NULL, NULL, 0 },
472
473 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
474 #define SPRG SPRBAT + 1
475 { 5, 16, insert_sprg, extract_sprg, 0 },
476
477 /* The SR field in an X form instruction. */
478 #define SR SPRG + 1
479 { 4, 16, NULL, NULL, 0 },
480
481 /* The STRM field in an X AltiVec form instruction. */
482 #define STRM SR + 1
483 #define STRM_MASK (0x3 << 21)
484 { 2, 21, NULL, NULL, 0 },
485
486 /* The SV field in a POWER SC form instruction. */
487 #define SV STRM + 1
488 { 14, 2, NULL, NULL, 0 },
489
490 /* The TBR field in an XFX form instruction. This is like the SPR
491 field, but it is optional. */
492 #define TBR SV + 1
493 { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
494
495 /* The TO field in a D or X form instruction. */
496 #define TO TBR + 1
497 #define TO_MASK (0x1f << 21)
498 { 5, 21, NULL, NULL, 0 },
499
500 /* The U field in an X form instruction. */
501 #define U TO + 1
502 { 4, 12, NULL, NULL, 0 },
503
504 /* The UI field in a D form instruction. */
505 #define UI U + 1
506 { 16, 0, NULL, NULL, 0 },
507
508 /* The VA field in a VA, VX or VXR form instruction. */
509 #define VA UI + 1
510 #define VA_MASK (0x1f << 16)
511 { 5, 16, NULL, NULL, PPC_OPERAND_VR },
512
513 /* The VB field in a VA, VX or VXR form instruction. */
514 #define VB VA + 1
515 #define VB_MASK (0x1f << 11)
516 { 5, 11, NULL, NULL, PPC_OPERAND_VR },
517
518 /* The VC field in a VA form instruction. */
519 #define VC VB + 1
520 #define VC_MASK (0x1f << 6)
521 { 5, 6, NULL, NULL, PPC_OPERAND_VR },
522
523 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
524 #define VD VC + 1
525 #define VS VD
526 #define VD_MASK (0x1f << 21)
527 { 5, 21, NULL, NULL, PPC_OPERAND_VR },
528
529 /* The SIMM field in a VX form instruction. */
530 #define SIMM VD + 1
531 { 5, 16, NULL, NULL, PPC_OPERAND_SIGNED},
532
533 /* The UIMM field in a VX form instruction. */
534 #define UIMM SIMM + 1
535 { 5, 16, NULL, NULL, 0 },
536
537 /* The SHB field in a VA form instruction. */
538 #define SHB UIMM + 1
539 { 4, 6, NULL, NULL, 0 },
540
541 /* The other UIMM field in a EVX form instruction. */
542 #define EVUIMM SHB + 1
543 { 5, 11, NULL, NULL, 0 },
544
545 /* The other UIMM field in a half word EVX form instruction. */
546 #define EVUIMM_2 EVUIMM + 1
547 { 32, 11, insert_ev2, extract_ev2, PPC_OPERAND_PARENS },
548
549 /* The other UIMM field in a word EVX form instruction. */
550 #define EVUIMM_4 EVUIMM_2 + 1
551 { 32, 11, insert_ev4, extract_ev4, PPC_OPERAND_PARENS },
552
553 /* The other UIMM field in a double EVX form instruction. */
554 #define EVUIMM_8 EVUIMM_4 + 1
555 { 32, 11, insert_ev8, extract_ev8, PPC_OPERAND_PARENS },
556
557 /* The WS field. */
558 #define WS EVUIMM_8 + 1
559 #define WS_MASK (0x7 << 11)
560 { 3, 11, NULL, NULL, 0 },
561
562 /* The L field in an mtmsrd instruction */
563 #define MTMSRD_L WS + 1
564 { 1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
565
566 };
567
568 /* The functions used to insert and extract complicated operands. */
569
570 /* The BA field in an XL form instruction when it must be the same as
571 the BT field in the same instruction. This operand is marked FAKE.
572 The insertion function just copies the BT field into the BA field,
573 and the extraction function just checks that the fields are the
574 same. */
575
576 static unsigned long
insert_bat(unsigned long insn,long value ATTRIBUTE_UNUSED,int dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)577 insert_bat (unsigned long insn,
578 long value ATTRIBUTE_UNUSED,
579 int dialect ATTRIBUTE_UNUSED,
580 const char **errmsg ATTRIBUTE_UNUSED)
581 {
582 return insn | (((insn >> 21) & 0x1f) << 16);
583 }
584
585 static long
extract_bat(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid)586 extract_bat (unsigned long insn,
587 int dialect ATTRIBUTE_UNUSED,
588 int *invalid)
589 {
590 if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
591 *invalid = 1;
592 return 0;
593 }
594
595 /* The BB field in an XL form instruction when it must be the same as
596 the BA field in the same instruction. This operand is marked FAKE.
597 The insertion function just copies the BA field into the BB field,
598 and the extraction function just checks that the fields are the
599 same. */
600
601 static unsigned long
insert_bba(unsigned long insn,long value ATTRIBUTE_UNUSED,int dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)602 insert_bba (unsigned long insn,
603 long value ATTRIBUTE_UNUSED,
604 int dialect ATTRIBUTE_UNUSED,
605 const char **errmsg ATTRIBUTE_UNUSED)
606 {
607 return insn | (((insn >> 16) & 0x1f) << 11);
608 }
609
610 static long
extract_bba(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid)611 extract_bba (unsigned long insn,
612 int dialect ATTRIBUTE_UNUSED,
613 int *invalid)
614 {
615 if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
616 *invalid = 1;
617 return 0;
618 }
619
620 /* The BD field in a B form instruction. The lower two bits are
621 forced to zero. */
622
623 static unsigned long
insert_bd(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)624 insert_bd (unsigned long insn,
625 long value,
626 int dialect ATTRIBUTE_UNUSED,
627 const char **errmsg ATTRIBUTE_UNUSED)
628 {
629 return insn | (value & 0xfffc);
630 }
631
632 static long
extract_bd(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)633 extract_bd (unsigned long insn,
634 int dialect ATTRIBUTE_UNUSED,
635 int *invalid ATTRIBUTE_UNUSED)
636 {
637 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
638 }
639
640 /* The BD field in a B form instruction when the - modifier is used.
641 This modifier means that the branch is not expected to be taken.
642 For chips built to versions of the architecture prior to version 2
643 (ie. not Power4 compatible), we set the y bit of the BO field to 1
644 if the offset is negative. When extracting, we require that the y
645 bit be 1 and that the offset be positive, since if the y bit is 0
646 we just want to print the normal form of the instruction.
647 Power4 compatible targets use two bits, "a", and "t", instead of
648 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
649 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
650 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
651 for branch on CTR. We only handle the taken/not-taken hint here. */
652
653 static unsigned long
insert_bdm(unsigned long insn,long value,int dialect,const char ** errmsg ATTRIBUTE_UNUSED)654 insert_bdm (unsigned long insn,
655 long value,
656 int dialect,
657 const char **errmsg ATTRIBUTE_UNUSED)
658 {
659 if ((dialect & PPC_OPCODE_POWER4) == 0)
660 {
661 if ((value & 0x8000) != 0)
662 insn |= 1 << 21;
663 }
664 else
665 {
666 if ((insn & (0x14 << 21)) == (0x04 << 21))
667 insn |= 0x02 << 21;
668 else if ((insn & (0x14 << 21)) == (0x10 << 21))
669 insn |= 0x08 << 21;
670 }
671 return insn | (value & 0xfffc);
672 }
673
674 static long
extract_bdm(unsigned long insn,int dialect,int * invalid)675 extract_bdm (unsigned long insn,
676 int dialect,
677 int *invalid)
678 {
679 if ((dialect & PPC_OPCODE_POWER4) == 0)
680 {
681 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
682 *invalid = 1;
683 }
684 else
685 {
686 if ((insn & (0x17 << 21)) != (0x06 << 21)
687 && (insn & (0x1d << 21)) != (0x18 << 21))
688 *invalid = 1;
689 }
690
691 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
692 }
693
694 /* The BD field in a B form instruction when the + modifier is used.
695 This is like BDM, above, except that the branch is expected to be
696 taken. */
697
698 static unsigned long
insert_bdp(unsigned long insn,long value,int dialect,const char ** errmsg ATTRIBUTE_UNUSED)699 insert_bdp (unsigned long insn,
700 long value,
701 int dialect,
702 const char **errmsg ATTRIBUTE_UNUSED)
703 {
704 if ((dialect & PPC_OPCODE_POWER4) == 0)
705 {
706 if ((value & 0x8000) == 0)
707 insn |= 1 << 21;
708 }
709 else
710 {
711 if ((insn & (0x14 << 21)) == (0x04 << 21))
712 insn |= 0x03 << 21;
713 else if ((insn & (0x14 << 21)) == (0x10 << 21))
714 insn |= 0x09 << 21;
715 }
716 return insn | (value & 0xfffc);
717 }
718
719 static long
extract_bdp(unsigned long insn,int dialect,int * invalid)720 extract_bdp (unsigned long insn,
721 int dialect,
722 int *invalid)
723 {
724 if ((dialect & PPC_OPCODE_POWER4) == 0)
725 {
726 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
727 *invalid = 1;
728 }
729 else
730 {
731 if ((insn & (0x17 << 21)) != (0x07 << 21)
732 && (insn & (0x1d << 21)) != (0x19 << 21))
733 *invalid = 1;
734 }
735
736 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
737 }
738
739 /* Check for legal values of a BO field. */
740
741 static int
valid_bo(long value,int dialect)742 valid_bo (long value, int dialect)
743 {
744 if ((dialect & PPC_OPCODE_POWER4) == 0)
745 {
746 /* Certain encodings have bits that are required to be zero.
747 These are (z must be zero, y may be anything):
748 001zy
749 011zy
750 1z00y
751 1z01y
752 1z1zz
753 */
754 switch (value & 0x14)
755 {
756 default:
757 case 0:
758 return 1;
759 case 0x4:
760 return (value & 0x2) == 0;
761 case 0x10:
762 return (value & 0x8) == 0;
763 case 0x14:
764 return value == 0x14;
765 }
766 }
767 else
768 {
769 /* Certain encodings have bits that are required to be zero.
770 These are (z must be zero, a & t may be anything):
771 0000z
772 0001z
773 0100z
774 0101z
775 001at
776 011at
777 1a00t
778 1a01t
779 1z1zz
780 */
781 if ((value & 0x14) == 0)
782 return (value & 0x1) == 0;
783 else if ((value & 0x14) == 0x14)
784 return value == 0x14;
785 else
786 return 1;
787 }
788 }
789
790 /* The BO field in a B form instruction. Warn about attempts to set
791 the field to an illegal value. */
792
793 static unsigned long
insert_bo(unsigned long insn,long value,int dialect,const char ** errmsg)794 insert_bo (unsigned long insn,
795 long value,
796 int dialect,
797 const char **errmsg)
798 {
799 if (!valid_bo (value, dialect))
800 *errmsg = _("invalid conditional option");
801 return insn | ((value & 0x1f) << 21);
802 }
803
804 static long
extract_bo(unsigned long insn,int dialect,int * invalid)805 extract_bo (unsigned long insn,
806 int dialect,
807 int *invalid)
808 {
809 long value;
810
811 value = (insn >> 21) & 0x1f;
812 if (!valid_bo (value, dialect))
813 *invalid = 1;
814 return value;
815 }
816
817 /* The BO field in a B form instruction when the + or - modifier is
818 used. This is like the BO field, but it must be even. When
819 extracting it, we force it to be even. */
820
821 static unsigned long
insert_boe(unsigned long insn,long value,int dialect,const char ** errmsg)822 insert_boe (unsigned long insn,
823 long value,
824 int dialect,
825 const char **errmsg)
826 {
827 if (!valid_bo (value, dialect))
828 *errmsg = _("invalid conditional option");
829 else if ((value & 1) != 0)
830 *errmsg = _("attempt to set y bit when using + or - modifier");
831
832 return insn | ((value & 0x1f) << 21);
833 }
834
835 static long
extract_boe(unsigned long insn,int dialect,int * invalid)836 extract_boe (unsigned long insn,
837 int dialect,
838 int *invalid)
839 {
840 long value;
841
842 value = (insn >> 21) & 0x1f;
843 if (!valid_bo (value, dialect))
844 *invalid = 1;
845 return value & 0x1e;
846 }
847
848 /* The DQ field in a DQ form instruction. This is like D, but the
849 lower four bits are forced to zero. */
850
851 static unsigned long
insert_dq(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg)852 insert_dq (unsigned long insn,
853 long value,
854 int dialect ATTRIBUTE_UNUSED,
855 const char **errmsg)
856 {
857 if ((value & 0xf) != 0)
858 *errmsg = _("offset not a multiple of 16");
859 return insn | (value & 0xfff0);
860 }
861
862 static long
extract_dq(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)863 extract_dq (unsigned long insn,
864 int dialect ATTRIBUTE_UNUSED,
865 int *invalid ATTRIBUTE_UNUSED)
866 {
867 return ((insn & 0xfff0) ^ 0x8000) - 0x8000;
868 }
869
870 static unsigned long
insert_ev2(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg)871 insert_ev2 (unsigned long insn,
872 long value,
873 int dialect ATTRIBUTE_UNUSED,
874 const char **errmsg)
875 {
876 if ((value & 1) != 0)
877 *errmsg = _("offset not a multiple of 2");
878 if ((value > 62) != 0)
879 *errmsg = _("offset greater than 62");
880 return insn | ((value & 0x3e) << 10);
881 }
882
883 static long
extract_ev2(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)884 extract_ev2 (unsigned long insn,
885 int dialect ATTRIBUTE_UNUSED,
886 int *invalid ATTRIBUTE_UNUSED)
887 {
888 return (insn >> 10) & 0x3e;
889 }
890
891 static unsigned long
insert_ev4(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg)892 insert_ev4 (unsigned long insn,
893 long value,
894 int dialect ATTRIBUTE_UNUSED,
895 const char **errmsg)
896 {
897 if ((value & 3) != 0)
898 *errmsg = _("offset not a multiple of 4");
899 if ((value > 124) != 0)
900 *errmsg = _("offset greater than 124");
901 return insn | ((value & 0x7c) << 9);
902 }
903
904 static long
extract_ev4(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)905 extract_ev4 (unsigned long insn,
906 int dialect ATTRIBUTE_UNUSED,
907 int *invalid ATTRIBUTE_UNUSED)
908 {
909 return (insn >> 9) & 0x7c;
910 }
911
912 static unsigned long
insert_ev8(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg)913 insert_ev8 (unsigned long insn,
914 long value,
915 int dialect ATTRIBUTE_UNUSED,
916 const char **errmsg)
917 {
918 if ((value & 7) != 0)
919 *errmsg = _("offset not a multiple of 8");
920 if ((value > 248) != 0)
921 *errmsg = _("offset greater than 248");
922 return insn | ((value & 0xf8) << 8);
923 }
924
925 static long
extract_ev8(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)926 extract_ev8 (unsigned long insn,
927 int dialect ATTRIBUTE_UNUSED,
928 int *invalid ATTRIBUTE_UNUSED)
929 {
930 return (insn >> 8) & 0xf8;
931 }
932
933 /* The DS field in a DS form instruction. This is like D, but the
934 lower two bits are forced to zero. */
935
936 static unsigned long
insert_ds(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg)937 insert_ds (unsigned long insn,
938 long value,
939 int dialect ATTRIBUTE_UNUSED,
940 const char **errmsg)
941 {
942 if ((value & 3) != 0)
943 *errmsg = _("offset not a multiple of 4");
944 return insn | (value & 0xfffc);
945 }
946
947 static long
extract_ds(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)948 extract_ds (unsigned long insn,
949 int dialect ATTRIBUTE_UNUSED,
950 int *invalid ATTRIBUTE_UNUSED)
951 {
952 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
953 }
954
955 /* The DE field in a DE form instruction. */
956
957 static unsigned long
insert_de(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg)958 insert_de (unsigned long insn,
959 long value,
960 int dialect ATTRIBUTE_UNUSED,
961 const char **errmsg)
962 {
963 if (value > 2047 || value < -2048)
964 *errmsg = _("offset not between -2048 and 2047");
965 return insn | ((value << 4) & 0xfff0);
966 }
967
968 static long
extract_de(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)969 extract_de (unsigned long insn,
970 int dialect ATTRIBUTE_UNUSED,
971 int *invalid ATTRIBUTE_UNUSED)
972 {
973 return (insn & 0xfff0) >> 4;
974 }
975
976 /* The DES field in a DES form instruction. */
977
978 static unsigned long
insert_des(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg)979 insert_des (unsigned long insn,
980 long value,
981 int dialect ATTRIBUTE_UNUSED,
982 const char **errmsg)
983 {
984 if (value > 8191 || value < -8192)
985 *errmsg = _("offset not between -8192 and 8191");
986 else if ((value & 3) != 0)
987 *errmsg = _("offset not a multiple of 4");
988 return insn | ((value << 2) & 0xfff0);
989 }
990
991 static long
extract_des(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)992 extract_des (unsigned long insn,
993 int dialect ATTRIBUTE_UNUSED,
994 int *invalid ATTRIBUTE_UNUSED)
995 {
996 return (((insn >> 2) & 0x3ffc) ^ 0x2000) - 0x2000;
997 }
998
999 /* FXM mask in mfcr and mtcrf instructions. */
1000
1001 static unsigned long
insert_fxm(unsigned long insn,long value,int dialect,const char ** errmsg)1002 insert_fxm (unsigned long insn,
1003 long value,
1004 int dialect,
1005 const char **errmsg)
1006 {
1007 /* If we're handling the mfocrf and mtocrf insns ensure that exactly
1008 one bit of the mask field is set. */
1009 if ((insn & (1 << 20)) != 0)
1010 {
1011 if (value == 0 || (value & -value) != value)
1012 {
1013 *errmsg = _("invalid mask field");
1014 value = 0;
1015 }
1016 }
1017
1018 /* If the optional field on mfcr is missing that means we want to use
1019 the old form of the instruction that moves the whole cr. In that
1020 case we'll have VALUE zero. There doesn't seem to be a way to
1021 distinguish this from the case where someone writes mfcr %r3,0. */
1022 else if (value == 0)
1023 ;
1024
1025 /* If only one bit of the FXM field is set, we can use the new form
1026 of the instruction, which is faster. Unlike the Power4 branch hint
1027 encoding, this is not backward compatible. Do not generate the
1028 new form unless -mpower4 has been given, or -many and the two
1029 operand form of mfcr was used. */
1030 else if ((value & -value) == value
1031 && ((dialect & PPC_OPCODE_POWER4) != 0
1032 || ((dialect & PPC_OPCODE_ANY) != 0
1033 && (insn & (0x3ff << 1)) == 19 << 1)))
1034 insn |= 1 << 20;
1035
1036 /* Any other value on mfcr is an error. */
1037 else if ((insn & (0x3ff << 1)) == 19 << 1)
1038 {
1039 *errmsg = _("ignoring invalid mfcr mask");
1040 value = 0;
1041 }
1042
1043 return insn | ((value & 0xff) << 12);
1044 }
1045
1046 static long
extract_fxm(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid)1047 extract_fxm (unsigned long insn,
1048 int dialect ATTRIBUTE_UNUSED,
1049 int *invalid)
1050 {
1051 long mask = (insn >> 12) & 0xff;
1052
1053 /* Is this a Power4 insn? */
1054 if ((insn & (1 << 20)) != 0)
1055 {
1056 /* Exactly one bit of MASK should be set. */
1057 if (mask == 0 || (mask & -mask) != mask)
1058 *invalid = 1;
1059 }
1060
1061 /* Check that non-power4 form of mfcr has a zero MASK. */
1062 else if ((insn & (0x3ff << 1)) == 19 << 1)
1063 {
1064 if (mask != 0)
1065 *invalid = 1;
1066 }
1067
1068 return mask;
1069 }
1070
1071 /* The LI field in an I form instruction. The lower two bits are
1072 forced to zero. */
1073
1074 static unsigned long
insert_li(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg)1075 insert_li (unsigned long insn,
1076 long value,
1077 int dialect ATTRIBUTE_UNUSED,
1078 const char **errmsg)
1079 {
1080 if ((value & 3) != 0)
1081 *errmsg = _("ignoring least significant bits in branch offset");
1082 return insn | (value & 0x3fffffc);
1083 }
1084
1085 static long
extract_li(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)1086 extract_li (unsigned long insn,
1087 int dialect ATTRIBUTE_UNUSED,
1088 int *invalid ATTRIBUTE_UNUSED)
1089 {
1090 return ((insn & 0x3fffffc) ^ 0x2000000) - 0x2000000;
1091 }
1092
1093 /* The MB and ME fields in an M form instruction expressed as a single
1094 operand which is itself a bitmask. The extraction function always
1095 marks it as invalid, since we never want to recognize an
1096 instruction which uses a field of this type. */
1097
1098 static unsigned long
insert_mbe(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg)1099 insert_mbe (unsigned long insn,
1100 long value,
1101 int dialect ATTRIBUTE_UNUSED,
1102 const char **errmsg)
1103 {
1104 unsigned long uval, mask;
1105 int mb, me, mx, count, last;
1106
1107 uval = value;
1108
1109 if (uval == 0)
1110 {
1111 *errmsg = _("illegal bitmask");
1112 return insn;
1113 }
1114
1115 mb = 0;
1116 me = 32;
1117 if ((uval & 1) != 0)
1118 last = 1;
1119 else
1120 last = 0;
1121 count = 0;
1122
1123 /* mb: location of last 0->1 transition */
1124 /* me: location of last 1->0 transition */
1125 /* count: # transitions */
1126
1127 for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
1128 {
1129 if ((uval & mask) && !last)
1130 {
1131 ++count;
1132 mb = mx;
1133 last = 1;
1134 }
1135 else if (!(uval & mask) && last)
1136 {
1137 ++count;
1138 me = mx;
1139 last = 0;
1140 }
1141 }
1142 if (me == 0)
1143 me = 32;
1144
1145 if (count != 2 && (count != 0 || ! last))
1146 *errmsg = _("illegal bitmask");
1147
1148 return insn | (mb << 6) | ((me - 1) << 1);
1149 }
1150
1151 static long
extract_mbe(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid)1152 extract_mbe (unsigned long insn,
1153 int dialect ATTRIBUTE_UNUSED,
1154 int *invalid)
1155 {
1156 long ret;
1157 int mb, me;
1158 int i;
1159
1160 *invalid = 1;
1161
1162 mb = (insn >> 6) & 0x1f;
1163 me = (insn >> 1) & 0x1f;
1164 if (mb < me + 1)
1165 {
1166 ret = 0;
1167 for (i = mb; i <= me; i++)
1168 ret |= 1L << (31 - i);
1169 }
1170 else if (mb == me + 1)
1171 ret = ~0;
1172 else /* (mb > me + 1) */
1173 {
1174 ret = ~0;
1175 for (i = me + 1; i < mb; i++)
1176 ret &= ~(1L << (31 - i));
1177 }
1178 return ret;
1179 }
1180
1181 /* The MB or ME field in an MD or MDS form instruction. The high bit
1182 is wrapped to the low end. */
1183
1184 static unsigned long
insert_mb6(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)1185 insert_mb6 (unsigned long insn,
1186 long value,
1187 int dialect ATTRIBUTE_UNUSED,
1188 const char **errmsg ATTRIBUTE_UNUSED)
1189 {
1190 return insn | ((value & 0x1f) << 6) | (value & 0x20);
1191 }
1192
1193 static long
extract_mb6(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)1194 extract_mb6 (unsigned long insn,
1195 int dialect ATTRIBUTE_UNUSED,
1196 int *invalid ATTRIBUTE_UNUSED)
1197 {
1198 return ((insn >> 6) & 0x1f) | (insn & 0x20);
1199 }
1200
1201 /* The NB field in an X form instruction. The value 32 is stored as
1202 0. */
1203
1204 static unsigned long
insert_nb(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg)1205 insert_nb (unsigned long insn,
1206 long value,
1207 int dialect ATTRIBUTE_UNUSED,
1208 const char **errmsg)
1209 {
1210 if (value < 0 || value > 32)
1211 *errmsg = _("value out of range");
1212 if (value == 32)
1213 value = 0;
1214 return insn | ((value & 0x1f) << 11);
1215 }
1216
1217 static long
extract_nb(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)1218 extract_nb (unsigned long insn,
1219 int dialect ATTRIBUTE_UNUSED,
1220 int *invalid ATTRIBUTE_UNUSED)
1221 {
1222 long ret;
1223
1224 ret = (insn >> 11) & 0x1f;
1225 if (ret == 0)
1226 ret = 32;
1227 return ret;
1228 }
1229
1230 /* The NSI field in a D form instruction. This is the same as the SI
1231 field, only negated. The extraction function always marks it as
1232 invalid, since we never want to recognize an instruction which uses
1233 a field of this type. */
1234
1235 static unsigned long
insert_nsi(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)1236 insert_nsi (unsigned long insn,
1237 long value,
1238 int dialect ATTRIBUTE_UNUSED,
1239 const char **errmsg ATTRIBUTE_UNUSED)
1240 {
1241 return insn | (-value & 0xffff);
1242 }
1243
1244 static long
extract_nsi(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid)1245 extract_nsi (unsigned long insn,
1246 int dialect ATTRIBUTE_UNUSED,
1247 int *invalid)
1248 {
1249 *invalid = 1;
1250 return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
1251 }
1252
1253 /* The RA field in a D or X form instruction which is an updating
1254 load, which means that the RA field may not be zero and may not
1255 equal the RT field. */
1256
1257 static unsigned long
insert_ral(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg)1258 insert_ral (unsigned long insn,
1259 long value,
1260 int dialect ATTRIBUTE_UNUSED,
1261 const char **errmsg)
1262 {
1263 if (value == 0
1264 || (unsigned long) value == ((insn >> 21) & 0x1f))
1265 *errmsg = "invalid register operand when updating";
1266 return insn | ((value & 0x1f) << 16);
1267 }
1268
1269 /* The RA field in an lmw instruction, which has special value
1270 restrictions. */
1271
1272 static unsigned long
insert_ram(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg)1273 insert_ram (unsigned long insn,
1274 long value,
1275 int dialect ATTRIBUTE_UNUSED,
1276 const char **errmsg)
1277 {
1278 if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1279 *errmsg = _("index register in load range");
1280 return insn | ((value & 0x1f) << 16);
1281 }
1282
1283 /* The RA field in the DQ form lq instruction, which has special
1284 value restrictions. */
1285
1286 static unsigned long
insert_raq(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg)1287 insert_raq (unsigned long insn,
1288 long value,
1289 int dialect ATTRIBUTE_UNUSED,
1290 const char **errmsg)
1291 {
1292 long rtvalue = (insn & RT_MASK) >> 21;
1293
1294 if (value == rtvalue)
1295 *errmsg = _("source and target register operands must be different");
1296 return insn | ((value & 0x1f) << 16);
1297 }
1298
1299 /* The RA field in a D or X form instruction which is an updating
1300 store or an updating floating point load, which means that the RA
1301 field may not be zero. */
1302
1303 static unsigned long
insert_ras(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg)1304 insert_ras (unsigned long insn,
1305 long value,
1306 int dialect ATTRIBUTE_UNUSED,
1307 const char **errmsg)
1308 {
1309 if (value == 0)
1310 *errmsg = _("invalid register operand when updating");
1311 return insn | ((value & 0x1f) << 16);
1312 }
1313
1314 /* The RB field in an X form instruction when it must be the same as
1315 the RS field in the instruction. This is used for extended
1316 mnemonics like mr. This operand is marked FAKE. The insertion
1317 function just copies the BT field into the BA field, and the
1318 extraction function just checks that the fields are the same. */
1319
1320 static unsigned long
insert_rbs(unsigned long insn,long value ATTRIBUTE_UNUSED,int dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)1321 insert_rbs (unsigned long insn,
1322 long value ATTRIBUTE_UNUSED,
1323 int dialect ATTRIBUTE_UNUSED,
1324 const char **errmsg ATTRIBUTE_UNUSED)
1325 {
1326 return insn | (((insn >> 21) & 0x1f) << 11);
1327 }
1328
1329 static long
extract_rbs(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid)1330 extract_rbs (unsigned long insn,
1331 int dialect ATTRIBUTE_UNUSED,
1332 int *invalid)
1333 {
1334 if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
1335 *invalid = 1;
1336 return 0;
1337 }
1338
1339 /* The RT field of the DQ form lq instruction, which has special
1340 value restrictions. */
1341
1342 static unsigned long
insert_rtq(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg)1343 insert_rtq (unsigned long insn,
1344 long value,
1345 int dialect ATTRIBUTE_UNUSED,
1346 const char **errmsg)
1347 {
1348 if ((value & 1) != 0)
1349 *errmsg = _("target register operand must be even");
1350 return insn | ((value & 0x1f) << 21);
1351 }
1352
1353 /* The RS field of the DS form stq instruction, which has special
1354 value restrictions. */
1355
1356 static unsigned long
insert_rsq(unsigned long insn,long value ATTRIBUTE_UNUSED,int dialect ATTRIBUTE_UNUSED,const char ** errmsg)1357 insert_rsq (unsigned long insn,
1358 long value ATTRIBUTE_UNUSED,
1359 int dialect ATTRIBUTE_UNUSED,
1360 const char **errmsg)
1361 {
1362 if ((value & 1) != 0)
1363 *errmsg = _("source register operand must be even");
1364 return insn | ((value & 0x1f) << 21);
1365 }
1366
1367 /* The SH field in an MD form instruction. This is split. */
1368
1369 static unsigned long
insert_sh6(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)1370 insert_sh6 (unsigned long insn,
1371 long value,
1372 int dialect ATTRIBUTE_UNUSED,
1373 const char **errmsg ATTRIBUTE_UNUSED)
1374 {
1375 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1376 }
1377
1378 static long
extract_sh6(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)1379 extract_sh6 (unsigned long insn,
1380 int dialect ATTRIBUTE_UNUSED,
1381 int *invalid ATTRIBUTE_UNUSED)
1382 {
1383 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1384 }
1385
1386 /* The SPR field in an XFX form instruction. This is flipped--the
1387 lower 5 bits are stored in the upper 5 and vice- versa. */
1388
1389 static unsigned long
insert_spr(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)1390 insert_spr (unsigned long insn,
1391 long value,
1392 int dialect ATTRIBUTE_UNUSED,
1393 const char **errmsg ATTRIBUTE_UNUSED)
1394 {
1395 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1396 }
1397
1398 static long
extract_spr(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)1399 extract_spr (unsigned long insn,
1400 int dialect ATTRIBUTE_UNUSED,
1401 int *invalid ATTRIBUTE_UNUSED)
1402 {
1403 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1404 }
1405
1406 /* Some dialects have 8 SPRG registers instead of the standard 4. */
1407
1408 static unsigned long
insert_sprg(unsigned long insn,long value,int dialect,const char ** errmsg)1409 insert_sprg (unsigned long insn,
1410 long value,
1411 int dialect,
1412 const char **errmsg)
1413 {
1414 /* This check uses PPC_OPCODE_403 because PPC405 is later defined
1415 as a synonym. If ever a 405 specific dialect is added this
1416 check should use that instead. */
1417 if (value > 7
1418 || (value > 3
1419 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
1420 *errmsg = _("invalid sprg number");
1421
1422 /* If this is mfsprg4..7 then use spr 260..263 which can be read in
1423 user mode. Anything else must use spr 272..279. */
1424 if (value <= 3 || (insn & 0x100) != 0)
1425 value |= 0x10;
1426
1427 return insn | ((value & 0x17) << 16);
1428 }
1429
1430 static long
extract_sprg(unsigned long insn,int dialect,int * invalid)1431 extract_sprg (unsigned long insn,
1432 int dialect,
1433 int *invalid)
1434 {
1435 unsigned long val = (insn >> 16) & 0x1f;
1436
1437 /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279
1438 If not BOOKE or 405, then both use only 272..275. */
1439 if (val <= 3
1440 || (val < 0x10 && (insn & 0x100) != 0)
1441 || (val - 0x10 > 3
1442 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
1443 *invalid = 1;
1444 return val & 7;
1445 }
1446
1447 /* The TBR field in an XFX instruction. This is just like SPR, but it
1448 is optional. When TBR is omitted, it must be inserted as 268 (the
1449 magic number of the TB register). These functions treat 0
1450 (indicating an omitted optional operand) as 268. This means that
1451 ``mftb 4,0'' is not handled correctly. This does not matter very
1452 much, since the architecture manual does not define mftb as
1453 accepting any values other than 268 or 269. */
1454
1455 #define TB (268)
1456
1457 static unsigned long
insert_tbr(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)1458 insert_tbr (unsigned long insn,
1459 long value,
1460 int dialect ATTRIBUTE_UNUSED,
1461 const char **errmsg ATTRIBUTE_UNUSED)
1462 {
1463 if (value == 0)
1464 value = TB;
1465 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1466 }
1467
1468 static long
extract_tbr(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)1469 extract_tbr (unsigned long insn,
1470 int dialect ATTRIBUTE_UNUSED,
1471 int *invalid ATTRIBUTE_UNUSED)
1472 {
1473 long ret;
1474
1475 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1476 if (ret == TB)
1477 ret = 0;
1478 return ret;
1479 }
1480
1481 /* Macros used to form opcodes. */
1482
1483 /* The main opcode. */
1484 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1485 #define OP_MASK OP (0x3f)
1486
1487 /* The main opcode combined with a trap code in the TO field of a D
1488 form instruction. Used for extended mnemonics for the trap
1489 instructions. */
1490 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1491 #define OPTO_MASK (OP_MASK | TO_MASK)
1492
1493 /* The main opcode combined with a comparison size bit in the L field
1494 of a D form or X form instruction. Used for extended mnemonics for
1495 the comparison instructions. */
1496 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1497 #define OPL_MASK OPL (0x3f,1)
1498
1499 /* An A form instruction. */
1500 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1501 #define A_MASK A (0x3f, 0x1f, 1)
1502
1503 /* An A_MASK with the FRB field fixed. */
1504 #define AFRB_MASK (A_MASK | FRB_MASK)
1505
1506 /* An A_MASK with the FRC field fixed. */
1507 #define AFRC_MASK (A_MASK | FRC_MASK)
1508
1509 /* An A_MASK with the FRA and FRC fields fixed. */
1510 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1511
1512 /* A B form instruction. */
1513 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1514 #define B_MASK B (0x3f, 1, 1)
1515
1516 /* A B form instruction setting the BO field. */
1517 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1518 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1519
1520 /* A BBO_MASK with the y bit of the BO field removed. This permits
1521 matching a conditional branch regardless of the setting of the y
1522 bit. Similarly for the 'at' bits used for power4 branch hints. */
1523 #define Y_MASK (((unsigned long) 1) << 21)
1524 #define AT1_MASK (((unsigned long) 3) << 21)
1525 #define AT2_MASK (((unsigned long) 9) << 21)
1526 #define BBOY_MASK (BBO_MASK &~ Y_MASK)
1527 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
1528
1529 /* A B form instruction setting the BO field and the condition bits of
1530 the BI field. */
1531 #define BBOCB(op, bo, cb, aa, lk) \
1532 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1533 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1534
1535 /* A BBOCB_MASK with the y bit of the BO field removed. */
1536 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
1537 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
1538 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
1539
1540 /* A BBOYCB_MASK in which the BI field is fixed. */
1541 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
1542 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
1543
1544 /* An Context form instruction. */
1545 #define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
1546 #define CTX_MASK CTX(0x3f, 0x7)
1547
1548 /* An User Context form instruction. */
1549 #define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1550 #define UCTX_MASK UCTX(0x3f, 0x1f)
1551
1552 /* The main opcode mask with the RA field clear. */
1553 #define DRA_MASK (OP_MASK | RA_MASK)
1554
1555 /* A DS form instruction. */
1556 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1557 #define DS_MASK DSO (0x3f, 3)
1558
1559 /* A DE form instruction. */
1560 #define DEO(op, xop) (OP (op) | ((xop) & 0xf))
1561 #define DE_MASK DEO (0x3e, 0xf)
1562
1563 /* An EVSEL form instruction. */
1564 #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
1565 #define EVSEL_MASK EVSEL(0x3f, 0xff)
1566
1567 /* An M form instruction. */
1568 #define M(op, rc) (OP (op) | ((rc) & 1))
1569 #define M_MASK M (0x3f, 1)
1570
1571 /* An M form instruction with the ME field specified. */
1572 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1573
1574 /* An M_MASK with the MB and ME fields fixed. */
1575 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1576
1577 /* An M_MASK with the SH and ME fields fixed. */
1578 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1579
1580 /* An MD form instruction. */
1581 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1582 #define MD_MASK MD (0x3f, 0x7, 1)
1583
1584 /* An MD_MASK with the MB field fixed. */
1585 #define MDMB_MASK (MD_MASK | MB6_MASK)
1586
1587 /* An MD_MASK with the SH field fixed. */
1588 #define MDSH_MASK (MD_MASK | SH6_MASK)
1589
1590 /* An MDS form instruction. */
1591 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1592 #define MDS_MASK MDS (0x3f, 0xf, 1)
1593
1594 /* An MDS_MASK with the MB field fixed. */
1595 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
1596
1597 /* An SC form instruction. */
1598 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1599 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1600
1601 /* An VX form instruction. */
1602 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1603
1604 /* The mask for an VX form instruction. */
1605 #define VX_MASK VX(0x3f, 0x7ff)
1606
1607 /* An VA form instruction. */
1608 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
1609
1610 /* The mask for an VA form instruction. */
1611 #define VXA_MASK VXA(0x3f, 0x3f)
1612
1613 /* An VXR form instruction. */
1614 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1615
1616 /* The mask for a VXR form instruction. */
1617 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
1618
1619 /* An X form instruction. */
1620 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1621
1622 /* An X form instruction with the RC bit specified. */
1623 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1624
1625 /* The mask for an X form instruction. */
1626 #define X_MASK XRC (0x3f, 0x3ff, 1)
1627
1628 /* An X_MASK with the RA field fixed. */
1629 #define XRA_MASK (X_MASK | RA_MASK)
1630
1631 /* An X_MASK with the RB field fixed. */
1632 #define XRB_MASK (X_MASK | RB_MASK)
1633
1634 /* An X_MASK with the RT field fixed. */
1635 #define XRT_MASK (X_MASK | RT_MASK)
1636
1637 /* An X_MASK with the RA and RB fields fixed. */
1638 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1639
1640 /* An XRARB_MASK, but with the L bit clear. */
1641 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
1642
1643 /* An X_MASK with the RT and RA fields fixed. */
1644 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1645
1646 /* An XRTRA_MASK, but with L bit clear. */
1647 #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
1648
1649 /* An X form instruction with the L bit specified. */
1650 #define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1651
1652 /* The mask for an X form comparison instruction. */
1653 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1654
1655 /* The mask for an X form comparison instruction with the L field
1656 fixed. */
1657 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
1658
1659 /* An X form trap instruction with the TO field specified. */
1660 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1661 #define XTO_MASK (X_MASK | TO_MASK)
1662
1663 /* An X form tlb instruction with the SH field specified. */
1664 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1665 #define XTLB_MASK (X_MASK | SH_MASK)
1666
1667 /* An X form sync instruction. */
1668 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1669
1670 /* An X form sync instruction with everything filled in except the LS field. */
1671 #define XSYNC_MASK (0xff9fffff)
1672
1673 /* An X form AltiVec dss instruction. */
1674 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1675 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
1676
1677 /* An XFL form instruction. */
1678 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1679 #define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
1680
1681 /* An X form isel instruction. */
1682 #define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1683 #define XISEL_MASK XISEL(0x3f, 0x1f)
1684
1685 /* An XL form instruction with the LK field set to 0. */
1686 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1687
1688 /* An XL form instruction which uses the LK field. */
1689 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1690
1691 /* The mask for an XL form instruction. */
1692 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
1693
1694 /* An XL form instruction which explicitly sets the BO field. */
1695 #define XLO(op, bo, xop, lk) \
1696 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1697 #define XLO_MASK (XL_MASK | BO_MASK)
1698
1699 /* An XL form instruction which explicitly sets the y bit of the BO
1700 field. */
1701 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1702 #define XLYLK_MASK (XL_MASK | Y_MASK)
1703
1704 /* An XL form instruction which sets the BO field and the condition
1705 bits of the BI field. */
1706 #define XLOCB(op, bo, cb, xop, lk) \
1707 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1708 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1709
1710 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
1711 #define XLBB_MASK (XL_MASK | BB_MASK)
1712 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1713 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1714
1715 /* A mask for branch instructions using the BH field. */
1716 #define XLBH_MASK (XL_MASK | (0x1c << 11))
1717
1718 /* An XL_MASK with the BO and BB fields fixed. */
1719 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1720
1721 /* An XL_MASK with the BO, BI and BB fields fixed. */
1722 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1723
1724 /* An XO form instruction. */
1725 #define XO(op, xop, oe, rc) \
1726 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1727 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1728
1729 /* An XO_MASK with the RB field fixed. */
1730 #define XORB_MASK (XO_MASK | RB_MASK)
1731
1732 /* An XS form instruction. */
1733 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1734 #define XS_MASK XS (0x3f, 0x1ff, 1)
1735
1736 /* A mask for the FXM version of an XFX form instruction. */
1737 #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
1738
1739 /* An XFX form instruction with the FXM field filled in. */
1740 #define XFXM(op, xop, fxm, p4) \
1741 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
1742 | ((unsigned long)(p4) << 20))
1743
1744 /* An XFX form instruction with the SPR field filled in. */
1745 #define XSPR(op, xop, spr) \
1746 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1747 #define XSPR_MASK (X_MASK | SPR_MASK)
1748
1749 /* An XFX form instruction with the SPR field filled in except for the
1750 SPRBAT field. */
1751 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1752
1753 /* An XFX form instruction with the SPR field filled in except for the
1754 SPRG field. */
1755 #define XSPRG_MASK (XSPR_MASK & ~(0x17 << 16))
1756
1757 /* An X form instruction with everything filled in except the E field. */
1758 #define XE_MASK (0xffff7fff)
1759
1760 /* An X form user context instruction. */
1761 #define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1762 #define XUC_MASK XUC(0x3f, 0x1f)
1763
1764 /* The BO encodings used in extended conditional branch mnemonics. */
1765 #define BODNZF (0x0)
1766 #define BODNZFP (0x1)
1767 #define BODZF (0x2)
1768 #define BODZFP (0x3)
1769 #define BODNZT (0x8)
1770 #define BODNZTP (0x9)
1771 #define BODZT (0xa)
1772 #define BODZTP (0xb)
1773
1774 #define BOF (0x4)
1775 #define BOFP (0x5)
1776 #define BOFM4 (0x6)
1777 #define BOFP4 (0x7)
1778 #define BOT (0xc)
1779 #define BOTP (0xd)
1780 #define BOTM4 (0xe)
1781 #define BOTP4 (0xf)
1782
1783 #define BODNZ (0x10)
1784 #define BODNZP (0x11)
1785 #define BODZ (0x12)
1786 #define BODZP (0x13)
1787 #define BODNZM4 (0x18)
1788 #define BODNZP4 (0x19)
1789 #define BODZM4 (0x1a)
1790 #define BODZP4 (0x1b)
1791
1792 #define BOU (0x14)
1793
1794 /* The BI condition bit encodings used in extended conditional branch
1795 mnemonics. */
1796 #define CBLT (0)
1797 #define CBGT (1)
1798 #define CBEQ (2)
1799 #define CBSO (3)
1800
1801 /* The TO encodings used in extended trap mnemonics. */
1802 #define TOLGT (0x1)
1803 #define TOLLT (0x2)
1804 #define TOEQ (0x4)
1805 #define TOLGE (0x5)
1806 #define TOLNL (0x5)
1807 #define TOLLE (0x6)
1808 #define TOLNG (0x6)
1809 #define TOGT (0x8)
1810 #define TOGE (0xc)
1811 #define TONL (0xc)
1812 #define TOLT (0x10)
1813 #define TOLE (0x14)
1814 #define TONG (0x14)
1815 #define TONE (0x18)
1816 #define TOU (0x1f)
1817
1818 /* Smaller names for the flags so each entry in the opcodes table will
1819 fit on a single line. */
1820 #undef PPC
1821 #define PPC PPC_OPCODE_PPC
1822 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1823 #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
1824 #define POWER4 PPC_OPCODE_POWER4
1825 #define POWER5 PPC_OPCODE_POWER5
1826 #define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC
1827 #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC
1828 #define PPC403 PPC_OPCODE_403
1829 #define PPC405 PPC403
1830 #define PPC440 PPC_OPCODE_440
1831 #define PPC750 PPC
1832 #define PPC860 PPC
1833 #define PPCVEC PPC_OPCODE_ALTIVEC
1834 #define POWER PPC_OPCODE_POWER
1835 #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1836 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1837 #define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32
1838 #define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1839 #define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32
1840 #define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
1841 #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
1842 #define MFDEC1 PPC_OPCODE_POWER
1843 #define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
1844 #define BOOKE PPC_OPCODE_BOOKE
1845 #define BOOKE64 PPC_OPCODE_BOOKE64
1846 #define CLASSIC PPC_OPCODE_CLASSIC
1847 #define PPCSPE PPC_OPCODE_SPE
1848 #define PPCISEL PPC_OPCODE_ISEL
1849 #define PPCEFS PPC_OPCODE_EFS
1850 #define PPCBRLK PPC_OPCODE_BRLOCK
1851 #define PPCPMR PPC_OPCODE_PMR
1852 #define PPCCHLK PPC_OPCODE_CACHELCK
1853 #define PPCCHLK64 PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
1854 #define PPCRFMCI PPC_OPCODE_RFMCI
1855
1856 /* The opcode table.
1857
1858 The format of the opcode table is:
1859
1860 NAME OPCODE MASK FLAGS { OPERANDS }
1861
1862 NAME is the name of the instruction.
1863 OPCODE is the instruction opcode.
1864 MASK is the opcode mask; this is used to tell the disassembler
1865 which bits in the actual opcode must match OPCODE.
1866 FLAGS are flags indicated what processors support the instruction.
1867 OPERANDS is the list of operands.
1868
1869 The disassembler reads the table in order and prints the first
1870 instruction which matches, so this table is sorted to put more
1871 specific instructions before more general instructions. It is also
1872 sorted by major opcode. */
1873
1874 const struct powerpc_opcode powerpc_opcodes[] = {
1875 { "attn", X(0,256), X_MASK, POWER4, { 0 } },
1876 { "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } },
1877 { "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } },
1878 { "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } },
1879 { "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, { RA, SI } },
1880 { "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, { RA, SI } },
1881 { "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } },
1882 { "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, { RA, SI } },
1883 { "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, { RA, SI } },
1884 { "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, { RA, SI } },
1885 { "tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, { RA, SI } },
1886 { "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, { RA, SI } },
1887 { "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, { RA, SI } },
1888 { "tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, { RA, SI } },
1889 { "tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, { RA, SI } },
1890 { "tdi", OP(2), OP_MASK, PPC64, { TO, RA, SI } },
1891
1892 { "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, { RA, SI } },
1893 { "tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, { RA, SI } },
1894 { "twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, { RA, SI } },
1895 { "tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, { RA, SI } },
1896 { "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, { RA, SI } },
1897 { "teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, { RA, SI } },
1898 { "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, { RA, SI } },
1899 { "tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, { RA, SI } },
1900 { "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, { RA, SI } },
1901 { "tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, { RA, SI } },
1902 { "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } },
1903 { "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } },
1904 { "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, { RA, SI } },
1905 { "tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, { RA, SI } },
1906 { "twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, { RA, SI } },
1907 { "tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, { RA, SI } },
1908 { "twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, { RA, SI } },
1909 { "tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, { RA, SI } },
1910 { "twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, { RA, SI } },
1911 { "tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, { RA, SI } },
1912 { "twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, { RA, SI } },
1913 { "tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, { RA, SI } },
1914 { "twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, { RA, SI } },
1915 { "tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, { RA, SI } },
1916 { "twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, { RA, SI } },
1917 { "tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, { RA, SI } },
1918 { "twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, { RA, SI } },
1919 { "tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, { RA, SI } },
1920 { "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } },
1921 { "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
1922
1923 { "macchw", XO(4,172,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1924 { "macchw.", XO(4,172,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1925 { "macchwo", XO(4,172,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1926 { "macchwo.", XO(4,172,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1927 { "macchws", XO(4,236,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1928 { "macchws.", XO(4,236,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1929 { "macchwso", XO(4,236,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1930 { "macchwso.", XO(4,236,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1931 { "macchwsu", XO(4,204,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1932 { "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1933 { "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1934 { "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1935 { "macchwu", XO(4,140,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1936 { "macchwu.", XO(4,140,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1937 { "macchwuo", XO(4,140,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1938 { "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1939 { "machhw", XO(4,44,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1940 { "machhw.", XO(4,44,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1941 { "machhwo", XO(4,44,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1942 { "machhwo.", XO(4,44,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1943 { "machhws", XO(4,108,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1944 { "machhws.", XO(4,108,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1945 { "machhwso", XO(4,108,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1946 { "machhwso.", XO(4,108,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1947 { "machhwsu", XO(4,76,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1948 { "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1949 { "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1950 { "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1951 { "machhwu", XO(4,12,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1952 { "machhwu.", XO(4,12,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1953 { "machhwuo", XO(4,12,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1954 { "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1955 { "maclhw", XO(4,428,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1956 { "maclhw.", XO(4,428,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1957 { "maclhwo", XO(4,428,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1958 { "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1959 { "maclhws", XO(4,492,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1960 { "maclhws.", XO(4,492,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1961 { "maclhwso", XO(4,492,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1962 { "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1963 { "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1964 { "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1965 { "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1966 { "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1967 { "maclhwu", XO(4,396,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1968 { "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1969 { "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1970 { "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1971 { "mulchw", XRC(4,168,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1972 { "mulchw.", XRC(4,168,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1973 { "mulchwu", XRC(4,136,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1974 { "mulchwu.", XRC(4,136,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1975 { "mulhhw", XRC(4,40,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1976 { "mulhhw.", XRC(4,40,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1977 { "mulhhwu", XRC(4,8,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1978 { "mulhhwu.", XRC(4,8,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1979 { "mullhw", XRC(4,424,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1980 { "mullhw.", XRC(4,424,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1981 { "mullhwu", XRC(4,392,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1982 { "mullhwu.", XRC(4,392,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1983 { "nmacchw", XO(4,174,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1984 { "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1985 { "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1986 { "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1987 { "nmacchws", XO(4,238,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1988 { "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1989 { "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1990 { "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1991 { "nmachhw", XO(4,46,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1992 { "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1993 { "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1994 { "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1995 { "nmachhws", XO(4,110,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1996 { "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1997 { "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1998 { "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1999 { "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2000 { "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2001 { "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2002 { "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2003 { "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2004 { "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2005 { "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2006 { "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2007 { "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } },
2008 { "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } },
2009
2010 /* Double-precision opcodes. */
2011 /* Some of these conflict with AltiVec, so move them before, since
2012 PPCVEC includes the PPC_OPCODE_PPC set. */
2013 { "efscfd", VX(4, 719), VX_MASK, PPCEFS, { RS, RB } },
2014 { "efdabs", VX(4, 740), VX_MASK, PPCEFS, { RS, RA } },
2015 { "efdnabs", VX(4, 741), VX_MASK, PPCEFS, { RS, RA } },
2016 { "efdneg", VX(4, 742), VX_MASK, PPCEFS, { RS, RA } },
2017 { "efdadd", VX(4, 736), VX_MASK, PPCEFS, { RS, RA, RB } },
2018 { "efdsub", VX(4, 737), VX_MASK, PPCEFS, { RS, RA, RB } },
2019 { "efdmul", VX(4, 744), VX_MASK, PPCEFS, { RS, RA, RB } },
2020 { "efddiv", VX(4, 745), VX_MASK, PPCEFS, { RS, RA, RB } },
2021 { "efdcmpgt", VX(4, 748), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2022 { "efdcmplt", VX(4, 749), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2023 { "efdcmpeq", VX(4, 750), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2024 { "efdtstgt", VX(4, 764), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2025 { "efdtstlt", VX(4, 765), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2026 { "efdtsteq", VX(4, 766), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2027 { "efdcfsi", VX(4, 753), VX_MASK, PPCEFS, { RS, RB } },
2028 { "efdcfsid", VX(4, 739), VX_MASK, PPCEFS, { RS, RB } },
2029 { "efdcfui", VX(4, 752), VX_MASK, PPCEFS, { RS, RB } },
2030 { "efdcfuid", VX(4, 738), VX_MASK, PPCEFS, { RS, RB } },
2031 { "efdcfsf", VX(4, 755), VX_MASK, PPCEFS, { RS, RB } },
2032 { "efdcfuf", VX(4, 754), VX_MASK, PPCEFS, { RS, RB } },
2033 { "efdctsi", VX(4, 757), VX_MASK, PPCEFS, { RS, RB } },
2034 { "efdctsidz",VX(4, 747), VX_MASK, PPCEFS, { RS, RB } },
2035 { "efdctsiz", VX(4, 762), VX_MASK, PPCEFS, { RS, RB } },
2036 { "efdctui", VX(4, 756), VX_MASK, PPCEFS, { RS, RB } },
2037 { "efdctuidz",VX(4, 746), VX_MASK, PPCEFS, { RS, RB } },
2038 { "efdctuiz", VX(4, 760), VX_MASK, PPCEFS, { RS, RB } },
2039 { "efdctsf", VX(4, 759), VX_MASK, PPCEFS, { RS, RB } },
2040 { "efdctuf", VX(4, 758), VX_MASK, PPCEFS, { RS, RB } },
2041 { "efdcfs", VX(4, 751), VX_MASK, PPCEFS, { RS, RB } },
2042 /* End of double-precision opcodes. */
2043
2044 { "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } },
2045 { "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } },
2046 { "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } },
2047 { "vaddshs", VX(4, 832), VX_MASK, PPCVEC, { VD, VA, VB } },
2048 { "vaddsws", VX(4, 896), VX_MASK, PPCVEC, { VD, VA, VB } },
2049 { "vaddubm", VX(4, 0), VX_MASK, PPCVEC, { VD, VA, VB } },
2050 { "vaddubs", VX(4, 512), VX_MASK, PPCVEC, { VD, VA, VB } },
2051 { "vadduhm", VX(4, 64), VX_MASK, PPCVEC, { VD, VA, VB } },
2052 { "vadduhs", VX(4, 576), VX_MASK, PPCVEC, { VD, VA, VB } },
2053 { "vadduwm", VX(4, 128), VX_MASK, PPCVEC, { VD, VA, VB } },
2054 { "vadduws", VX(4, 640), VX_MASK, PPCVEC, { VD, VA, VB } },
2055 { "vand", VX(4, 1028), VX_MASK, PPCVEC, { VD, VA, VB } },
2056 { "vandc", VX(4, 1092), VX_MASK, PPCVEC, { VD, VA, VB } },
2057 { "vavgsb", VX(4, 1282), VX_MASK, PPCVEC, { VD, VA, VB } },
2058 { "vavgsh", VX(4, 1346), VX_MASK, PPCVEC, { VD, VA, VB } },
2059 { "vavgsw", VX(4, 1410), VX_MASK, PPCVEC, { VD, VA, VB } },
2060 { "vavgub", VX(4, 1026), VX_MASK, PPCVEC, { VD, VA, VB } },
2061 { "vavguh", VX(4, 1090), VX_MASK, PPCVEC, { VD, VA, VB } },
2062 { "vavguw", VX(4, 1154), VX_MASK, PPCVEC, { VD, VA, VB } },
2063 { "vcfsx", VX(4, 842), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2064 { "vcfux", VX(4, 778), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2065 { "vcmpbfp", VXR(4, 966, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2066 { "vcmpbfp.", VXR(4, 966, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2067 { "vcmpeqfp", VXR(4, 198, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2068 { "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2069 { "vcmpequb", VXR(4, 6, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2070 { "vcmpequb.", VXR(4, 6, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2071 { "vcmpequh", VXR(4, 70, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2072 { "vcmpequh.", VXR(4, 70, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2073 { "vcmpequw", VXR(4, 134, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2074 { "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2075 { "vcmpgefp", VXR(4, 454, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2076 { "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2077 { "vcmpgtfp", VXR(4, 710, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2078 { "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2079 { "vcmpgtsb", VXR(4, 774, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2080 { "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2081 { "vcmpgtsh", VXR(4, 838, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2082 { "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2083 { "vcmpgtsw", VXR(4, 902, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2084 { "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2085 { "vcmpgtub", VXR(4, 518, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2086 { "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2087 { "vcmpgtuh", VXR(4, 582, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2088 { "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2089 { "vcmpgtuw", VXR(4, 646, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2090 { "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2091 { "vctsxs", VX(4, 970), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2092 { "vctuxs", VX(4, 906), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2093 { "vexptefp", VX(4, 394), VX_MASK, PPCVEC, { VD, VB } },
2094 { "vlogefp", VX(4, 458), VX_MASK, PPCVEC, { VD, VB } },
2095 { "vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
2096 { "vmaxfp", VX(4, 1034), VX_MASK, PPCVEC, { VD, VA, VB } },
2097 { "vmaxsb", VX(4, 258), VX_MASK, PPCVEC, { VD, VA, VB } },
2098 { "vmaxsh", VX(4, 322), VX_MASK, PPCVEC, { VD, VA, VB } },
2099 { "vmaxsw", VX(4, 386), VX_MASK, PPCVEC, { VD, VA, VB } },
2100 { "vmaxub", VX(4, 2), VX_MASK, PPCVEC, { VD, VA, VB } },
2101 { "vmaxuh", VX(4, 66), VX_MASK, PPCVEC, { VD, VA, VB } },
2102 { "vmaxuw", VX(4, 130), VX_MASK, PPCVEC, { VD, VA, VB } },
2103 { "vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2104 { "vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2105 { "vminfp", VX(4, 1098), VX_MASK, PPCVEC, { VD, VA, VB } },
2106 { "vminsb", VX(4, 770), VX_MASK, PPCVEC, { VD, VA, VB } },
2107 { "vminsh", VX(4, 834), VX_MASK, PPCVEC, { VD, VA, VB } },
2108 { "vminsw", VX(4, 898), VX_MASK, PPCVEC, { VD, VA, VB } },
2109 { "vminub", VX(4, 514), VX_MASK, PPCVEC, { VD, VA, VB } },
2110 { "vminuh", VX(4, 578), VX_MASK, PPCVEC, { VD, VA, VB } },
2111 { "vminuw", VX(4, 642), VX_MASK, PPCVEC, { VD, VA, VB } },
2112 { "vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2113 { "vmrghb", VX(4, 12), VX_MASK, PPCVEC, { VD, VA, VB } },
2114 { "vmrghh", VX(4, 76), VX_MASK, PPCVEC, { VD, VA, VB } },
2115 { "vmrghw", VX(4, 140), VX_MASK, PPCVEC, { VD, VA, VB } },
2116 { "vmrglb", VX(4, 268), VX_MASK, PPCVEC, { VD, VA, VB } },
2117 { "vmrglh", VX(4, 332), VX_MASK, PPCVEC, { VD, VA, VB } },
2118 { "vmrglw", VX(4, 396), VX_MASK, PPCVEC, { VD, VA, VB } },
2119 { "vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2120 { "vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2121 { "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2122 { "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2123 { "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2124 { "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2125 { "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } },
2126 { "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } },
2127 { "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } },
2128 { "vmuleuh", VX(4, 584), VX_MASK, PPCVEC, { VD, VA, VB } },
2129 { "vmulosb", VX(4, 264), VX_MASK, PPCVEC, { VD, VA, VB } },
2130 { "vmulosh", VX(4, 328), VX_MASK, PPCVEC, { VD, VA, VB } },
2131 { "vmuloub", VX(4, 8), VX_MASK, PPCVEC, { VD, VA, VB } },
2132 { "vmulouh", VX(4, 72), VX_MASK, PPCVEC, { VD, VA, VB } },
2133 { "vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
2134 { "vnor", VX(4, 1284), VX_MASK, PPCVEC, { VD, VA, VB } },
2135 { "vor", VX(4, 1156), VX_MASK, PPCVEC, { VD, VA, VB } },
2136 { "vperm", VXA(4, 43), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2137 { "vpkpx", VX(4, 782), VX_MASK, PPCVEC, { VD, VA, VB } },
2138 { "vpkshss", VX(4, 398), VX_MASK, PPCVEC, { VD, VA, VB } },
2139 { "vpkshus", VX(4, 270), VX_MASK, PPCVEC, { VD, VA, VB } },
2140 { "vpkswss", VX(4, 462), VX_MASK, PPCVEC, { VD, VA, VB } },
2141 { "vpkswus", VX(4, 334), VX_MASK, PPCVEC, { VD, VA, VB } },
2142 { "vpkuhum", VX(4, 14), VX_MASK, PPCVEC, { VD, VA, VB } },
2143 { "vpkuhus", VX(4, 142), VX_MASK, PPCVEC, { VD, VA, VB } },
2144 { "vpkuwum", VX(4, 78), VX_MASK, PPCVEC, { VD, VA, VB } },
2145 { "vpkuwus", VX(4, 206), VX_MASK, PPCVEC, { VD, VA, VB } },
2146 { "vrefp", VX(4, 266), VX_MASK, PPCVEC, { VD, VB } },
2147 { "vrfim", VX(4, 714), VX_MASK, PPCVEC, { VD, VB } },
2148 { "vrfin", VX(4, 522), VX_MASK, PPCVEC, { VD, VB } },
2149 { "vrfip", VX(4, 650), VX_MASK, PPCVEC, { VD, VB } },
2150 { "vrfiz", VX(4, 586), VX_MASK, PPCVEC, { VD, VB } },
2151 { "vrlb", VX(4, 4), VX_MASK, PPCVEC, { VD, VA, VB } },
2152 { "vrlh", VX(4, 68), VX_MASK, PPCVEC, { VD, VA, VB } },
2153 { "vrlw", VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB } },
2154 { "vrsqrtefp", VX(4, 330), VX_MASK, PPCVEC, { VD, VB } },
2155 { "vsel", VXA(4, 42), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2156 { "vsl", VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB } },
2157 { "vslb", VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB } },
2158 { "vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, { VD, VA, VB, SHB } },
2159 { "vslh", VX(4, 324), VX_MASK, PPCVEC, { VD, VA, VB } },
2160 { "vslo", VX(4, 1036), VX_MASK, PPCVEC, { VD, VA, VB } },
2161 { "vslw", VX(4, 388), VX_MASK, PPCVEC, { VD, VA, VB } },
2162 { "vspltb", VX(4, 524), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2163 { "vsplth", VX(4, 588), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2164 { "vspltisb", VX(4, 780), VX_MASK, PPCVEC, { VD, SIMM } },
2165 { "vspltish", VX(4, 844), VX_MASK, PPCVEC, { VD, SIMM } },
2166 { "vspltisw", VX(4, 908), VX_MASK, PPCVEC, { VD, SIMM } },
2167 { "vspltw", VX(4, 652), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2168 { "vsr", VX(4, 708), VX_MASK, PPCVEC, { VD, VA, VB } },
2169 { "vsrab", VX(4, 772), VX_MASK, PPCVEC, { VD, VA, VB } },
2170 { "vsrah", VX(4, 836), VX_MASK, PPCVEC, { VD, VA, VB } },
2171 { "vsraw", VX(4, 900), VX_MASK, PPCVEC, { VD, VA, VB } },
2172 { "vsrb", VX(4, 516), VX_MASK, PPCVEC, { VD, VA, VB } },
2173 { "vsrh", VX(4, 580), VX_MASK, PPCVEC, { VD, VA, VB } },
2174 { "vsro", VX(4, 1100), VX_MASK, PPCVEC, { VD, VA, VB } },
2175 { "vsrw", VX(4, 644), VX_MASK, PPCVEC, { VD, VA, VB } },
2176 { "vsubcuw", VX(4, 1408), VX_MASK, PPCVEC, { VD, VA, VB } },
2177 { "vsubfp", VX(4, 74), VX_MASK, PPCVEC, { VD, VA, VB } },
2178 { "vsubsbs", VX(4, 1792), VX_MASK, PPCVEC, { VD, VA, VB } },
2179 { "vsubshs", VX(4, 1856), VX_MASK, PPCVEC, { VD, VA, VB } },
2180 { "vsubsws", VX(4, 1920), VX_MASK, PPCVEC, { VD, VA, VB } },
2181 { "vsububm", VX(4, 1024), VX_MASK, PPCVEC, { VD, VA, VB } },
2182 { "vsububs", VX(4, 1536), VX_MASK, PPCVEC, { VD, VA, VB } },
2183 { "vsubuhm", VX(4, 1088), VX_MASK, PPCVEC, { VD, VA, VB } },
2184 { "vsubuhs", VX(4, 1600), VX_MASK, PPCVEC, { VD, VA, VB } },
2185 { "vsubuwm", VX(4, 1152), VX_MASK, PPCVEC, { VD, VA, VB } },
2186 { "vsubuws", VX(4, 1664), VX_MASK, PPCVEC, { VD, VA, VB } },
2187 { "vsumsws", VX(4, 1928), VX_MASK, PPCVEC, { VD, VA, VB } },
2188 { "vsum2sws", VX(4, 1672), VX_MASK, PPCVEC, { VD, VA, VB } },
2189 { "vsum4sbs", VX(4, 1800), VX_MASK, PPCVEC, { VD, VA, VB } },
2190 { "vsum4shs", VX(4, 1608), VX_MASK, PPCVEC, { VD, VA, VB } },
2191 { "vsum4ubs", VX(4, 1544), VX_MASK, PPCVEC, { VD, VA, VB } },
2192 { "vupkhpx", VX(4, 846), VX_MASK, PPCVEC, { VD, VB } },
2193 { "vupkhsb", VX(4, 526), VX_MASK, PPCVEC, { VD, VB } },
2194 { "vupkhsh", VX(4, 590), VX_MASK, PPCVEC, { VD, VB } },
2195 { "vupklpx", VX(4, 974), VX_MASK, PPCVEC, { VD, VB } },
2196 { "vupklsb", VX(4, 654), VX_MASK, PPCVEC, { VD, VB } },
2197 { "vupklsh", VX(4, 718), VX_MASK, PPCVEC, { VD, VB } },
2198 { "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } },
2199
2200 { "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RS, RA, RB } },
2201 { "evaddiw", VX(4, 514), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2202 { "evsubfw", VX(4, 516), VX_MASK, PPCSPE, { RS, RA, RB } },
2203 { "evsubw", VX(4, 516), VX_MASK, PPCSPE, { RS, RB, RA } },
2204 { "evsubifw", VX(4, 518), VX_MASK, PPCSPE, { RS, UIMM, RB } },
2205 { "evsubiw", VX(4, 518), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2206 { "evabs", VX(4, 520), VX_MASK, PPCSPE, { RS, RA } },
2207 { "evneg", VX(4, 521), VX_MASK, PPCSPE, { RS, RA } },
2208 { "evextsb", VX(4, 522), VX_MASK, PPCSPE, { RS, RA } },
2209 { "evextsh", VX(4, 523), VX_MASK, PPCSPE, { RS, RA } },
2210 { "evrndw", VX(4, 524), VX_MASK, PPCSPE, { RS, RA } },
2211 { "evcntlzw", VX(4, 525), VX_MASK, PPCSPE, { RS, RA } },
2212 { "evcntlsw", VX(4, 526), VX_MASK, PPCSPE, { RS, RA } },
2213
2214 { "brinc", VX(4, 527), VX_MASK, PPCSPE, { RS, RA, RB } },
2215
2216 { "evand", VX(4, 529), VX_MASK, PPCSPE, { RS, RA, RB } },
2217 { "evandc", VX(4, 530), VX_MASK, PPCSPE, { RS, RA, RB } },
2218 { "evmr", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, BBA } },
2219 { "evor", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, RB } },
2220 { "evorc", VX(4, 539), VX_MASK, PPCSPE, { RS, RA, RB } },
2221 { "evxor", VX(4, 534), VX_MASK, PPCSPE, { RS, RA, RB } },
2222 { "eveqv", VX(4, 537), VX_MASK, PPCSPE, { RS, RA, RB } },
2223 { "evnand", VX(4, 542), VX_MASK, PPCSPE, { RS, RA, RB } },
2224 { "evnot", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, BBA } },
2225 { "evnor", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, RB } },
2226
2227 { "evrlw", VX(4, 552), VX_MASK, PPCSPE, { RS, RA, RB } },
2228 { "evrlwi", VX(4, 554), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2229 { "evslw", VX(4, 548), VX_MASK, PPCSPE, { RS, RA, RB } },
2230 { "evslwi", VX(4, 550), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2231 { "evsrws", VX(4, 545), VX_MASK, PPCSPE, { RS, RA, RB } },
2232 { "evsrwu", VX(4, 544), VX_MASK, PPCSPE, { RS, RA, RB } },
2233 { "evsrwis", VX(4, 547), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2234 { "evsrwiu", VX(4, 546), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2235 { "evsplati", VX(4, 553), VX_MASK, PPCSPE, { RS, SIMM } },
2236 { "evsplatfi", VX(4, 555), VX_MASK, PPCSPE, { RS, SIMM } },
2237 { "evmergehi", VX(4, 556), VX_MASK, PPCSPE, { RS, RA, RB } },
2238 { "evmergelo", VX(4, 557), VX_MASK, PPCSPE, { RS, RA, RB } },
2239 { "evmergehilo",VX(4,558), VX_MASK, PPCSPE, { RS, RA, RB } },
2240 { "evmergelohi",VX(4,559), VX_MASK, PPCSPE, { RS, RA, RB } },
2241
2242 { "evcmpgts", VX(4, 561), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2243 { "evcmpgtu", VX(4, 560), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2244 { "evcmplts", VX(4, 563), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2245 { "evcmpltu", VX(4, 562), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2246 { "evcmpeq", VX(4, 564), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2247 { "evsel", EVSEL(4,79),EVSEL_MASK, PPCSPE, { RS, RA, RB, CRFS } },
2248
2249 { "evldd", VX(4, 769), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2250 { "evlddx", VX(4, 768), VX_MASK, PPCSPE, { RS, RA, RB } },
2251 { "evldw", VX(4, 771), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2252 { "evldwx", VX(4, 770), VX_MASK, PPCSPE, { RS, RA, RB } },
2253 { "evldh", VX(4, 773), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2254 { "evldhx", VX(4, 772), VX_MASK, PPCSPE, { RS, RA, RB } },
2255 { "evlwhe", VX(4, 785), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2256 { "evlwhex", VX(4, 784), VX_MASK, PPCSPE, { RS, RA, RB } },
2257 { "evlwhou", VX(4, 789), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2258 { "evlwhoux", VX(4, 788), VX_MASK, PPCSPE, { RS, RA, RB } },
2259 { "evlwhos", VX(4, 791), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2260 { "evlwhosx", VX(4, 790), VX_MASK, PPCSPE, { RS, RA, RB } },
2261 { "evlwwsplat",VX(4, 793), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2262 { "evlwwsplatx",VX(4, 792), VX_MASK, PPCSPE, { RS, RA, RB } },
2263 { "evlwhsplat",VX(4, 797), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2264 { "evlwhsplatx",VX(4, 796), VX_MASK, PPCSPE, { RS, RA, RB } },
2265 { "evlhhesplat",VX(4, 777), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2266 { "evlhhesplatx",VX(4, 776), VX_MASK, PPCSPE, { RS, RA, RB } },
2267 { "evlhhousplat",VX(4, 781), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2268 { "evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, { RS, RA, RB } },
2269 { "evlhhossplat",VX(4, 783), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2270 { "evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, { RS, RA, RB } },
2271
2272 { "evstdd", VX(4, 801), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2273 { "evstddx", VX(4, 800), VX_MASK, PPCSPE, { RS, RA, RB } },
2274 { "evstdw", VX(4, 803), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2275 { "evstdwx", VX(4, 802), VX_MASK, PPCSPE, { RS, RA, RB } },
2276 { "evstdh", VX(4, 805), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2277 { "evstdhx", VX(4, 804), VX_MASK, PPCSPE, { RS, RA, RB } },
2278 { "evstwwe", VX(4, 825), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2279 { "evstwwex", VX(4, 824), VX_MASK, PPCSPE, { RS, RA, RB } },
2280 { "evstwwo", VX(4, 829), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2281 { "evstwwox", VX(4, 828), VX_MASK, PPCSPE, { RS, RA, RB } },
2282 { "evstwhe", VX(4, 817), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2283 { "evstwhex", VX(4, 816), VX_MASK, PPCSPE, { RS, RA, RB } },
2284 { "evstwho", VX(4, 821), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2285 { "evstwhox", VX(4, 820), VX_MASK, PPCSPE, { RS, RA, RB } },
2286
2287 { "evfsabs", VX(4, 644), VX_MASK, PPCSPE, { RS, RA } },
2288 { "evfsnabs", VX(4, 645), VX_MASK, PPCSPE, { RS, RA } },
2289 { "evfsneg", VX(4, 646), VX_MASK, PPCSPE, { RS, RA } },
2290 { "evfsadd", VX(4, 640), VX_MASK, PPCSPE, { RS, RA, RB } },
2291 { "evfssub", VX(4, 641), VX_MASK, PPCSPE, { RS, RA, RB } },
2292 { "evfsmul", VX(4, 648), VX_MASK, PPCSPE, { RS, RA, RB } },
2293 { "evfsdiv", VX(4, 649), VX_MASK, PPCSPE, { RS, RA, RB } },
2294 { "evfscmpgt", VX(4, 652), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2295 { "evfscmplt", VX(4, 653), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2296 { "evfscmpeq", VX(4, 654), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2297 { "evfststgt", VX(4, 668), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2298 { "evfststlt", VX(4, 669), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2299 { "evfststeq", VX(4, 670), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2300 { "evfscfui", VX(4, 656), VX_MASK, PPCSPE, { RS, RB } },
2301 { "evfsctuiz", VX(4, 664), VX_MASK, PPCSPE, { RS, RB } },
2302 { "evfscfsi", VX(4, 657), VX_MASK, PPCSPE, { RS, RB } },
2303 { "evfscfuf", VX(4, 658), VX_MASK, PPCSPE, { RS, RB } },
2304 { "evfscfsf", VX(4, 659), VX_MASK, PPCSPE, { RS, RB } },
2305 { "evfsctui", VX(4, 660), VX_MASK, PPCSPE, { RS, RB } },
2306 { "evfsctsi", VX(4, 661), VX_MASK, PPCSPE, { RS, RB } },
2307 { "evfsctsiz", VX(4, 666), VX_MASK, PPCSPE, { RS, RB } },
2308 { "evfsctuf", VX(4, 662), VX_MASK, PPCSPE, { RS, RB } },
2309 { "evfsctsf", VX(4, 663), VX_MASK, PPCSPE, { RS, RB } },
2310
2311 { "efsabs", VX(4, 708), VX_MASK, PPCEFS, { RS, RA } },
2312 { "efsnabs", VX(4, 709), VX_MASK, PPCEFS, { RS, RA } },
2313 { "efsneg", VX(4, 710), VX_MASK, PPCEFS, { RS, RA } },
2314 { "efsadd", VX(4, 704), VX_MASK, PPCEFS, { RS, RA, RB } },
2315 { "efssub", VX(4, 705), VX_MASK, PPCEFS, { RS, RA, RB } },
2316 { "efsmul", VX(4, 712), VX_MASK, PPCEFS, { RS, RA, RB } },
2317 { "efsdiv", VX(4, 713), VX_MASK, PPCEFS, { RS, RA, RB } },
2318 { "efscmpgt", VX(4, 716), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2319 { "efscmplt", VX(4, 717), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2320 { "efscmpeq", VX(4, 718), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2321 { "efststgt", VX(4, 732), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2322 { "efststlt", VX(4, 733), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2323 { "efststeq", VX(4, 734), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2324 { "efscfui", VX(4, 720), VX_MASK, PPCEFS, { RS, RB } },
2325 { "efsctuiz", VX(4, 728), VX_MASK, PPCEFS, { RS, RB } },
2326 { "efscfsi", VX(4, 721), VX_MASK, PPCEFS, { RS, RB } },
2327 { "efscfuf", VX(4, 722), VX_MASK, PPCEFS, { RS, RB } },
2328 { "efscfsf", VX(4, 723), VX_MASK, PPCEFS, { RS, RB } },
2329 { "efsctui", VX(4, 724), VX_MASK, PPCEFS, { RS, RB } },
2330 { "efsctsi", VX(4, 725), VX_MASK, PPCEFS, { RS, RB } },
2331 { "efsctsiz", VX(4, 730), VX_MASK, PPCEFS, { RS, RB } },
2332 { "efsctuf", VX(4, 726), VX_MASK, PPCEFS, { RS, RB } },
2333 { "efsctsf", VX(4, 727), VX_MASK, PPCEFS, { RS, RB } },
2334
2335 { "evmhossf", VX(4, 1031), VX_MASK, PPCSPE, { RS, RA, RB } },
2336 { "evmhossfa", VX(4, 1063), VX_MASK, PPCSPE, { RS, RA, RB } },
2337 { "evmhosmf", VX(4, 1039), VX_MASK, PPCSPE, { RS, RA, RB } },
2338 { "evmhosmfa", VX(4, 1071), VX_MASK, PPCSPE, { RS, RA, RB } },
2339 { "evmhosmi", VX(4, 1037), VX_MASK, PPCSPE, { RS, RA, RB } },
2340 { "evmhosmia", VX(4, 1069), VX_MASK, PPCSPE, { RS, RA, RB } },
2341 { "evmhoumi", VX(4, 1036), VX_MASK, PPCSPE, { RS, RA, RB } },
2342 { "evmhoumia", VX(4, 1068), VX_MASK, PPCSPE, { RS, RA, RB } },
2343 { "evmhessf", VX(4, 1027), VX_MASK, PPCSPE, { RS, RA, RB } },
2344 { "evmhessfa", VX(4, 1059), VX_MASK, PPCSPE, { RS, RA, RB } },
2345 { "evmhesmf", VX(4, 1035), VX_MASK, PPCSPE, { RS, RA, RB } },
2346 { "evmhesmfa", VX(4, 1067), VX_MASK, PPCSPE, { RS, RA, RB } },
2347 { "evmhesmi", VX(4, 1033), VX_MASK, PPCSPE, { RS, RA, RB } },
2348 { "evmhesmia", VX(4, 1065), VX_MASK, PPCSPE, { RS, RA, RB } },
2349 { "evmheumi", VX(4, 1032), VX_MASK, PPCSPE, { RS, RA, RB } },
2350 { "evmheumia", VX(4, 1064), VX_MASK, PPCSPE, { RS, RA, RB } },
2351
2352 { "evmhossfaaw",VX(4, 1287), VX_MASK, PPCSPE, { RS, RA, RB } },
2353 { "evmhossiaaw",VX(4, 1285), VX_MASK, PPCSPE, { RS, RA, RB } },
2354 { "evmhosmfaaw",VX(4, 1295), VX_MASK, PPCSPE, { RS, RA, RB } },
2355 { "evmhosmiaaw",VX(4, 1293), VX_MASK, PPCSPE, { RS, RA, RB } },
2356 { "evmhousiaaw",VX(4, 1284), VX_MASK, PPCSPE, { RS, RA, RB } },
2357 { "evmhoumiaaw",VX(4, 1292), VX_MASK, PPCSPE, { RS, RA, RB } },
2358 { "evmhessfaaw",VX(4, 1283), VX_MASK, PPCSPE, { RS, RA, RB } },
2359 { "evmhessiaaw",VX(4, 1281), VX_MASK, PPCSPE, { RS, RA, RB } },
2360 { "evmhesmfaaw",VX(4, 1291), VX_MASK, PPCSPE, { RS, RA, RB } },
2361 { "evmhesmiaaw",VX(4, 1289), VX_MASK, PPCSPE, { RS, RA, RB } },
2362 { "evmheusiaaw",VX(4, 1280), VX_MASK, PPCSPE, { RS, RA, RB } },
2363 { "evmheumiaaw",VX(4, 1288), VX_MASK, PPCSPE, { RS, RA, RB } },
2364
2365 { "evmhossfanw",VX(4, 1415), VX_MASK, PPCSPE, { RS, RA, RB } },
2366 { "evmhossianw",VX(4, 1413), VX_MASK, PPCSPE, { RS, RA, RB } },
2367 { "evmhosmfanw",VX(4, 1423), VX_MASK, PPCSPE, { RS, RA, RB } },
2368 { "evmhosmianw",VX(4, 1421), VX_MASK, PPCSPE, { RS, RA, RB } },
2369 { "evmhousianw",VX(4, 1412), VX_MASK, PPCSPE, { RS, RA, RB } },
2370 { "evmhoumianw",VX(4, 1420), VX_MASK, PPCSPE, { RS, RA, RB } },
2371 { "evmhessfanw",VX(4, 1411), VX_MASK, PPCSPE, { RS, RA, RB } },
2372 { "evmhessianw",VX(4, 1409), VX_MASK, PPCSPE, { RS, RA, RB } },
2373 { "evmhesmfanw",VX(4, 1419), VX_MASK, PPCSPE, { RS, RA, RB } },
2374 { "evmhesmianw",VX(4, 1417), VX_MASK, PPCSPE, { RS, RA, RB } },
2375 { "evmheusianw",VX(4, 1408), VX_MASK, PPCSPE, { RS, RA, RB } },
2376 { "evmheumianw",VX(4, 1416), VX_MASK, PPCSPE, { RS, RA, RB } },
2377
2378 { "evmhogsmfaa",VX(4, 1327), VX_MASK, PPCSPE, { RS, RA, RB } },
2379 { "evmhogsmiaa",VX(4, 1325), VX_MASK, PPCSPE, { RS, RA, RB } },
2380 { "evmhogumiaa",VX(4, 1324), VX_MASK, PPCSPE, { RS, RA, RB } },
2381 { "evmhegsmfaa",VX(4, 1323), VX_MASK, PPCSPE, { RS, RA, RB } },
2382 { "evmhegsmiaa",VX(4, 1321), VX_MASK, PPCSPE, { RS, RA, RB } },
2383 { "evmhegumiaa",VX(4, 1320), VX_MASK, PPCSPE, { RS, RA, RB } },
2384
2385 { "evmhogsmfan",VX(4, 1455), VX_MASK, PPCSPE, { RS, RA, RB } },
2386 { "evmhogsmian",VX(4, 1453), VX_MASK, PPCSPE, { RS, RA, RB } },
2387 { "evmhogumian",VX(4, 1452), VX_MASK, PPCSPE, { RS, RA, RB } },
2388 { "evmhegsmfan",VX(4, 1451), VX_MASK, PPCSPE, { RS, RA, RB } },
2389 { "evmhegsmian",VX(4, 1449), VX_MASK, PPCSPE, { RS, RA, RB } },
2390 { "evmhegumian",VX(4, 1448), VX_MASK, PPCSPE, { RS, RA, RB } },
2391
2392 { "evmwhssf", VX(4, 1095), VX_MASK, PPCSPE, { RS, RA, RB } },
2393 { "evmwhssfa", VX(4, 1127), VX_MASK, PPCSPE, { RS, RA, RB } },
2394 { "evmwhsmf", VX(4, 1103), VX_MASK, PPCSPE, { RS, RA, RB } },
2395 { "evmwhsmfa", VX(4, 1135), VX_MASK, PPCSPE, { RS, RA, RB } },
2396 { "evmwhsmi", VX(4, 1101), VX_MASK, PPCSPE, { RS, RA, RB } },
2397 { "evmwhsmia", VX(4, 1133), VX_MASK, PPCSPE, { RS, RA, RB } },
2398 { "evmwhumi", VX(4, 1100), VX_MASK, PPCSPE, { RS, RA, RB } },
2399 { "evmwhumia", VX(4, 1132), VX_MASK, PPCSPE, { RS, RA, RB } },
2400
2401 { "evmwlumi", VX(4, 1096), VX_MASK, PPCSPE, { RS, RA, RB } },
2402 { "evmwlumia", VX(4, 1128), VX_MASK, PPCSPE, { RS, RA, RB } },
2403
2404 { "evmwlssiaaw",VX(4, 1345), VX_MASK, PPCSPE, { RS, RA, RB } },
2405 { "evmwlsmiaaw",VX(4, 1353), VX_MASK, PPCSPE, { RS, RA, RB } },
2406 { "evmwlusiaaw",VX(4, 1344), VX_MASK, PPCSPE, { RS, RA, RB } },
2407 { "evmwlumiaaw",VX(4, 1352), VX_MASK, PPCSPE, { RS, RA, RB } },
2408
2409 { "evmwlssianw",VX(4, 1473), VX_MASK, PPCSPE, { RS, RA, RB } },
2410 { "evmwlsmianw",VX(4, 1481), VX_MASK, PPCSPE, { RS, RA, RB } },
2411 { "evmwlusianw",VX(4, 1472), VX_MASK, PPCSPE, { RS, RA, RB } },
2412 { "evmwlumianw",VX(4, 1480), VX_MASK, PPCSPE, { RS, RA, RB } },
2413
2414 { "evmwssf", VX(4, 1107), VX_MASK, PPCSPE, { RS, RA, RB } },
2415 { "evmwssfa", VX(4, 1139), VX_MASK, PPCSPE, { RS, RA, RB } },
2416 { "evmwsmf", VX(4, 1115), VX_MASK, PPCSPE, { RS, RA, RB } },
2417 { "evmwsmfa", VX(4, 1147), VX_MASK, PPCSPE, { RS, RA, RB } },
2418 { "evmwsmi", VX(4, 1113), VX_MASK, PPCSPE, { RS, RA, RB } },
2419 { "evmwsmia", VX(4, 1145), VX_MASK, PPCSPE, { RS, RA, RB } },
2420 { "evmwumi", VX(4, 1112), VX_MASK, PPCSPE, { RS, RA, RB } },
2421 { "evmwumia", VX(4, 1144), VX_MASK, PPCSPE, { RS, RA, RB } },
2422
2423 { "evmwssfaa", VX(4, 1363), VX_MASK, PPCSPE, { RS, RA, RB } },
2424 { "evmwsmfaa", VX(4, 1371), VX_MASK, PPCSPE, { RS, RA, RB } },
2425 { "evmwsmiaa", VX(4, 1369), VX_MASK, PPCSPE, { RS, RA, RB } },
2426 { "evmwumiaa", VX(4, 1368), VX_MASK, PPCSPE, { RS, RA, RB } },
2427
2428 { "evmwssfan", VX(4, 1491), VX_MASK, PPCSPE, { RS, RA, RB } },
2429 { "evmwsmfan", VX(4, 1499), VX_MASK, PPCSPE, { RS, RA, RB } },
2430 { "evmwsmian", VX(4, 1497), VX_MASK, PPCSPE, { RS, RA, RB } },
2431 { "evmwumian", VX(4, 1496), VX_MASK, PPCSPE, { RS, RA, RB } },
2432
2433 { "evaddssiaaw",VX(4, 1217), VX_MASK, PPCSPE, { RS, RA } },
2434 { "evaddsmiaaw",VX(4, 1225), VX_MASK, PPCSPE, { RS, RA } },
2435 { "evaddusiaaw",VX(4, 1216), VX_MASK, PPCSPE, { RS, RA } },
2436 { "evaddumiaaw",VX(4, 1224), VX_MASK, PPCSPE, { RS, RA } },
2437
2438 { "evsubfssiaaw",VX(4, 1219), VX_MASK, PPCSPE, { RS, RA } },
2439 { "evsubfsmiaaw",VX(4, 1227), VX_MASK, PPCSPE, { RS, RA } },
2440 { "evsubfusiaaw",VX(4, 1218), VX_MASK, PPCSPE, { RS, RA } },
2441 { "evsubfumiaaw",VX(4, 1226), VX_MASK, PPCSPE, { RS, RA } },
2442
2443 { "evmra", VX(4, 1220), VX_MASK, PPCSPE, { RS, RA } },
2444
2445 { "evdivws", VX(4, 1222), VX_MASK, PPCSPE, { RS, RA, RB } },
2446 { "evdivwu", VX(4, 1223), VX_MASK, PPCSPE, { RS, RA, RB } },
2447
2448 { "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } },
2449 { "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
2450
2451 { "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } },
2452 { "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
2453
2454 { "dozi", OP(9), OP_MASK, M601, { RT, RA, SI } },
2455
2456 { "bce", B(9,0,0), B_MASK, BOOKE64, { BO, BI, BD } },
2457 { "bcel", B(9,0,1), B_MASK, BOOKE64, { BO, BI, BD } },
2458 { "bcea", B(9,1,0), B_MASK, BOOKE64, { BO, BI, BDA } },
2459 { "bcela", B(9,1,1), B_MASK, BOOKE64, { BO, BI, BDA } },
2460
2461 { "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } },
2462 { "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } },
2463 { "cmpli", OP(10), OP_MASK, PPC, { BF, L, RA, UI } },
2464 { "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
2465
2466 { "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } },
2467 { "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } },
2468 { "cmpi", OP(11), OP_MASK, PPC, { BF, L, RA, SI } },
2469 { "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
2470
2471 { "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } },
2472 { "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI } },
2473 { "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } },
2474
2475 { "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } },
2476 { "ai.", OP(13), OP_MASK, PWRCOM, { RT, RA, SI } },
2477 { "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } },
2478
2479 { "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } },
2480 { "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
2481 { "addi", OP(14), OP_MASK, PPCCOM, { RT, RA0, SI } },
2482 { "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA0 } },
2483 { "subi", OP(14), OP_MASK, PPCCOM, { RT, RA0, NSI } },
2484 { "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA0 } },
2485
2486 { "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } },
2487 { "liu", OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT } },
2488 { "addis", OP(15), OP_MASK, PPCCOM, { RT,RA0,SISIGNOPT } },
2489 { "cau", OP(15), OP_MASK, PWRCOM, { RT,RA0,SISIGNOPT } },
2490 { "subis", OP(15), OP_MASK, PPCCOM, { RT, RA0, NSI } },
2491
2492 { "bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
2493 { "bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
2494 { "bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BD } },
2495 { "bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, { BD } },
2496 { "bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
2497 { "bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
2498 { "bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BD } },
2499 { "bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, { BD } },
2500 { "bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
2501 { "bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
2502 { "bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDA } },
2503 { "bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, { BDA } },
2504 { "bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
2505 { "bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
2506 { "bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDA } },
2507 { "bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, { BDA } },
2508 { "bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
2509 { "bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
2510 { "bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, { BD } },
2511 { "bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
2512 { "bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
2513 { "bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, { BD } },
2514 { "bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
2515 { "bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
2516 { "bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, { BDA } },
2517 { "bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
2518 { "bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
2519 { "bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, { BDA } },
2520 { "blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2521 { "blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2522 { "blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2523 { "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2524 { "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2525 { "bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2526 { "blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2527 { "blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2528 { "blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2529 { "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2530 { "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2531 { "bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2532 { "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2533 { "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2534 { "bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2535 { "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2536 { "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2537 { "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2538 { "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2539 { "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2540 { "bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2541 { "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2542 { "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2543 { "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2544 { "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2545 { "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2546 { "beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
2547 { "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2548 { "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2549 { "beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
2550 { "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2551 { "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2552 { "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2553 { "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2554 { "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2555 { "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2556 { "bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2557 { "bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2558 { "bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
2559 { "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2560 { "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2561 { "bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
2562 { "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2563 { "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2564 { "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2565 { "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2566 { "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2567 { "bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2568 { "bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2569 { "bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2570 { "bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
2571 { "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2572 { "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2573 { "bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
2574 { "buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2575 { "buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2576 { "buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2577 { "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2578 { "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2579 { "bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2580 { "bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2581 { "bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2582 { "bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2583 { "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2584 { "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2585 { "bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2586 { "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2587 { "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2588 { "bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2589 { "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2590 { "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2591 { "bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2592 { "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2593 { "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2594 { "bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2595 { "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2596 { "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2597 { "bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2598 { "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2599 { "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2600 { "bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2601 { "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2602 { "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2603 { "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2604 { "ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2605 { "ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2606 { "ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2607 { "blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2608 { "blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2609 { "blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2610 { "blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2611 { "blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2612 { "blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2613 { "blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2614 { "blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2615 { "blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2616 { "bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2617 { "bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2618 { "bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2619 { "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2620 { "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2621 { "bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2622 { "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2623 { "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2624 { "bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2625 { "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2626 { "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2627 { "bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2628 { "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2629 { "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2630 { "bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
2631 { "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2632 { "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2633 { "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
2634 { "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2635 { "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2636 { "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2637 { "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2638 { "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2639 { "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2640 { "bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2641 { "bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2642 { "bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
2643 { "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2644 { "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2645 { "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
2646 { "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2647 { "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2648 { "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2649 { "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2650 { "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2651 { "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2652 { "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2653 { "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2654 { "bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
2655 { "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2656 { "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2657 { "bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
2658 { "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2659 { "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2660 { "bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2661 { "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2662 { "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2663 { "bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2664 { "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2665 { "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2666 { "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2667 { "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2668 { "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2669 { "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2670 { "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2671 { "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2672 { "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2673 { "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2674 { "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2675 { "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2676 { "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2677 { "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2678 { "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2679 { "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2680 { "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2681 { "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2682 { "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2683 { "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2684 { "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2685 { "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2686 { "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2687 { "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2688 { "bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
2689 { "bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
2690 { "bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
2691 { "bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
2692 { "btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
2693 { "btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
2694 { "btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
2695 { "bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
2696 { "bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2697 { "bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2698 { "bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
2699 { "bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
2700 { "btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2701 { "btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2702 { "btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
2703 { "bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
2704 { "bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
2705 { "bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
2706 { "bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
2707 { "bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
2708 { "bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
2709 { "bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
2710 { "bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
2711 { "bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
2712 { "bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2713 { "bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2714 { "bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
2715 { "bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
2716 { "bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2717 { "bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2718 { "bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
2719 { "bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
2720 { "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2721 { "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2722 { "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2723 { "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2724 { "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2725 { "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2726 { "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2727 { "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2728 { "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2729 { "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2730 { "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2731 { "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2732 { "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2733 { "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2734 { "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2735 { "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2736 { "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2737 { "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2738 { "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2739 { "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2740 { "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2741 { "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2742 { "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2743 { "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2744 { "bc-", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDM } },
2745 { "bc+", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDP } },
2746 { "bc", B(16,0,0), B_MASK, COM, { BO, BI, BD } },
2747 { "bcl-", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDM } },
2748 { "bcl+", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDP } },
2749 { "bcl", B(16,0,1), B_MASK, COM, { BO, BI, BD } },
2750 { "bca-", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDMA } },
2751 { "bca+", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDPA } },
2752 { "bca", B(16,1,0), B_MASK, COM, { BO, BI, BDA } },
2753 { "bcla-", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDMA } },
2754 { "bcla+", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDPA } },
2755 { "bcla", B(16,1,1), B_MASK, COM, { BO, BI, BDA } },
2756
2757 { "sc", SC(17,1,0), SC_MASK, PPC, { LEV } },
2758 { "svc", SC(17,0,0), SC_MASK, POWER, { SVC_LEV, FL1, FL2 } },
2759 { "svcl", SC(17,0,1), SC_MASK, POWER, { SVC_LEV, FL1, FL2 } },
2760 { "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } },
2761 { "svcla", SC(17,1,1), SC_MASK, POWER, { SV } },
2762
2763 { "b", B(18,0,0), B_MASK, COM, { LI } },
2764 { "bl", B(18,0,1), B_MASK, COM, { LI } },
2765 { "ba", B(18,1,0), B_MASK, COM, { LIA } },
2766 { "bla", B(18,1,1), B_MASK, COM, { LIA } },
2767
2768 { "mcrf", XL(19,0), XLBB_MASK|(3 << 21)|(3 << 16), COM, { BF, BFA } },
2769
2770 { "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2771 { "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, { 0 } },
2772 { "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2773 { "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, { 0 } },
2774 { "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2775 { "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2776 { "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2777 { "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2778 { "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2779 { "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2780 { "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2781 { "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2782 { "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2783 { "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2784 { "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2785 { "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2786 { "bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2787 { "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2788 { "bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2789 { "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2790 { "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2791 { "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2792 { "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2793 { "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2794 { "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2795 { "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2796 { "bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2797 { "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2798 { "bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2799 { "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2800 { "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2801 { "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2802 { "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2803 { "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2804 { "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2805 { "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2806 { "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2807 { "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2808 { "bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2809 { "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2810 { "bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2811 { "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2812 { "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2813 { "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2814 { "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2815 { "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2816 { "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2817 { "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2818 { "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2819 { "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2820 { "beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2821 { "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2822 { "beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2823 { "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2824 { "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2825 { "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2826 { "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2827 { "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2828 { "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2829 { "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2830 { "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2831 { "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2832 { "bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2833 { "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2834 { "bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2835 { "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2836 { "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2837 { "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2838 { "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2839 { "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2840 { "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2841 { "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2842 { "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2843 { "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2844 { "bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2845 { "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2846 { "bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2847 { "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2848 { "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2849 { "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2850 { "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2851 { "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2852 { "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2853 { "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2854 { "bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2855 { "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2856 { "bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2857 { "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2858 { "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2859 { "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2860 { "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2861 { "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2862 { "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2863 { "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2864 { "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2865 { "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2866 { "bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2867 { "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2868 { "bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2869 { "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2870 { "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2871 { "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2872 { "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2873 { "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2874 { "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2875 { "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2876 { "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2877 { "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2878 { "blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2879 { "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2880 { "blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2881 { "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2882 { "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2883 { "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2884 { "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2885 { "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2886 { "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2887 { "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2888 { "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2889 { "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2890 { "bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2891 { "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2892 { "bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2893 { "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2894 { "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2895 { "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2896 { "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2897 { "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2898 { "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2899 { "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2900 { "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2901 { "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2902 { "bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2903 { "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2904 { "bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2905 { "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2906 { "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2907 { "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2908 { "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2909 { "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2910 { "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2911 { "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2912 { "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2913 { "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2914 { "bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2915 { "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2916 { "bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2917 { "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2918 { "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2919 { "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2920 { "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2921 { "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2922 { "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2923 { "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2924 { "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2925 { "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2926 { "bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2927 { "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2928 { "bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2929 { "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2930 { "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2931 { "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2932 { "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2933 { "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2934 { "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2935 { "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2936 { "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI } },
2937 { "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2938 { "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI } },
2939 { "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, { BI } },
2940 { "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2941 { "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2942 { "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI } },
2943 { "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2944 { "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI } },
2945 { "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, { BI } },
2946 { "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2947 { "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2948 { "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI } },
2949 { "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2950 { "bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, { BI } },
2951 { "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, { BI } },
2952 { "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2953 { "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2954 { "bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, { BI } },
2955 { "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2956 { "bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, { BI } },
2957 { "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, { BI } },
2958 { "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2959 { "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2960 { "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2961 { "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2962 { "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2963 { "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2964 { "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2965 { "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2966 { "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2967 { "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2968 { "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2969 { "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2970 { "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2971 { "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2972 { "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2973 { "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2974 { "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2975 { "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2976 { "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2977 { "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2978 { "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2979 { "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2980 { "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2981 { "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2982 { "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2983 { "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
2984 { "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2985 { "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
2986 { "bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, { BO, BI, BH } },
2987 { "bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, { BO, BI, BH } },
2988 { "bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, { BO, BI } },
2989 { "bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, { BO, BI } },
2990 { "bclre", XLLK(19,17,0), XLBB_MASK, BOOKE64, { BO, BI } },
2991 { "bclrel", XLLK(19,17,1), XLBB_MASK, BOOKE64, { BO, BI } },
2992
2993 { "rfid", XL(19,18), 0xffffffff, PPC64, { 0 } },
2994
2995 { "crnot", XL(19,33), XL_MASK, PPCCOM, { BT, BA, BBA } },
2996 { "crnor", XL(19,33), XL_MASK, COM, { BT, BA, BB } },
2997 { "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } },
2998
2999 { "rfi", XL(19,50), 0xffffffff, COM, { 0 } },
3000 { "rfci", XL(19,51), 0xffffffff, PPC403 | BOOKE, { 0 } },
3001
3002 { "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } },
3003
3004 { "crandc", XL(19,129), XL_MASK, COM, { BT, BA, BB } },
3005
3006 { "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } },
3007 { "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } },
3008
3009 { "crclr", XL(19,193), XL_MASK, PPCCOM, { BT, BAT, BBA } },
3010 { "crxor", XL(19,193), XL_MASK, COM, { BT, BA, BB } },
3011
3012 { "crnand", XL(19,225), XL_MASK, COM, { BT, BA, BB } },
3013
3014 { "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB } },
3015
3016 { "hrfid", XL(19,274), 0xffffffff, POWER5, { 0 } },
3017
3018 { "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } },
3019 { "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } },
3020
3021 { "crorc", XL(19,417), XL_MASK, COM, { BT, BA, BB } },
3022
3023 { "crmove", XL(19,449), XL_MASK, PPCCOM, { BT, BA, BBA } },
3024 { "cror", XL(19,449), XL_MASK, COM, { BT, BA, BB } },
3025
3026 { "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } },
3027 { "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } },
3028 { "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3029 { "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3030 { "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3031 { "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3032 { "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3033 { "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3034 { "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3035 { "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3036 { "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3037 { "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3038 { "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3039 { "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3040 { "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3041 { "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3042 { "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3043 { "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3044 { "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3045 { "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3046 { "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3047 { "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3048 { "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3049 { "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3050 { "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3051 { "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3052 { "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3053 { "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3054 { "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3055 { "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3056 { "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3057 { "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3058 { "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3059 { "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3060 { "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3061 { "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3062 { "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3063 { "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3064 { "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3065 { "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3066 { "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3067 { "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3068 { "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3069 { "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3070 { "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3071 { "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3072 { "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3073 { "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3074 { "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3075 { "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3076 { "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3077 { "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3078 { "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3079 { "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3080 { "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3081 { "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3082 { "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3083 { "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3084 { "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3085 { "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3086 { "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3087 { "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3088 { "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3089 { "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3090 { "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3091 { "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3092 { "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3093 { "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3094 { "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3095 { "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3096 { "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3097 { "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3098 { "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3099 { "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3100 { "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3101 { "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3102 { "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3103 { "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3104 { "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3105 { "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3106 { "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3107 { "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3108 { "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3109 { "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3110 { "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3111 { "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3112 { "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3113 { "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3114 { "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3115 { "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3116 { "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3117 { "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3118 { "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3119 { "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3120 { "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3121 { "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3122 { "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3123 { "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3124 { "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3125 { "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3126 { "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3127 { "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3128 { "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3129 { "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3130 { "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3131 { "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3132 { "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3133 { "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3134 { "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3135 { "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3136 { "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3137 { "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3138 { "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3139 { "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3140 { "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3141 { "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3142 { "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3143 { "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3144 { "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3145 { "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3146 { "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3147 { "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3148 { "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } },
3149 { "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3150 { "btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3151 { "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3152 { "btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } },
3153 { "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } },
3154 { "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3155 { "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3156 { "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3157 { "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } },
3158 { "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } },
3159 { "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3160 { "bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3161 { "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3162 { "bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } },
3163 { "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } },
3164 { "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3165 { "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3166 { "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3167 { "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } },
3168 { "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
3169 { "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
3170 { "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
3171 { "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
3172 { "bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, { BO, BI, BH } },
3173 { "bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, { BO, BI, BH } },
3174 { "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI } },
3175 { "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } },
3176 { "bcctre", XLLK(19,529,0), XLYBB_MASK, BOOKE64, { BO, BI } },
3177 { "bcctrel", XLLK(19,529,1), XLYBB_MASK, BOOKE64, { BO, BI } },
3178
3179 { "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3180 { "rlimi", M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3181
3182 { "rlwimi.", M(20,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3183 { "rlimi.", M(20,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3184
3185 { "rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, { RA, RS, SH } },
3186 { "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } },
3187 { "rlwinm", M(21,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3188 { "rlinm", M(21,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3189 { "rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, { RA,RS,SH } },
3190 { "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } },
3191 { "rlwinm.", M(21,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3192 { "rlinm.", M(21,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3193
3194 { "rlmi", M(22,0), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3195 { "rlmi.", M(22,1), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3196
3197 { "be", B(22,0,0), B_MASK, BOOKE64, { LI } },
3198 { "bel", B(22,0,1), B_MASK, BOOKE64, { LI } },
3199 { "bea", B(22,1,0), B_MASK, BOOKE64, { LIA } },
3200 { "bela", B(22,1,1), B_MASK, BOOKE64, { LIA } },
3201
3202 { "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3203 { "rlwnm", M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3204 { "rlnm", M(23,0), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3205 { "rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3206 { "rlwnm.", M(23,1), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3207 { "rlnm.", M(23,1), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3208
3209 { "nop", OP(24), 0xffffffff, PPCCOM, { 0 } },
3210 { "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI } },
3211 { "oril", OP(24), OP_MASK, PWRCOM, { RA, RS, UI } },
3212
3213 { "oris", OP(25), OP_MASK, PPCCOM, { RA, RS, UI } },
3214 { "oriu", OP(25), OP_MASK, PWRCOM, { RA, RS, UI } },
3215
3216 { "xori", OP(26), OP_MASK, PPCCOM, { RA, RS, UI } },
3217 { "xoril", OP(26), OP_MASK, PWRCOM, { RA, RS, UI } },
3218
3219 { "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI } },
3220 { "xoriu", OP(27), OP_MASK, PWRCOM, { RA, RS, UI } },
3221
3222 { "andi.", OP(28), OP_MASK, PPCCOM, { RA, RS, UI } },
3223 { "andil.", OP(28), OP_MASK, PWRCOM, { RA, RS, UI } },
3224
3225 { "andis.", OP(29), OP_MASK, PPCCOM, { RA, RS, UI } },
3226 { "andiu.", OP(29), OP_MASK, PWRCOM, { RA, RS, UI } },
3227
3228 { "rotldi", MD(30,0,0), MDMB_MASK, PPC64, { RA, RS, SH6 } },
3229 { "clrldi", MD(30,0,0), MDSH_MASK, PPC64, { RA, RS, MB6 } },
3230 { "rldicl", MD(30,0,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3231 { "rotldi.", MD(30,0,1), MDMB_MASK, PPC64, { RA, RS, SH6 } },
3232 { "clrldi.", MD(30,0,1), MDSH_MASK, PPC64, { RA, RS, MB6 } },
3233 { "rldicl.", MD(30,0,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3234
3235 { "rldicr", MD(30,1,0), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
3236 { "rldicr.", MD(30,1,1), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
3237
3238 { "rldic", MD(30,2,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3239 { "rldic.", MD(30,2,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3240
3241 { "rldimi", MD(30,3,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3242 { "rldimi.", MD(30,3,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3243
3244 { "rotld", MDS(30,8,0), MDSMB_MASK, PPC64, { RA, RS, RB } },
3245 { "rldcl", MDS(30,8,0), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3246 { "rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, { RA, RS, RB } },
3247 { "rldcl.", MDS(30,8,1), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3248
3249 { "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3250 { "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3251
3252 { "cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3253 { "cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
3254 { "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } },
3255 { "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
3256
3257 { "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } },
3258 { "tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, { RA, RB } },
3259 { "twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, { RA, RB } },
3260 { "tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, { RA, RB } },
3261 { "tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, { RA, RB } },
3262 { "teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, { RA, RB } },
3263 { "twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, { RA, RB } },
3264 { "tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, { RA, RB } },
3265 { "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, { RA, RB } },
3266 { "tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, { RA, RB } },
3267 { "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } },
3268 { "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } },
3269 { "twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, { RA, RB } },
3270 { "tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, { RA, RB } },
3271 { "twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, { RA, RB } },
3272 { "tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, { RA, RB } },
3273 { "twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, { RA, RB } },
3274 { "tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, { RA, RB } },
3275 { "twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, { RA, RB } },
3276 { "tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, { RA, RB } },
3277 { "twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, { RA, RB } },
3278 { "tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, { RA, RB } },
3279 { "twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, { RA, RB } },
3280 { "tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, { RA, RB } },
3281 { "twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, { RA, RB } },
3282 { "tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, { RA, RB } },
3283 { "twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, { RA, RB } },
3284 { "tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, { RA, RB } },
3285 { "trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, { 0 } },
3286 { "tw", X(31,4), X_MASK, PPCCOM, { TO, RA, RB } },
3287 { "t", X(31,4), X_MASK, PWRCOM, { TO, RA, RB } },
3288
3289 { "subfc", XO(31,8,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3290 { "sf", XO(31,8,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3291 { "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } },
3292 { "subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3293 { "sf.", XO(31,8,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3294 { "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA } },
3295 { "subfco", XO(31,8,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3296 { "sfo", XO(31,8,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3297 { "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } },
3298 { "subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3299 { "sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3300 { "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } },
3301
3302 { "mulhdu", XO(31,9,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3303 { "mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3304
3305 { "addc", XO(31,10,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3306 { "a", XO(31,10,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3307 { "addc.", XO(31,10,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3308 { "a.", XO(31,10,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3309 { "addco", XO(31,10,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3310 { "ao", XO(31,10,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3311 { "addco.", XO(31,10,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3312 { "ao.", XO(31,10,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3313
3314 { "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } },
3315 { "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } },
3316
3317 { "isellt", X(31,15), X_MASK, PPCISEL, { RT, RA, RB } },
3318 { "iselgt", X(31,47), X_MASK, PPCISEL, { RT, RA, RB } },
3319 { "iseleq", X(31,79), X_MASK, PPCISEL, { RT, RA, RB } },
3320 { "isel", XISEL(31,15), XISEL_MASK, PPCISEL, { RT, RA, RB, CRB } },
3321
3322 { "mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, { RT, FXM } },
3323 { "mfcr", X(31,19), XRARB_MASK, NOPOWER4, { RT } },
3324 { "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } },
3325
3326 { "lwarx", X(31,20), X_MASK, PPC, { RT, RA0, RB } },
3327
3328 { "ldx", X(31,21), X_MASK, PPC64, { RT, RA0, RB } },
3329
3330 { "icbt", X(31,22), X_MASK, BOOKE, { CT, RA, RB } },
3331 { "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } },
3332
3333 { "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA0, RB } },
3334 { "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } },
3335
3336 { "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } },
3337 { "sl", XRC(31,24,0), X_MASK, PWRCOM, { RA, RS, RB } },
3338 { "slw.", XRC(31,24,1), X_MASK, PPCCOM, { RA, RS, RB } },
3339 { "sl.", XRC(31,24,1), X_MASK, PWRCOM, { RA, RS, RB } },
3340
3341 { "cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, { RA, RS } },
3342 { "cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, { RA, RS } },
3343 { "cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, { RA, RS } },
3344 { "cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, { RA, RS } },
3345
3346 { "sld", XRC(31,27,0), X_MASK, PPC64, { RA, RS, RB } },
3347 { "sld.", XRC(31,27,1), X_MASK, PPC64, { RA, RS, RB } },
3348
3349 { "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB } },
3350 { "and.", XRC(31,28,1), X_MASK, COM, { RA, RS, RB } },
3351
3352 { "maskg", XRC(31,29,0), X_MASK, M601, { RA, RS, RB } },
3353 { "maskg.", XRC(31,29,1), X_MASK, M601, { RA, RS, RB } },
3354
3355 { "icbte", X(31,30), X_MASK, BOOKE64, { CT, RA, RB } },
3356
3357 { "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA0, RB } },
3358
3359 { "cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3360 { "cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
3361 { "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } },
3362 { "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
3363
3364 { "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } },
3365 { "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } },
3366 { "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } },
3367 { "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } },
3368 { "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } },
3369 { "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } },
3370 { "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } },
3371 { "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } },
3372
3373 { "ldux", X(31,53), X_MASK, PPC64, { RT, RAL, RB } },
3374
3375 { "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } },
3376
3377 { "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } },
3378 { "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB } },
3379
3380 { "dcbste", X(31,62), XRT_MASK, BOOKE64, { RA, RB } },
3381
3382 { "lwzuxe", X(31,63), X_MASK, BOOKE64, { RT, RAL, RB } },
3383
3384 { "cntlzd", XRC(31,58,0), XRB_MASK, PPC64, { RA, RS } },
3385 { "cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, { RA, RS } },
3386
3387 { "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } },
3388 { "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } },
3389
3390 { "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, { RA, RB } },
3391 { "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, { RA, RB } },
3392 { "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, { RA, RB } },
3393 { "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, { RA, RB } },
3394 { "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, { RA, RB } },
3395 { "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },
3396 { "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, { RA, RB } },
3397 { "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, { RA, RB } },
3398 { "tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, { RA, RB } },
3399 { "tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, { RA, RB } },
3400 { "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, { RA, RB } },
3401 { "tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, { RA, RB } },
3402 { "tdng", XTO(31,68,TONG), XTO_MASK, PPC64, { RA, RB } },
3403 { "tdne", XTO(31,68,TONE), XTO_MASK, PPC64, { RA, RB } },
3404 { "td", X(31,68), X_MASK, PPC64, { TO, RA, RB } },
3405
3406 { "mulhd", XO(31,73,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3407 { "mulhd.", XO(31,73,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3408
3409 { "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } },
3410 { "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } },
3411
3412 { "dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440, { RA, RS, RB } },
3413 { "dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440, { RA, RS, RB } },
3414
3415 { "mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, { SR, RS } },
3416
3417 { "mfmsr", X(31,83), XRARB_MASK, COM, { RT } },
3418
3419 { "ldarx", X(31,84), X_MASK, PPC64, { RT, RA0, RB } },
3420
3421 { "dcbf", X(31,86), XRT_MASK, PPC, { RA, RB } },
3422
3423 { "lbzx", X(31,87), X_MASK, COM, { RT, RA0, RB } },
3424
3425 { "dcbfe", X(31,94), XRT_MASK, BOOKE64, { RA, RB } },
3426
3427 { "lbzxe", X(31,95), X_MASK, BOOKE64, { RT, RA0, RB } },
3428
3429 { "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } },
3430 { "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA } },
3431 { "nego", XO(31,104,1,0), XORB_MASK, COM, { RT, RA } },
3432 { "nego.", XO(31,104,1,1), XORB_MASK, COM, { RT, RA } },
3433
3434 { "mul", XO(31,107,0,0), XO_MASK, M601, { RT, RA, RB } },
3435 { "mul.", XO(31,107,0,1), XO_MASK, M601, { RT, RA, RB } },
3436 { "mulo", XO(31,107,1,0), XO_MASK, M601, { RT, RA, RB } },
3437 { "mulo.", XO(31,107,1,1), XO_MASK, M601, { RT, RA, RB } },
3438
3439 { "mtsrdin", X(31,114), XRA_MASK, PPC64, { RS, RB } },
3440
3441 { "clf", X(31,118), XTO_MASK, POWER, { RA, RB } },
3442
3443 { "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } },
3444
3445 { "popcntb", X(31,122), XRB_MASK, POWER5, { RA, RS } },
3446
3447 { "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } },
3448 { "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } },
3449 { "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } },
3450 { "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } },
3451
3452 { "lwarxe", X(31,126), X_MASK, BOOKE64, { RT, RA0, RB } },
3453
3454 { "lbzuxe", X(31,127), X_MASK, BOOKE64, { RT, RAL, RB } },
3455
3456 { "wrtee", X(31,131), XRARB_MASK, PPC403 | BOOKE, { RS } },
3457
3458 { "dcbtstls",X(31,134), X_MASK, PPCCHLK, { CT, RA, RB }},
3459
3460 { "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3461 { "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3462 { "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3463 { "sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3464 { "subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3465 { "sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3466 { "subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3467 { "sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3468
3469 { "adde", XO(31,138,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3470 { "ae", XO(31,138,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3471 { "adde.", XO(31,138,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3472 { "ae.", XO(31,138,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3473 { "addeo", XO(31,138,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3474 { "aeo", XO(31,138,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3475 { "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3476 { "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3477
3478 { "dcbtstlse",X(31,142),X_MASK, PPCCHLK64, { CT, RA, RB }},
3479
3480 { "mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, { FXM, RS } },
3481 { "mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, { RS }},
3482 { "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } },
3483
3484 { "mtmsr", X(31,146), XRARB_MASK, COM, { RS } },
3485
3486 { "stdx", X(31,149), X_MASK, PPC64, { RS, RA0, RB } },
3487
3488 { "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA0, RB } },
3489
3490 { "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA0, RB } },
3491 { "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } },
3492
3493 { "stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, { RS, RA0, RB } },
3494
3495 { "stwxe", X(31,159), X_MASK, BOOKE64, { RS, RA0, RB } },
3496
3497 { "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } },
3498 { "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } },
3499
3500 { "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } },
3501 { "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } },
3502
3503 { "wrteei", X(31,163), XE_MASK, PPC403 | BOOKE, { E } },
3504
3505 { "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }},
3506 { "dcbtlse", X(31,174), X_MASK, PPCCHLK64, { CT, RA, RB }},
3507
3508 { "mtmsrd", X(31,178), XRLARB_MASK, PPC64, { RS, MTMSRD_L } },
3509
3510 { "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } },
3511
3512 { "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } },
3513 { "stux", X(31,183), X_MASK, PWRCOM, { RS, RA0, RB } },
3514
3515 { "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } },
3516 { "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } },
3517
3518 { "stwuxe", X(31,191), X_MASK, BOOKE64, { RS, RAS, RB } },
3519
3520 { "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3521 { "sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3522 { "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3523 { "sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3524 { "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3525 { "sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3526 { "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3527 { "sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3528
3529 { "addze", XO(31,202,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3530 { "aze", XO(31,202,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3531 { "addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3532 { "aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3533 { "addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3534 { "azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3535 { "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3536 { "azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3537
3538 { "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } },
3539
3540 { "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA0, RB } },
3541
3542 { "stbx", X(31,215), X_MASK, COM, { RS, RA0, RB } },
3543
3544 { "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB } },
3545 { "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB } },
3546
3547 { "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } },
3548 { "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } },
3549
3550 { "stbxe", X(31,223), X_MASK, BOOKE64, { RS, RA0, RB } },
3551
3552 { "icblc", X(31,230), X_MASK, PPCCHLK, { CT, RA, RB }},
3553
3554 { "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3555 { "sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3556 { "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3557 { "sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3558 { "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3559 { "sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3560 { "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3561 { "sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3562
3563 { "mulld", XO(31,233,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3564 { "mulld.", XO(31,233,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3565 { "mulldo", XO(31,233,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3566 { "mulldo.", XO(31,233,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3567
3568 { "addme", XO(31,234,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3569 { "ame", XO(31,234,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3570 { "addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3571 { "ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3572 { "addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3573 { "ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3574 { "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3575 { "ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3576
3577 { "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3578 { "muls", XO(31,235,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3579 { "mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3580 { "muls.", XO(31,235,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3581 { "mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3582 { "mulso", XO(31,235,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3583 { "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3584 { "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3585
3586 { "icblce", X(31,238), X_MASK, PPCCHLK64, { CT, RA, RB }},
3587 { "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } },
3588 { "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } },
3589
3590 { "dcbtst", X(31,246), X_MASK, PPC, { CT, RA, RB } },
3591
3592 { "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } },
3593
3594 { "slliq", XRC(31,248,0), X_MASK, M601, { RA, RS, SH } },
3595 { "slliq.", XRC(31,248,1), X_MASK, M601, { RA, RS, SH } },
3596
3597 { "dcbtste", X(31,253), X_MASK, BOOKE64, { CT, RA, RB } },
3598
3599 { "stbuxe", X(31,255), X_MASK, BOOKE64, { RS, RAS, RB } },
3600
3601 { "mfdcrx", X(31,259), X_MASK, BOOKE, { RS, RA } },
3602
3603 { "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } },
3604 { "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } },
3605 { "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } },
3606 { "dozo.", XO(31,264,1,1), XO_MASK, M601, { RT, RA, RB } },
3607
3608 { "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3609 { "cax", XO(31,266,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3610 { "add.", XO(31,266,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3611 { "cax.", XO(31,266,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3612 { "addo", XO(31,266,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3613 { "caxo", XO(31,266,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3614 { "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3615 { "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3616
3617 { "tlbiel", X(31,274), XRTLRA_MASK, POWER4, { RB, L } },
3618
3619 { "mfapidi", X(31,275), X_MASK, BOOKE, { RT, RA } },
3620
3621 { "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } },
3622 { "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } },
3623
3624 { "dcbt", X(31,278), X_MASK, PPC, { CT, RA, RB } },
3625
3626 { "lhzx", X(31,279), X_MASK, COM, { RT, RA0, RB } },
3627
3628 { "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } },
3629 { "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } },
3630
3631 { "dcbte", X(31,286), X_MASK, BOOKE64, { CT, RA, RB } },
3632
3633 { "lhzxe", X(31,287), X_MASK, BOOKE64, { RT, RA0, RB } },
3634
3635 { "tlbie", X(31,306), XRTLRA_MASK, PPC, { RB, L } },
3636 { "tlbi", X(31,306), XRT_MASK, POWER, { RA0, RB } },
3637
3638 { "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } },
3639
3640 { "lhzux", X(31,311), X_MASK, COM, { RT, RAL, RB } },
3641
3642 { "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } },
3643 { "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB } },
3644
3645 { "lhzuxe", X(31,319), X_MASK, BOOKE64, { RT, RAL, RB } },
3646
3647 { "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403, { RT } },
3648 { "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403, { RT } },
3649 { "mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, { RT } },
3650 { "mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, { RT } },
3651 { "mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, { RT } },
3652 { "mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, { RT } },
3653 { "mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, { RT } },
3654 { "mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, { RT } },
3655 { "mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, { RT } },
3656 { "mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, { RT } },
3657 { "mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, { RT } },
3658 { "mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, { RT } },
3659 { "mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, { RT } },
3660 { "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, { RT } },
3661 { "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, { RT } },
3662 { "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, { RT } },
3663 { "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, { RT } },
3664 { "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, { RT } },
3665 { "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, { RT } },
3666 { "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, { RT } },
3667 { "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, { RT } },
3668 { "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, { RT } },
3669 { "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, { RT } },
3670 { "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, { RT } },
3671 { "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, { RT } },
3672 { "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, { RT } },
3673 { "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, { RT } },
3674 { "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, { RT } },
3675 { "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, { RT } },
3676 { "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, { RT } },
3677 { "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, { RT } },
3678 { "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, { RT } },
3679 { "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, { RT } },
3680 { "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, { RT } },
3681 { "mfdcr", X(31,323), X_MASK, PPC403 | BOOKE, { RT, SPR } },
3682
3683 { "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } },
3684 { "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } },
3685 { "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB } },
3686 { "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB } },
3687
3688 { "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }},
3689
3690 { "mfmq", XSPR(31,339,0), XSPR_MASK, M601, { RT } },
3691 { "mfxer", XSPR(31,339,1), XSPR_MASK, COM, { RT } },
3692 { "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT } },
3693 { "mfrtcl", XSPR(31,339,5), XSPR_MASK, COM, { RT } },
3694 { "mfdec", XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT } },
3695 { "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } },
3696 { "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } },
3697 { "mfctr", XSPR(31,339,9), XSPR_MASK, COM, { RT } },
3698 { "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } },
3699 { "mfdsisr", XSPR(31,339,18), XSPR_MASK, COM, { RT } },
3700 { "mfdar", XSPR(31,339,19), XSPR_MASK, COM, { RT } },
3701 { "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } },
3702 { "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } },
3703 { "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } },
3704 { "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } },
3705 { "mfpid", XSPR(31,339,48), XSPR_MASK, BOOKE, { RT } },
3706 { "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } },
3707 { "mfcsrr0", XSPR(31,339,58), XSPR_MASK, BOOKE, { RT } },
3708 { "mfcsrr1", XSPR(31,339,59), XSPR_MASK, BOOKE, { RT } },
3709 { "mfdear", XSPR(31,339,61), XSPR_MASK, BOOKE, { RT } },
3710 { "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } },
3711 { "mfesr", XSPR(31,339,62), XSPR_MASK, BOOKE, { RT } },
3712 { "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } },
3713 { "mfivpr", XSPR(31,339,63), XSPR_MASK, BOOKE, { RT } },
3714 { "mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, { RT } },
3715 { "mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, { RT } },
3716 { "mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, { RT } },
3717 { "mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, { RT } },
3718 { "mficr", XSPR(31,339,148), XSPR_MASK, PPC860, { RT } },
3719 { "mfder", XSPR(31,339,149), XSPR_MASK, PPC860, { RT } },
3720 { "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, { RT } },
3721 { "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, { RT } },
3722 { "mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, { RT } },
3723 { "mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, { RT } },
3724 { "mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, { RT } },
3725 { "mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, { RT } },
3726 { "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, { RT } },
3727 { "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, { RT } },
3728 { "mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, { RT } },
3729 { "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT } },
3730 { "mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, { RT } },
3731 { "mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, { RT } },
3732 { "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR } },
3733 { "mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
3734 { "mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, { RT } },
3735 { "mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
3736 { "mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, { RT } },
3737 { "mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, { RT } },
3738 { "mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, { RT, SPRG } },
3739 { "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } },
3740 { "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } },
3741 { "mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, { RT } },
3742 { "mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, { RT } },
3743 { "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405 | BOOKE, { RT } },
3744 { "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405 | BOOKE, { RT } },
3745 { "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405 | BOOKE, { RT } },
3746 { "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405 | BOOKE, { RT } },
3747 { "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } },
3748 { "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } },
3749 { "mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, { RT } },
3750 { "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } },
3751 { "mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, { RT } },
3752 { "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } },
3753 { "mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, { RT } },
3754 { "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, { RT } },
3755 { "mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, { RT } },
3756 { "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT } },
3757 { "mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, { RT } },
3758 { "mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, { RT } },
3759 { "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } },
3760 { "mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, { RT } },
3761 { "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } },
3762 { "mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, { RT } },
3763 { "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, { RT } },
3764 { "mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, { RT } },
3765 { "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, { RT } },
3766 { "mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, { RT } },
3767 { "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } },
3768 { "mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, { RT } },
3769 { "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } },
3770 { "mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, { RT } },
3771 { "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, { RT } },
3772 { "mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, { RT } },
3773 { "mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, { RT } },
3774 { "mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, { RT } },
3775 { "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, { RT } },
3776 { "mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, { RT } },
3777 { "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, { RT } },
3778 { "mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, { RT } },
3779 { "mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, { RT } },
3780 { "mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, { RT } },
3781 { "mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, { RT } },
3782 { "mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, { RT } },
3783 { "mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, { RT } },
3784 { "mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, { RT } },
3785 { "mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, { RT } },
3786 { "mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, { RT } },
3787 { "mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, { RT } },
3788 { "mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, { RT } },
3789 { "mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, { RT } },
3790 { "mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, { RT } },
3791 { "mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, { RT } },
3792 { "mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, { RT } },
3793 { "mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, { RT } },
3794 { "mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, { RT } },
3795 { "mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, { RT } },
3796 { "mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, { RT } },
3797 { "mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, { RT } },
3798 { "mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, { RT } },
3799 { "mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, { RT } },
3800 { "mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, { RT } },
3801 { "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3802 { "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3803 { "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3804 { "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3805 { "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, { RT } },
3806 { "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, { RT } },
3807 { "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, { RT } },
3808 { "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, { RT } },
3809 { "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, { RT } },
3810 { "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } },
3811 { "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, { RT } },
3812 { "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } },
3813 { "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } },
3814 { "mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, { RT } },
3815 { "mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, { RT } },
3816 { "mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, { RT } },
3817 { "mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, { RT } },
3818 { "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, { RT } },
3819 { "mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, { RT } },
3820 { "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, { RT } },
3821 { "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, { RT } },
3822 { "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, { RT } },
3823 { "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, { RT } },
3824 { "mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, { RT } },
3825 { "mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, { RT } },
3826 { "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, { RT } },
3827 { "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, { RT } },
3828 { "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, { RT } },
3829 { "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, { RT } },
3830 { "mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, { RT } },
3831 { "mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, { RT } },
3832 { "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860, { RT } },
3833 { "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860, { RT } },
3834 { "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, { RT } },
3835 { "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860, { RT } },
3836 { "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860, { RT } },
3837 { "mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, { RT } },
3838 { "mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, { RT } },
3839 { "mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, { RT } },
3840 { "mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, { RT } },
3841 { "mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, { RT } },
3842 { "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT } },
3843 { "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT } },
3844 { "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } },
3845 { "mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, { RT } },
3846 { "mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, { RT } },
3847 { "mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, { RT } },
3848 { "mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, { RT } },
3849 { "mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, { RT } },
3850 { "mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, { RT } },
3851 { "mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, { RT } },
3852 { "mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, { RT } },
3853 { "mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, { RT } },
3854 { "mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, { RT } },
3855 { "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, { RT } },
3856 { "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, { RT } },
3857 { "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, { RT } },
3858 { "mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, { RT } },
3859 { "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, { RT } },
3860 { "mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, { RT } },
3861 { "mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, { RT } },
3862 { "mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, { RT } },
3863 { "mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, { RT } },
3864 { "mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, { RT } },
3865 { "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, { RT } },
3866 { "mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, { RT } },
3867 { "mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, { RT } },
3868 { "mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, { RT } },
3869 { "mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, { RT } },
3870 { "mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, { RT } },
3871 { "mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, { RT } },
3872 { "mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, { RT } },
3873 { "mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, { RT } },
3874 { "mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, { RT } },
3875 { "mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, { RT } },
3876 { "mfspr", X(31,339), X_MASK, COM, { RT, SPR } },
3877
3878 { "lwax", X(31,341), X_MASK, PPC64, { RT, RA0, RB } },
3879
3880 { "dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3881 { "dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3882
3883 { "lhax", X(31,343), X_MASK, COM, { RT, RA0, RB } },
3884
3885 { "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA0, RB } },
3886
3887 { "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3888 { "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3889
3890 { "dccci", X(31,454), XRT_MASK, PPC403|PPC440, { RA, RB } },
3891
3892 { "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } },
3893 { "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA } },
3894 { "abso", XO(31,360,1,0), XORB_MASK, M601, { RT, RA } },
3895 { "abso.", XO(31,360,1,1), XORB_MASK, M601, { RT, RA } },
3896
3897 { "divs", XO(31,363,0,0), XO_MASK, M601, { RT, RA, RB } },
3898 { "divs.", XO(31,363,0,1), XO_MASK, M601, { RT, RA, RB } },
3899 { "divso", XO(31,363,1,0), XO_MASK, M601, { RT, RA, RB } },
3900 { "divso.", XO(31,363,1,1), XO_MASK, M601, { RT, RA, RB } },
3901
3902 { "tlbia", X(31,370), 0xffffffff, PPC, { 0 } },
3903
3904 { "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } },
3905
3906 { "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } },
3907
3908 { "lhauxe", X(31,383), X_MASK, BOOKE64, { RT, RAL, RB } },
3909
3910 { "mtdcrx", X(31,387), X_MASK, BOOKE, { RA, RS } },
3911
3912 { "dcblc", X(31,390), X_MASK, PPCCHLK, { CT, RA, RB }},
3913
3914 { "subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3915 { "subfe64o",XO(31,392,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3916
3917 { "adde64", XO(31,394,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3918 { "adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3919
3920 { "dcblce", X(31,398), X_MASK, PPCCHLK64, { CT, RA, RB }},
3921
3922 { "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } },
3923
3924 { "sthx", X(31,407), X_MASK, COM, { RS, RA0, RB } },
3925
3926 { "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } },
3927
3928 { "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } },
3929
3930 { "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } },
3931
3932 { "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } },
3933
3934 { "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } },
3935 { "orc.", XRC(31,412,1), X_MASK, COM, { RA, RS, RB } },
3936
3937 { "sradi", XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 } },
3938 { "sradi.", XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 } },
3939
3940 { "sthxe", X(31,415), X_MASK, BOOKE64, { RS, RA0, RB } },
3941
3942 { "slbie", X(31,434), XRTRA_MASK, PPC64, { RB } },
3943
3944 { "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } },
3945
3946 { "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB } },
3947
3948 { "sthuxe", X(31,447), X_MASK, BOOKE64, { RS, RAS, RB } },
3949
3950 { "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } },
3951 { "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } },
3952 { "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } },
3953 { "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } },
3954
3955 { "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403, { RS } },
3956 { "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403, { RS } },
3957 { "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, { RS } },
3958 { "mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, { RS } },
3959 { "mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, { RS } },
3960 { "mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, { RS } },
3961 { "mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, { RS } },
3962 { "mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, { RS } },
3963 { "mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, { RS } },
3964 { "mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, { RS } },
3965 { "mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, { RS } },
3966 { "mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, { RS } },
3967 { "mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, { RS } },
3968 { "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, { RS } },
3969 { "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, { RS } },
3970 { "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, { RS } },
3971 { "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, { RS } },
3972 { "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, { RS } },
3973 { "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, { RS } },
3974 { "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, { RS } },
3975 { "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, { RS } },
3976 { "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, { RS } },
3977 { "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, { RS } },
3978 { "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, { RS } },
3979 { "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, { RS } },
3980 { "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, { RS } },
3981 { "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, { RS } },
3982 { "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, { RS } },
3983 { "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, { RS } },
3984 { "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, { RS } },
3985 { "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, { RS } },
3986 { "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RS } },
3987 { "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RS } },
3988 { "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RS } },
3989 { "mtdcr", X(31,451), X_MASK, PPC403 | BOOKE, { SPR, RS } },
3990
3991 { "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64, { RT, RA } },
3992 { "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64, { RT, RA } },
3993
3994 { "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3995 { "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3996 { "divduo", XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3997 { "divduo.", XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3998
3999 { "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4000 { "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4001
4002 { "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } },
4003 { "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } },
4004 { "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } },
4005 { "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } },
4006
4007 { "mtmq", XSPR(31,467,0), XSPR_MASK, M601, { RS } },
4008 { "mtxer", XSPR(31,467,1), XSPR_MASK, COM, { RS } },
4009 { "mtlr", XSPR(31,467,8), XSPR_MASK, COM, { RS } },
4010 { "mtctr", XSPR(31,467,9), XSPR_MASK, COM, { RS } },
4011 { "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } },
4012 { "mtdsisr", XSPR(31,467,18), XSPR_MASK, COM, { RS } },
4013 { "mtdar", XSPR(31,467,19), XSPR_MASK, COM, { RS } },
4014 { "mtrtcu", XSPR(31,467,20), XSPR_MASK, COM, { RS } },
4015 { "mtrtcl", XSPR(31,467,21), XSPR_MASK, COM, { RS } },
4016 { "mtdec", XSPR(31,467,22), XSPR_MASK, COM, { RS } },
4017 { "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } },
4018 { "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } },
4019 { "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } },
4020 { "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } },
4021 { "mtpid", XSPR(31,467,48), XSPR_MASK, BOOKE, { RS } },
4022 { "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RS } },
4023 { "mtdecar", XSPR(31,467,54), XSPR_MASK, BOOKE, { RS } },
4024 { "mtcsrr0", XSPR(31,467,58), XSPR_MASK, BOOKE, { RS } },
4025 { "mtcsrr1", XSPR(31,467,59), XSPR_MASK, BOOKE, { RS } },
4026 { "mtdear", XSPR(31,467,61), XSPR_MASK, BOOKE, { RS } },
4027 { "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RS } },
4028 { "mtesr", XSPR(31,467,62), XSPR_MASK, BOOKE, { RS } },
4029 { "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RS } },
4030 { "mtivpr", XSPR(31,467,63), XSPR_MASK, BOOKE, { RS } },
4031 { "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RS } },
4032 { "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RS } },
4033 { "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, { RS } },
4034 { "mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, { RS } },
4035 { "mticr", XSPR(31,467,148), XSPR_MASK, PPC860, { RS } },
4036 { "mtder", XSPR(31,467,149), XSPR_MASK, PPC860, { RS } },
4037 { "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, { RS } },
4038 { "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, { RS } },
4039 { "mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, { RS } },
4040 { "mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, { RS } },
4041 { "mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, { RS } },
4042 { "mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, { RS } },
4043 { "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, { RS } },
4044 { "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, { RS } },
4045 { "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RS } },
4046 { "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RS } },
4047 { "mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, { RS } },
4048 { "mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, { RS } },
4049 { "mtsprg", XSPR(31,467,256), XSPRG_MASK,PPC, { SPRG, RS } },
4050 { "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RS } },
4051 { "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RS } },
4052 { "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RS } },
4053 { "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RS } },
4054 { "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405 | BOOKE, { RS } },
4055 { "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405 | BOOKE, { RS } },
4056 { "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405 | BOOKE, { RS } },
4057 { "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405 | BOOKE, { RS } },
4058 { "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS } },
4059 { "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } },
4060 { "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } },
4061 { "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } },
4062 { "mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, { RS } },
4063 { "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RS } },
4064 { "mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, { RS } },
4065 { "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, { RS } },
4066 { "mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, { RS } },
4067 { "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RS } },
4068 { "mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, { RS } },
4069 { "mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, { RS } },
4070 { "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RS } },
4071 { "mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, { RS } },
4072 { "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RS } },
4073 { "mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, { RS } },
4074 { "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, { RS } },
4075 { "mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, { RS } },
4076 { "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RS } },
4077 { "mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, { RS } },
4078 { "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RS } },
4079 { "mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, { RS } },
4080 { "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RS } },
4081 { "mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, { RS } },
4082 { "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RS } },
4083 { "mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, { RS } },
4084 { "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RS } },
4085 { "mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, { RS } },
4086 { "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RS } },
4087 { "mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, { RS } },
4088 { "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, { RS } },
4089 { "mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, { RS } },
4090 { "mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, { RS } },
4091 { "mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, { RS } },
4092 { "mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, { RS } },
4093 { "mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, { RS } },
4094 { "mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, { RS } },
4095 { "mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, { RS } },
4096 { "mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, { RS } },
4097 { "mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, { RS } },
4098 { "mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, { RS } },
4099 { "mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, { RS } },
4100 { "mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, { RS } },
4101 { "mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, { RS } },
4102 { "mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, { RS } },
4103 { "mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, { RS } },
4104 { "mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, { RS } },
4105 { "mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, { RS } },
4106 { "mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, { RS } },
4107 { "mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, { RS } },
4108 { "mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, { RS } },
4109 { "mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, { RS } },
4110 { "mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, { RS } },
4111 { "mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, { RS } },
4112 { "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4113 { "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4114 { "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4115 { "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4116 { "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } },
4117 { "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } },
4118 { "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } },
4119 { "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RS } },
4120 { "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RS } },
4121 { "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RS } },
4122 { "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RS } },
4123 { "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RS } },
4124 { "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RS } },
4125 { "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RS } },
4126 { "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RS } },
4127 { "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RS } },
4128 { "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RS } },
4129 { "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RS } },
4130 { "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RS } },
4131 { "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RS } },
4132 { "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RS } },
4133 { "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RS } },
4134 { "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RS } },
4135 { "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RS } },
4136 { "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RS } },
4137 { "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RS } },
4138 { "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RS } },
4139 { "mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, { RS } },
4140 { "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RS } },
4141 { "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RS } },
4142 { "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, { RS } },
4143 { "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, { RS } },
4144 { "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, { RS } },
4145 { "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RS } },
4146 { "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RS } },
4147 { "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RS } },
4148 { "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RS } },
4149 { "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RS } },
4150 { "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RS } },
4151 { "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RS } },
4152 { "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RS } },
4153 { "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RS } },
4154 { "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RS } },
4155 { "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RS } },
4156 { "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RS } },
4157 { "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RS } },
4158 { "mtspr", X(31,467), X_MASK, COM, { SPR, RS } },
4159
4160 { "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
4161
4162 { "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB } },
4163 { "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB } },
4164
4165 { "dcbie", X(31,478), XRT_MASK, BOOKE64, { RA, RB } },
4166
4167 { "dcread", X(31,486), X_MASK, PPC403|PPC440, { RT, RA, RB }},
4168
4169 { "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }},
4170
4171 { "icbtls", X(31,486), X_MASK, PPCCHLK, { CT, RA, RB }},
4172
4173 { "nabs", XO(31,488,0,0), XORB_MASK, M601, { RT, RA } },
4174 { "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4175 { "nabs.", XO(31,488,0,1), XORB_MASK, M601, { RT, RA } },
4176 { "nabso", XO(31,488,1,0), XORB_MASK, M601, { RT, RA } },
4177 { "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4178 { "nabso.", XO(31,488,1,1), XORB_MASK, M601, { RT, RA } },
4179
4180 { "divd", XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB } },
4181 { "divd.", XO(31,489,0,1), XO_MASK, PPC64, { RT, RA, RB } },
4182 { "divdo", XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB } },
4183 { "divdo.", XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB } },
4184
4185 { "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4186 { "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4187
4188 { "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } },
4189 { "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } },
4190 { "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } },
4191 { "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } },
4192
4193 { "icbtlse", X(31,494), X_MASK, PPCCHLK64, { CT, RA, RB }},
4194
4195 { "slbia", X(31,498), 0xffffffff, PPC64, { 0 } },
4196
4197 { "cli", X(31,502), XRB_MASK, POWER, { RT, RA } },
4198
4199 { "stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, { RS, RA, RB } },
4200
4201 { "mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, { BF } },
4202
4203 { "bblels", X(31,518), X_MASK, PPCBRLK, { 0 }},
4204 { "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64, { BF } },
4205
4206 { "clcs", X(31,531), XRB_MASK, M601, { RT, RA } },
4207
4208 { "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA0, RB } },
4209 { "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } },
4210
4211 { "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA0, RB } },
4212 { "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB } },
4213
4214 { "lfsx", X(31,535), X_MASK, COM, { FRT, RA0, RB } },
4215
4216 { "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } },
4217 { "sr", XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB } },
4218 { "srw.", XRC(31,536,1), X_MASK, PPCCOM, { RA, RS, RB } },
4219 { "sr.", XRC(31,536,1), X_MASK, PWRCOM, { RA, RS, RB } },
4220
4221 { "rrib", XRC(31,537,0), X_MASK, M601, { RA, RS, RB } },
4222 { "rrib.", XRC(31,537,1), X_MASK, M601, { RA, RS, RB } },
4223
4224 { "srd", XRC(31,539,0), X_MASK, PPC64, { RA, RS, RB } },
4225 { "srd.", XRC(31,539,1), X_MASK, PPC64, { RA, RS, RB } },
4226
4227 { "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } },
4228 { "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } },
4229
4230 { "lwbrxe", X(31,542), X_MASK, BOOKE64, { RT, RA0, RB } },
4231
4232 { "lfsxe", X(31,543), X_MASK, BOOKE64, { FRT, RA0, RB } },
4233
4234 { "bbelr", X(31,550), X_MASK, PPCBRLK, { 0 }},
4235
4236 { "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } },
4237
4238 { "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } },
4239
4240 { "lfsuxe", X(31,575), X_MASK, BOOKE64, { FRT, RAS, RB } },
4241
4242 { "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } },
4243
4244 { "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA0, NB } },
4245 { "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA0, NB } },
4246
4247 { "lwsync", XSYNC(31,598,1), 0xffffffff, PPC, { 0 } },
4248 { "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, { 0 } },
4249 { "msync", X(31,598), 0xffffffff, BOOKE, { 0 } },
4250 { "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } },
4251 { "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
4252
4253 { "lfdx", X(31,599), X_MASK, COM, { FRT, RA0, RB } },
4254
4255 { "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA0, RB } },
4256
4257 { "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } },
4258
4259 { "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA } },
4260
4261 { "lfdux", X(31,631), X_MASK, COM, { FRT, RAS, RB } },
4262
4263 { "lfduxe", X(31,639), X_MASK, BOOKE64, { FRT, RAS, RB } },
4264
4265 { "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } },
4266
4267 { "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA0, RB } },
4268 { "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA0, RB } },
4269
4270 { "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA0, RB } },
4271 { "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA0, RB } },
4272
4273 { "stfsx", X(31,663), X_MASK, COM, { FRS, RA0, RB } },
4274
4275 { "srq", XRC(31,664,0), X_MASK, M601, { RA, RS, RB } },
4276 { "srq.", XRC(31,664,1), X_MASK, M601, { RA, RS, RB } },
4277
4278 { "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } },
4279 { "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } },
4280
4281 { "stwbrxe", X(31,670), X_MASK, BOOKE64, { RS, RA0, RB } },
4282
4283 { "stfsxe", X(31,671), X_MASK, BOOKE64, { FRS, RA0, RB } },
4284
4285 { "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } },
4286
4287 { "sriq", XRC(31,696,0), X_MASK, M601, { RA, RS, SH } },
4288 { "sriq.", XRC(31,696,1), X_MASK, M601, { RA, RS, SH } },
4289
4290 { "stfsuxe", X(31,703), X_MASK, BOOKE64, { FRS, RAS, RB } },
4291
4292 { "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA0, NB } },
4293 { "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA0, NB } },
4294
4295 { "stfdx", X(31,727), X_MASK, COM, { FRS, RA0, RB } },
4296
4297 { "srlq", XRC(31,728,0), X_MASK, M601, { RA, RS, RB } },
4298 { "srlq.", XRC(31,728,1), X_MASK, M601, { RA, RS, RB } },
4299
4300 { "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } },
4301 { "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } },
4302
4303 { "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA0, RB } },
4304
4305 { "dcba", X(31,758), XRT_MASK, PPC405 | BOOKE, { RA, RB } },
4306
4307 { "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } },
4308
4309 { "srliq", XRC(31,760,0), X_MASK, M601, { RA, RS, SH } },
4310 { "srliq.", XRC(31,760,1), X_MASK, M601, { RA, RS, SH } },
4311
4312 { "dcbae", X(31,766), XRT_MASK, BOOKE64, { RA, RB } },
4313
4314 { "stfduxe", X(31,767), X_MASK, BOOKE64, { FRS, RAS, RB } },
4315
4316 { "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } },
4317 { "tlbivaxe",X(31,787), XRT_MASK, BOOKE64, { RA, RB } },
4318
4319 { "lhbrx", X(31,790), X_MASK, COM, { RT, RA0, RB } },
4320
4321 { "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } },
4322 { "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } },
4323 { "sraw.", XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB } },
4324 { "sra.", XRC(31,792,1), X_MASK, PWRCOM, { RA, RS, RB } },
4325
4326 { "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } },
4327 { "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } },
4328
4329 { "lhbrxe", X(31,798), X_MASK, BOOKE64, { RT, RA0, RB } },
4330
4331 { "ldxe", X(31,799), X_MASK, BOOKE64, { RT, RA0, RB } },
4332 { "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA0, RB } },
4333
4334 { "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } },
4335
4336 { "dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, { STRM } },
4337 { "dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, { 0 } },
4338
4339 { "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } },
4340 { "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } },
4341 { "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } },
4342 { "srai.", XRC(31,824,1), X_MASK, PWRCOM, { RA, RS, SH } },
4343
4344 { "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } },
4345
4346 { "mbar", X(31,854), X_MASK, BOOKE, { MO } },
4347 { "eieio", X(31,854), 0xffffffff, PPC, { 0 } },
4348
4349 { "tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE, { RTO, RA, RB } },
4350 { "tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE, { RTO, RA, RB } },
4351 { "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, { RA, RB } },
4352 { "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, { RA, RB } },
4353
4354 { "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } },
4355
4356 { "sthbrx", X(31,918), X_MASK, COM, { RS, RA0, RB } },
4357
4358 { "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } },
4359 { "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB } },
4360
4361 { "srea", XRC(31,921,0), X_MASK, M601, { RA, RS, RB } },
4362 { "srea.", XRC(31,921,1), X_MASK, M601, { RA, RS, RB } },
4363
4364 { "extsh", XRC(31,922,0), XRB_MASK, PPCCOM, { RA, RS } },
4365 { "exts", XRC(31,922,0), XRB_MASK, PWRCOM, { RA, RS } },
4366 { "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } },
4367 { "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } },
4368
4369 { "sthbrxe", X(31,926), X_MASK, BOOKE64, { RS, RA0, RB } },
4370
4371 { "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA0, RB } },
4372
4373 { "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } },
4374 { "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } },
4375 { "tlbre", X(31,946), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } },
4376
4377 { "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } },
4378 { "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } },
4379
4380 { "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} },
4381 { "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} },
4382
4383 { "stduxe", X(31,959), X_MASK, BOOKE64, { RS, RAS, RB } },
4384
4385 { "iccci", X(31,966), XRT_MASK, PPC403|PPC440, { RA, RB } },
4386
4387 { "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } },
4388 { "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } },
4389 { "tlbwe", X(31,978), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } },
4390 { "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } },
4391
4392 { "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } },
4393
4394 { "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA0, RB } },
4395
4396 { "extsw", XRC(31,986,0), XRB_MASK, PPC64 | BOOKE64,{ RA, RS } },
4397 { "extsw.", XRC(31,986,1), XRB_MASK, PPC64, { RA, RS } },
4398
4399 { "icread", X(31,998), XRT_MASK, PPC403|PPC440, { RA, RB } },
4400
4401 { "icbie", X(31,990), XRT_MASK, BOOKE64, { RA, RB } },
4402 { "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA0, RB } },
4403
4404 { "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } },
4405
4406 { "dcbzl", XOPL(31,1014,1), XRT_MASK,POWER4, { RA, RB } },
4407 { "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4408 { "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4409
4410 { "dcbze", X(31,1022), XRT_MASK, BOOKE64, { RA, RB } },
4411
4412 { "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB } },
4413 { "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB } },
4414 { "lvewx", X(31, 71), X_MASK, PPCVEC, { VD, RA, RB } },
4415 { "lvsl", X(31, 6), X_MASK, PPCVEC, { VD, RA, RB } },
4416 { "lvsr", X(31, 38), X_MASK, PPCVEC, { VD, RA, RB } },
4417 { "lvx", X(31, 103), X_MASK, PPCVEC, { VD, RA, RB } },
4418 { "lvxl", X(31, 359), X_MASK, PPCVEC, { VD, RA, RB } },
4419 { "stvebx", X(31, 135), X_MASK, PPCVEC, { VS, RA, RB } },
4420 { "stvehx", X(31, 167), X_MASK, PPCVEC, { VS, RA, RB } },
4421 { "stvewx", X(31, 199), X_MASK, PPCVEC, { VS, RA, RB } },
4422 { "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } },
4423 { "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } },
4424
4425 { "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA0 } },
4426 { "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA0 } },
4427
4428 { "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL } },
4429 { "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA0 } },
4430
4431 { "lbz", OP(34), OP_MASK, COM, { RT, D, RA0 } },
4432
4433 { "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL } },
4434
4435 { "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA0 } },
4436 { "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA0 } },
4437
4438 { "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } },
4439 { "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA0 } },
4440
4441 { "stb", OP(38), OP_MASK, COM, { RS, D, RA0 } },
4442
4443 { "stbu", OP(39), OP_MASK, COM, { RS, D, RAS } },
4444
4445 { "lhz", OP(40), OP_MASK, COM, { RT, D, RA0 } },
4446
4447 { "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL } },
4448
4449 { "lha", OP(42), OP_MASK, COM, { RT, D, RA0 } },
4450
4451 { "lhau", OP(43), OP_MASK, COM, { RT, D, RAL } },
4452
4453 { "sth", OP(44), OP_MASK, COM, { RS, D, RA0 } },
4454
4455 { "sthu", OP(45), OP_MASK, COM, { RS, D, RAS } },
4456
4457 { "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM } },
4458 { "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA0 } },
4459
4460 { "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA0 } },
4461 { "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA0 } },
4462
4463 { "lfs", OP(48), OP_MASK, COM, { FRT, D, RA0 } },
4464
4465 { "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } },
4466
4467 { "lfd", OP(50), OP_MASK, COM, { FRT, D, RA0 } },
4468
4469 { "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } },
4470
4471 { "stfs", OP(52), OP_MASK, COM, { FRS, D, RA0 } },
4472
4473 { "stfsu", OP(53), OP_MASK, COM, { FRS, D, RAS } },
4474
4475 { "stfd", OP(54), OP_MASK, COM, { FRS, D, RA0 } },
4476
4477 { "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } },
4478
4479 { "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } },
4480
4481 { "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA0 } },
4482
4483 { "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA0 } },
4484
4485 { "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4486 { "lbzue", DEO(58,1), DE_MASK, BOOKE64, { RT, DE, RAL } },
4487 { "lhze", DEO(58,2), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4488 { "lhzue", DEO(58,3), DE_MASK, BOOKE64, { RT, DE, RAL } },
4489 { "lhae", DEO(58,4), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4490 { "lhaue", DEO(58,5), DE_MASK, BOOKE64, { RT, DE, RAL } },
4491 { "lwze", DEO(58,6), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4492 { "lwzue", DEO(58,7), DE_MASK, BOOKE64, { RT, DE, RAL } },
4493 { "stbe", DEO(58,8), DE_MASK, BOOKE64, { RS, DE, RA0 } },
4494 { "stbue", DEO(58,9), DE_MASK, BOOKE64, { RS, DE, RAS } },
4495 { "sthe", DEO(58,10), DE_MASK, BOOKE64, { RS, DE, RA0 } },
4496 { "sthue", DEO(58,11), DE_MASK, BOOKE64, { RS, DE, RAS } },
4497 { "stwe", DEO(58,14), DE_MASK, BOOKE64, { RS, DE, RA0 } },
4498 { "stwue", DEO(58,15), DE_MASK, BOOKE64, { RS, DE, RAS } },
4499
4500 { "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA0 } },
4501
4502 { "ldu", DSO(58,1), DS_MASK, PPC64, { RT, DS, RAL } },
4503
4504 { "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA0 } },
4505
4506 { "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4507 { "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4508
4509 { "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4510 { "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4511
4512 { "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4513 { "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4514
4515 { "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4516 { "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4517
4518 { "fres", A(59,24,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4519 { "fres.", A(59,24,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4520
4521 { "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } },
4522 { "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } },
4523
4524 { "fsqrtes", A(59,26,0), AFRAFRC_MASK, POWER5, { FRT, FRB } },
4525 { "fsqrtes.", A(59,26,1), AFRAFRC_MASK, POWER5, { FRT, FRB } },
4526
4527 { "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4528 { "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4529
4530 { "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4531 { "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4532
4533 { "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4534 { "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4535
4536 { "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4537 { "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4538
4539 { "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } },
4540
4541 { "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } },
4542
4543 { "lde", DEO(62,0), DE_MASK, BOOKE64, { RT, DES, RA0 } },
4544 { "ldue", DEO(62,1), DE_MASK, BOOKE64, { RT, DES, RA0 } },
4545 { "lfse", DEO(62,4), DE_MASK, BOOKE64, { FRT, DES, RA0 } },
4546 { "lfsue", DEO(62,5), DE_MASK, BOOKE64, { FRT, DES, RAS } },
4547 { "lfde", DEO(62,6), DE_MASK, BOOKE64, { FRT, DES, RA0 } },
4548 { "lfdue", DEO(62,7), DE_MASK, BOOKE64, { FRT, DES, RAS } },
4549 { "stde", DEO(62,8), DE_MASK, BOOKE64, { RS, DES, RA0 } },
4550 { "stdue", DEO(62,9), DE_MASK, BOOKE64, { RS, DES, RAS } },
4551 { "stfse", DEO(62,12), DE_MASK, BOOKE64, { FRS, DES, RA0 } },
4552 { "stfsue", DEO(62,13), DE_MASK, BOOKE64, { FRS, DES, RAS } },
4553 { "stfde", DEO(62,14), DE_MASK, BOOKE64, { FRS, DES, RA0 } },
4554 { "stfdue", DEO(62,15), DE_MASK, BOOKE64, { FRS, DES, RAS } },
4555
4556 { "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA0 } },
4557
4558 { "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } },
4559
4560 { "stq", DSO(62,2), DS_MASK, POWER4, { RSQ, DS, RA0 } },
4561
4562 { "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
4563
4564 { "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } },
4565 { "frsp.", XRC(63,12,1), XRA_MASK, COM, { FRT, FRB } },
4566
4567 { "fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, { FRT, FRB } },
4568 { "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } },
4569 { "fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, { FRT, FRB } },
4570 { "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } },
4571
4572 { "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB } },
4573 { "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } },
4574 { "fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, { FRT, FRB } },
4575 { "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } },
4576
4577 { "fdiv", A(63,18,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4578 { "fd", A(63,18,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4579 { "fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4580 { "fd.", A(63,18,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4581
4582 { "fsub", A(63,20,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4583 { "fs", A(63,20,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4584 { "fsub.", A(63,20,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4585 { "fs.", A(63,20,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4586
4587 { "fadd", A(63,21,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4588 { "fa", A(63,21,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4589 { "fadd.", A(63,21,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4590 { "fa.", A(63,21,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4591
4592 { "fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
4593 { "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
4594
4595 { "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4596 { "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4597
4598 { "fre", A(63,24,0), AFRAFRC_MASK, POWER5, { FRT, FRB } },
4599 { "fre.", A(63,24,1), AFRAFRC_MASK, POWER5, { FRT, FRB } },
4600
4601 { "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
4602 { "fm", A(63,25,0), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
4603 { "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
4604 { "fm.", A(63,25,1), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
4605
4606 { "frsqrte", A(63,26,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4607 { "frsqrte.",A(63,26,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4608
4609 { "fmsub", A(63,28,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4610 { "fms", A(63,28,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4611 { "fmsub.", A(63,28,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4612 { "fms.", A(63,28,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4613
4614 { "fmadd", A(63,29,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4615 { "fma", A(63,29,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4616 { "fmadd.", A(63,29,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4617 { "fma.", A(63,29,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4618
4619 { "fnmsub", A(63,30,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4620 { "fnms", A(63,30,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4621 { "fnmsub.", A(63,30,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4622 { "fnms.", A(63,30,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4623
4624 { "fnmadd", A(63,31,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4625 { "fnma", A(63,31,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4626 { "fnmadd.", A(63,31,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4627 { "fnma.", A(63,31,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4628
4629 { "fcmpo", X(63,32), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
4630
4631 { "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, { BT } },
4632 { "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, { BT } },
4633
4634 { "fneg", XRC(63,40,0), XRA_MASK, COM, { FRT, FRB } },
4635 { "fneg.", XRC(63,40,1), XRA_MASK, COM, { FRT, FRB } },
4636
4637 { "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
4638
4639 { "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } },
4640 { "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } },
4641
4642 { "fmr", XRC(63,72,0), XRA_MASK, COM, { FRT, FRB } },
4643 { "fmr.", XRC(63,72,1), XRA_MASK, COM, { FRT, FRB } },
4644
4645 { "mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4646 { "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4647
4648 { "fnabs", XRC(63,136,0), XRA_MASK, COM, { FRT, FRB } },
4649 { "fnabs.", XRC(63,136,1), XRA_MASK, COM, { FRT, FRB } },
4650
4651 { "fabs", XRC(63,264,0), XRA_MASK, COM, { FRT, FRB } },
4652 { "fabs.", XRC(63,264,1), XRA_MASK, COM, { FRT, FRB } },
4653
4654 { "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } },
4655 { "mffs.", XRC(63,583,1), XRARB_MASK, COM, { FRT } },
4656
4657 { "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB } },
4658 { "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB } },
4659
4660 { "fctid", XRC(63,814,0), XRA_MASK, PPC64, { FRT, FRB } },
4661 { "fctid.", XRC(63,814,1), XRA_MASK, PPC64, { FRT, FRB } },
4662
4663 { "fctidz", XRC(63,815,0), XRA_MASK, PPC64, { FRT, FRB } },
4664 { "fctidz.", XRC(63,815,1), XRA_MASK, PPC64, { FRT, FRB } },
4665
4666 { "fcfid", XRC(63,846,0), XRA_MASK, PPC64, { FRT, FRB } },
4667 { "fcfid.", XRC(63,846,1), XRA_MASK, PPC64, { FRT, FRB } },
4668
4669 };
4670
4671 const int powerpc_num_opcodes =
4672 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
4673
4674 /* The macro table. This is only used by the assembler. */
4675
4676 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
4677 when x=0; 32-x when x is between 1 and 31; are negative if x is
4678 negative; and are 32 or more otherwise. This is what you want
4679 when, for instance, you are emulating a right shift by a
4680 rotate-left-and-mask, because the underlying instructions support
4681 shifts of size 0 but not shifts of size 32. By comparison, when
4682 extracting x bits from some word you want to use just 32-x, because
4683 the underlying instructions don't support extracting 0 bits but do
4684 support extracting the whole word (32 bits in this case). */
4685
4686 const struct powerpc_macro powerpc_macros[] = {
4687 { "extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1" },
4688 { "extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1" },
4689 { "extrdi", 4, PPC64, "rldicl %0,%1,(%2)+(%3),64-(%2)" },
4690 { "extrdi.", 4, PPC64, "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
4691 { "insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3" },
4692 { "insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3" },
4693 { "rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" },
4694 { "rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" },
4695 { "sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)" },
4696 { "sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)" },
4697 { "srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" },
4698 { "srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" },
4699 { "clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)" },
4700 { "clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)" },
4701 { "clrlsldi",4, PPC64, "rldic %0,%1,%3,(%2)-(%3)" },
4702 { "clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)" },
4703
4704 { "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" },
4705 { "extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1" },
4706 { "extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
4707 { "extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
4708 { "inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" },
4709 { "inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
4710 { "insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
4711 { "insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
4712 { "rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4713 { "rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4714 { "slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)" },
4715 { "sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)" },
4716 { "slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)" },
4717 { "sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)" },
4718 { "srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4719 { "sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4720 { "srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4721 { "sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4722 { "clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)" },
4723 { "clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)" },
4724 { "clrlslwi",4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
4725 { "clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
4726 };
4727
4728 const int powerpc_num_macros =
4729 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);
4730