1 /* Instruction printing code for the ARC.
2 Copyright 1994, 1995, 1997, 1998, 2000, 2001, 2002, 2005
3 Free Software Foundation, Inc.
4 Contributed by Doug Evans (dje@cygnus.com).
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
20
21 #include "ansidecl.h"
22 #include "libiberty.h"
23 #include "dis-asm.h"
24 #include "opcode/arc.h"
25 #include "elf-bfd.h"
26 #include "elf/arc.h"
27 #include <string.h>
28 #include "opintl.h"
29
30 #include <stdarg.h>
31 #include "arc-dis.h"
32 #include "arc-ext.h"
33
34 #ifndef dbg
35 #define dbg (0)
36 #endif
37
38 /* Classification of the opcodes for the decoder to print
39 the instructions. */
40
41 typedef enum
42 {
43 CLASS_A4_ARITH,
44 CLASS_A4_OP3_GENERAL,
45 CLASS_A4_FLAG,
46 /* All branches other than JC. */
47 CLASS_A4_BRANCH,
48 CLASS_A4_JC ,
49 /* All loads other than immediate
50 indexed loads. */
51 CLASS_A4_LD0,
52 CLASS_A4_LD1,
53 CLASS_A4_ST,
54 CLASS_A4_SR,
55 /* All single operand instructions. */
56 CLASS_A4_OP3_SUBOPC3F,
57 CLASS_A4_LR
58 } a4_decoding_class;
59
60 #define BIT(word,n) ((word) & (1 << n))
61 #define BITS(word,s,e) (((word) << (31 - e)) >> (s + (31 - e)))
62 #define OPCODE(word) (BITS ((word), 27, 31))
63 #define FIELDA(word) (BITS ((word), 21, 26))
64 #define FIELDB(word) (BITS ((word), 15, 20))
65 #define FIELDC(word) (BITS ((word), 9, 14))
66
67 /* FIELD D is signed in all of its uses, so we make sure argument is
68 treated as signed for bit shifting purposes: */
69 #define FIELDD(word) (BITS (((signed int)word), 0, 8))
70
71 #define PUT_NEXT_WORD_IN(a) \
72 do \
73 { \
74 if (is_limm == 1 && !NEXT_WORD (1)) \
75 mwerror (state, _("Illegal limm reference in last instruction!\n")); \
76 a = state->words[1]; \
77 } \
78 while (0)
79
80 #define CHECK_FLAG_COND_NULLIFY() \
81 do \
82 { \
83 if (is_shimm == 0) \
84 { \
85 flag = BIT (state->words[0], 8); \
86 state->nullifyMode = BITS (state->words[0], 5, 6); \
87 cond = BITS (state->words[0], 0, 4); \
88 } \
89 } \
90 while (0)
91
92 #define CHECK_COND() \
93 do \
94 { \
95 if (is_shimm == 0) \
96 cond = BITS (state->words[0], 0, 4); \
97 } \
98 while (0)
99
100 #define CHECK_FIELD(field) \
101 do \
102 { \
103 if (field == 62) \
104 { \
105 is_limm++; \
106 field##isReg = 0; \
107 PUT_NEXT_WORD_IN (field); \
108 limm_value = field; \
109 } \
110 else if (field > 60) \
111 { \
112 field##isReg = 0; \
113 is_shimm++; \
114 flag = (field == 61); \
115 field = FIELDD (state->words[0]); \
116 } \
117 } \
118 while (0)
119
120 #define CHECK_FIELD_A() \
121 do \
122 { \
123 fieldA = FIELDA (state->words[0]); \
124 if (fieldA > 60) \
125 { \
126 fieldAisReg = 0; \
127 fieldA = 0; \
128 } \
129 } \
130 while (0)
131
132 #define CHECK_FIELD_B() \
133 do \
134 { \
135 fieldB = FIELDB (state->words[0]); \
136 CHECK_FIELD (fieldB); \
137 } \
138 while (0)
139
140 #define CHECK_FIELD_C() \
141 do \
142 { \
143 fieldC = FIELDC (state->words[0]); \
144 CHECK_FIELD (fieldC); \
145 } \
146 while (0)
147
148 #define IS_SMALL(x) (((field##x) < 256) && ((field##x) > -257))
149 #define IS_REG(x) (field##x##isReg)
150 #define WRITE_FORMAT_LB_Rx_RB(x) WRITE_FORMAT (x, "[","]","","")
151 #define WRITE_FORMAT_x_COMMA_LB(x) WRITE_FORMAT (x, "",",[","",",[")
152 #define WRITE_FORMAT_COMMA_x_RB(x) WRITE_FORMAT (x, ",","]",",","]")
153 #define WRITE_FORMAT_x_RB(x) WRITE_FORMAT (x, "","]","","]")
154 #define WRITE_FORMAT_COMMA_x(x) WRITE_FORMAT (x, ",","",",","")
155 #define WRITE_FORMAT_x_COMMA(x) WRITE_FORMAT (x, "",",","",",")
156 #define WRITE_FORMAT_x(x) WRITE_FORMAT (x, "","","","")
157 #define WRITE_FORMAT(x,cb1,ca1,cb,ca) strcat (formatString, \
158 (IS_REG (x) ? cb1"%r"ca1 : \
159 usesAuxReg ? cb"%a"ca : \
160 IS_SMALL (x) ? cb"%d"ca : cb"%h"ca))
161 #define WRITE_FORMAT_RB() strcat (formatString, "]")
162 #define WRITE_COMMENT(str) (state->comm[state->commNum++] = (str))
163 #define WRITE_NOP_COMMENT() if (!fieldAisReg && !flag) WRITE_COMMENT ("nop");
164
165 #define NEXT_WORD(x) (offset += 4, state->words[x])
166
167 #define add_target(x) (state->targets[state->tcnt++] = (x))
168
169 static char comment_prefix[] = "\t; ";
170
171 static const char *
core_reg_name(struct arcDisState * state,int val)172 core_reg_name (struct arcDisState * state, int val)
173 {
174 if (state->coreRegName)
175 return (*state->coreRegName)(state->_this, val);
176 return 0;
177 }
178
179 static const char *
aux_reg_name(struct arcDisState * state,int val)180 aux_reg_name (struct arcDisState * state, int val)
181 {
182 if (state->auxRegName)
183 return (*state->auxRegName)(state->_this, val);
184 return 0;
185 }
186
187 static const char *
cond_code_name(struct arcDisState * state,int val)188 cond_code_name (struct arcDisState * state, int val)
189 {
190 if (state->condCodeName)
191 return (*state->condCodeName)(state->_this, val);
192 return 0;
193 }
194
195 static const char *
instruction_name(struct arcDisState * state,int op1,int op2,int * flags)196 instruction_name (struct arcDisState * state,
197 int op1,
198 int op2,
199 int * flags)
200 {
201 if (state->instName)
202 return (*state->instName)(state->_this, op1, op2, flags);
203 return 0;
204 }
205
206 static void
mwerror(struct arcDisState * state,const char * msg)207 mwerror (struct arcDisState * state, const char * msg)
208 {
209 if (state->err != 0)
210 (*state->err)(state->_this, (msg));
211 }
212
213 static const char *
post_address(struct arcDisState * state,int addr)214 post_address (struct arcDisState * state, int addr)
215 {
216 static char id[3 * ARRAY_SIZE (state->addresses)];
217 int j, i = state->acnt;
218
219 if (i < ((int) ARRAY_SIZE (state->addresses)))
220 {
221 state->addresses[i] = addr;
222 ++state->acnt;
223 j = i*3;
224 id[j+0] = '@';
225 id[j+1] = '0'+i;
226 id[j+2] = 0;
227
228 return id + j;
229 }
230 return "";
231 }
232
233 static void
arc_sprintf(struct arcDisState * state,char * buf,const char * format,...)234 arc_sprintf (struct arcDisState *state, char *buf, const char *format, ...)
235 {
236 char *bp;
237 const char *p;
238 int size, leading_zero, regMap[2];
239 long auxNum;
240 va_list ap;
241
242 va_start (ap, format);
243
244 bp = buf;
245 *bp = 0;
246 p = format;
247 auxNum = -1;
248 regMap[0] = 0;
249 regMap[1] = 0;
250
251 while (1)
252 switch (*p++)
253 {
254 case 0:
255 goto DOCOMM; /* (return) */
256 default:
257 *bp++ = p[-1];
258 break;
259 case '%':
260 size = 0;
261 leading_zero = 0;
262 RETRY: ;
263 switch (*p++)
264 {
265 case '0':
266 case '1':
267 case '2':
268 case '3':
269 case '4':
270 case '5':
271 case '6':
272 case '7':
273 case '8':
274 case '9':
275 {
276 /* size. */
277 size = p[-1] - '0';
278 if (size == 0)
279 leading_zero = 1; /* e.g. %08x */
280 while (*p >= '0' && *p <= '9')
281 {
282 size = size * 10 + *p - '0';
283 p++;
284 }
285 goto RETRY;
286 }
287 #define inc_bp() bp = bp + strlen (bp)
288
289 case 'h':
290 {
291 unsigned u = va_arg (ap, int);
292
293 /* Hex. We can change the format to 0x%08x in
294 one place, here, if we wish.
295 We add underscores for easy reading. */
296 if (u > 65536)
297 sprintf (bp, "0x%x_%04x", u >> 16, u & 0xffff);
298 else
299 sprintf (bp, "0x%x", u);
300 inc_bp ();
301 }
302 break;
303 case 'X': case 'x':
304 {
305 int val = va_arg (ap, int);
306
307 if (size != 0)
308 if (leading_zero)
309 sprintf (bp, "%0*x", size, val);
310 else
311 sprintf (bp, "%*x", size, val);
312 else
313 sprintf (bp, "%x", val);
314 inc_bp ();
315 }
316 break;
317 case 'd':
318 {
319 int val = va_arg (ap, int);
320
321 if (size != 0)
322 sprintf (bp, "%*d", size, val);
323 else
324 sprintf (bp, "%d", val);
325 inc_bp ();
326 }
327 break;
328 case 'r':
329 {
330 /* Register. */
331 int val = va_arg (ap, int);
332
333 #define REG2NAME(num, name) case num: sprintf (bp, ""name); \
334 regMap[(num < 32) ? 0 : 1] |= 1 << (num - ((num < 32) ? 0 : 32)); break;
335
336 switch (val)
337 {
338 REG2NAME (26, "gp");
339 REG2NAME (27, "fp");
340 REG2NAME (28, "sp");
341 REG2NAME (29, "ilink1");
342 REG2NAME (30, "ilink2");
343 REG2NAME (31, "blink");
344 REG2NAME (60, "lp_count");
345 default:
346 {
347 const char * ext;
348
349 ext = core_reg_name (state, val);
350 if (ext)
351 sprintf (bp, "%s", ext);
352 else
353 sprintf (bp,"r%d",val);
354 }
355 break;
356 }
357 inc_bp ();
358 } break;
359
360 case 'a':
361 {
362 /* Aux Register. */
363 int val = va_arg (ap, int);
364
365 #define AUXREG2NAME(num, name) case num: sprintf (bp,name); break;
366
367 switch (val)
368 {
369 AUXREG2NAME (0x0, "status");
370 AUXREG2NAME (0x1, "semaphore");
371 AUXREG2NAME (0x2, "lp_start");
372 AUXREG2NAME (0x3, "lp_end");
373 AUXREG2NAME (0x4, "identity");
374 AUXREG2NAME (0x5, "debug");
375 default:
376 {
377 const char *ext;
378
379 ext = aux_reg_name (state, val);
380 if (ext)
381 sprintf (bp, "%s", ext);
382 else
383 arc_sprintf (state, bp, "%h", val);
384 }
385 break;
386 }
387 inc_bp ();
388 }
389 break;
390
391 case 's':
392 {
393 sprintf (bp, "%s", va_arg (ap, char *));
394 inc_bp ();
395 }
396 break;
397
398 default:
399 fprintf (stderr, "?? format %c\n", p[-1]);
400 break;
401 }
402 }
403
404 DOCOMM: *bp = 0;
405 va_end (ap);
406 }
407
408 static void
write_comments_(struct arcDisState * state,int shimm,int is_limm,long limm_value)409 write_comments_(struct arcDisState * state,
410 int shimm,
411 int is_limm,
412 long limm_value)
413 {
414 if (state->commentBuffer != 0)
415 {
416 int i;
417
418 if (is_limm)
419 {
420 const char *name = post_address (state, limm_value + shimm);
421
422 if (*name != 0)
423 WRITE_COMMENT (name);
424 }
425 for (i = 0; i < state->commNum; i++)
426 {
427 if (i == 0)
428 strcpy (state->commentBuffer, comment_prefix);
429 else
430 strcat (state->commentBuffer, ", ");
431 strcat (state->commentBuffer, state->comm[i]);
432 }
433 }
434 }
435
436 #define write_comments2(x) write_comments_ (state, x, is_limm, limm_value)
437 #define write_comments() write_comments2 (0)
438
439 static const char *condName[] =
440 {
441 /* 0..15. */
442 "" , "z" , "nz" , "p" , "n" , "c" , "nc" , "v" ,
443 "nv" , "gt" , "ge" , "lt" , "le" , "hi" , "ls" , "pnz"
444 };
445
446 static void
write_instr_name_(struct arcDisState * state,const char * instrName,int cond,int condCodeIsPartOfName,int flag,int signExtend,int addrWriteBack,int directMem)447 write_instr_name_(struct arcDisState * state,
448 const char * instrName,
449 int cond,
450 int condCodeIsPartOfName,
451 int flag,
452 int signExtend,
453 int addrWriteBack,
454 int directMem)
455 {
456 strcpy (state->instrBuffer, instrName);
457
458 if (cond > 0)
459 {
460 const char *cc = 0;
461
462 if (!condCodeIsPartOfName)
463 strcat (state->instrBuffer, ".");
464
465 if (cond < 16)
466 cc = condName[cond];
467 else
468 cc = cond_code_name (state, cond);
469
470 if (!cc)
471 cc = "???";
472
473 strcat (state->instrBuffer, cc);
474 }
475
476 if (flag)
477 strcat (state->instrBuffer, ".f");
478
479 switch (state->nullifyMode)
480 {
481 case BR_exec_always:
482 strcat (state->instrBuffer, ".d");
483 break;
484 case BR_exec_when_jump:
485 strcat (state->instrBuffer, ".jd");
486 break;
487 }
488
489 if (signExtend)
490 strcat (state->instrBuffer, ".x");
491
492 if (addrWriteBack)
493 strcat (state->instrBuffer, ".a");
494
495 if (directMem)
496 strcat (state->instrBuffer, ".di");
497 }
498
499 #define write_instr_name() \
500 do \
501 { \
502 write_instr_name_(state, instrName,cond, condCodeIsPartOfName, \
503 flag, signExtend, addrWriteBack, directMem); \
504 formatString[0] = '\0'; \
505 } \
506 while (0)
507
508 enum
509 {
510 op_LD0 = 0, op_LD1 = 1, op_ST = 2, op_3 = 3,
511 op_BC = 4, op_BLC = 5, op_LPC = 6, op_JC = 7,
512 op_ADD = 8, op_ADC = 9, op_SUB = 10, op_SBC = 11,
513 op_AND = 12, op_OR = 13, op_BIC = 14, op_XOR = 15
514 };
515
516 extern disassemble_info tm_print_insn_info;
517
518 static int
dsmOneArcInst(bfd_vma addr,struct arcDisState * state)519 dsmOneArcInst (bfd_vma addr, struct arcDisState * state)
520 {
521 int condCodeIsPartOfName = 0;
522 a4_decoding_class decodingClass;
523 const char * instrName;
524 int repeatsOp = 0;
525 int fieldAisReg = 1;
526 int fieldBisReg = 1;
527 int fieldCisReg = 1;
528 int fieldA;
529 int fieldB;
530 int fieldC = 0;
531 int flag = 0;
532 int cond = 0;
533 int is_shimm = 0;
534 int is_limm = 0;
535 long limm_value = 0;
536 int signExtend = 0;
537 int addrWriteBack = 0;
538 int directMem = 0;
539 int is_linked = 0;
540 int offset = 0;
541 int usesAuxReg = 0;
542 int flags;
543 int ignoreFirstOpd;
544 char formatString[60];
545
546 state->instructionLen = 4;
547 state->nullifyMode = BR_exec_when_no_jump;
548 state->opWidth = 12;
549 state->isBranch = 0;
550
551 state->_mem_load = 0;
552 state->_ea_present = 0;
553 state->_load_len = 0;
554 state->ea_reg1 = no_reg;
555 state->ea_reg2 = no_reg;
556 state->_offset = 0;
557
558 if (! NEXT_WORD (0))
559 return 0;
560
561 state->_opcode = OPCODE (state->words[0]);
562 instrName = 0;
563 decodingClass = CLASS_A4_ARITH; /* default! */
564 repeatsOp = 0;
565 condCodeIsPartOfName=0;
566 state->commNum = 0;
567 state->tcnt = 0;
568 state->acnt = 0;
569 state->flow = noflow;
570 ignoreFirstOpd = 0;
571
572 if (state->commentBuffer)
573 state->commentBuffer[0] = '\0';
574
575 switch (state->_opcode)
576 {
577 case op_LD0:
578 switch (BITS (state->words[0],1,2))
579 {
580 case 0:
581 instrName = "ld";
582 state->_load_len = 4;
583 break;
584 case 1:
585 instrName = "ldb";
586 state->_load_len = 1;
587 break;
588 case 2:
589 instrName = "ldw";
590 state->_load_len = 2;
591 break;
592 default:
593 instrName = "??? (0[3])";
594 state->flow = invalid_instr;
595 break;
596 }
597 decodingClass = CLASS_A4_LD0;
598 break;
599
600 case op_LD1:
601 if (BIT (state->words[0],13))
602 {
603 instrName = "lr";
604 decodingClass = CLASS_A4_LR;
605 }
606 else
607 {
608 switch (BITS (state->words[0], 10, 11))
609 {
610 case 0:
611 instrName = "ld";
612 state->_load_len = 4;
613 break;
614 case 1:
615 instrName = "ldb";
616 state->_load_len = 1;
617 break;
618 case 2:
619 instrName = "ldw";
620 state->_load_len = 2;
621 break;
622 default:
623 instrName = "??? (1[3])";
624 state->flow = invalid_instr;
625 break;
626 }
627 decodingClass = CLASS_A4_LD1;
628 }
629 break;
630
631 case op_ST:
632 if (BIT (state->words[0], 25))
633 {
634 instrName = "sr";
635 decodingClass = CLASS_A4_SR;
636 }
637 else
638 {
639 switch (BITS (state->words[0], 22, 23))
640 {
641 case 0:
642 instrName = "st";
643 break;
644 case 1:
645 instrName = "stb";
646 break;
647 case 2:
648 instrName = "stw";
649 break;
650 default:
651 instrName = "??? (2[3])";
652 state->flow = invalid_instr;
653 break;
654 }
655 decodingClass = CLASS_A4_ST;
656 }
657 break;
658
659 case op_3:
660 decodingClass = CLASS_A4_OP3_GENERAL; /* default for opcode 3... */
661 switch (FIELDC (state->words[0]))
662 {
663 case 0:
664 instrName = "flag";
665 decodingClass = CLASS_A4_FLAG;
666 break;
667 case 1:
668 instrName = "asr";
669 break;
670 case 2:
671 instrName = "lsr";
672 break;
673 case 3:
674 instrName = "ror";
675 break;
676 case 4:
677 instrName = "rrc";
678 break;
679 case 5:
680 instrName = "sexb";
681 break;
682 case 6:
683 instrName = "sexw";
684 break;
685 case 7:
686 instrName = "extb";
687 break;
688 case 8:
689 instrName = "extw";
690 break;
691 case 0x3f:
692 {
693 decodingClass = CLASS_A4_OP3_SUBOPC3F;
694 switch (FIELDD (state->words[0]))
695 {
696 case 0:
697 instrName = "brk";
698 break;
699 case 1:
700 instrName = "sleep";
701 break;
702 case 2:
703 instrName = "swi";
704 break;
705 default:
706 instrName = "???";
707 state->flow=invalid_instr;
708 break;
709 }
710 }
711 break;
712
713 /* ARC Extension Library Instructions
714 NOTE: We assume that extension codes are these instrs. */
715 default:
716 instrName = instruction_name (state,
717 state->_opcode,
718 FIELDC (state->words[0]),
719 &flags);
720 if (!instrName)
721 {
722 instrName = "???";
723 state->flow = invalid_instr;
724 }
725 if (flags & IGNORE_FIRST_OPD)
726 ignoreFirstOpd = 1;
727 break;
728 }
729 break;
730
731 case op_BC:
732 instrName = "b";
733 case op_BLC:
734 if (!instrName)
735 instrName = "bl";
736 case op_LPC:
737 if (!instrName)
738 instrName = "lp";
739 case op_JC:
740 if (!instrName)
741 {
742 if (BITS (state->words[0],9,9))
743 {
744 instrName = "jl";
745 is_linked = 1;
746 }
747 else
748 {
749 instrName = "j";
750 is_linked = 0;
751 }
752 }
753 condCodeIsPartOfName = 1;
754 decodingClass = ((state->_opcode == op_JC) ? CLASS_A4_JC : CLASS_A4_BRANCH );
755 state->isBranch = 1;
756 break;
757
758 case op_ADD:
759 case op_ADC:
760 case op_AND:
761 repeatsOp = (FIELDC (state->words[0]) == FIELDB (state->words[0]));
762
763 switch (state->_opcode)
764 {
765 case op_ADD:
766 instrName = (repeatsOp ? "asl" : "add");
767 break;
768 case op_ADC:
769 instrName = (repeatsOp ? "rlc" : "adc");
770 break;
771 case op_AND:
772 instrName = (repeatsOp ? "mov" : "and");
773 break;
774 }
775 break;
776
777 case op_SUB: instrName = "sub";
778 break;
779 case op_SBC: instrName = "sbc";
780 break;
781 case op_OR: instrName = "or";
782 break;
783 case op_BIC: instrName = "bic";
784 break;
785
786 case op_XOR:
787 if (state->words[0] == 0x7fffffff)
788 {
789 /* NOP encoded as xor -1, -1, -1. */
790 instrName = "nop";
791 decodingClass = CLASS_A4_OP3_SUBOPC3F;
792 }
793 else
794 instrName = "xor";
795 break;
796
797 default:
798 instrName = instruction_name (state,state->_opcode,0,&flags);
799 /* if (instrName) printf("FLAGS=0x%x\n", flags); */
800 if (!instrName)
801 {
802 instrName = "???";
803 state->flow=invalid_instr;
804 }
805 if (flags & IGNORE_FIRST_OPD)
806 ignoreFirstOpd = 1;
807 break;
808 }
809
810 fieldAisReg = fieldBisReg = fieldCisReg = 1; /* Assume regs for now. */
811 flag = cond = is_shimm = is_limm = 0;
812 state->nullifyMode = BR_exec_when_no_jump; /* 0 */
813 signExtend = addrWriteBack = directMem = 0;
814 usesAuxReg = 0;
815
816 switch (decodingClass)
817 {
818 case CLASS_A4_ARITH:
819 CHECK_FIELD_A ();
820 CHECK_FIELD_B ();
821 if (!repeatsOp)
822 CHECK_FIELD_C ();
823 CHECK_FLAG_COND_NULLIFY ();
824
825 write_instr_name ();
826 if (!ignoreFirstOpd)
827 {
828 WRITE_FORMAT_x (A);
829 WRITE_FORMAT_COMMA_x (B);
830 if (!repeatsOp)
831 WRITE_FORMAT_COMMA_x (C);
832 WRITE_NOP_COMMENT ();
833 arc_sprintf (state, state->operandBuffer, formatString,
834 fieldA, fieldB, fieldC);
835 }
836 else
837 {
838 WRITE_FORMAT_x (B);
839 if (!repeatsOp)
840 WRITE_FORMAT_COMMA_x (C);
841 arc_sprintf (state, state->operandBuffer, formatString,
842 fieldB, fieldC);
843 }
844 write_comments ();
845 break;
846
847 case CLASS_A4_OP3_GENERAL:
848 CHECK_FIELD_A ();
849 CHECK_FIELD_B ();
850 CHECK_FLAG_COND_NULLIFY ();
851
852 write_instr_name ();
853 if (!ignoreFirstOpd)
854 {
855 WRITE_FORMAT_x (A);
856 WRITE_FORMAT_COMMA_x (B);
857 WRITE_NOP_COMMENT ();
858 arc_sprintf (state, state->operandBuffer, formatString,
859 fieldA, fieldB);
860 }
861 else
862 {
863 WRITE_FORMAT_x (B);
864 arc_sprintf (state, state->operandBuffer, formatString, fieldB);
865 }
866 write_comments ();
867 break;
868
869 case CLASS_A4_FLAG:
870 CHECK_FIELD_B ();
871 CHECK_FLAG_COND_NULLIFY ();
872 flag = 0; /* This is the FLAG instruction -- it's redundant. */
873
874 write_instr_name ();
875 WRITE_FORMAT_x (B);
876 arc_sprintf (state, state->operandBuffer, formatString, fieldB);
877 write_comments ();
878 break;
879
880 case CLASS_A4_BRANCH:
881 fieldA = BITS (state->words[0],7,26) << 2;
882 fieldA = (fieldA << 10) >> 10; /* Make it signed. */
883 fieldA += addr + 4;
884 CHECK_FLAG_COND_NULLIFY ();
885 flag = 0;
886
887 write_instr_name ();
888 /* This address could be a label we know. Convert it. */
889 if (state->_opcode != op_LPC /* LP */)
890 {
891 add_target (fieldA); /* For debugger. */
892 state->flow = state->_opcode == op_BLC /* BL */
893 ? direct_call
894 : direct_jump;
895 /* indirect calls are achieved by "lr blink,[status];
896 lr dest<- func addr; j [dest]" */
897 }
898
899 strcat (formatString, "%s"); /* Address/label name. */
900 arc_sprintf (state, state->operandBuffer, formatString,
901 post_address (state, fieldA));
902 write_comments ();
903 break;
904
905 case CLASS_A4_JC:
906 /* For op_JC -- jump to address specified.
907 Also covers jump and link--bit 9 of the instr. word
908 selects whether linked, thus "is_linked" is set above. */
909 fieldA = 0;
910 CHECK_FIELD_B ();
911 CHECK_FLAG_COND_NULLIFY ();
912
913 if (!fieldBisReg)
914 {
915 fieldAisReg = 0;
916 fieldA = (fieldB >> 25) & 0x7F; /* Flags. */
917 fieldB = (fieldB & 0xFFFFFF) << 2;
918 state->flow = is_linked ? direct_call : direct_jump;
919 add_target (fieldB);
920 /* Screwy JLcc requires .jd mode to execute correctly
921 but we pretend it is .nd (no delay slot). */
922 if (is_linked && state->nullifyMode == BR_exec_when_jump)
923 state->nullifyMode = BR_exec_when_no_jump;
924 }
925 else
926 {
927 state->flow = is_linked ? indirect_call : indirect_jump;
928 /* We should also treat this as indirect call if NOT linked
929 but the preceding instruction was a "lr blink,[status]"
930 and we have a delay slot with "add blink,blink,2".
931 For now we can't detect such. */
932 state->register_for_indirect_jump = fieldB;
933 }
934
935 write_instr_name ();
936 strcat (formatString,
937 IS_REG (B) ? "[%r]" : "%s"); /* Address/label name. */
938 if (fieldA != 0)
939 {
940 fieldAisReg = 0;
941 WRITE_FORMAT_COMMA_x (A);
942 }
943 if (IS_REG (B))
944 arc_sprintf (state, state->operandBuffer, formatString, fieldB, fieldA);
945 else
946 arc_sprintf (state, state->operandBuffer, formatString,
947 post_address (state, fieldB), fieldA);
948 write_comments ();
949 break;
950
951 case CLASS_A4_LD0:
952 /* LD instruction.
953 B and C can be regs, or one (both?) can be limm. */
954 CHECK_FIELD_A ();
955 CHECK_FIELD_B ();
956 CHECK_FIELD_C ();
957 if (dbg)
958 printf ("5:b reg %d %d c reg %d %d \n",
959 fieldBisReg,fieldB,fieldCisReg,fieldC);
960 state->_offset = 0;
961 state->_ea_present = 1;
962 if (fieldBisReg)
963 state->ea_reg1 = fieldB;
964 else
965 state->_offset += fieldB;
966 if (fieldCisReg)
967 state->ea_reg2 = fieldC;
968 else
969 state->_offset += fieldC;
970 state->_mem_load = 1;
971
972 directMem = BIT (state->words[0], 5);
973 addrWriteBack = BIT (state->words[0], 3);
974 signExtend = BIT (state->words[0], 0);
975
976 write_instr_name ();
977 WRITE_FORMAT_x_COMMA_LB(A);
978 if (fieldBisReg || fieldB != 0)
979 WRITE_FORMAT_x_COMMA (B);
980 else
981 fieldB = fieldC;
982
983 WRITE_FORMAT_x_RB (C);
984 arc_sprintf (state, state->operandBuffer, formatString,
985 fieldA, fieldB, fieldC);
986 write_comments ();
987 break;
988
989 case CLASS_A4_LD1:
990 /* LD instruction. */
991 CHECK_FIELD_B ();
992 CHECK_FIELD_A ();
993 fieldC = FIELDD (state->words[0]);
994
995 if (dbg)
996 printf ("6:b reg %d %d c 0x%x \n",
997 fieldBisReg, fieldB, fieldC);
998 state->_ea_present = 1;
999 state->_offset = fieldC;
1000 state->_mem_load = 1;
1001 if (fieldBisReg)
1002 state->ea_reg1 = fieldB;
1003 /* Field B is either a shimm (same as fieldC) or limm (different!)
1004 Say ea is not present, so only one of us will do the name lookup. */
1005 else
1006 state->_offset += fieldB, state->_ea_present = 0;
1007
1008 directMem = BIT (state->words[0],14);
1009 addrWriteBack = BIT (state->words[0],12);
1010 signExtend = BIT (state->words[0],9);
1011
1012 write_instr_name ();
1013 WRITE_FORMAT_x_COMMA_LB (A);
1014 if (!fieldBisReg)
1015 {
1016 fieldB = state->_offset;
1017 WRITE_FORMAT_x_RB (B);
1018 }
1019 else
1020 {
1021 WRITE_FORMAT_x (B);
1022 if (fieldC != 0 && !BIT (state->words[0],13))
1023 {
1024 fieldCisReg = 0;
1025 WRITE_FORMAT_COMMA_x_RB (C);
1026 }
1027 else
1028 WRITE_FORMAT_RB ();
1029 }
1030 arc_sprintf (state, state->operandBuffer, formatString,
1031 fieldA, fieldB, fieldC);
1032 write_comments ();
1033 break;
1034
1035 case CLASS_A4_ST:
1036 /* ST instruction. */
1037 CHECK_FIELD_B();
1038 CHECK_FIELD_C();
1039 fieldA = FIELDD(state->words[0]); /* shimm */
1040
1041 /* [B,A offset] */
1042 if (dbg) printf("7:b reg %d %x off %x\n",
1043 fieldBisReg,fieldB,fieldA);
1044 state->_ea_present = 1;
1045 state->_offset = fieldA;
1046 if (fieldBisReg)
1047 state->ea_reg1 = fieldB;
1048 /* Field B is either a shimm (same as fieldA) or limm (different!)
1049 Say ea is not present, so only one of us will do the name lookup.
1050 (for is_limm we do the name translation here). */
1051 else
1052 state->_offset += fieldB, state->_ea_present = 0;
1053
1054 directMem = BIT (state->words[0], 26);
1055 addrWriteBack = BIT (state->words[0], 24);
1056
1057 write_instr_name ();
1058 WRITE_FORMAT_x_COMMA_LB(C);
1059
1060 if (!fieldBisReg)
1061 {
1062 fieldB = state->_offset;
1063 WRITE_FORMAT_x_RB (B);
1064 }
1065 else
1066 {
1067 WRITE_FORMAT_x (B);
1068 if (fieldBisReg && fieldA != 0)
1069 {
1070 fieldAisReg = 0;
1071 WRITE_FORMAT_COMMA_x_RB(A);
1072 }
1073 else
1074 WRITE_FORMAT_RB();
1075 }
1076 arc_sprintf (state, state->operandBuffer, formatString,
1077 fieldC, fieldB, fieldA);
1078 write_comments2 (fieldA);
1079 break;
1080
1081 case CLASS_A4_SR:
1082 /* SR instruction */
1083 CHECK_FIELD_B();
1084 CHECK_FIELD_C();
1085
1086 write_instr_name ();
1087 WRITE_FORMAT_x_COMMA_LB(C);
1088 /* Try to print B as an aux reg if it is not a core reg. */
1089 usesAuxReg = 1;
1090 WRITE_FORMAT_x (B);
1091 WRITE_FORMAT_RB ();
1092 arc_sprintf (state, state->operandBuffer, formatString, fieldC, fieldB);
1093 write_comments ();
1094 break;
1095
1096 case CLASS_A4_OP3_SUBOPC3F:
1097 write_instr_name ();
1098 state->operandBuffer[0] = '\0';
1099 break;
1100
1101 case CLASS_A4_LR:
1102 /* LR instruction */
1103 CHECK_FIELD_A ();
1104 CHECK_FIELD_B ();
1105
1106 write_instr_name ();
1107 WRITE_FORMAT_x_COMMA_LB (A);
1108 /* Try to print B as an aux reg if it is not a core reg. */
1109 usesAuxReg = 1;
1110 WRITE_FORMAT_x (B);
1111 WRITE_FORMAT_RB ();
1112 arc_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB);
1113 write_comments ();
1114 break;
1115
1116 default:
1117 mwerror (state, "Bad decoding class in ARC disassembler");
1118 break;
1119 }
1120
1121 state->_cond = cond;
1122 return state->instructionLen = offset;
1123 }
1124
1125
1126 /* Returns the name the user specified core extension register. */
1127
1128 static const char *
_coreRegName(void * arg ATTRIBUTE_UNUSED,int regval)1129 _coreRegName(void * arg ATTRIBUTE_UNUSED, int regval)
1130 {
1131 return arcExtMap_coreRegName (regval);
1132 }
1133
1134 /* Returns the name the user specified AUX extension register. */
1135
1136 static const char *
_auxRegName(void * _this ATTRIBUTE_UNUSED,int regval)1137 _auxRegName(void *_this ATTRIBUTE_UNUSED, int regval)
1138 {
1139 return arcExtMap_auxRegName(regval);
1140 }
1141
1142 /* Returns the name the user specified condition code name. */
1143
1144 static const char *
_condCodeName(void * _this ATTRIBUTE_UNUSED,int regval)1145 _condCodeName(void *_this ATTRIBUTE_UNUSED, int regval)
1146 {
1147 return arcExtMap_condCodeName(regval);
1148 }
1149
1150 /* Returns the name the user specified extension instruction. */
1151
1152 static const char *
_instName(void * _this ATTRIBUTE_UNUSED,int majop,int minop,int * flags)1153 _instName (void *_this ATTRIBUTE_UNUSED, int majop, int minop, int *flags)
1154 {
1155 return arcExtMap_instName(majop, minop, flags);
1156 }
1157
1158 /* Decode an instruction returning the size of the instruction
1159 in bytes or zero if unrecognized. */
1160
1161 static int
decodeInstr(bfd_vma address,disassemble_info * info)1162 decodeInstr (bfd_vma address, /* Address of this instruction. */
1163 disassemble_info * info)
1164 {
1165 int status;
1166 bfd_byte buffer[4];
1167 struct arcDisState s; /* ARC Disassembler state. */
1168 void *stream = info->stream; /* Output stream. */
1169 fprintf_ftype func = info->fprintf_func;
1170 int bytes;
1171
1172 memset (&s, 0, sizeof(struct arcDisState));
1173
1174 /* read first instruction */
1175 status = (*info->read_memory_func) (address, buffer, 4, info);
1176 if (status != 0)
1177 {
1178 (*info->memory_error_func) (status, address, info);
1179 return 0;
1180 }
1181 if (info->endian == BFD_ENDIAN_LITTLE)
1182 s.words[0] = bfd_getl32(buffer);
1183 else
1184 s.words[0] = bfd_getb32(buffer);
1185 /* Always read second word in case of limm. */
1186
1187 /* We ignore the result since last insn may not have a limm. */
1188 status = (*info->read_memory_func) (address + 4, buffer, 4, info);
1189 if (info->endian == BFD_ENDIAN_LITTLE)
1190 s.words[1] = bfd_getl32(buffer);
1191 else
1192 s.words[1] = bfd_getb32(buffer);
1193
1194 s._this = &s;
1195 s.coreRegName = _coreRegName;
1196 s.auxRegName = _auxRegName;
1197 s.condCodeName = _condCodeName;
1198 s.instName = _instName;
1199
1200 /* Disassemble. */
1201 bytes = dsmOneArcInst (address, (void *)& s);
1202
1203 /* Display the disassembly instruction. */
1204 (*func) (stream, "%08x ", s.words[0]);
1205 (*func) (stream, " ");
1206 (*func) (stream, "%-10s ", s.instrBuffer);
1207
1208 if (__TRANSLATION_REQUIRED (s))
1209 {
1210 bfd_vma addr = s.addresses[s.operandBuffer[1] - '0'];
1211
1212 (*info->print_address_func) ((bfd_vma) addr, info);
1213 (*func) (stream, "\n");
1214 }
1215 else
1216 (*func) (stream, "%s",s.operandBuffer);
1217
1218 return s.instructionLen;
1219 }
1220
1221 /* Return the print_insn function to use.
1222 Side effect: load (possibly empty) extension section */
1223
1224 disassembler_ftype
arc_get_disassembler(void * ptr)1225 arc_get_disassembler (void *ptr)
1226 {
1227 if (ptr)
1228 build_ARC_extmap (ptr);
1229 return decodeInstr;
1230 }
1231