1 /* ppc.h -- Header file for PowerPC opcode table 2 Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004 3 Free Software Foundation, Inc. 4 Written by Ian Lance Taylor, Cygnus Support 5 6 This file is part of GDB, GAS, and the GNU binutils. 7 8 GDB, GAS, and the GNU binutils are free software; you can redistribute 9 them and/or modify them under the terms of the GNU General Public 10 License as published by the Free Software Foundation; either version 11 1, or (at your option) any later version. 12 13 GDB, GAS, and the GNU binutils are distributed in the hope that they 14 will be useful, but WITHOUT ANY WARRANTY; without even the implied 15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 16 the GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this file; see the file COPYING. If not, write to the Free 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 21 22 #ifndef PPC_H 23 #define PPC_H 24 25 /* The opcode table is an array of struct powerpc_opcode. */ 26 27 struct powerpc_opcode 28 { 29 /* The opcode name. */ 30 const char *name; 31 32 /* The opcode itself. Those bits which will be filled in with 33 operands are zeroes. */ 34 unsigned long opcode; 35 36 /* The opcode mask. This is used by the disassembler. This is a 37 mask containing ones indicating those bits which must match the 38 opcode field, and zeroes indicating those bits which need not 39 match (and are presumably filled in by operands). */ 40 unsigned long mask; 41 42 /* One bit flags for the opcode. These are used to indicate which 43 specific processors support the instructions. The defined values 44 are listed below. */ 45 unsigned long flags; 46 47 /* An array of operand codes. Each code is an index into the 48 operand table. They appear in the order which the operands must 49 appear in assembly code, and are terminated by a zero. */ 50 unsigned char operands[8]; 51 }; 52 53 /* The table itself is sorted by major opcode number, and is otherwise 54 in the order in which the disassembler should consider 55 instructions. */ 56 extern const struct powerpc_opcode powerpc_opcodes[]; 57 extern const int powerpc_num_opcodes; 58 59 /* Values defined for the flags field of a struct powerpc_opcode. */ 60 61 /* Opcode is defined for the PowerPC architecture. */ 62 #define PPC_OPCODE_PPC 1 63 64 /* Opcode is defined for the POWER (RS/6000) architecture. */ 65 #define PPC_OPCODE_POWER 2 66 67 /* Opcode is defined for the POWER2 (Rios 2) architecture. */ 68 #define PPC_OPCODE_POWER2 4 69 70 /* Opcode is only defined on 32 bit architectures. */ 71 #define PPC_OPCODE_32 8 72 73 /* Opcode is only defined on 64 bit architectures. */ 74 #define PPC_OPCODE_64 0x10 75 76 /* Opcode is supported by the Motorola PowerPC 601 processor. The 601 77 is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions, 78 but it also supports many additional POWER instructions. */ 79 #define PPC_OPCODE_601 0x20 80 81 /* Opcode is supported in both the Power and PowerPC architectures 82 (ie, compiler's -mcpu=common or assembler's -mcom). */ 83 #define PPC_OPCODE_COMMON 0x40 84 85 /* Opcode is supported for any Power or PowerPC platform (this is 86 for the assembler's -many option, and it eliminates duplicates). */ 87 #define PPC_OPCODE_ANY 0x80 88 89 /* Opcode is supported as part of the 64-bit bridge. */ 90 #define PPC_OPCODE_64_BRIDGE 0x100 91 92 /* Opcode is supported by Altivec Vector Unit */ 93 #define PPC_OPCODE_ALTIVEC 0x200 94 95 /* Opcode is supported by PowerPC 403 processor. */ 96 #define PPC_OPCODE_403 0x400 97 98 /* Opcode is supported by PowerPC BookE processor. */ 99 #define PPC_OPCODE_BOOKE 0x800 100 101 /* Opcode is only supported by 64-bit PowerPC BookE processor. */ 102 #define PPC_OPCODE_BOOKE64 0x1000 103 104 /* Opcode is supported by PowerPC 440 processor. */ 105 #define PPC_OPCODE_440 0x2000 106 107 /* Opcode is only supported by Power4 architecture. */ 108 #define PPC_OPCODE_POWER4 0x4000 109 110 /* Opcode isn't supported by Power4 architecture. */ 111 #define PPC_OPCODE_NOPOWER4 0x8000 112 113 /* Opcode is only supported by POWERPC Classic architecture. */ 114 #define PPC_OPCODE_CLASSIC 0x10000 115 116 /* Opcode is only supported by e500x2 Core. */ 117 #define PPC_OPCODE_SPE 0x20000 118 119 /* Opcode is supported by e500x2 Integer select APU. */ 120 #define PPC_OPCODE_ISEL 0x40000 121 122 /* Opcode is an e500 SPE floating point instruction. */ 123 #define PPC_OPCODE_EFS 0x80000 124 125 /* Opcode is supported by branch locking APU. */ 126 #define PPC_OPCODE_BRLOCK 0x100000 127 128 /* Opcode is supported by performance monitor APU. */ 129 #define PPC_OPCODE_PMR 0x200000 130 131 /* Opcode is supported by cache locking APU. */ 132 #define PPC_OPCODE_CACHELCK 0x400000 133 134 /* Opcode is supported by machine check APU. */ 135 #define PPC_OPCODE_RFMCI 0x800000 136 137 /* Opcode is only supported by Power5 architecture. */ 138 #define PPC_OPCODE_POWER5 0x1000000 139 140 /* A macro to extract the major opcode from an instruction. */ 141 #define PPC_OP(i) (((i) >> 26) & 0x3f) 142 143 /* The operands table is an array of struct powerpc_operand. */ 144 145 struct powerpc_operand 146 { 147 /* The number of bits in the operand. */ 148 int bits; 149 150 /* How far the operand is left shifted in the instruction. */ 151 int shift; 152 153 /* Insertion function. This is used by the assembler. To insert an 154 operand value into an instruction, check this field. 155 156 If it is NULL, execute 157 i |= (op & ((1 << o->bits) - 1)) << o->shift; 158 (i is the instruction which we are filling in, o is a pointer to 159 this structure, and op is the opcode value; this assumes twos 160 complement arithmetic). 161 162 If this field is not NULL, then simply call it with the 163 instruction and the operand value. It will return the new value 164 of the instruction. If the ERRMSG argument is not NULL, then if 165 the operand value is illegal, *ERRMSG will be set to a warning 166 string (the operand will be inserted in any case). If the 167 operand value is legal, *ERRMSG will be unchanged (most operands 168 can accept any value). */ 169 unsigned long (*insert) 170 (unsigned long instruction, long op, int dialect, const char **errmsg); 171 172 /* Extraction function. This is used by the disassembler. To 173 extract this operand type from an instruction, check this field. 174 175 If it is NULL, compute 176 op = ((i) >> o->shift) & ((1 << o->bits) - 1); 177 if ((o->flags & PPC_OPERAND_SIGNED) != 0 178 && (op & (1 << (o->bits - 1))) != 0) 179 op -= 1 << o->bits; 180 (i is the instruction, o is a pointer to this structure, and op 181 is the result; this assumes twos complement arithmetic). 182 183 If this field is not NULL, then simply call it with the 184 instruction value. It will return the value of the operand. If 185 the INVALID argument is not NULL, *INVALID will be set to 186 non-zero if this operand type can not actually be extracted from 187 this operand (i.e., the instruction does not match). If the 188 operand is valid, *INVALID will not be changed. */ 189 long (*extract) (unsigned long instruction, int dialect, int *invalid); 190 191 /* One bit syntax flags. */ 192 unsigned long flags; 193 }; 194 195 /* Elements in the table are retrieved by indexing with values from 196 the operands field of the powerpc_opcodes table. */ 197 198 extern const struct powerpc_operand powerpc_operands[]; 199 200 /* Values defined for the flags field of a struct powerpc_operand. */ 201 202 /* This operand takes signed values. */ 203 #define PPC_OPERAND_SIGNED (01) 204 205 /* This operand takes signed values, but also accepts a full positive 206 range of values when running in 32 bit mode. That is, if bits is 207 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode, 208 this flag is ignored. */ 209 #define PPC_OPERAND_SIGNOPT (02) 210 211 /* This operand does not actually exist in the assembler input. This 212 is used to support extended mnemonics such as mr, for which two 213 operands fields are identical. The assembler should call the 214 insert function with any op value. The disassembler should call 215 the extract function, ignore the return value, and check the value 216 placed in the valid argument. */ 217 #define PPC_OPERAND_FAKE (04) 218 219 /* The next operand should be wrapped in parentheses rather than 220 separated from this one by a comma. This is used for the load and 221 store instructions which want their operands to look like 222 reg,displacement(reg) 223 */ 224 #define PPC_OPERAND_PARENS (010) 225 226 /* This operand may use the symbolic names for the CR fields, which 227 are 228 lt 0 gt 1 eq 2 so 3 un 3 229 cr0 0 cr1 1 cr2 2 cr3 3 230 cr4 4 cr5 5 cr6 6 cr7 7 231 These may be combined arithmetically, as in cr2*4+gt. These are 232 only supported on the PowerPC, not the POWER. */ 233 #define PPC_OPERAND_CR (020) 234 235 /* This operand names a register. The disassembler uses this to print 236 register names with a leading 'r'. */ 237 #define PPC_OPERAND_GPR (040) 238 239 /* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */ 240 #define PPC_OPERAND_GPR_0 (0100) 241 242 /* This operand names a floating point register. The disassembler 243 prints these with a leading 'f'. */ 244 #define PPC_OPERAND_FPR (0200) 245 246 /* This operand is a relative branch displacement. The disassembler 247 prints these symbolically if possible. */ 248 #define PPC_OPERAND_RELATIVE (0400) 249 250 /* This operand is an absolute branch address. The disassembler 251 prints these symbolically if possible. */ 252 #define PPC_OPERAND_ABSOLUTE (01000) 253 254 /* This operand is optional, and is zero if omitted. This is used for 255 example, in the optional BF field in the comparison instructions. The 256 assembler must count the number of operands remaining on the line, 257 and the number of operands remaining for the opcode, and decide 258 whether this operand is present or not. The disassembler should 259 print this operand out only if it is not zero. */ 260 #define PPC_OPERAND_OPTIONAL (02000) 261 262 /* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand 263 is omitted, then for the next operand use this operand value plus 264 1, ignoring the next operand field for the opcode. This wretched 265 hack is needed because the Power rotate instructions can take 266 either 4 or 5 operands. The disassembler should print this operand 267 out regardless of the PPC_OPERAND_OPTIONAL field. */ 268 #define PPC_OPERAND_NEXT (04000) 269 270 /* This operand should be regarded as a negative number for the 271 purposes of overflow checking (i.e., the normal most negative 272 number is disallowed and one more than the normal most positive 273 number is allowed). This flag will only be set for a signed 274 operand. */ 275 #define PPC_OPERAND_NEGATIVE (010000) 276 277 /* This operand names a vector unit register. The disassembler 278 prints these with a leading 'v'. */ 279 #define PPC_OPERAND_VR (020000) 280 281 /* This operand is for the DS field in a DS form instruction. */ 282 #define PPC_OPERAND_DS (040000) 283 284 /* This operand is for the DQ field in a DQ form instruction. */ 285 #define PPC_OPERAND_DQ (0100000) 286 287 /* The POWER and PowerPC assemblers use a few macros. We keep them 288 with the operands table for simplicity. The macro table is an 289 array of struct powerpc_macro. */ 290 291 struct powerpc_macro 292 { 293 /* The macro name. */ 294 const char *name; 295 296 /* The number of operands the macro takes. */ 297 unsigned int operands; 298 299 /* One bit flags for the opcode. These are used to indicate which 300 specific processors support the instructions. The values are the 301 same as those for the struct powerpc_opcode flags field. */ 302 unsigned long flags; 303 304 /* A format string to turn the macro into a normal instruction. 305 Each %N in the string is replaced with operand number N (zero 306 based). */ 307 const char *format; 308 }; 309 310 extern const struct powerpc_macro powerpc_macros[]; 311 extern const int powerpc_num_macros; 312 313 #endif /* PPC_H */ 314