1 /* Target-dependent code for Renesas Super-H, for GDB.
2
3 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
4 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
22
23 /*
24 Contributed by Steve Chamberlain
25 sac@cygnus.com
26 */
27
28 #include "defs.h"
29 #include "frame.h"
30 #include "frame-base.h"
31 #include "frame-unwind.h"
32 #include "dwarf2-frame.h"
33 #include "symtab.h"
34 #include "gdbtypes.h"
35 #include "gdbcmd.h"
36 #include "gdbcore.h"
37 #include "value.h"
38 #include "dis-asm.h"
39 #include "inferior.h"
40 #include "gdb_string.h"
41 #include "gdb_assert.h"
42 #include "arch-utils.h"
43 #include "regcache.h"
44 #include "osabi.h"
45
46 #include "elf-bfd.h"
47
48 /* sh flags */
49 #include "elf/sh.h"
50 /* registers numbers shared with the simulator */
51 #include "gdb/sim-sh.h"
52
53 /* Information that is dependent on the processor variant. */
54 enum sh_abi
55 {
56 SH_ABI_UNKNOWN,
57 SH_ABI_32,
58 SH_ABI_64
59 };
60
61 struct gdbarch_tdep
62 {
63 enum sh_abi sh_abi;
64 };
65
66 struct sh64_frame_cache
67 {
68 /* Base address. */
69 CORE_ADDR base;
70 LONGEST sp_offset;
71 CORE_ADDR pc;
72
73 /* Flag showing that a frame has been created in the prologue code. */
74 int uses_fp;
75
76 int media_mode;
77
78 /* Saved registers. */
79 CORE_ADDR saved_regs[SIM_SH64_NR_REGS];
80 CORE_ADDR saved_sp;
81 };
82
83 /* Registers of SH5 */
84 enum
85 {
86 R0_REGNUM = 0,
87 DEFAULT_RETURN_REGNUM = 2,
88 STRUCT_RETURN_REGNUM = 2,
89 ARG0_REGNUM = 2,
90 ARGLAST_REGNUM = 9,
91 FLOAT_ARGLAST_REGNUM = 11,
92 MEDIA_FP_REGNUM = 14,
93 PR_REGNUM = 18,
94 SR_REGNUM = 65,
95 DR0_REGNUM = 141,
96 DR_LAST_REGNUM = 172,
97 /* FPP stands for Floating Point Pair, to avoid confusion with
98 GDB's FP0_REGNUM, which is the number of the first Floating
99 point register. Unfortunately on the sh5, the floating point
100 registers are called FR, and the floating point pairs are called FP. */
101 FPP0_REGNUM = 173,
102 FPP_LAST_REGNUM = 204,
103 FV0_REGNUM = 205,
104 FV_LAST_REGNUM = 220,
105 R0_C_REGNUM = 221,
106 R_LAST_C_REGNUM = 236,
107 PC_C_REGNUM = 237,
108 GBR_C_REGNUM = 238,
109 MACH_C_REGNUM = 239,
110 MACL_C_REGNUM = 240,
111 PR_C_REGNUM = 241,
112 T_C_REGNUM = 242,
113 FPSCR_C_REGNUM = 243,
114 FPUL_C_REGNUM = 244,
115 FP0_C_REGNUM = 245,
116 FP_LAST_C_REGNUM = 260,
117 DR0_C_REGNUM = 261,
118 DR_LAST_C_REGNUM = 268,
119 FV0_C_REGNUM = 269,
120 FV_LAST_C_REGNUM = 272,
121 FPSCR_REGNUM = SIM_SH64_FPCSR_REGNUM,
122 SSR_REGNUM = SIM_SH64_SSR_REGNUM,
123 SPC_REGNUM = SIM_SH64_SPC_REGNUM,
124 TR7_REGNUM = SIM_SH64_TR0_REGNUM + 7,
125 FP_LAST_REGNUM = SIM_SH64_FR0_REGNUM + SIM_SH64_NR_FP_REGS - 1
126 };
127
128 static const char *
sh64_register_name(int reg_nr)129 sh64_register_name (int reg_nr)
130 {
131 static char *register_names[] =
132 {
133 /* SH MEDIA MODE (ISA 32) */
134 /* general registers (64-bit) 0-63 */
135 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
136 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
137 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
138 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
139 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
140 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
141 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
142 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
143
144 /* pc (64-bit) 64 */
145 "pc",
146
147 /* status reg., saved status reg., saved pc reg. (64-bit) 65-67 */
148 "sr", "ssr", "spc",
149
150 /* target registers (64-bit) 68-75*/
151 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7",
152
153 /* floating point state control register (32-bit) 76 */
154 "fpscr",
155
156 /* single precision floating point registers (32-bit) 77-140*/
157 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
158 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
159 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23",
160 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31",
161 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39",
162 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47",
163 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55",
164 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63",
165
166 /* double precision registers (pseudo) 141-172 */
167 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
168 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30",
169 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46",
170 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62",
171
172 /* floating point pairs (pseudo) 173-204*/
173 "fp0", "fp2", "fp4", "fp6", "fp8", "fp10", "fp12", "fp14",
174 "fp16", "fp18", "fp20", "fp22", "fp24", "fp26", "fp28", "fp30",
175 "fp32", "fp34", "fp36", "fp38", "fp40", "fp42", "fp44", "fp46",
176 "fp48", "fp50", "fp52", "fp54", "fp56", "fp58", "fp60", "fp62",
177
178 /* floating point vectors (4 floating point regs) (pseudo) 205-220*/
179 "fv0", "fv4", "fv8", "fv12", "fv16", "fv20", "fv24", "fv28",
180 "fv32", "fv36", "fv40", "fv44", "fv48", "fv52", "fv56", "fv60",
181
182 /* SH COMPACT MODE (ISA 16) (all pseudo) 221-272*/
183 "r0_c", "r1_c", "r2_c", "r3_c", "r4_c", "r5_c", "r6_c", "r7_c",
184 "r8_c", "r9_c", "r10_c", "r11_c", "r12_c", "r13_c", "r14_c", "r15_c",
185 "pc_c",
186 "gbr_c", "mach_c", "macl_c", "pr_c", "t_c",
187 "fpscr_c", "fpul_c",
188 "fr0_c", "fr1_c", "fr2_c", "fr3_c", "fr4_c", "fr5_c", "fr6_c", "fr7_c",
189 "fr8_c", "fr9_c", "fr10_c", "fr11_c", "fr12_c", "fr13_c", "fr14_c", "fr15_c",
190 "dr0_c", "dr2_c", "dr4_c", "dr6_c", "dr8_c", "dr10_c", "dr12_c", "dr14_c",
191 "fv0_c", "fv4_c", "fv8_c", "fv12_c",
192 /* FIXME!!!! XF0 XF15, XD0 XD14 ?????*/
193 };
194
195 if (reg_nr < 0)
196 return NULL;
197 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
198 return NULL;
199 return register_names[reg_nr];
200 }
201
202 #define NUM_PSEUDO_REGS_SH_MEDIA 80
203 #define NUM_PSEUDO_REGS_SH_COMPACT 51
204
205 /* Macros and functions for setting and testing a bit in a minimal
206 symbol that marks it as 32-bit function. The MSB of the minimal
207 symbol's "info" field is used for this purpose.
208
209 ELF_MAKE_MSYMBOL_SPECIAL
210 tests whether an ELF symbol is "special", i.e. refers
211 to a 32-bit function, and sets a "special" bit in a
212 minimal symbol to mark it as a 32-bit function
213 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
214
215 #define MSYMBOL_IS_SPECIAL(msym) \
216 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
217
218 static void
sh64_elf_make_msymbol_special(asymbol * sym,struct minimal_symbol * msym)219 sh64_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym)
220 {
221 if (msym == NULL)
222 return;
223
224 if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_SH5_ISA32)
225 {
226 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) | 0x80000000);
227 SYMBOL_VALUE_ADDRESS (msym) |= 1;
228 }
229 }
230
231 /* ISA32 (shmedia) function addresses are odd (bit 0 is set). Here
232 are some macros to test, set, or clear bit 0 of addresses. */
233 #define IS_ISA32_ADDR(addr) ((addr) & 1)
234 #define MAKE_ISA32_ADDR(addr) ((addr) | 1)
235 #define UNMAKE_ISA32_ADDR(addr) ((addr) & ~1)
236
237 static int
pc_is_isa32(bfd_vma memaddr)238 pc_is_isa32 (bfd_vma memaddr)
239 {
240 struct minimal_symbol *sym;
241
242 /* If bit 0 of the address is set, assume this is a
243 ISA32 (shmedia) address. */
244 if (IS_ISA32_ADDR (memaddr))
245 return 1;
246
247 /* A flag indicating that this is a ISA32 function is stored by elfread.c in
248 the high bit of the info field. Use this to decide if the function is
249 ISA16 or ISA32. */
250 sym = lookup_minimal_symbol_by_pc (memaddr);
251 if (sym)
252 return MSYMBOL_IS_SPECIAL (sym);
253 else
254 return 0;
255 }
256
257 static const unsigned char *
sh64_breakpoint_from_pc(CORE_ADDR * pcptr,int * lenptr)258 sh64_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
259 {
260 /* The BRK instruction for shmedia is
261 01101111 11110101 11111111 11110000
262 which translates in big endian mode to 0x6f, 0xf5, 0xff, 0xf0
263 and in little endian mode to 0xf0, 0xff, 0xf5, 0x6f */
264
265 /* The BRK instruction for shcompact is
266 00000000 00111011
267 which translates in big endian mode to 0x0, 0x3b
268 and in little endian mode to 0x3b, 0x0*/
269
270 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
271 {
272 if (pc_is_isa32 (*pcptr))
273 {
274 static unsigned char big_breakpoint_media[] = {0x6f, 0xf5, 0xff, 0xf0};
275 *pcptr = UNMAKE_ISA32_ADDR (*pcptr);
276 *lenptr = sizeof (big_breakpoint_media);
277 return big_breakpoint_media;
278 }
279 else
280 {
281 static unsigned char big_breakpoint_compact[] = {0x0, 0x3b};
282 *lenptr = sizeof (big_breakpoint_compact);
283 return big_breakpoint_compact;
284 }
285 }
286 else
287 {
288 if (pc_is_isa32 (*pcptr))
289 {
290 static unsigned char little_breakpoint_media[] = {0xf0, 0xff, 0xf5, 0x6f};
291 *pcptr = UNMAKE_ISA32_ADDR (*pcptr);
292 *lenptr = sizeof (little_breakpoint_media);
293 return little_breakpoint_media;
294 }
295 else
296 {
297 static unsigned char little_breakpoint_compact[] = {0x3b, 0x0};
298 *lenptr = sizeof (little_breakpoint_compact);
299 return little_breakpoint_compact;
300 }
301 }
302 }
303
304 /* Prologue looks like
305 [mov.l <regs>,@-r15]...
306 [sts.l pr,@-r15]
307 [mov.l r14,@-r15]
308 [mov r15,r14]
309
310 Actually it can be more complicated than this. For instance, with
311 newer gcc's:
312
313 mov.l r14,@-r15
314 add #-12,r15
315 mov r15,r14
316 mov r4,r1
317 mov r5,r2
318 mov.l r6,@(4,r14)
319 mov.l r7,@(8,r14)
320 mov.b r1,@r14
321 mov r14,r1
322 mov r14,r1
323 add #2,r1
324 mov.w r2,@r1
325
326 */
327
328 /* PTABS/L Rn, TRa 0110101111110001nnnnnnl00aaa0000
329 with l=1 and n = 18 0110101111110001010010100aaa0000 */
330 #define IS_PTABSL_R18(x) (((x) & 0xffffff8f) == 0x6bf14a00)
331
332 /* STS.L PR,@-r0 0100000000100010
333 r0-4-->r0, PR-->(r0) */
334 #define IS_STS_R0(x) ((x) == 0x4022)
335
336 /* STS PR, Rm 0000mmmm00101010
337 PR-->Rm */
338 #define IS_STS_PR(x) (((x) & 0xf0ff) == 0x2a)
339
340 /* MOV.L Rm,@(disp,r15) 00011111mmmmdddd
341 Rm-->(dispx4+r15) */
342 #define IS_MOV_TO_R15(x) (((x) & 0xff00) == 0x1f00)
343
344 /* MOV.L R14,@(disp,r15) 000111111110dddd
345 R14-->(dispx4+r15) */
346 #define IS_MOV_R14(x) (((x) & 0xfff0) == 0x1fe0)
347
348 /* ST.Q R14, disp, R18 101011001110dddddddddd0100100000
349 R18-->(dispx8+R14) */
350 #define IS_STQ_R18_R14(x) (((x) & 0xfff003ff) == 0xace00120)
351
352 /* ST.Q R15, disp, R18 101011001111dddddddddd0100100000
353 R18-->(dispx8+R15) */
354 #define IS_STQ_R18_R15(x) (((x) & 0xfff003ff) == 0xacf00120)
355
356 /* ST.L R15, disp, R18 101010001111dddddddddd0100100000
357 R18-->(dispx4+R15) */
358 #define IS_STL_R18_R15(x) (((x) & 0xfff003ff) == 0xa8f00120)
359
360 /* ST.Q R15, disp, R14 1010 1100 1111 dddd dddd dd00 1110 0000
361 R14-->(dispx8+R15) */
362 #define IS_STQ_R14_R15(x) (((x) & 0xfff003ff) == 0xacf000e0)
363
364 /* ST.L R15, disp, R14 1010 1000 1111 dddd dddd dd00 1110 0000
365 R14-->(dispx4+R15) */
366 #define IS_STL_R14_R15(x) (((x) & 0xfff003ff) == 0xa8f000e0)
367
368 /* ADDI.L R15,imm,R15 1101 0100 1111 ssss ssss ss00 1111 0000
369 R15 + imm --> R15 */
370 #define IS_ADDIL_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd4f000f0)
371
372 /* ADDI R15,imm,R15 1101 0000 1111 ssss ssss ss00 1111 0000
373 R15 + imm --> R15 */
374 #define IS_ADDI_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd0f000f0)
375
376 /* ADD.L R15,R63,R14 0000 0000 1111 1000 1111 1100 1110 0000
377 R15 + R63 --> R14 */
378 #define IS_ADDL_SP_FP_MEDIA(x) ((x) == 0x00f8fce0)
379
380 /* ADD R15,R63,R14 0000 0000 1111 1001 1111 1100 1110 0000
381 R15 + R63 --> R14 */
382 #define IS_ADD_SP_FP_MEDIA(x) ((x) == 0x00f9fce0)
383
384 #define IS_MOV_SP_FP_MEDIA(x) (IS_ADDL_SP_FP_MEDIA(x) || IS_ADD_SP_FP_MEDIA(x))
385
386 /* MOV #imm, R0 1110 0000 ssss ssss
387 #imm-->R0 */
388 #define IS_MOV_R0(x) (((x) & 0xff00) == 0xe000)
389
390 /* MOV.L @(disp,PC), R0 1101 0000 iiii iiii */
391 #define IS_MOVL_R0(x) (((x) & 0xff00) == 0xd000)
392
393 /* ADD r15,r0 0011 0000 1111 1100
394 r15+r0-->r0 */
395 #define IS_ADD_SP_R0(x) ((x) == 0x30fc)
396
397 /* MOV.L R14 @-R0 0010 0000 1110 0110
398 R14-->(R0-4), R0-4-->R0 */
399 #define IS_MOV_R14_R0(x) ((x) == 0x20e6)
400
401 /* ADD Rm,R63,Rn Rm+R63-->Rn 0000 00mm mmmm 1001 1111 11nn nnnn 0000
402 where Rm is one of r2-r9 which are the argument registers. */
403 /* FIXME: Recognize the float and double register moves too! */
404 #define IS_MEDIA_IND_ARG_MOV(x) \
405 ((((x) & 0xfc0ffc0f) == 0x0009fc00) && (((x) & 0x03f00000) >= 0x00200000 && ((x) & 0x03f00000) <= 0x00900000))
406
407 /* ST.Q Rn,0,Rm Rm-->Rn+0 1010 11nn nnnn 0000 0000 00mm mmmm 0000
408 or ST.L Rn,0,Rm Rm-->Rn+0 1010 10nn nnnn 0000 0000 00mm mmmm 0000
409 where Rm is one of r2-r9 which are the argument registers. */
410 #define IS_MEDIA_ARG_MOV(x) \
411 (((((x) & 0xfc0ffc0f) == 0xac000000) || (((x) & 0xfc0ffc0f) == 0xa8000000)) \
412 && (((x) & 0x000003f0) >= 0x00000020 && ((x) & 0x000003f0) <= 0x00000090))
413
414 /* ST.B R14,0,Rn Rn-->(R14+0) 1010 0000 1110 0000 0000 00nn nnnn 0000*/
415 /* ST.W R14,0,Rn Rn-->(R14+0) 1010 0100 1110 0000 0000 00nn nnnn 0000*/
416 /* ST.L R14,0,Rn Rn-->(R14+0) 1010 1000 1110 0000 0000 00nn nnnn 0000*/
417 /* FST.S R14,0,FRn Rn-->(R14+0) 1011 0100 1110 0000 0000 00nn nnnn 0000*/
418 /* FST.D R14,0,DRn Rn-->(R14+0) 1011 1100 1110 0000 0000 00nn nnnn 0000*/
419 #define IS_MEDIA_MOV_TO_R14(x) \
420 ((((x) & 0xfffffc0f) == 0xa0e00000) \
421 || (((x) & 0xfffffc0f) == 0xa4e00000) \
422 || (((x) & 0xfffffc0f) == 0xa8e00000) \
423 || (((x) & 0xfffffc0f) == 0xb4e00000) \
424 || (((x) & 0xfffffc0f) == 0xbce00000))
425
426 /* MOV Rm, Rn Rm-->Rn 0110 nnnn mmmm 0011
427 where Rm is r2-r9 */
428 #define IS_COMPACT_IND_ARG_MOV(x) \
429 ((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0020) && (((x) & 0x00f0) <= 0x0090))
430
431 /* compact direct arg move!
432 MOV.L Rn, @r14 0010 1110 mmmm 0010 */
433 #define IS_COMPACT_ARG_MOV(x) \
434 (((((x) & 0xff0f) == 0x2e02) && (((x) & 0x00f0) >= 0x0020) && ((x) & 0x00f0) <= 0x0090))
435
436 /* MOV.B Rm, @R14 0010 1110 mmmm 0000
437 MOV.W Rm, @R14 0010 1110 mmmm 0001 */
438 #define IS_COMPACT_MOV_TO_R14(x) \
439 ((((x) & 0xff0f) == 0x2e00) || (((x) & 0xff0f) == 0x2e01))
440
441 #define IS_JSR_R0(x) ((x) == 0x400b)
442 #define IS_NOP(x) ((x) == 0x0009)
443
444
445 /* MOV r15,r14 0110111011110011
446 r15-->r14 */
447 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
448
449 /* ADD #imm,r15 01111111iiiiiiii
450 r15+imm-->r15 */
451 #define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00)
452
453 /* Skip any prologue before the guts of a function */
454
455 /* Skip the prologue using the debug information. If this fails we'll
456 fall back on the 'guess' method below. */
457 static CORE_ADDR
after_prologue(CORE_ADDR pc)458 after_prologue (CORE_ADDR pc)
459 {
460 struct symtab_and_line sal;
461 CORE_ADDR func_addr, func_end;
462
463 /* If we can not find the symbol in the partial symbol table, then
464 there is no hope we can determine the function's start address
465 with this code. */
466 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
467 return 0;
468
469
470 /* Get the line associated with FUNC_ADDR. */
471 sal = find_pc_line (func_addr, 0);
472
473 /* There are only two cases to consider. First, the end of the source line
474 is within the function bounds. In that case we return the end of the
475 source line. Second is the end of the source line extends beyond the
476 bounds of the current function. We need to use the slow code to
477 examine instructions in that case. */
478 if (sal.end < func_end)
479 return sal.end;
480 else
481 return 0;
482 }
483
484 static CORE_ADDR
look_for_args_moves(CORE_ADDR start_pc,int media_mode)485 look_for_args_moves (CORE_ADDR start_pc, int media_mode)
486 {
487 CORE_ADDR here, end;
488 int w;
489 int insn_size = (media_mode ? 4 : 2);
490
491 for (here = start_pc, end = start_pc + (insn_size * 28); here < end;)
492 {
493 if (media_mode)
494 {
495 w = read_memory_integer (UNMAKE_ISA32_ADDR (here), insn_size);
496 here += insn_size;
497 if (IS_MEDIA_IND_ARG_MOV (w))
498 {
499 /* This must be followed by a store to r14, so the argument
500 is where the debug info says it is. This can happen after
501 the SP has been saved, unfortunately. */
502
503 int next_insn = read_memory_integer (UNMAKE_ISA32_ADDR (here),
504 insn_size);
505 here += insn_size;
506 if (IS_MEDIA_MOV_TO_R14 (next_insn))
507 start_pc = here;
508 }
509 else if (IS_MEDIA_ARG_MOV (w))
510 {
511 /* These instructions store directly the argument in r14. */
512 start_pc = here;
513 }
514 else
515 break;
516 }
517 else
518 {
519 w = read_memory_integer (here, insn_size);
520 w = w & 0xffff;
521 here += insn_size;
522 if (IS_COMPACT_IND_ARG_MOV (w))
523 {
524 /* This must be followed by a store to r14, so the argument
525 is where the debug info says it is. This can happen after
526 the SP has been saved, unfortunately. */
527
528 int next_insn = 0xffff & read_memory_integer (here, insn_size);
529 here += insn_size;
530 if (IS_COMPACT_MOV_TO_R14 (next_insn))
531 start_pc = here;
532 }
533 else if (IS_COMPACT_ARG_MOV (w))
534 {
535 /* These instructions store directly the argument in r14. */
536 start_pc = here;
537 }
538 else if (IS_MOVL_R0 (w))
539 {
540 /* There is a function that gcc calls to get the arguments
541 passed correctly to the function. Only after this
542 function call the arguments will be found at the place
543 where they are supposed to be. This happens in case the
544 argument has to be stored into a 64-bit register (for
545 instance doubles, long longs). SHcompact doesn't have
546 access to the full 64-bits, so we store the register in
547 stack slot and store the address of the stack slot in
548 the register, then do a call through a wrapper that
549 loads the memory value into the register. A SHcompact
550 callee calls an argument decoder
551 (GCC_shcompact_incoming_args) that stores the 64-bit
552 value in a stack slot and stores the address of the
553 stack slot in the register. GCC thinks the argument is
554 just passed by transparent reference, but this is only
555 true after the argument decoder is called. Such a call
556 needs to be considered part of the prologue. */
557
558 /* This must be followed by a JSR @r0 instruction and by
559 a NOP instruction. After these, the prologue is over! */
560
561 int next_insn = 0xffff & read_memory_integer (here, insn_size);
562 here += insn_size;
563 if (IS_JSR_R0 (next_insn))
564 {
565 next_insn = 0xffff & read_memory_integer (here, insn_size);
566 here += insn_size;
567
568 if (IS_NOP (next_insn))
569 start_pc = here;
570 }
571 }
572 else
573 break;
574 }
575 }
576
577 return start_pc;
578 }
579
580 static CORE_ADDR
sh64_skip_prologue_hard_way(CORE_ADDR start_pc)581 sh64_skip_prologue_hard_way (CORE_ADDR start_pc)
582 {
583 CORE_ADDR here, end;
584 int updated_fp = 0;
585 int insn_size = 4;
586 int media_mode = 1;
587
588 if (!start_pc)
589 return 0;
590
591 if (pc_is_isa32 (start_pc) == 0)
592 {
593 insn_size = 2;
594 media_mode = 0;
595 }
596
597 for (here = start_pc, end = start_pc + (insn_size * 28); here < end;)
598 {
599
600 if (media_mode)
601 {
602 int w = read_memory_integer (UNMAKE_ISA32_ADDR (here), insn_size);
603 here += insn_size;
604 if (IS_STQ_R18_R14 (w) || IS_STQ_R18_R15 (w) || IS_STQ_R14_R15 (w)
605 || IS_STL_R14_R15 (w) || IS_STL_R18_R15 (w)
606 || IS_ADDIL_SP_MEDIA (w) || IS_ADDI_SP_MEDIA (w) || IS_PTABSL_R18 (w))
607 {
608 start_pc = here;
609 }
610 else if (IS_MOV_SP_FP (w) || IS_MOV_SP_FP_MEDIA(w))
611 {
612 start_pc = here;
613 updated_fp = 1;
614 }
615 else
616 if (updated_fp)
617 {
618 /* Don't bail out yet, we may have arguments stored in
619 registers here, according to the debug info, so that
620 gdb can print the frames correctly. */
621 start_pc = look_for_args_moves (here - insn_size, media_mode);
622 break;
623 }
624 }
625 else
626 {
627 int w = 0xffff & read_memory_integer (here, insn_size);
628 here += insn_size;
629
630 if (IS_STS_R0 (w) || IS_STS_PR (w)
631 || IS_MOV_TO_R15 (w) || IS_MOV_R14 (w)
632 || IS_MOV_R0 (w) || IS_ADD_SP_R0 (w) || IS_MOV_R14_R0 (w))
633 {
634 start_pc = here;
635 }
636 else if (IS_MOV_SP_FP (w))
637 {
638 start_pc = here;
639 updated_fp = 1;
640 }
641 else
642 if (updated_fp)
643 {
644 /* Don't bail out yet, we may have arguments stored in
645 registers here, according to the debug info, so that
646 gdb can print the frames correctly. */
647 start_pc = look_for_args_moves (here - insn_size, media_mode);
648 break;
649 }
650 }
651 }
652
653 return start_pc;
654 }
655
656 static CORE_ADDR
sh64_skip_prologue(CORE_ADDR pc)657 sh64_skip_prologue (CORE_ADDR pc)
658 {
659 CORE_ADDR post_prologue_pc;
660
661 /* See if we can determine the end of the prologue via the symbol table.
662 If so, then return either PC, or the PC after the prologue, whichever
663 is greater. */
664 post_prologue_pc = after_prologue (pc);
665
666 /* If after_prologue returned a useful address, then use it. Else
667 fall back on the instruction skipping code. */
668 if (post_prologue_pc != 0)
669 return max (pc, post_prologue_pc);
670 else
671 return sh64_skip_prologue_hard_way (pc);
672 }
673
674 /* Should call_function allocate stack space for a struct return? */
675 static int
sh64_use_struct_convention(struct type * type)676 sh64_use_struct_convention (struct type *type)
677 {
678 return (TYPE_LENGTH (type) > 8);
679 }
680
681 /* Disassemble an instruction. */
682 static int
gdb_print_insn_sh64(bfd_vma memaddr,disassemble_info * info)683 gdb_print_insn_sh64 (bfd_vma memaddr, disassemble_info *info)
684 {
685 info->endian = TARGET_BYTE_ORDER;
686 return print_insn_sh (memaddr, info);
687 }
688
689 /* For vectors of 4 floating point registers. */
690 static int
sh64_fv_reg_base_num(int fv_regnum)691 sh64_fv_reg_base_num (int fv_regnum)
692 {
693 int fp_regnum;
694
695 fp_regnum = FP0_REGNUM +
696 (fv_regnum - FV0_REGNUM) * 4;
697 return fp_regnum;
698 }
699
700 /* For double precision floating point registers, i.e 2 fp regs.*/
701 static int
sh64_dr_reg_base_num(int dr_regnum)702 sh64_dr_reg_base_num (int dr_regnum)
703 {
704 int fp_regnum;
705
706 fp_regnum = FP0_REGNUM +
707 (dr_regnum - DR0_REGNUM) * 2;
708 return fp_regnum;
709 }
710
711 /* For pairs of floating point registers */
712 static int
sh64_fpp_reg_base_num(int fpp_regnum)713 sh64_fpp_reg_base_num (int fpp_regnum)
714 {
715 int fp_regnum;
716
717 fp_regnum = FP0_REGNUM +
718 (fpp_regnum - FPP0_REGNUM) * 2;
719 return fp_regnum;
720 }
721
722 /* *INDENT-OFF* */
723 /*
724 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
725 GDB_REGNUM BASE_REGNUM
726 r0_c 221 0
727 r1_c 222 1
728 r2_c 223 2
729 r3_c 224 3
730 r4_c 225 4
731 r5_c 226 5
732 r6_c 227 6
733 r7_c 228 7
734 r8_c 229 8
735 r9_c 230 9
736 r10_c 231 10
737 r11_c 232 11
738 r12_c 233 12
739 r13_c 234 13
740 r14_c 235 14
741 r15_c 236 15
742
743 pc_c 237 64
744 gbr_c 238 16
745 mach_c 239 17
746 macl_c 240 17
747 pr_c 241 18
748 t_c 242 19
749 fpscr_c 243 76
750 fpul_c 244 109
751
752 fr0_c 245 77
753 fr1_c 246 78
754 fr2_c 247 79
755 fr3_c 248 80
756 fr4_c 249 81
757 fr5_c 250 82
758 fr6_c 251 83
759 fr7_c 252 84
760 fr8_c 253 85
761 fr9_c 254 86
762 fr10_c 255 87
763 fr11_c 256 88
764 fr12_c 257 89
765 fr13_c 258 90
766 fr14_c 259 91
767 fr15_c 260 92
768
769 dr0_c 261 77
770 dr2_c 262 79
771 dr4_c 263 81
772 dr6_c 264 83
773 dr8_c 265 85
774 dr10_c 266 87
775 dr12_c 267 89
776 dr14_c 268 91
777
778 fv0_c 269 77
779 fv4_c 270 81
780 fv8_c 271 85
781 fv12_c 272 91
782 */
783 /* *INDENT-ON* */
784 static int
sh64_compact_reg_base_num(int reg_nr)785 sh64_compact_reg_base_num (int reg_nr)
786 {
787 int base_regnum = reg_nr;
788
789 /* general register N maps to general register N */
790 if (reg_nr >= R0_C_REGNUM
791 && reg_nr <= R_LAST_C_REGNUM)
792 base_regnum = reg_nr - R0_C_REGNUM;
793
794 /* floating point register N maps to floating point register N */
795 else if (reg_nr >= FP0_C_REGNUM
796 && reg_nr <= FP_LAST_C_REGNUM)
797 base_regnum = reg_nr - FP0_C_REGNUM + FP0_REGNUM;
798
799 /* double prec register N maps to base regnum for double prec register N */
800 else if (reg_nr >= DR0_C_REGNUM
801 && reg_nr <= DR_LAST_C_REGNUM)
802 base_regnum = sh64_dr_reg_base_num (DR0_REGNUM + reg_nr - DR0_C_REGNUM);
803
804 /* vector N maps to base regnum for vector register N */
805 else if (reg_nr >= FV0_C_REGNUM
806 && reg_nr <= FV_LAST_C_REGNUM)
807 base_regnum = sh64_fv_reg_base_num (FV0_REGNUM + reg_nr - FV0_C_REGNUM);
808
809 else if (reg_nr == PC_C_REGNUM)
810 base_regnum = PC_REGNUM;
811
812 else if (reg_nr == GBR_C_REGNUM)
813 base_regnum = 16;
814
815 else if (reg_nr == MACH_C_REGNUM
816 || reg_nr == MACL_C_REGNUM)
817 base_regnum = 17;
818
819 else if (reg_nr == PR_C_REGNUM)
820 base_regnum = PR_REGNUM;
821
822 else if (reg_nr == T_C_REGNUM)
823 base_regnum = 19;
824
825 else if (reg_nr == FPSCR_C_REGNUM)
826 base_regnum = FPSCR_REGNUM; /*???? this register is a mess. */
827
828 else if (reg_nr == FPUL_C_REGNUM)
829 base_regnum = FP0_REGNUM + 32;
830
831 return base_regnum;
832 }
833
834 static int
sign_extend(int value,int bits)835 sign_extend (int value, int bits)
836 {
837 value = value & ((1 << bits) - 1);
838 return (value & (1 << (bits - 1))
839 ? value | (~((1 << bits) - 1))
840 : value);
841 }
842
843 static void
sh64_analyze_prologue(struct gdbarch * gdbarch,struct sh64_frame_cache * cache,CORE_ADDR func_pc,CORE_ADDR current_pc)844 sh64_analyze_prologue (struct gdbarch *gdbarch,
845 struct sh64_frame_cache *cache,
846 CORE_ADDR func_pc,
847 CORE_ADDR current_pc)
848 {
849 int reg_nr;
850 int pc;
851 int opc;
852 int insn;
853 int r0_val = 0;
854 int insn_size;
855 int gdb_register_number;
856 int register_number;
857 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
858
859 cache->sp_offset = 0;
860
861 /* Loop around examining the prologue insns until we find something
862 that does not appear to be part of the prologue. But give up
863 after 20 of them, since we're getting silly then. */
864
865 pc = func_pc;
866
867 if (cache->media_mode)
868 insn_size = 4;
869 else
870 insn_size = 2;
871
872 opc = pc + (insn_size * 28);
873 if (opc > current_pc)
874 opc = current_pc;
875 for ( ; pc <= opc; pc += insn_size)
876 {
877 insn = read_memory_integer (cache->media_mode ? UNMAKE_ISA32_ADDR (pc)
878 : pc,
879 insn_size);
880
881 if (!cache->media_mode)
882 {
883 if (IS_STS_PR (insn))
884 {
885 int next_insn = read_memory_integer (pc + insn_size, insn_size);
886 if (IS_MOV_TO_R15 (next_insn))
887 {
888 cache->saved_regs[PR_REGNUM] =
889 cache->sp_offset - ((((next_insn & 0xf) ^ 0x8) - 0x8) << 2);
890 pc += insn_size;
891 }
892 }
893
894 else if (IS_MOV_R14 (insn))
895 cache->saved_regs[MEDIA_FP_REGNUM] =
896 cache->sp_offset - ((((insn & 0xf) ^ 0x8) - 0x8) << 2);
897
898 else if (IS_MOV_R0 (insn))
899 {
900 /* Put in R0 the offset from SP at which to store some
901 registers. We are interested in this value, because it
902 will tell us where the given registers are stored within
903 the frame. */
904 r0_val = ((insn & 0xff) ^ 0x80) - 0x80;
905 }
906
907 else if (IS_ADD_SP_R0 (insn))
908 {
909 /* This instruction still prepares r0, but we don't care.
910 We already have the offset in r0_val. */
911 }
912
913 else if (IS_STS_R0 (insn))
914 {
915 /* Store PR at r0_val-4 from SP. Decrement r0 by 4*/
916 cache->saved_regs[PR_REGNUM] = cache->sp_offset - (r0_val - 4);
917 r0_val -= 4;
918 }
919
920 else if (IS_MOV_R14_R0 (insn))
921 {
922 /* Store R14 at r0_val-4 from SP. Decrement r0 by 4 */
923 cache->saved_regs[MEDIA_FP_REGNUM] = cache->sp_offset
924 - (r0_val - 4);
925 r0_val -= 4;
926 }
927
928 else if (IS_ADD_SP (insn))
929 cache->sp_offset -= ((insn & 0xff) ^ 0x80) - 0x80;
930
931 else if (IS_MOV_SP_FP (insn))
932 break;
933 }
934 else
935 {
936 if (IS_ADDIL_SP_MEDIA (insn) || IS_ADDI_SP_MEDIA (insn))
937 cache->sp_offset -=
938 sign_extend ((((insn & 0xffc00) ^ 0x80000) - 0x80000) >> 10, 9);
939
940 else if (IS_STQ_R18_R15 (insn))
941 cache->saved_regs[PR_REGNUM] =
942 cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3);
943
944 else if (IS_STL_R18_R15 (insn))
945 cache->saved_regs[PR_REGNUM] =
946 cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2);
947
948 else if (IS_STQ_R14_R15 (insn))
949 cache->saved_regs[MEDIA_FP_REGNUM] =
950 cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3);
951
952 else if (IS_STL_R14_R15 (insn))
953 cache->saved_regs[MEDIA_FP_REGNUM] =
954 cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2);
955
956 else if (IS_MOV_SP_FP_MEDIA (insn))
957 break;
958 }
959 }
960
961 if (cache->saved_regs[MEDIA_FP_REGNUM] >= 0)
962 cache->uses_fp = 1;
963 }
964
965 static CORE_ADDR
sh64_extract_struct_value_address(struct regcache * regcache)966 sh64_extract_struct_value_address (struct regcache *regcache)
967 {
968 /* FIXME: cagney/2004-01-17: Does the ABI guarantee that the return
969 address regster is preserved across function calls? Probably
970 not, making this function wrong. */
971 ULONGEST val;
972 regcache_raw_read_unsigned (regcache, STRUCT_RETURN_REGNUM, &val);
973 return val;
974 }
975
976 static CORE_ADDR
sh64_frame_align(struct gdbarch * ignore,CORE_ADDR sp)977 sh64_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
978 {
979 return sp & ~7;
980 }
981
982 /* Function: push_dummy_call
983 Setup the function arguments for calling a function in the inferior.
984
985 On the Renesas SH architecture, there are four registers (R4 to R7)
986 which are dedicated for passing function arguments. Up to the first
987 four arguments (depending on size) may go into these registers.
988 The rest go on the stack.
989
990 Arguments that are smaller than 4 bytes will still take up a whole
991 register or a whole 32-bit word on the stack, and will be
992 right-justified in the register or the stack word. This includes
993 chars, shorts, and small aggregate types.
994
995 Arguments that are larger than 4 bytes may be split between two or
996 more registers. If there are not enough registers free, an argument
997 may be passed partly in a register (or registers), and partly on the
998 stack. This includes doubles, long longs, and larger aggregates.
999 As far as I know, there is no upper limit to the size of aggregates
1000 that will be passed in this way; in other words, the convention of
1001 passing a pointer to a large aggregate instead of a copy is not used.
1002
1003 An exceptional case exists for struct arguments (and possibly other
1004 aggregates such as arrays) if the size is larger than 4 bytes but
1005 not a multiple of 4 bytes. In this case the argument is never split
1006 between the registers and the stack, but instead is copied in its
1007 entirety onto the stack, AND also copied into as many registers as
1008 there is room for. In other words, space in registers permitting,
1009 two copies of the same argument are passed in. As far as I can tell,
1010 only the one on the stack is used, although that may be a function
1011 of the level of compiler optimization. I suspect this is a compiler
1012 bug. Arguments of these odd sizes are left-justified within the
1013 word (as opposed to arguments smaller than 4 bytes, which are
1014 right-justified).
1015
1016 If the function is to return an aggregate type such as a struct, it
1017 is either returned in the normal return value register R0 (if its
1018 size is no greater than one byte), or else the caller must allocate
1019 space into which the callee will copy the return value (if the size
1020 is greater than one byte). In this case, a pointer to the return
1021 value location is passed into the callee in register R2, which does
1022 not displace any of the other arguments passed in via registers R4
1023 to R7. */
1024
1025 /* R2-R9 for integer types and integer equivalent (char, pointers) and
1026 non-scalar (struct, union) elements (even if the elements are
1027 floats).
1028 FR0-FR11 for single precision floating point (float)
1029 DR0-DR10 for double precision floating point (double)
1030
1031 If a float is argument number 3 (for instance) and arguments number
1032 1,2, and 4 are integer, the mapping will be:
1033 arg1 -->R2, arg2 --> R3, arg3 -->FR0, arg4 --> R5. I.e. R4 is not used.
1034
1035 If a float is argument number 10 (for instance) and arguments number
1036 1 through 10 are integer, the mapping will be:
1037 arg1->R2, arg2->R3, arg3->R4, arg4->R5, arg5->R6, arg6->R7, arg7->R8,
1038 arg8->R9, arg9->(0,SP)stack(8-byte aligned), arg10->FR0, arg11->stack(16,SP).
1039 I.e. there is hole in the stack.
1040
1041 Different rules apply for variable arguments functions, and for functions
1042 for which the prototype is not known. */
1043
1044 static CORE_ADDR
sh64_push_dummy_call(struct gdbarch * gdbarch,struct value * function,struct regcache * regcache,CORE_ADDR bp_addr,int nargs,struct value ** args,CORE_ADDR sp,int struct_return,CORE_ADDR struct_addr)1045 sh64_push_dummy_call (struct gdbarch *gdbarch,
1046 struct value *function,
1047 struct regcache *regcache,
1048 CORE_ADDR bp_addr,
1049 int nargs, struct value **args,
1050 CORE_ADDR sp, int struct_return,
1051 CORE_ADDR struct_addr)
1052 {
1053 int stack_offset, stack_alloc;
1054 int int_argreg;
1055 int float_argreg;
1056 int double_argreg;
1057 int float_arg_index = 0;
1058 int double_arg_index = 0;
1059 int argnum;
1060 struct type *type;
1061 CORE_ADDR regval;
1062 char *val;
1063 char valbuf[8];
1064 char valbuf_tmp[8];
1065 int len;
1066 int argreg_size;
1067 int fp_args[12];
1068
1069 memset (fp_args, 0, sizeof (fp_args));
1070
1071 /* first force sp to a 8-byte alignment */
1072 sp = sh64_frame_align (gdbarch, sp);
1073
1074 /* The "struct return pointer" pseudo-argument has its own dedicated
1075 register */
1076
1077 if (struct_return)
1078 regcache_cooked_write_unsigned (regcache,
1079 STRUCT_RETURN_REGNUM, struct_addr);
1080
1081 /* Now make sure there's space on the stack */
1082 for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
1083 stack_alloc += ((TYPE_LENGTH (value_type (args[argnum])) + 7) & ~7);
1084 sp -= stack_alloc; /* make room on stack for args */
1085
1086 /* Now load as many as possible of the first arguments into
1087 registers, and push the rest onto the stack. There are 64 bytes
1088 in eight registers available. Loop thru args from first to last. */
1089
1090 int_argreg = ARG0_REGNUM;
1091 float_argreg = FP0_REGNUM;
1092 double_argreg = DR0_REGNUM;
1093
1094 for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
1095 {
1096 type = value_type (args[argnum]);
1097 len = TYPE_LENGTH (type);
1098 memset (valbuf, 0, sizeof (valbuf));
1099
1100 if (TYPE_CODE (type) != TYPE_CODE_FLT)
1101 {
1102 argreg_size = register_size (current_gdbarch, int_argreg);
1103
1104 if (len < argreg_size)
1105 {
1106 /* value gets right-justified in the register or stack word */
1107 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1108 memcpy (valbuf + argreg_size - len,
1109 (char *) value_contents (args[argnum]), len);
1110 else
1111 memcpy (valbuf, (char *) value_contents (args[argnum]), len);
1112
1113 val = valbuf;
1114 }
1115 else
1116 val = (char *) value_contents (args[argnum]);
1117
1118 while (len > 0)
1119 {
1120 if (int_argreg > ARGLAST_REGNUM)
1121 {
1122 /* must go on the stack */
1123 write_memory (sp + stack_offset, (const bfd_byte *) val,
1124 argreg_size);
1125 stack_offset += 8;/*argreg_size;*/
1126 }
1127 /* NOTE WELL!!!!! This is not an "else if" clause!!!
1128 That's because some *&^%$ things get passed on the stack
1129 AND in the registers! */
1130 if (int_argreg <= ARGLAST_REGNUM)
1131 {
1132 /* there's room in a register */
1133 regval = extract_unsigned_integer (val, argreg_size);
1134 regcache_cooked_write_unsigned (regcache, int_argreg, regval);
1135 }
1136 /* Store the value 8 bytes at a time. This means that
1137 things larger than 8 bytes may go partly in registers
1138 and partly on the stack. FIXME: argreg is incremented
1139 before we use its size. */
1140 len -= argreg_size;
1141 val += argreg_size;
1142 int_argreg++;
1143 }
1144 }
1145 else
1146 {
1147 val = (char *) value_contents (args[argnum]);
1148 if (len == 4)
1149 {
1150 /* Where is it going to be stored? */
1151 while (fp_args[float_arg_index])
1152 float_arg_index ++;
1153
1154 /* Now float_argreg points to the register where it
1155 should be stored. Are we still within the allowed
1156 register set? */
1157 if (float_arg_index <= FLOAT_ARGLAST_REGNUM)
1158 {
1159 /* Goes in FR0...FR11 */
1160 regcache_cooked_write (regcache,
1161 FP0_REGNUM + float_arg_index,
1162 val);
1163 fp_args[float_arg_index] = 1;
1164 /* Skip the corresponding general argument register. */
1165 int_argreg ++;
1166 }
1167 else
1168 ;
1169 /* Store it as the integers, 8 bytes at the time, if
1170 necessary spilling on the stack. */
1171
1172 }
1173 else if (len == 8)
1174 {
1175 /* Where is it going to be stored? */
1176 while (fp_args[double_arg_index])
1177 double_arg_index += 2;
1178 /* Now double_argreg points to the register
1179 where it should be stored.
1180 Are we still within the allowed register set? */
1181 if (double_arg_index < FLOAT_ARGLAST_REGNUM)
1182 {
1183 /* Goes in DR0...DR10 */
1184 /* The numbering of the DRi registers is consecutive,
1185 i.e. includes odd numbers. */
1186 int double_register_offset = double_arg_index / 2;
1187 int regnum = DR0_REGNUM + double_register_offset;
1188 regcache_cooked_write (regcache, regnum, val);
1189 fp_args[double_arg_index] = 1;
1190 fp_args[double_arg_index + 1] = 1;
1191 /* Skip the corresponding general argument register. */
1192 int_argreg ++;
1193 }
1194 else
1195 ;
1196 /* Store it as the integers, 8 bytes at the time, if
1197 necessary spilling on the stack. */
1198 }
1199 }
1200 }
1201 /* Store return address. */
1202 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
1203
1204 /* Update stack pointer. */
1205 regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp);
1206
1207 return sp;
1208 }
1209
1210 /* Find a function's return value in the appropriate registers (in
1211 regbuf), and copy it into valbuf. Extract from an array REGBUF
1212 containing the (raw) register state a function return value of type
1213 TYPE, and copy that, in virtual format, into VALBUF. */
1214 static void
sh64_extract_return_value(struct type * type,struct regcache * regcache,void * valbuf)1215 sh64_extract_return_value (struct type *type, struct regcache *regcache,
1216 void *valbuf)
1217 {
1218 int len = TYPE_LENGTH (type);
1219
1220 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1221 {
1222 if (len == 4)
1223 {
1224 /* Return value stored in FP0_REGNUM */
1225 regcache_raw_read (regcache, FP0_REGNUM, valbuf);
1226 }
1227 else if (len == 8)
1228 {
1229 /* return value stored in DR0_REGNUM */
1230 DOUBLEST val;
1231 char buf[8];
1232
1233 regcache_cooked_read (regcache, DR0_REGNUM, &buf);
1234
1235 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
1236 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
1237 buf, &val);
1238 else
1239 floatformat_to_doublest (&floatformat_ieee_double_big,
1240 buf, &val);
1241 store_typed_floating (valbuf, type, val);
1242 }
1243 }
1244 else
1245 {
1246 if (len <= 8)
1247 {
1248 int offset;
1249 char buf[8];
1250 /* Result is in register 2. If smaller than 8 bytes, it is padded
1251 at the most significant end. */
1252 regcache_raw_read (regcache, DEFAULT_RETURN_REGNUM, buf);
1253
1254 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1255 offset = register_size (current_gdbarch, DEFAULT_RETURN_REGNUM)
1256 - len;
1257 else
1258 offset = 0;
1259 memcpy (valbuf, buf + offset, len);
1260 }
1261 else
1262 error ("bad size for return value");
1263 }
1264 }
1265
1266 /* Write into appropriate registers a function return value
1267 of type TYPE, given in virtual format.
1268 If the architecture is sh4 or sh3e, store a function's return value
1269 in the R0 general register or in the FP0 floating point register,
1270 depending on the type of the return value. In all the other cases
1271 the result is stored in r0, left-justified. */
1272
1273 static void
sh64_store_return_value(struct type * type,struct regcache * regcache,const void * valbuf)1274 sh64_store_return_value (struct type *type, struct regcache *regcache,
1275 const void *valbuf)
1276 {
1277 char buf[64]; /* more than enough... */
1278 int len = TYPE_LENGTH (type);
1279
1280 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1281 {
1282 int i, regnum = FP0_REGNUM;
1283 for (i = 0; i < len; i += 4)
1284 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
1285 regcache_raw_write (regcache, regnum++,
1286 (char *) valbuf + len - 4 - i);
1287 else
1288 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
1289 }
1290 else
1291 {
1292 int return_register = DEFAULT_RETURN_REGNUM;
1293 int offset = 0;
1294
1295 if (len <= register_size (current_gdbarch, return_register))
1296 {
1297 /* Pad with zeros. */
1298 memset (buf, 0, register_size (current_gdbarch, return_register));
1299 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
1300 offset = 0; /*register_size (current_gdbarch,
1301 return_register) - len;*/
1302 else
1303 offset = register_size (current_gdbarch, return_register) - len;
1304
1305 memcpy (buf + offset, valbuf, len);
1306 regcache_raw_write (regcache, return_register, buf);
1307 }
1308 else
1309 regcache_raw_write (regcache, return_register, valbuf);
1310 }
1311 }
1312
1313 static enum return_value_convention
sh64_return_value(struct gdbarch * gdbarch,struct type * type,struct regcache * regcache,void * readbuf,const void * writebuf)1314 sh64_return_value (struct gdbarch *gdbarch, struct type *type,
1315 struct regcache *regcache,
1316 void *readbuf, const void *writebuf)
1317 {
1318 if (sh64_use_struct_convention (type))
1319 return RETURN_VALUE_STRUCT_CONVENTION;
1320 if (writebuf)
1321 sh64_store_return_value (type, regcache, writebuf);
1322 else if (readbuf)
1323 sh64_extract_return_value (type, regcache, readbuf);
1324 return RETURN_VALUE_REGISTER_CONVENTION;
1325 }
1326
1327 static void
sh64_show_media_regs(void)1328 sh64_show_media_regs (void)
1329 {
1330 int i;
1331
1332 printf_filtered ("PC=%s SR=%016llx \n",
1333 paddr (read_register (PC_REGNUM)),
1334 (long long) read_register (SR_REGNUM));
1335
1336 printf_filtered ("SSR=%016llx SPC=%016llx \n",
1337 (long long) read_register (SSR_REGNUM),
1338 (long long) read_register (SPC_REGNUM));
1339 printf_filtered ("FPSCR=%016lx\n ",
1340 (long) read_register (FPSCR_REGNUM));
1341
1342 for (i = 0; i < 64; i = i + 4)
1343 printf_filtered ("\nR%d-R%d %016llx %016llx %016llx %016llx\n",
1344 i, i + 3,
1345 (long long) read_register (i + 0),
1346 (long long) read_register (i + 1),
1347 (long long) read_register (i + 2),
1348 (long long) read_register (i + 3));
1349
1350 printf_filtered ("\n");
1351
1352 for (i = 0; i < 64; i = i + 8)
1353 printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1354 i, i + 7,
1355 (long) read_register (FP0_REGNUM + i + 0),
1356 (long) read_register (FP0_REGNUM + i + 1),
1357 (long) read_register (FP0_REGNUM + i + 2),
1358 (long) read_register (FP0_REGNUM + i + 3),
1359 (long) read_register (FP0_REGNUM + i + 4),
1360 (long) read_register (FP0_REGNUM + i + 5),
1361 (long) read_register (FP0_REGNUM + i + 6),
1362 (long) read_register (FP0_REGNUM + i + 7));
1363 }
1364
1365 static void
sh64_show_compact_regs(void)1366 sh64_show_compact_regs (void)
1367 {
1368 int i;
1369
1370 printf_filtered ("PC=%s \n",
1371 paddr (read_register (PC_C_REGNUM)));
1372
1373 printf_filtered ("GBR=%08lx MACH=%08lx MACL=%08lx PR=%08lx T=%08lx\n",
1374 (long) read_register (GBR_C_REGNUM),
1375 (long) read_register (MACH_C_REGNUM),
1376 (long) read_register (MACL_C_REGNUM),
1377 (long) read_register (PR_C_REGNUM),
1378 (long) read_register (T_C_REGNUM));
1379 printf_filtered ("FPSCR=%08lx FPUL=%08lx\n",
1380 (long) read_register (FPSCR_C_REGNUM),
1381 (long) read_register (FPUL_C_REGNUM));
1382
1383 for (i = 0; i < 16; i = i + 4)
1384 printf_filtered ("\nR%d-R%d %08lx %08lx %08lx %08lx\n",
1385 i, i + 3,
1386 (long) read_register (i + 0),
1387 (long) read_register (i + 1),
1388 (long) read_register (i + 2),
1389 (long) read_register (i + 3));
1390
1391 printf_filtered ("\n");
1392
1393 for (i = 0; i < 16; i = i + 8)
1394 printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1395 i, i + 7,
1396 (long) read_register (FP0_REGNUM + i + 0),
1397 (long) read_register (FP0_REGNUM + i + 1),
1398 (long) read_register (FP0_REGNUM + i + 2),
1399 (long) read_register (FP0_REGNUM + i + 3),
1400 (long) read_register (FP0_REGNUM + i + 4),
1401 (long) read_register (FP0_REGNUM + i + 5),
1402 (long) read_register (FP0_REGNUM + i + 6),
1403 (long) read_register (FP0_REGNUM + i + 7));
1404 }
1405
1406 /* FIXME!!! This only shows the registers for shmedia, excluding the
1407 pseudo registers. */
1408 void
sh64_show_regs(void)1409 sh64_show_regs (void)
1410 {
1411 if (deprecated_selected_frame
1412 && pc_is_isa32 (get_frame_pc (deprecated_selected_frame)))
1413 sh64_show_media_regs ();
1414 else
1415 sh64_show_compact_regs ();
1416 }
1417
1418 /* *INDENT-OFF* */
1419 /*
1420 SH MEDIA MODE (ISA 32)
1421 general registers (64-bit) 0-63
1422 0 r0, r1, r2, r3, r4, r5, r6, r7,
1423 64 r8, r9, r10, r11, r12, r13, r14, r15,
1424 128 r16, r17, r18, r19, r20, r21, r22, r23,
1425 192 r24, r25, r26, r27, r28, r29, r30, r31,
1426 256 r32, r33, r34, r35, r36, r37, r38, r39,
1427 320 r40, r41, r42, r43, r44, r45, r46, r47,
1428 384 r48, r49, r50, r51, r52, r53, r54, r55,
1429 448 r56, r57, r58, r59, r60, r61, r62, r63,
1430
1431 pc (64-bit) 64
1432 512 pc,
1433
1434 status reg., saved status reg., saved pc reg. (64-bit) 65-67
1435 520 sr, ssr, spc,
1436
1437 target registers (64-bit) 68-75
1438 544 tr0, tr1, tr2, tr3, tr4, tr5, tr6, tr7,
1439
1440 floating point state control register (32-bit) 76
1441 608 fpscr,
1442
1443 single precision floating point registers (32-bit) 77-140
1444 612 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
1445 644 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15,
1446 676 fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23,
1447 708 fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31,
1448 740 fr32, fr33, fr34, fr35, fr36, fr37, fr38, fr39,
1449 772 fr40, fr41, fr42, fr43, fr44, fr45, fr46, fr47,
1450 804 fr48, fr49, fr50, fr51, fr52, fr53, fr54, fr55,
1451 836 fr56, fr57, fr58, fr59, fr60, fr61, fr62, fr63,
1452
1453 TOTAL SPACE FOR REGISTERS: 868 bytes
1454
1455 From here on they are all pseudo registers: no memory allocated.
1456 REGISTER_BYTE returns the register byte for the base register.
1457
1458 double precision registers (pseudo) 141-172
1459 dr0, dr2, dr4, dr6, dr8, dr10, dr12, dr14,
1460 dr16, dr18, dr20, dr22, dr24, dr26, dr28, dr30,
1461 dr32, dr34, dr36, dr38, dr40, dr42, dr44, dr46,
1462 dr48, dr50, dr52, dr54, dr56, dr58, dr60, dr62,
1463
1464 floating point pairs (pseudo) 173-204
1465 fp0, fp2, fp4, fp6, fp8, fp10, fp12, fp14,
1466 fp16, fp18, fp20, fp22, fp24, fp26, fp28, fp30,
1467 fp32, fp34, fp36, fp38, fp40, fp42, fp44, fp46,
1468 fp48, fp50, fp52, fp54, fp56, fp58, fp60, fp62,
1469
1470 floating point vectors (4 floating point regs) (pseudo) 205-220
1471 fv0, fv4, fv8, fv12, fv16, fv20, fv24, fv28,
1472 fv32, fv36, fv40, fv44, fv48, fv52, fv56, fv60,
1473
1474 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
1475 r0_c, r1_c, r2_c, r3_c, r4_c, r5_c, r6_c, r7_c,
1476 r8_c, r9_c, r10_c, r11_c, r12_c, r13_c, r14_c, r15_c,
1477 pc_c,
1478 gbr_c, mach_c, macl_c, pr_c, t_c,
1479 fpscr_c, fpul_c,
1480 fr0_c, fr1_c, fr2_c, fr3_c, fr4_c, fr5_c, fr6_c, fr7_c,
1481 fr8_c, fr9_c, fr10_c, fr11_c, fr12_c, fr13_c, fr14_c, fr15_c
1482 dr0_c, dr2_c, dr4_c, dr6_c, dr8_c, dr10_c, dr12_c, dr14_c
1483 fv0_c, fv4_c, fv8_c, fv12_c
1484 */
1485
1486 static struct type *
sh64_build_float_register_type(int high)1487 sh64_build_float_register_type (int high)
1488 {
1489 struct type *temp;
1490
1491 temp = create_range_type (NULL, builtin_type_int, 0, high);
1492 return create_array_type (NULL, builtin_type_float, temp);
1493 }
1494
1495 /* Return the GDB type object for the "standard" data type
1496 of data in register REG_NR. */
1497 static struct type *
sh64_register_type(struct gdbarch * gdbarch,int reg_nr)1498 sh64_register_type (struct gdbarch *gdbarch, int reg_nr)
1499 {
1500 if ((reg_nr >= FP0_REGNUM
1501 && reg_nr <= FP_LAST_REGNUM)
1502 || (reg_nr >= FP0_C_REGNUM
1503 && reg_nr <= FP_LAST_C_REGNUM))
1504 return builtin_type_float;
1505 else if ((reg_nr >= DR0_REGNUM
1506 && reg_nr <= DR_LAST_REGNUM)
1507 || (reg_nr >= DR0_C_REGNUM
1508 && reg_nr <= DR_LAST_C_REGNUM))
1509 return builtin_type_double;
1510 else if (reg_nr >= FPP0_REGNUM
1511 && reg_nr <= FPP_LAST_REGNUM)
1512 return sh64_build_float_register_type (1);
1513 else if ((reg_nr >= FV0_REGNUM
1514 && reg_nr <= FV_LAST_REGNUM)
1515 ||(reg_nr >= FV0_C_REGNUM
1516 && reg_nr <= FV_LAST_C_REGNUM))
1517 return sh64_build_float_register_type (3);
1518 else if (reg_nr == FPSCR_REGNUM)
1519 return builtin_type_int;
1520 else if (reg_nr >= R0_C_REGNUM
1521 && reg_nr < FP0_C_REGNUM)
1522 return builtin_type_int;
1523 else
1524 return builtin_type_long_long;
1525 }
1526
1527 static void
sh64_register_convert_to_virtual(int regnum,struct type * type,char * from,char * to)1528 sh64_register_convert_to_virtual (int regnum, struct type *type,
1529 char *from, char *to)
1530 {
1531 if (TARGET_BYTE_ORDER != BFD_ENDIAN_LITTLE)
1532 {
1533 /* It is a no-op. */
1534 memcpy (to, from, register_size (current_gdbarch, regnum));
1535 return;
1536 }
1537
1538 if ((regnum >= DR0_REGNUM
1539 && regnum <= DR_LAST_REGNUM)
1540 || (regnum >= DR0_C_REGNUM
1541 && regnum <= DR_LAST_C_REGNUM))
1542 {
1543 DOUBLEST val;
1544 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
1545 from, &val);
1546 store_typed_floating (to, type, val);
1547 }
1548 else
1549 error ("sh64_register_convert_to_virtual called with non DR register number");
1550 }
1551
1552 static void
sh64_register_convert_to_raw(struct type * type,int regnum,const void * from,void * to)1553 sh64_register_convert_to_raw (struct type *type, int regnum,
1554 const void *from, void *to)
1555 {
1556 if (TARGET_BYTE_ORDER != BFD_ENDIAN_LITTLE)
1557 {
1558 /* It is a no-op. */
1559 memcpy (to, from, register_size (current_gdbarch, regnum));
1560 return;
1561 }
1562
1563 if ((regnum >= DR0_REGNUM
1564 && regnum <= DR_LAST_REGNUM)
1565 || (regnum >= DR0_C_REGNUM
1566 && regnum <= DR_LAST_C_REGNUM))
1567 {
1568 DOUBLEST val = deprecated_extract_floating (from, TYPE_LENGTH(type));
1569 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword,
1570 &val, to);
1571 }
1572 else
1573 error ("sh64_register_convert_to_raw called with non DR register number");
1574 }
1575
1576 static void
sh64_pseudo_register_read(struct gdbarch * gdbarch,struct regcache * regcache,int reg_nr,void * buffer)1577 sh64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
1578 int reg_nr, void *buffer)
1579 {
1580 int base_regnum;
1581 int portion;
1582 int offset = 0;
1583 char temp_buffer[MAX_REGISTER_SIZE];
1584
1585 if (reg_nr >= DR0_REGNUM
1586 && reg_nr <= DR_LAST_REGNUM)
1587 {
1588 base_regnum = sh64_dr_reg_base_num (reg_nr);
1589
1590 /* Build the value in the provided buffer. */
1591 /* DR regs are double precision registers obtained by
1592 concatenating 2 single precision floating point registers. */
1593 for (portion = 0; portion < 2; portion++)
1594 regcache_raw_read (regcache, base_regnum + portion,
1595 (temp_buffer
1596 + register_size (gdbarch, base_regnum) * portion));
1597
1598 /* We must pay attention to the endianness. */
1599 sh64_register_convert_to_virtual (reg_nr,
1600 gdbarch_register_type (gdbarch,
1601 reg_nr),
1602 temp_buffer, buffer);
1603
1604 }
1605
1606 else if (reg_nr >= FPP0_REGNUM
1607 && reg_nr <= FPP_LAST_REGNUM)
1608 {
1609 base_regnum = sh64_fpp_reg_base_num (reg_nr);
1610
1611 /* Build the value in the provided buffer. */
1612 /* FPP regs are pairs of single precision registers obtained by
1613 concatenating 2 single precision floating point registers. */
1614 for (portion = 0; portion < 2; portion++)
1615 regcache_raw_read (regcache, base_regnum + portion,
1616 ((char *) buffer
1617 + register_size (gdbarch, base_regnum) * portion));
1618 }
1619
1620 else if (reg_nr >= FV0_REGNUM
1621 && reg_nr <= FV_LAST_REGNUM)
1622 {
1623 base_regnum = sh64_fv_reg_base_num (reg_nr);
1624
1625 /* Build the value in the provided buffer. */
1626 /* FV regs are vectors of single precision registers obtained by
1627 concatenating 4 single precision floating point registers. */
1628 for (portion = 0; portion < 4; portion++)
1629 regcache_raw_read (regcache, base_regnum + portion,
1630 ((char *) buffer
1631 + register_size (gdbarch, base_regnum) * portion));
1632 }
1633
1634 /* sh compact pseudo registers. 1-to-1 with a shmedia register */
1635 else if (reg_nr >= R0_C_REGNUM
1636 && reg_nr <= T_C_REGNUM)
1637 {
1638 base_regnum = sh64_compact_reg_base_num (reg_nr);
1639
1640 /* Build the value in the provided buffer. */
1641 regcache_raw_read (regcache, base_regnum, temp_buffer);
1642 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1643 offset = 4;
1644 memcpy (buffer, temp_buffer + offset, 4); /* get LOWER 32 bits only????*/
1645 }
1646
1647 else if (reg_nr >= FP0_C_REGNUM
1648 && reg_nr <= FP_LAST_C_REGNUM)
1649 {
1650 base_regnum = sh64_compact_reg_base_num (reg_nr);
1651
1652 /* Build the value in the provided buffer. */
1653 /* Floating point registers map 1-1 to the media fp regs,
1654 they have the same size and endianness. */
1655 regcache_raw_read (regcache, base_regnum, buffer);
1656 }
1657
1658 else if (reg_nr >= DR0_C_REGNUM
1659 && reg_nr <= DR_LAST_C_REGNUM)
1660 {
1661 base_regnum = sh64_compact_reg_base_num (reg_nr);
1662
1663 /* DR_C regs are double precision registers obtained by
1664 concatenating 2 single precision floating point registers. */
1665 for (portion = 0; portion < 2; portion++)
1666 regcache_raw_read (regcache, base_regnum + portion,
1667 (temp_buffer
1668 + register_size (gdbarch, base_regnum) * portion));
1669
1670 /* We must pay attention to the endianness. */
1671 sh64_register_convert_to_virtual (reg_nr,
1672 gdbarch_register_type (gdbarch,
1673 reg_nr),
1674 temp_buffer, buffer);
1675 }
1676
1677 else if (reg_nr >= FV0_C_REGNUM
1678 && reg_nr <= FV_LAST_C_REGNUM)
1679 {
1680 base_regnum = sh64_compact_reg_base_num (reg_nr);
1681
1682 /* Build the value in the provided buffer. */
1683 /* FV_C regs are vectors of single precision registers obtained by
1684 concatenating 4 single precision floating point registers. */
1685 for (portion = 0; portion < 4; portion++)
1686 regcache_raw_read (regcache, base_regnum + portion,
1687 ((char *) buffer
1688 + register_size (gdbarch, base_regnum) * portion));
1689 }
1690
1691 else if (reg_nr == FPSCR_C_REGNUM)
1692 {
1693 int fpscr_base_regnum;
1694 int sr_base_regnum;
1695 unsigned int fpscr_value;
1696 unsigned int sr_value;
1697 unsigned int fpscr_c_value;
1698 unsigned int fpscr_c_part1_value;
1699 unsigned int fpscr_c_part2_value;
1700
1701 fpscr_base_regnum = FPSCR_REGNUM;
1702 sr_base_regnum = SR_REGNUM;
1703
1704 /* Build the value in the provided buffer. */
1705 /* FPSCR_C is a very weird register that contains sparse bits
1706 from the FPSCR and the SR architectural registers.
1707 Specifically: */
1708 /* *INDENT-OFF* */
1709 /*
1710 FPSRC_C bit
1711 0 Bit 0 of FPSCR
1712 1 reserved
1713 2-17 Bit 2-18 of FPSCR
1714 18-20 Bits 12,13,14 of SR
1715 21-31 reserved
1716 */
1717 /* *INDENT-ON* */
1718 /* Get FPSCR into a local buffer */
1719 regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer);
1720 /* Get value as an int. */
1721 fpscr_value = extract_unsigned_integer (temp_buffer, 4);
1722 /* Get SR into a local buffer */
1723 regcache_raw_read (regcache, sr_base_regnum, temp_buffer);
1724 /* Get value as an int. */
1725 sr_value = extract_unsigned_integer (temp_buffer, 4);
1726 /* Build the new value. */
1727 fpscr_c_part1_value = fpscr_value & 0x3fffd;
1728 fpscr_c_part2_value = (sr_value & 0x7000) << 6;
1729 fpscr_c_value = fpscr_c_part1_value | fpscr_c_part2_value;
1730 /* Store that in out buffer!!! */
1731 store_unsigned_integer (buffer, 4, fpscr_c_value);
1732 /* FIXME There is surely an endianness gotcha here. */
1733 }
1734
1735 else if (reg_nr == FPUL_C_REGNUM)
1736 {
1737 base_regnum = sh64_compact_reg_base_num (reg_nr);
1738
1739 /* FPUL_C register is floating point register 32,
1740 same size, same endianness. */
1741 regcache_raw_read (regcache, base_regnum, buffer);
1742 }
1743 }
1744
1745 static void
sh64_pseudo_register_write(struct gdbarch * gdbarch,struct regcache * regcache,int reg_nr,const void * buffer)1746 sh64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
1747 int reg_nr, const void *buffer)
1748 {
1749 int base_regnum, portion;
1750 int offset;
1751 char temp_buffer[MAX_REGISTER_SIZE];
1752
1753 if (reg_nr >= DR0_REGNUM
1754 && reg_nr <= DR_LAST_REGNUM)
1755 {
1756 base_regnum = sh64_dr_reg_base_num (reg_nr);
1757 /* We must pay attention to the endianness. */
1758 sh64_register_convert_to_raw (gdbarch_register_type (gdbarch, reg_nr),
1759 reg_nr,
1760 buffer, temp_buffer);
1761
1762 /* Write the real regs for which this one is an alias. */
1763 for (portion = 0; portion < 2; portion++)
1764 regcache_raw_write (regcache, base_regnum + portion,
1765 (temp_buffer
1766 + register_size (gdbarch,
1767 base_regnum) * portion));
1768 }
1769
1770 else if (reg_nr >= FPP0_REGNUM
1771 && reg_nr <= FPP_LAST_REGNUM)
1772 {
1773 base_regnum = sh64_fpp_reg_base_num (reg_nr);
1774
1775 /* Write the real regs for which this one is an alias. */
1776 for (portion = 0; portion < 2; portion++)
1777 regcache_raw_write (regcache, base_regnum + portion,
1778 ((char *) buffer
1779 + register_size (gdbarch,
1780 base_regnum) * portion));
1781 }
1782
1783 else if (reg_nr >= FV0_REGNUM
1784 && reg_nr <= FV_LAST_REGNUM)
1785 {
1786 base_regnum = sh64_fv_reg_base_num (reg_nr);
1787
1788 /* Write the real regs for which this one is an alias. */
1789 for (portion = 0; portion < 4; portion++)
1790 regcache_raw_write (regcache, base_regnum + portion,
1791 ((char *) buffer
1792 + register_size (gdbarch,
1793 base_regnum) * portion));
1794 }
1795
1796 /* sh compact general pseudo registers. 1-to-1 with a shmedia
1797 register but only 4 bytes of it. */
1798 else if (reg_nr >= R0_C_REGNUM
1799 && reg_nr <= T_C_REGNUM)
1800 {
1801 base_regnum = sh64_compact_reg_base_num (reg_nr);
1802 /* reg_nr is 32 bit here, and base_regnum is 64 bits. */
1803 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1804 offset = 4;
1805 else
1806 offset = 0;
1807 /* Let's read the value of the base register into a temporary
1808 buffer, so that overwriting the last four bytes with the new
1809 value of the pseudo will leave the upper 4 bytes unchanged. */
1810 regcache_raw_read (regcache, base_regnum, temp_buffer);
1811 /* Write as an 8 byte quantity */
1812 memcpy (temp_buffer + offset, buffer, 4);
1813 regcache_raw_write (regcache, base_regnum, temp_buffer);
1814 }
1815
1816 /* sh floating point compact pseudo registers. 1-to-1 with a shmedia
1817 registers. Both are 4 bytes. */
1818 else if (reg_nr >= FP0_C_REGNUM
1819 && reg_nr <= FP_LAST_C_REGNUM)
1820 {
1821 base_regnum = sh64_compact_reg_base_num (reg_nr);
1822 regcache_raw_write (regcache, base_regnum, buffer);
1823 }
1824
1825 else if (reg_nr >= DR0_C_REGNUM
1826 && reg_nr <= DR_LAST_C_REGNUM)
1827 {
1828 base_regnum = sh64_compact_reg_base_num (reg_nr);
1829 for (portion = 0; portion < 2; portion++)
1830 {
1831 /* We must pay attention to the endianness. */
1832 sh64_register_convert_to_raw (gdbarch_register_type (gdbarch,
1833 reg_nr),
1834 reg_nr,
1835 buffer, temp_buffer);
1836
1837 regcache_raw_write (regcache, base_regnum + portion,
1838 (temp_buffer
1839 + register_size (gdbarch,
1840 base_regnum) * portion));
1841 }
1842 }
1843
1844 else if (reg_nr >= FV0_C_REGNUM
1845 && reg_nr <= FV_LAST_C_REGNUM)
1846 {
1847 base_regnum = sh64_compact_reg_base_num (reg_nr);
1848
1849 for (portion = 0; portion < 4; portion++)
1850 {
1851 regcache_raw_write (regcache, base_regnum + portion,
1852 ((char *) buffer
1853 + register_size (gdbarch,
1854 base_regnum) * portion));
1855 }
1856 }
1857
1858 else if (reg_nr == FPSCR_C_REGNUM)
1859 {
1860 int fpscr_base_regnum;
1861 int sr_base_regnum;
1862 unsigned int fpscr_value;
1863 unsigned int sr_value;
1864 unsigned int old_fpscr_value;
1865 unsigned int old_sr_value;
1866 unsigned int fpscr_c_value;
1867 unsigned int fpscr_mask;
1868 unsigned int sr_mask;
1869
1870 fpscr_base_regnum = FPSCR_REGNUM;
1871 sr_base_regnum = SR_REGNUM;
1872
1873 /* FPSCR_C is a very weird register that contains sparse bits
1874 from the FPSCR and the SR architectural registers.
1875 Specifically: */
1876 /* *INDENT-OFF* */
1877 /*
1878 FPSRC_C bit
1879 0 Bit 0 of FPSCR
1880 1 reserved
1881 2-17 Bit 2-18 of FPSCR
1882 18-20 Bits 12,13,14 of SR
1883 21-31 reserved
1884 */
1885 /* *INDENT-ON* */
1886 /* Get value as an int. */
1887 fpscr_c_value = extract_unsigned_integer (buffer, 4);
1888
1889 /* Build the new values. */
1890 fpscr_mask = 0x0003fffd;
1891 sr_mask = 0x001c0000;
1892
1893 fpscr_value = fpscr_c_value & fpscr_mask;
1894 sr_value = (fpscr_value & sr_mask) >> 6;
1895
1896 regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer);
1897 old_fpscr_value = extract_unsigned_integer (temp_buffer, 4);
1898 old_fpscr_value &= 0xfffc0002;
1899 fpscr_value |= old_fpscr_value;
1900 store_unsigned_integer (temp_buffer, 4, fpscr_value);
1901 regcache_raw_write (regcache, fpscr_base_regnum, temp_buffer);
1902
1903 regcache_raw_read (regcache, sr_base_regnum, temp_buffer);
1904 old_sr_value = extract_unsigned_integer (temp_buffer, 4);
1905 old_sr_value &= 0xffff8fff;
1906 sr_value |= old_sr_value;
1907 store_unsigned_integer (temp_buffer, 4, sr_value);
1908 regcache_raw_write (regcache, sr_base_regnum, temp_buffer);
1909 }
1910
1911 else if (reg_nr == FPUL_C_REGNUM)
1912 {
1913 base_regnum = sh64_compact_reg_base_num (reg_nr);
1914 regcache_raw_write (regcache, base_regnum, buffer);
1915 }
1916 }
1917
1918 /* FIXME:!! THIS SHOULD TAKE CARE OF GETTING THE RIGHT PORTION OF THE
1919 shmedia REGISTERS. */
1920 /* Control registers, compact mode. */
1921 static void
sh64_do_cr_c_register_info(struct ui_file * file,struct frame_info * frame,int cr_c_regnum)1922 sh64_do_cr_c_register_info (struct ui_file *file, struct frame_info *frame,
1923 int cr_c_regnum)
1924 {
1925 switch (cr_c_regnum)
1926 {
1927 case PC_C_REGNUM:
1928 fprintf_filtered (file, "pc_c\t0x%08x\n",
1929 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1930 break;
1931 case GBR_C_REGNUM:
1932 fprintf_filtered (file, "gbr_c\t0x%08x\n",
1933 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1934 break;
1935 case MACH_C_REGNUM:
1936 fprintf_filtered (file, "mach_c\t0x%08x\n",
1937 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1938 break;
1939 case MACL_C_REGNUM:
1940 fprintf_filtered (file, "macl_c\t0x%08x\n",
1941 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1942 break;
1943 case PR_C_REGNUM:
1944 fprintf_filtered (file, "pr_c\t0x%08x\n",
1945 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1946 break;
1947 case T_C_REGNUM:
1948 fprintf_filtered (file, "t_c\t0x%08x\n",
1949 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1950 break;
1951 case FPSCR_C_REGNUM:
1952 fprintf_filtered (file, "fpscr_c\t0x%08x\n",
1953 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1954 break;
1955 case FPUL_C_REGNUM:
1956 fprintf_filtered (file, "fpul_c\t0x%08x\n",
1957 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1958 break;
1959 }
1960 }
1961
1962 static void
sh64_do_fp_register(struct gdbarch * gdbarch,struct ui_file * file,struct frame_info * frame,int regnum)1963 sh64_do_fp_register (struct gdbarch *gdbarch, struct ui_file *file,
1964 struct frame_info *frame, int regnum)
1965 { /* do values for FP (float) regs */
1966 unsigned char *raw_buffer;
1967 double flt; /* double extracted from raw hex data */
1968 int inv;
1969 int j;
1970
1971 /* Allocate space for the float. */
1972 raw_buffer = (unsigned char *) alloca (register_size (gdbarch, FP0_REGNUM));
1973
1974 /* Get the data in raw format. */
1975 if (!frame_register_read (frame, regnum, raw_buffer))
1976 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
1977
1978 /* Get the register as a number */
1979 flt = unpack_double (builtin_type_float, raw_buffer, &inv);
1980
1981 /* Print the name and some spaces. */
1982 fputs_filtered (REGISTER_NAME (regnum), file);
1983 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
1984
1985 /* Print the value. */
1986 if (inv)
1987 fprintf_filtered (file, "<invalid float>");
1988 else
1989 fprintf_filtered (file, "%-10.9g", flt);
1990
1991 /* Print the fp register as hex. */
1992 fprintf_filtered (file, "\t(raw 0x");
1993 for (j = 0; j < register_size (gdbarch, regnum); j++)
1994 {
1995 int idx = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? j
1996 : register_size (gdbarch, regnum) - 1 - j;
1997 fprintf_filtered (file, "%02x", raw_buffer[idx]);
1998 }
1999 fprintf_filtered (file, ")");
2000 fprintf_filtered (file, "\n");
2001 }
2002
2003 static void
sh64_do_pseudo_register(struct gdbarch * gdbarch,struct ui_file * file,struct frame_info * frame,int regnum)2004 sh64_do_pseudo_register (struct gdbarch *gdbarch, struct ui_file *file,
2005 struct frame_info *frame, int regnum)
2006 {
2007 /* All the sh64-compact mode registers are pseudo registers. */
2008
2009 if (regnum < NUM_REGS
2010 || regnum >= NUM_REGS + NUM_PSEUDO_REGS_SH_MEDIA
2011 + NUM_PSEUDO_REGS_SH_COMPACT)
2012 internal_error (__FILE__, __LINE__,
2013 _("Invalid pseudo register number %d\n"), regnum);
2014
2015 else if ((regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM))
2016 {
2017 int fp_regnum = sh64_dr_reg_base_num (regnum);
2018 fprintf_filtered (file, "dr%d\t0x%08x%08x\n", regnum - DR0_REGNUM,
2019 (unsigned) get_frame_register_unsigned (frame, fp_regnum),
2020 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1));
2021 }
2022
2023 else if ((regnum >= DR0_C_REGNUM && regnum <= DR_LAST_C_REGNUM))
2024 {
2025 int fp_regnum = sh64_compact_reg_base_num (regnum);
2026 fprintf_filtered (file, "dr%d_c\t0x%08x%08x\n", regnum - DR0_C_REGNUM,
2027 (unsigned) get_frame_register_unsigned (frame, fp_regnum),
2028 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1));
2029 }
2030
2031 else if ((regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM))
2032 {
2033 int fp_regnum = sh64_fv_reg_base_num (regnum);
2034 fprintf_filtered (file, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
2035 regnum - FV0_REGNUM,
2036 (unsigned) get_frame_register_unsigned (frame, fp_regnum),
2037 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1),
2038 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 2),
2039 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 3));
2040 }
2041
2042 else if ((regnum >= FV0_C_REGNUM && regnum <= FV_LAST_C_REGNUM))
2043 {
2044 int fp_regnum = sh64_compact_reg_base_num (regnum);
2045 fprintf_filtered (file, "fv%d_c\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
2046 regnum - FV0_C_REGNUM,
2047 (unsigned) get_frame_register_unsigned (frame, fp_regnum),
2048 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1),
2049 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 2),
2050 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 3));
2051 }
2052
2053 else if (regnum >= FPP0_REGNUM && regnum <= FPP_LAST_REGNUM)
2054 {
2055 int fp_regnum = sh64_fpp_reg_base_num (regnum);
2056 fprintf_filtered (file, "fpp%d\t0x%08x\t0x%08x\n", regnum - FPP0_REGNUM,
2057 (unsigned) get_frame_register_unsigned (frame, fp_regnum),
2058 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1));
2059 }
2060
2061 else if (regnum >= R0_C_REGNUM && regnum <= R_LAST_C_REGNUM)
2062 {
2063 int c_regnum = sh64_compact_reg_base_num (regnum);
2064 fprintf_filtered (file, "r%d_c\t0x%08x\n", regnum - R0_C_REGNUM,
2065 (unsigned) get_frame_register_unsigned (frame, c_regnum));
2066 }
2067 else if (regnum >= FP0_C_REGNUM && regnum <= FP_LAST_C_REGNUM)
2068 /* This should work also for pseudoregs. */
2069 sh64_do_fp_register (gdbarch, file, frame, regnum);
2070 else if (regnum >= PC_C_REGNUM && regnum <= FPUL_C_REGNUM)
2071 sh64_do_cr_c_register_info (file, frame, regnum);
2072 }
2073
2074 static void
sh64_do_register(struct gdbarch * gdbarch,struct ui_file * file,struct frame_info * frame,int regnum)2075 sh64_do_register (struct gdbarch *gdbarch, struct ui_file *file,
2076 struct frame_info *frame, int regnum)
2077 {
2078 unsigned char raw_buffer[MAX_REGISTER_SIZE];
2079
2080 fputs_filtered (REGISTER_NAME (regnum), file);
2081 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
2082
2083 /* Get the data in raw format. */
2084 if (!frame_register_read (frame, regnum, raw_buffer))
2085 fprintf_filtered (file, "*value not available*\n");
2086
2087 val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
2088 file, 'x', 1, 0, Val_pretty_default);
2089 fprintf_filtered (file, "\t");
2090 val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
2091 file, 0, 1, 0, Val_pretty_default);
2092 fprintf_filtered (file, "\n");
2093 }
2094
2095 static void
sh64_print_register(struct gdbarch * gdbarch,struct ui_file * file,struct frame_info * frame,int regnum)2096 sh64_print_register (struct gdbarch *gdbarch, struct ui_file *file,
2097 struct frame_info *frame, int regnum)
2098 {
2099 if (regnum < 0 || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
2100 internal_error (__FILE__, __LINE__,
2101 _("Invalid register number %d\n"), regnum);
2102
2103 else if (regnum >= 0 && regnum < NUM_REGS)
2104 {
2105 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
2106 sh64_do_fp_register (gdbarch, file, frame, regnum); /* FP regs */
2107 else
2108 sh64_do_register (gdbarch, file, frame, regnum);
2109 }
2110
2111 else if (regnum < NUM_REGS + NUM_PSEUDO_REGS)
2112 sh64_do_pseudo_register (gdbarch, file, frame, regnum);
2113 }
2114
2115 static void
sh64_media_print_registers_info(struct gdbarch * gdbarch,struct ui_file * file,struct frame_info * frame,int regnum,int fpregs)2116 sh64_media_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
2117 struct frame_info *frame, int regnum,
2118 int fpregs)
2119 {
2120 if (regnum != -1) /* do one specified register */
2121 {
2122 if (*(REGISTER_NAME (regnum)) == '\0')
2123 error ("Not a valid register for the current processor type");
2124
2125 sh64_print_register (gdbarch, file, frame, regnum);
2126 }
2127 else
2128 /* do all (or most) registers */
2129 {
2130 regnum = 0;
2131 while (regnum < NUM_REGS)
2132 {
2133 /* If the register name is empty, it is undefined for this
2134 processor, so don't display anything. */
2135 if (REGISTER_NAME (regnum) == NULL
2136 || *(REGISTER_NAME (regnum)) == '\0')
2137 {
2138 regnum++;
2139 continue;
2140 }
2141
2142 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum))
2143 == TYPE_CODE_FLT)
2144 {
2145 if (fpregs)
2146 {
2147 /* true for "INFO ALL-REGISTERS" command */
2148 sh64_do_fp_register (gdbarch, file, frame, regnum);
2149 regnum ++;
2150 }
2151 else
2152 regnum += FP_LAST_REGNUM - FP0_REGNUM; /* skip FP regs */
2153 }
2154 else
2155 {
2156 sh64_do_register (gdbarch, file, frame, regnum);
2157 regnum++;
2158 }
2159 }
2160
2161 if (fpregs)
2162 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
2163 {
2164 sh64_do_pseudo_register (gdbarch, file, frame, regnum);
2165 regnum++;
2166 }
2167 }
2168 }
2169
2170 static void
sh64_compact_print_registers_info(struct gdbarch * gdbarch,struct ui_file * file,struct frame_info * frame,int regnum,int fpregs)2171 sh64_compact_print_registers_info (struct gdbarch *gdbarch,
2172 struct ui_file *file,
2173 struct frame_info *frame, int regnum,
2174 int fpregs)
2175 {
2176 if (regnum != -1) /* do one specified register */
2177 {
2178 if (*(REGISTER_NAME (regnum)) == '\0')
2179 error ("Not a valid register for the current processor type");
2180
2181 if (regnum >= 0 && regnum < R0_C_REGNUM)
2182 error ("Not a valid register for the current processor mode.");
2183
2184 sh64_print_register (gdbarch, file, frame, regnum);
2185 }
2186 else
2187 /* do all compact registers */
2188 {
2189 regnum = R0_C_REGNUM;
2190 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
2191 {
2192 sh64_do_pseudo_register (gdbarch, file, frame, regnum);
2193 regnum++;
2194 }
2195 }
2196 }
2197
2198 static void
sh64_print_registers_info(struct gdbarch * gdbarch,struct ui_file * file,struct frame_info * frame,int regnum,int fpregs)2199 sh64_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
2200 struct frame_info *frame, int regnum, int fpregs)
2201 {
2202 if (pc_is_isa32 (get_frame_pc (frame)))
2203 sh64_media_print_registers_info (gdbarch, file, frame, regnum, fpregs);
2204 else
2205 sh64_compact_print_registers_info (gdbarch, file, frame, regnum, fpregs);
2206 }
2207
2208 static struct sh64_frame_cache *
sh64_alloc_frame_cache(void)2209 sh64_alloc_frame_cache (void)
2210 {
2211 struct sh64_frame_cache *cache;
2212 int i;
2213
2214 cache = FRAME_OBSTACK_ZALLOC (struct sh64_frame_cache);
2215
2216 /* Base address. */
2217 cache->base = 0;
2218 cache->saved_sp = 0;
2219 cache->sp_offset = 0;
2220 cache->pc = 0;
2221
2222 /* Frameless until proven otherwise. */
2223 cache->uses_fp = 0;
2224
2225 /* Saved registers. We initialize these to -1 since zero is a valid
2226 offset (that's where fp is supposed to be stored). */
2227 for (i = 0; i < SIM_SH64_NR_REGS; i++)
2228 {
2229 cache->saved_regs[i] = -1;
2230 }
2231
2232 return cache;
2233 }
2234
2235 static struct sh64_frame_cache *
sh64_frame_cache(struct frame_info * next_frame,void ** this_cache)2236 sh64_frame_cache (struct frame_info *next_frame, void **this_cache)
2237 {
2238 struct sh64_frame_cache *cache;
2239 CORE_ADDR current_pc;
2240 int i;
2241
2242 if (*this_cache)
2243 return *this_cache;
2244
2245 cache = sh64_alloc_frame_cache ();
2246 *this_cache = cache;
2247
2248 current_pc = frame_pc_unwind (next_frame);
2249 cache->media_mode = pc_is_isa32 (current_pc);
2250
2251 /* In principle, for normal frames, fp holds the frame pointer,
2252 which holds the base address for the current stack frame.
2253 However, for functions that don't need it, the frame pointer is
2254 optional. For these "frameless" functions the frame pointer is
2255 actually the frame pointer of the calling frame. */
2256 cache->base = frame_unwind_register_unsigned (next_frame, MEDIA_FP_REGNUM);
2257 if (cache->base == 0)
2258 return cache;
2259
2260 cache->pc = frame_func_unwind (next_frame);
2261 if (cache->pc != 0)
2262 sh64_analyze_prologue (current_gdbarch, cache, cache->pc, current_pc);
2263
2264 if (!cache->uses_fp)
2265 {
2266 /* We didn't find a valid frame, which means that CACHE->base
2267 currently holds the frame pointer for our calling frame. If
2268 we're at the start of a function, or somewhere half-way its
2269 prologue, the function's frame probably hasn't been fully
2270 setup yet. Try to reconstruct the base address for the stack
2271 frame by looking at the stack pointer. For truly "frameless"
2272 functions this might work too. */
2273 cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
2274 }
2275
2276 /* Now that we have the base address for the stack frame we can
2277 calculate the value of sp in the calling frame. */
2278 cache->saved_sp = cache->base + cache->sp_offset;
2279
2280 /* Adjust all the saved registers such that they contain addresses
2281 instead of offsets. */
2282 for (i = 0; i < SIM_SH64_NR_REGS; i++)
2283 if (cache->saved_regs[i] != -1)
2284 cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i];
2285
2286 return cache;
2287 }
2288
2289 static void
sh64_frame_prev_register(struct frame_info * next_frame,void ** this_cache,int regnum,int * optimizedp,enum lval_type * lvalp,CORE_ADDR * addrp,int * realnump,void * valuep)2290 sh64_frame_prev_register (struct frame_info *next_frame, void **this_cache,
2291 int regnum, int *optimizedp,
2292 enum lval_type *lvalp, CORE_ADDR *addrp,
2293 int *realnump, void *valuep)
2294 {
2295 struct sh64_frame_cache *cache = sh64_frame_cache (next_frame, this_cache);
2296
2297 gdb_assert (regnum >= 0);
2298
2299 if (regnum == SP_REGNUM && cache->saved_sp)
2300 {
2301 *optimizedp = 0;
2302 *lvalp = not_lval;
2303 *addrp = 0;
2304 *realnump = -1;
2305 if (valuep)
2306 {
2307 /* Store the value. */
2308 store_unsigned_integer (valuep,
2309 register_size (current_gdbarch, SP_REGNUM),
2310 cache->saved_sp);
2311 }
2312 return;
2313 }
2314
2315 /* The PC of the previous frame is stored in the PR register of
2316 the current frame. Frob regnum so that we pull the value from
2317 the correct place. */
2318 if (regnum == PC_REGNUM)
2319 regnum = PR_REGNUM;
2320
2321 if (regnum < SIM_SH64_NR_REGS && cache->saved_regs[regnum] != -1)
2322 {
2323 int reg_size = register_size (current_gdbarch, regnum);
2324 int size;
2325
2326 *optimizedp = 0;
2327 *lvalp = lval_memory;
2328 *addrp = cache->saved_regs[regnum];
2329 *realnump = -1;
2330 if (gdbarch_tdep (current_gdbarch)->sh_abi == SH_ABI_32
2331 && (regnum == MEDIA_FP_REGNUM || regnum == PR_REGNUM))
2332 size = 4;
2333 else
2334 size = reg_size;
2335 if (valuep)
2336 {
2337 memset (valuep, 0, reg_size);
2338 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
2339 read_memory (*addrp, valuep, size);
2340 else
2341 read_memory (*addrp, (char *) valuep + reg_size - size, size);
2342 }
2343 return;
2344 }
2345
2346 *optimizedp = 0;
2347 *lvalp = lval_register;
2348 *addrp = 0;
2349 *realnump = regnum;
2350 if (valuep)
2351 frame_unwind_register (next_frame, (*realnump), valuep);
2352 }
2353
2354 static void
sh64_frame_this_id(struct frame_info * next_frame,void ** this_cache,struct frame_id * this_id)2355 sh64_frame_this_id (struct frame_info *next_frame, void **this_cache,
2356 struct frame_id *this_id)
2357 {
2358 struct sh64_frame_cache *cache = sh64_frame_cache (next_frame, this_cache);
2359
2360 /* This marks the outermost frame. */
2361 if (cache->base == 0)
2362 return;
2363
2364 *this_id = frame_id_build (cache->saved_sp, cache->pc);
2365 }
2366
2367 static const struct frame_unwind sh64_frame_unwind = {
2368 NORMAL_FRAME,
2369 sh64_frame_this_id,
2370 sh64_frame_prev_register
2371 };
2372
2373 static const struct frame_unwind *
sh64_frame_sniffer(struct frame_info * next_frame)2374 sh64_frame_sniffer (struct frame_info *next_frame)
2375 {
2376 return &sh64_frame_unwind;
2377 }
2378
2379 static CORE_ADDR
sh64_unwind_sp(struct gdbarch * gdbarch,struct frame_info * next_frame)2380 sh64_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
2381 {
2382 return frame_unwind_register_unsigned (next_frame, SP_REGNUM);
2383 }
2384
2385 static CORE_ADDR
sh64_unwind_pc(struct gdbarch * gdbarch,struct frame_info * next_frame)2386 sh64_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2387 {
2388 return frame_unwind_register_unsigned (next_frame, PC_REGNUM);
2389 }
2390
2391 static struct frame_id
sh64_unwind_dummy_id(struct gdbarch * gdbarch,struct frame_info * next_frame)2392 sh64_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
2393 {
2394 return frame_id_build (sh64_unwind_sp (gdbarch, next_frame),
2395 frame_pc_unwind (next_frame));
2396 }
2397
2398 static CORE_ADDR
sh64_frame_base_address(struct frame_info * next_frame,void ** this_cache)2399 sh64_frame_base_address (struct frame_info *next_frame, void **this_cache)
2400 {
2401 struct sh64_frame_cache *cache = sh64_frame_cache (next_frame, this_cache);
2402
2403 return cache->base;
2404 }
2405
2406 static const struct frame_base sh64_frame_base = {
2407 &sh64_frame_unwind,
2408 sh64_frame_base_address,
2409 sh64_frame_base_address,
2410 sh64_frame_base_address
2411 };
2412
2413
2414 struct gdbarch *
sh64_gdbarch_init(struct gdbarch_info info,struct gdbarch_list * arches)2415 sh64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2416 {
2417 struct gdbarch *gdbarch;
2418 struct gdbarch_tdep *tdep;
2419
2420 /* If there is already a candidate, use it. */
2421 arches = gdbarch_list_lookup_by_info (arches, &info);
2422 if (arches != NULL)
2423 return arches->gdbarch;
2424
2425 /* None found, create a new architecture from the information
2426 provided. */
2427 tdep = XMALLOC (struct gdbarch_tdep);
2428 gdbarch = gdbarch_alloc (&info, tdep);
2429
2430 /* Determine the ABI */
2431 if (info.abfd && bfd_get_arch_size (info.abfd) == 64)
2432 {
2433 /* If the ABI is the 64-bit one, it can only be sh-media. */
2434 tdep->sh_abi = SH_ABI_64;
2435 set_gdbarch_ptr_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2436 set_gdbarch_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2437 }
2438 else
2439 {
2440 /* If the ABI is the 32-bit one it could be either media or
2441 compact. */
2442 tdep->sh_abi = SH_ABI_32;
2443 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2444 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2445 }
2446
2447 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2448 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2449 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2450 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2451 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2452 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2453 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2454
2455 /* The number of real registers is the same whether we are in
2456 ISA16(compact) or ISA32(media). */
2457 set_gdbarch_num_regs (gdbarch, SIM_SH64_NR_REGS);
2458 set_gdbarch_sp_regnum (gdbarch, 15);
2459 set_gdbarch_pc_regnum (gdbarch, 64);
2460 set_gdbarch_fp0_regnum (gdbarch, SIM_SH64_FR0_REGNUM);
2461 set_gdbarch_num_pseudo_regs (gdbarch, NUM_PSEUDO_REGS_SH_MEDIA
2462 + NUM_PSEUDO_REGS_SH_COMPACT);
2463
2464 set_gdbarch_register_name (gdbarch, sh64_register_name);
2465 set_gdbarch_register_type (gdbarch, sh64_register_type);
2466
2467 set_gdbarch_pseudo_register_read (gdbarch, sh64_pseudo_register_read);
2468 set_gdbarch_pseudo_register_write (gdbarch, sh64_pseudo_register_write);
2469
2470 set_gdbarch_breakpoint_from_pc (gdbarch, sh64_breakpoint_from_pc);
2471
2472 set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh64);
2473 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
2474
2475 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
2476
2477 set_gdbarch_return_value (gdbarch, sh64_return_value);
2478 set_gdbarch_deprecated_extract_struct_value_address (gdbarch,
2479 sh64_extract_struct_value_address);
2480
2481 set_gdbarch_skip_prologue (gdbarch, sh64_skip_prologue);
2482 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2483
2484 set_gdbarch_push_dummy_call (gdbarch, sh64_push_dummy_call);
2485
2486 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2487
2488 set_gdbarch_frame_align (gdbarch, sh64_frame_align);
2489 set_gdbarch_unwind_sp (gdbarch, sh64_unwind_sp);
2490 set_gdbarch_unwind_pc (gdbarch, sh64_unwind_pc);
2491 set_gdbarch_unwind_dummy_id (gdbarch, sh64_unwind_dummy_id);
2492 frame_base_set_default (gdbarch, &sh64_frame_base);
2493
2494 set_gdbarch_print_registers_info (gdbarch, sh64_print_registers_info);
2495
2496 set_gdbarch_elf_make_msymbol_special (gdbarch,
2497 sh64_elf_make_msymbol_special);
2498
2499 /* Hook in ABI-specific overrides, if they have been registered. */
2500 gdbarch_init_osabi (info, gdbarch);
2501
2502 frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer);
2503 frame_unwind_append_sniffer (gdbarch, sh64_frame_sniffer);
2504
2505 return gdbarch;
2506 }
2507