1 /* Target-dependent code for GNU/Linux on MIPS processors.
2
3 Copyright 2001, 2002, 2004, 2005 Free Software Foundation, Inc.
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22 #include "defs.h"
23 #include "gdbcore.h"
24 #include "target.h"
25 #include "solib-svr4.h"
26 #include "osabi.h"
27 #include "mips-tdep.h"
28 #include "gdb_string.h"
29 #include "gdb_assert.h"
30 #include "frame.h"
31 #include "regcache.h"
32 #include "trad-frame.h"
33 #include "tramp-frame.h"
34
35 /* Copied from <asm/elf.h>. */
36 #define ELF_NGREG 45
37 #define ELF_NFPREG 33
38
39 typedef unsigned char elf_greg_t[4];
40 typedef elf_greg_t elf_gregset_t[ELF_NGREG];
41
42 typedef unsigned char elf_fpreg_t[8];
43 typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
44
45 /* 0 - 31 are integer registers, 32 - 63 are fp registers. */
46 #define FPR_BASE 32
47 #define PC 64
48 #define CAUSE 65
49 #define BADVADDR 66
50 #define MMHI 67
51 #define MMLO 68
52 #define FPC_CSR 69
53 #define FPC_EIR 70
54
55 #define EF_REG0 6
56 #define EF_REG31 37
57 #define EF_LO 38
58 #define EF_HI 39
59 #define EF_CP0_EPC 40
60 #define EF_CP0_BADVADDR 41
61 #define EF_CP0_STATUS 42
62 #define EF_CP0_CAUSE 43
63
64 #define EF_SIZE 180
65
66 /* Figure out where the longjmp will land.
67 We expect the first arg to be a pointer to the jmp_buf structure
68 from which we extract the pc (MIPS_LINUX_JB_PC) that we will land
69 at. The pc is copied into PC. This routine returns 1 on
70 success. */
71
72 #define MIPS_LINUX_JB_ELEMENT_SIZE 4
73 #define MIPS_LINUX_JB_PC 0
74
75 static int
mips_linux_get_longjmp_target(CORE_ADDR * pc)76 mips_linux_get_longjmp_target (CORE_ADDR *pc)
77 {
78 CORE_ADDR jb_addr;
79 char buf[TARGET_PTR_BIT / TARGET_CHAR_BIT];
80
81 jb_addr = read_register (MIPS_A0_REGNUM);
82
83 if (target_read_memory (jb_addr
84 + MIPS_LINUX_JB_PC * MIPS_LINUX_JB_ELEMENT_SIZE,
85 buf, TARGET_PTR_BIT / TARGET_CHAR_BIT))
86 return 0;
87
88 *pc = extract_unsigned_integer (buf, TARGET_PTR_BIT / TARGET_CHAR_BIT);
89
90 return 1;
91 }
92
93 /* Transform the bits comprising a 32-bit register to the right size
94 for regcache_raw_supply(). This is needed when mips_isa_regsize()
95 is 8. */
96
97 static void
supply_32bit_reg(int regnum,const void * addr)98 supply_32bit_reg (int regnum, const void *addr)
99 {
100 char buf[MAX_REGISTER_SIZE];
101 store_signed_integer (buf, register_size (current_gdbarch, regnum),
102 extract_signed_integer (addr, 4));
103 regcache_raw_supply (current_regcache, regnum, buf);
104 }
105
106 /* Unpack an elf_gregset_t into GDB's register cache. */
107
108 void
supply_gregset(elf_gregset_t * gregsetp)109 supply_gregset (elf_gregset_t *gregsetp)
110 {
111 int regi;
112 elf_greg_t *regp = *gregsetp;
113 char zerobuf[MAX_REGISTER_SIZE];
114
115 memset (zerobuf, 0, MAX_REGISTER_SIZE);
116
117 for (regi = EF_REG0; regi <= EF_REG31; regi++)
118 supply_32bit_reg ((regi - EF_REG0), (char *)(regp + regi));
119
120 supply_32bit_reg (mips_regnum (current_gdbarch)->lo,
121 (char *)(regp + EF_LO));
122 supply_32bit_reg (mips_regnum (current_gdbarch)->hi,
123 (char *)(regp + EF_HI));
124
125 supply_32bit_reg (mips_regnum (current_gdbarch)->pc,
126 (char *)(regp + EF_CP0_EPC));
127 supply_32bit_reg (mips_regnum (current_gdbarch)->badvaddr,
128 (char *)(regp + EF_CP0_BADVADDR));
129 supply_32bit_reg (MIPS_PS_REGNUM, (char *)(regp + EF_CP0_STATUS));
130 supply_32bit_reg (mips_regnum (current_gdbarch)->cause,
131 (char *)(regp + EF_CP0_CAUSE));
132
133 /* Fill inaccessible registers with zero. */
134 regcache_raw_supply (current_regcache, MIPS_UNUSED_REGNUM, zerobuf);
135 for (regi = MIPS_FIRST_EMBED_REGNUM;
136 regi < MIPS_LAST_EMBED_REGNUM;
137 regi++)
138 regcache_raw_supply (current_regcache, regi, zerobuf);
139 }
140
141 /* Pack our registers (or one register) into an elf_gregset_t. */
142
143 void
fill_gregset(elf_gregset_t * gregsetp,int regno)144 fill_gregset (elf_gregset_t *gregsetp, int regno)
145 {
146 int regaddr, regi;
147 elf_greg_t *regp = *gregsetp;
148 void *dst;
149
150 if (regno == -1)
151 {
152 memset (regp, 0, sizeof (elf_gregset_t));
153 for (regi = 0; regi < 32; regi++)
154 fill_gregset (gregsetp, regi);
155 fill_gregset (gregsetp, mips_regnum (current_gdbarch)->lo);
156 fill_gregset (gregsetp, mips_regnum (current_gdbarch)->hi);
157 fill_gregset (gregsetp, mips_regnum (current_gdbarch)->pc);
158 fill_gregset (gregsetp, mips_regnum (current_gdbarch)->badvaddr);
159 fill_gregset (gregsetp, MIPS_PS_REGNUM);
160 fill_gregset (gregsetp, mips_regnum (current_gdbarch)->cause);
161
162 return;
163 }
164
165 if (regno < 32)
166 {
167 dst = regp + regno + EF_REG0;
168 regcache_raw_collect (current_regcache, regno, dst);
169 return;
170 }
171
172 if (regno == mips_regnum (current_gdbarch)->lo)
173 regaddr = EF_LO;
174 else if (regno == mips_regnum (current_gdbarch)->hi)
175 regaddr = EF_HI;
176 else if (regno == mips_regnum (current_gdbarch)->pc)
177 regaddr = EF_CP0_EPC;
178 else if (regno == mips_regnum (current_gdbarch)->badvaddr)
179 regaddr = EF_CP0_BADVADDR;
180 else if (regno == MIPS_PS_REGNUM)
181 regaddr = EF_CP0_STATUS;
182 else if (regno == mips_regnum (current_gdbarch)->cause)
183 regaddr = EF_CP0_CAUSE;
184 else
185 regaddr = -1;
186
187 if (regaddr != -1)
188 {
189 dst = regp + regaddr;
190 regcache_raw_collect (current_regcache, regno, dst);
191 }
192 }
193
194 /* Likewise, unpack an elf_fpregset_t. */
195
196 void
supply_fpregset(elf_fpregset_t * fpregsetp)197 supply_fpregset (elf_fpregset_t *fpregsetp)
198 {
199 int regi;
200 char zerobuf[MAX_REGISTER_SIZE];
201
202 memset (zerobuf, 0, MAX_REGISTER_SIZE);
203
204 for (regi = 0; regi < 32; regi++)
205 regcache_raw_supply (current_regcache, FP0_REGNUM + regi,
206 (char *)(*fpregsetp + regi));
207
208 regcache_raw_supply (current_regcache,
209 mips_regnum (current_gdbarch)->fp_control_status,
210 (char *)(*fpregsetp + 32));
211
212 /* FIXME: how can we supply FCRIR? The ABI doesn't tell us. */
213 regcache_raw_supply (current_regcache,
214 mips_regnum (current_gdbarch)->fp_implementation_revision,
215 zerobuf);
216 }
217
218 /* Likewise, pack one or all floating point registers into an
219 elf_fpregset_t. */
220
221 void
fill_fpregset(elf_fpregset_t * fpregsetp,int regno)222 fill_fpregset (elf_fpregset_t *fpregsetp, int regno)
223 {
224 char *from, *to;
225
226 if ((regno >= FP0_REGNUM) && (regno < FP0_REGNUM + 32))
227 {
228 to = (char *) (*fpregsetp + regno - FP0_REGNUM);
229 regcache_raw_collect (current_regcache, regno, to);
230 }
231 else if (regno == mips_regnum (current_gdbarch)->fp_control_status)
232 {
233 to = (char *) (*fpregsetp + 32);
234 regcache_raw_collect (current_regcache, regno, to);
235 }
236 else if (regno == -1)
237 {
238 int regi;
239
240 for (regi = 0; regi < 32; regi++)
241 fill_fpregset (fpregsetp, FP0_REGNUM + regi);
242 fill_fpregset (fpregsetp,
243 mips_regnum (current_gdbarch)->fp_control_status);
244 }
245 }
246
247 /* Map gdb internal register number to ptrace ``address''.
248 These ``addresses'' are normally defined in <asm/ptrace.h>. */
249
250 static CORE_ADDR
mips_linux_register_addr(int regno,CORE_ADDR blockend)251 mips_linux_register_addr (int regno, CORE_ADDR blockend)
252 {
253 int regaddr;
254
255 if (regno < 0 || regno >= NUM_REGS)
256 error (_("Bogon register number %d."), regno);
257
258 if (regno < 32)
259 regaddr = regno;
260 else if ((regno >= mips_regnum (current_gdbarch)->fp0)
261 && (regno < mips_regnum (current_gdbarch)->fp0 + 32))
262 regaddr = FPR_BASE + (regno - mips_regnum (current_gdbarch)->fp0);
263 else if (regno == mips_regnum (current_gdbarch)->pc)
264 regaddr = PC;
265 else if (regno == mips_regnum (current_gdbarch)->cause)
266 regaddr = CAUSE;
267 else if (regno == mips_regnum (current_gdbarch)->badvaddr)
268 regaddr = BADVADDR;
269 else if (regno == mips_regnum (current_gdbarch)->lo)
270 regaddr = MMLO;
271 else if (regno == mips_regnum (current_gdbarch)->hi)
272 regaddr = MMHI;
273 else if (regno == mips_regnum (current_gdbarch)->fp_control_status)
274 regaddr = FPC_CSR;
275 else if (regno == mips_regnum (current_gdbarch)->fp_implementation_revision)
276 regaddr = FPC_EIR;
277 else
278 error (_("Unknowable register number %d."), regno);
279
280 return regaddr;
281 }
282
283
284 /* Fetch (and possibly build) an appropriate link_map_offsets
285 structure for native GNU/Linux MIPS targets using the struct
286 offsets defined in link.h (but without actual reference to that
287 file).
288
289 This makes it possible to access GNU/Linux MIPS shared libraries
290 from a GDB that was built on a different host platform (for cross
291 debugging). */
292
293 static struct link_map_offsets *
mips_linux_svr4_fetch_link_map_offsets(void)294 mips_linux_svr4_fetch_link_map_offsets (void)
295 {
296 static struct link_map_offsets lmo;
297 static struct link_map_offsets *lmp = NULL;
298
299 if (lmp == NULL)
300 {
301 lmp = &lmo;
302
303 lmo.r_debug_size = 8; /* The actual size is 20 bytes, but
304 this is all we need. */
305 lmo.r_map_offset = 4;
306 lmo.r_map_size = 4;
307
308 lmo.link_map_size = 20;
309
310 lmo.l_addr_offset = 0;
311 lmo.l_addr_size = 4;
312
313 lmo.l_name_offset = 4;
314 lmo.l_name_size = 4;
315
316 lmo.l_next_offset = 12;
317 lmo.l_next_size = 4;
318
319 lmo.l_prev_offset = 16;
320 lmo.l_prev_size = 4;
321 }
322
323 return lmp;
324 }
325
326 /* Support for 64-bit ABIs. */
327
328 /* Copied from <asm/elf.h>. */
329 #define MIPS64_ELF_NGREG 45
330 #define MIPS64_ELF_NFPREG 33
331
332 typedef unsigned char mips64_elf_greg_t[8];
333 typedef mips64_elf_greg_t mips64_elf_gregset_t[MIPS64_ELF_NGREG];
334
335 typedef unsigned char mips64_elf_fpreg_t[8];
336 typedef mips64_elf_fpreg_t mips64_elf_fpregset_t[MIPS64_ELF_NFPREG];
337
338 /* 0 - 31 are integer registers, 32 - 63 are fp registers. */
339 #define MIPS64_FPR_BASE 32
340 #define MIPS64_PC 64
341 #define MIPS64_CAUSE 65
342 #define MIPS64_BADVADDR 66
343 #define MIPS64_MMHI 67
344 #define MIPS64_MMLO 68
345 #define MIPS64_FPC_CSR 69
346 #define MIPS64_FPC_EIR 70
347
348 #define MIPS64_EF_REG0 0
349 #define MIPS64_EF_REG31 31
350 #define MIPS64_EF_LO 32
351 #define MIPS64_EF_HI 33
352 #define MIPS64_EF_CP0_EPC 34
353 #define MIPS64_EF_CP0_BADVADDR 35
354 #define MIPS64_EF_CP0_STATUS 36
355 #define MIPS64_EF_CP0_CAUSE 37
356
357 #define MIPS64_EF_SIZE 304
358
359 /* Figure out where the longjmp will land.
360 We expect the first arg to be a pointer to the jmp_buf structure
361 from which we extract the pc (MIPS_LINUX_JB_PC) that we will land
362 at. The pc is copied into PC. This routine returns 1 on
363 success. */
364
365 /* Details about jmp_buf. */
366
367 #define MIPS64_LINUX_JB_PC 0
368
369 static int
mips64_linux_get_longjmp_target(CORE_ADDR * pc)370 mips64_linux_get_longjmp_target (CORE_ADDR *pc)
371 {
372 CORE_ADDR jb_addr;
373 void *buf = alloca (TARGET_PTR_BIT / TARGET_CHAR_BIT);
374 int element_size = TARGET_PTR_BIT == 32 ? 4 : 8;
375
376 jb_addr = read_register (MIPS_A0_REGNUM);
377
378 if (target_read_memory (jb_addr + MIPS64_LINUX_JB_PC * element_size,
379 buf, TARGET_PTR_BIT / TARGET_CHAR_BIT))
380 return 0;
381
382 *pc = extract_unsigned_integer (buf, TARGET_PTR_BIT / TARGET_CHAR_BIT);
383
384 return 1;
385 }
386
387 /* Unpack an elf_gregset_t into GDB's register cache. */
388
389 static void
mips64_supply_gregset(mips64_elf_gregset_t * gregsetp)390 mips64_supply_gregset (mips64_elf_gregset_t *gregsetp)
391 {
392 int regi;
393 mips64_elf_greg_t *regp = *gregsetp;
394 char zerobuf[MAX_REGISTER_SIZE];
395
396 memset (zerobuf, 0, MAX_REGISTER_SIZE);
397
398 for (regi = MIPS64_EF_REG0; regi <= MIPS64_EF_REG31; regi++)
399 regcache_raw_supply (current_regcache, (regi - MIPS64_EF_REG0),
400 (char *)(regp + regi));
401
402 regcache_raw_supply (current_regcache,
403 mips_regnum (current_gdbarch)->lo,
404 (char *) (regp + MIPS64_EF_LO));
405 regcache_raw_supply (current_regcache,
406 mips_regnum (current_gdbarch)->hi,
407 (char *) (regp + MIPS64_EF_HI));
408
409 regcache_raw_supply (current_regcache,
410 mips_regnum (current_gdbarch)->pc,
411 (char *) (regp + MIPS64_EF_CP0_EPC));
412 regcache_raw_supply (current_regcache,
413 mips_regnum (current_gdbarch)->badvaddr,
414 (char *) (regp + MIPS64_EF_CP0_BADVADDR));
415 regcache_raw_supply (current_regcache, MIPS_PS_REGNUM,
416 (char *) (regp + MIPS64_EF_CP0_STATUS));
417 regcache_raw_supply (current_regcache,
418 mips_regnum (current_gdbarch)->cause,
419 (char *) (regp + MIPS64_EF_CP0_CAUSE));
420
421 /* Fill inaccessible registers with zero. */
422 regcache_raw_supply (current_regcache, MIPS_UNUSED_REGNUM, zerobuf);
423 for (regi = MIPS_FIRST_EMBED_REGNUM;
424 regi < MIPS_LAST_EMBED_REGNUM;
425 regi++)
426 regcache_raw_supply (current_regcache, regi, zerobuf);
427 }
428
429 /* Pack our registers (or one register) into an elf_gregset_t. */
430
431 static void
mips64_fill_gregset(mips64_elf_gregset_t * gregsetp,int regno)432 mips64_fill_gregset (mips64_elf_gregset_t *gregsetp, int regno)
433 {
434 int regaddr, regi;
435 mips64_elf_greg_t *regp = *gregsetp;
436 void *src, *dst;
437
438 if (regno == -1)
439 {
440 memset (regp, 0, sizeof (mips64_elf_gregset_t));
441 for (regi = 0; regi < 32; regi++)
442 mips64_fill_gregset (gregsetp, regi);
443 mips64_fill_gregset (gregsetp, mips_regnum (current_gdbarch)->lo);
444 mips64_fill_gregset (gregsetp, mips_regnum (current_gdbarch)->hi);
445 mips64_fill_gregset (gregsetp, mips_regnum (current_gdbarch)->pc);
446 mips64_fill_gregset (gregsetp,
447 mips_regnum (current_gdbarch)->badvaddr);
448 mips64_fill_gregset (gregsetp, MIPS_PS_REGNUM);
449 mips64_fill_gregset (gregsetp,
450 mips_regnum (current_gdbarch)->cause);
451
452 return;
453 }
454
455 if (regno < 32)
456 {
457 dst = regp + regno + MIPS64_EF_REG0;
458 regcache_raw_collect (current_regcache, regno, dst);
459 return;
460 }
461
462 if (regno == mips_regnum (current_gdbarch)->lo)
463 regaddr = MIPS64_EF_LO;
464 else if (regno == mips_regnum (current_gdbarch)->hi)
465 regaddr = MIPS64_EF_HI;
466 else if (regno == mips_regnum (current_gdbarch)->pc)
467 regaddr = MIPS64_EF_CP0_EPC;
468 else if (regno == mips_regnum (current_gdbarch)->badvaddr)
469 regaddr = MIPS64_EF_CP0_BADVADDR;
470 else if (regno == MIPS_PS_REGNUM)
471 regaddr = MIPS64_EF_CP0_STATUS;
472 else if (regno == mips_regnum (current_gdbarch)->cause)
473 regaddr = MIPS64_EF_CP0_CAUSE;
474 else
475 regaddr = -1;
476
477 if (regaddr != -1)
478 {
479 dst = regp + regaddr;
480 regcache_raw_collect (current_regcache, regno, dst);
481 }
482 }
483
484 /* Likewise, unpack an elf_fpregset_t. */
485
486 static void
mips64_supply_fpregset(mips64_elf_fpregset_t * fpregsetp)487 mips64_supply_fpregset (mips64_elf_fpregset_t *fpregsetp)
488 {
489 int regi;
490 char zerobuf[MAX_REGISTER_SIZE];
491
492 memset (zerobuf, 0, MAX_REGISTER_SIZE);
493
494 for (regi = 0; regi < 32; regi++)
495 regcache_raw_supply (current_regcache, FP0_REGNUM + regi,
496 (char *)(*fpregsetp + regi));
497
498 regcache_raw_supply (current_regcache,
499 mips_regnum (current_gdbarch)->fp_control_status,
500 (char *)(*fpregsetp + 32));
501
502 /* FIXME: how can we supply FCRIR? The ABI doesn't tell us. */
503 regcache_raw_supply (current_regcache,
504 mips_regnum (current_gdbarch)->fp_implementation_revision,
505 zerobuf);
506 }
507
508 /* Likewise, pack one or all floating point registers into an
509 elf_fpregset_t. */
510
511 static void
mips64_fill_fpregset(mips64_elf_fpregset_t * fpregsetp,int regno)512 mips64_fill_fpregset (mips64_elf_fpregset_t *fpregsetp, int regno)
513 {
514 char *from, *to;
515
516 if ((regno >= FP0_REGNUM) && (regno < FP0_REGNUM + 32))
517 {
518 to = (char *) (*fpregsetp + regno - FP0_REGNUM);
519 regcache_raw_collect (current_regcache, regno, to);
520 }
521 else if (regno == mips_regnum (current_gdbarch)->fp_control_status)
522 {
523 to = (char *) (*fpregsetp + 32);
524 regcache_raw_collect (current_regcache, regno, to);
525 }
526 else if (regno == -1)
527 {
528 int regi;
529
530 for (regi = 0; regi < 32; regi++)
531 mips64_fill_fpregset (fpregsetp, FP0_REGNUM + regi);
532 mips64_fill_fpregset(fpregsetp,
533 mips_regnum (current_gdbarch)->fp_control_status);
534 }
535 }
536
537
538 /* Map gdb internal register number to ptrace ``address''.
539 These ``addresses'' are normally defined in <asm/ptrace.h>. */
540
541 static CORE_ADDR
mips64_linux_register_addr(int regno,CORE_ADDR blockend)542 mips64_linux_register_addr (int regno, CORE_ADDR blockend)
543 {
544 int regaddr;
545
546 if (regno < 0 || regno >= NUM_REGS)
547 error (_("Bogon register number %d."), regno);
548
549 if (regno < 32)
550 regaddr = regno;
551 else if ((regno >= mips_regnum (current_gdbarch)->fp0)
552 && (regno < mips_regnum (current_gdbarch)->fp0 + 32))
553 regaddr = MIPS64_FPR_BASE + (regno - FP0_REGNUM);
554 else if (regno == mips_regnum (current_gdbarch)->pc)
555 regaddr = MIPS64_PC;
556 else if (regno == mips_regnum (current_gdbarch)->cause)
557 regaddr = MIPS64_CAUSE;
558 else if (regno == mips_regnum (current_gdbarch)->badvaddr)
559 regaddr = MIPS64_BADVADDR;
560 else if (regno == mips_regnum (current_gdbarch)->lo)
561 regaddr = MIPS64_MMLO;
562 else if (regno == mips_regnum (current_gdbarch)->hi)
563 regaddr = MIPS64_MMHI;
564 else if (regno == mips_regnum (current_gdbarch)->fp_control_status)
565 regaddr = MIPS64_FPC_CSR;
566 else if (regno == mips_regnum (current_gdbarch)->fp_implementation_revision)
567 regaddr = MIPS64_FPC_EIR;
568 else
569 error (_("Unknowable register number %d."), regno);
570
571 return regaddr;
572 }
573
574 /* Use a local version of this function to get the correct types for
575 regsets, until multi-arch core support is ready. */
576
577 static void
fetch_core_registers(char * core_reg_sect,unsigned core_reg_size,int which,CORE_ADDR reg_addr)578 fetch_core_registers (char *core_reg_sect, unsigned core_reg_size,
579 int which, CORE_ADDR reg_addr)
580 {
581 elf_gregset_t gregset;
582 elf_fpregset_t fpregset;
583 mips64_elf_gregset_t gregset64;
584 mips64_elf_fpregset_t fpregset64;
585
586 if (which == 0)
587 {
588 if (core_reg_size == sizeof (gregset))
589 {
590 memcpy ((char *) &gregset, core_reg_sect, sizeof (gregset));
591 supply_gregset (&gregset);
592 }
593 else if (core_reg_size == sizeof (gregset64))
594 {
595 memcpy ((char *) &gregset64, core_reg_sect, sizeof (gregset64));
596 mips64_supply_gregset (&gregset64);
597 }
598 else
599 {
600 warning (_("wrong size gregset struct in core file"));
601 }
602 }
603 else if (which == 2)
604 {
605 if (core_reg_size == sizeof (fpregset))
606 {
607 memcpy ((char *) &fpregset, core_reg_sect, sizeof (fpregset));
608 supply_fpregset (&fpregset);
609 }
610 else if (core_reg_size == sizeof (fpregset64))
611 {
612 memcpy ((char *) &fpregset64, core_reg_sect,
613 sizeof (fpregset64));
614 mips64_supply_fpregset (&fpregset64);
615 }
616 else
617 {
618 warning (_("wrong size fpregset struct in core file"));
619 }
620 }
621 }
622
623 /* Register that we are able to handle ELF file formats using standard
624 procfs "regset" structures. */
625
626 static struct core_fns regset_core_fns =
627 {
628 bfd_target_elf_flavour, /* core_flavour */
629 default_check_format, /* check_format */
630 default_core_sniffer, /* core_sniffer */
631 fetch_core_registers, /* core_read_registers */
632 NULL /* next */
633 };
634
635 /* Fetch (and possibly build) an appropriate link_map_offsets
636 structure for native GNU/Linux MIPS targets using the struct
637 offsets defined in link.h (but without actual reference to that
638 file).
639
640 This makes it possible to access GNU/Linux MIPS shared libraries
641 from a GDB that was built on a different host platform (for cross
642 debugging). */
643
644 static struct link_map_offsets *
mips64_linux_svr4_fetch_link_map_offsets(void)645 mips64_linux_svr4_fetch_link_map_offsets (void)
646 {
647 static struct link_map_offsets lmo;
648 static struct link_map_offsets *lmp = NULL;
649
650 if (lmp == NULL)
651 {
652 lmp = &lmo;
653
654 lmo.r_debug_size = 16; /* The actual size is 40 bytes, but
655 this is all we need. */
656 lmo.r_map_offset = 8;
657 lmo.r_map_size = 8;
658
659 lmo.link_map_size = 40;
660
661 lmo.l_addr_offset = 0;
662 lmo.l_addr_size = 8;
663
664 lmo.l_name_offset = 8;
665 lmo.l_name_size = 8;
666
667 lmo.l_next_offset = 24;
668 lmo.l_next_size = 8;
669
670 lmo.l_prev_offset = 32;
671 lmo.l_prev_size = 8;
672 }
673
674 return lmp;
675 }
676
677 /* Handle for obtaining pointer to the current register_addr()
678 function for a given architecture. */
679 static struct gdbarch_data *register_addr_data;
680
681 CORE_ADDR
register_addr(int regno,CORE_ADDR blockend)682 register_addr (int regno, CORE_ADDR blockend)
683 {
684 CORE_ADDR (*register_addr_ptr) (int, CORE_ADDR) =
685 gdbarch_data (current_gdbarch, register_addr_data);
686
687 gdb_assert (register_addr_ptr != 0);
688
689 return register_addr_ptr (regno, blockend);
690 }
691
692 static void
set_mips_linux_register_addr(struct gdbarch * gdbarch,CORE_ADDR (* register_addr_ptr)(int,CORE_ADDR))693 set_mips_linux_register_addr (struct gdbarch *gdbarch,
694 CORE_ADDR (*register_addr_ptr) (int,
695 CORE_ADDR))
696 {
697 deprecated_set_gdbarch_data (gdbarch, register_addr_data,
698 register_addr_ptr);
699 }
700
701 static void *
init_register_addr_data(struct gdbarch * gdbarch)702 init_register_addr_data (struct gdbarch *gdbarch)
703 {
704 return 0;
705 }
706
707 /* Check the code at PC for a dynamic linker lazy resolution stub.
708 Because they aren't in the .plt section, we pattern-match on the
709 code generated by GNU ld. They look like this:
710
711 lw t9,0x8010(gp)
712 addu t7,ra
713 jalr t9,ra
714 addiu t8,zero,INDEX
715
716 (with the appropriate doubleword instructions for N64). Also
717 return the dynamic symbol index used in the last instruction. */
718
719 static int
mips_linux_in_dynsym_stub(CORE_ADDR pc,char * name)720 mips_linux_in_dynsym_stub (CORE_ADDR pc, char *name)
721 {
722 unsigned char buf[28], *p;
723 ULONGEST insn, insn1;
724 int n64 = (mips_abi (current_gdbarch) == MIPS_ABI_N64);
725
726 read_memory (pc - 12, buf, 28);
727
728 if (n64)
729 {
730 /* ld t9,0x8010(gp) */
731 insn1 = 0xdf998010;
732 }
733 else
734 {
735 /* lw t9,0x8010(gp) */
736 insn1 = 0x8f998010;
737 }
738
739 p = buf + 12;
740 while (p >= buf)
741 {
742 insn = extract_unsigned_integer (p, 4);
743 if (insn == insn1)
744 break;
745 p -= 4;
746 }
747 if (p < buf)
748 return 0;
749
750 insn = extract_unsigned_integer (p + 4, 4);
751 if (n64)
752 {
753 /* daddu t7,ra */
754 if (insn != 0x03e0782d)
755 return 0;
756 }
757 else
758 {
759 /* addu t7,ra */
760 if (insn != 0x03e07821)
761 return 0;
762 }
763
764 insn = extract_unsigned_integer (p + 8, 4);
765 /* jalr t9,ra */
766 if (insn != 0x0320f809)
767 return 0;
768
769 insn = extract_unsigned_integer (p + 12, 4);
770 if (n64)
771 {
772 /* daddiu t8,zero,0 */
773 if ((insn & 0xffff0000) != 0x64180000)
774 return 0;
775 }
776 else
777 {
778 /* addiu t8,zero,0 */
779 if ((insn & 0xffff0000) != 0x24180000)
780 return 0;
781 }
782
783 return (insn & 0xffff);
784 }
785
786 /* Return non-zero iff PC belongs to the dynamic linker resolution
787 code or to a stub. */
788
789 int
mips_linux_in_dynsym_resolve_code(CORE_ADDR pc)790 mips_linux_in_dynsym_resolve_code (CORE_ADDR pc)
791 {
792 /* Check whether PC is in the dynamic linker. This also checks
793 whether it is in the .plt section, which MIPS does not use. */
794 if (in_solib_dynsym_resolve_code (pc))
795 return 1;
796
797 /* Pattern match for the stub. It would be nice if there were a
798 more efficient way to avoid this check. */
799 if (mips_linux_in_dynsym_stub (pc, NULL))
800 return 1;
801
802 return 0;
803 }
804
805 /* See the comments for SKIP_SOLIB_RESOLVER at the top of infrun.c,
806 and glibc_skip_solib_resolver in glibc-tdep.c. The normal glibc
807 implementation of this triggers at "fixup" from the same objfile as
808 "_dl_runtime_resolve"; MIPS GNU/Linux can trigger at
809 "__dl_runtime_resolve" directly. An unresolved PLT entry will
810 point to _dl_runtime_resolve, which will first call
811 __dl_runtime_resolve, and then pass control to the resolved
812 function. */
813
814 static CORE_ADDR
mips_linux_skip_resolver(struct gdbarch * gdbarch,CORE_ADDR pc)815 mips_linux_skip_resolver (struct gdbarch *gdbarch, CORE_ADDR pc)
816 {
817 struct minimal_symbol *resolver;
818
819 resolver = lookup_minimal_symbol ("__dl_runtime_resolve", NULL, NULL);
820
821 if (resolver && SYMBOL_VALUE_ADDRESS (resolver) == pc)
822 return frame_pc_unwind (get_current_frame ());
823
824 return 0;
825 }
826
827 /* Signal trampoline support. There are four supported layouts for a
828 signal frame: o32 sigframe, o32 rt_sigframe, n32 rt_sigframe, and
829 n64 rt_sigframe. We handle them all independently; not the most
830 efficient way, but simplest. First, declare all the unwinders. */
831
832 static void mips_linux_o32_sigframe_init (const struct tramp_frame *self,
833 struct frame_info *next_frame,
834 struct trad_frame_cache *this_cache,
835 CORE_ADDR func);
836
837 static void mips_linux_n32n64_sigframe_init (const struct tramp_frame *self,
838 struct frame_info *next_frame,
839 struct trad_frame_cache *this_cache,
840 CORE_ADDR func);
841
842 #define MIPS_NR_LINUX 4000
843 #define MIPS_NR_N64_LINUX 5000
844 #define MIPS_NR_N32_LINUX 6000
845
846 #define MIPS_NR_sigreturn MIPS_NR_LINUX + 119
847 #define MIPS_NR_rt_sigreturn MIPS_NR_LINUX + 193
848 #define MIPS_NR_N64_rt_sigreturn MIPS_NR_N64_LINUX + 211
849 #define MIPS_NR_N32_rt_sigreturn MIPS_NR_N32_LINUX + 211
850
851 #define MIPS_INST_LI_V0_SIGRETURN 0x24020000 + MIPS_NR_sigreturn
852 #define MIPS_INST_LI_V0_RT_SIGRETURN 0x24020000 + MIPS_NR_rt_sigreturn
853 #define MIPS_INST_LI_V0_N64_RT_SIGRETURN 0x24020000 + MIPS_NR_N64_rt_sigreturn
854 #define MIPS_INST_LI_V0_N32_RT_SIGRETURN 0x24020000 + MIPS_NR_N32_rt_sigreturn
855 #define MIPS_INST_SYSCALL 0x0000000c
856
857 static const struct tramp_frame mips_linux_o32_sigframe = {
858 SIGTRAMP_FRAME,
859 4,
860 {
861 { MIPS_INST_LI_V0_SIGRETURN, -1 },
862 { MIPS_INST_SYSCALL, -1 },
863 { TRAMP_SENTINEL_INSN, -1 }
864 },
865 mips_linux_o32_sigframe_init
866 };
867
868 static const struct tramp_frame mips_linux_o32_rt_sigframe = {
869 SIGTRAMP_FRAME,
870 4,
871 {
872 { MIPS_INST_LI_V0_RT_SIGRETURN, -1 },
873 { MIPS_INST_SYSCALL, -1 },
874 { TRAMP_SENTINEL_INSN, -1 } },
875 mips_linux_o32_sigframe_init
876 };
877
878 static const struct tramp_frame mips_linux_n32_rt_sigframe = {
879 SIGTRAMP_FRAME,
880 4,
881 {
882 { MIPS_INST_LI_V0_N32_RT_SIGRETURN, -1 },
883 { MIPS_INST_SYSCALL, -1 },
884 { TRAMP_SENTINEL_INSN, -1 }
885 },
886 mips_linux_n32n64_sigframe_init
887 };
888
889 static const struct tramp_frame mips_linux_n64_rt_sigframe = {
890 SIGTRAMP_FRAME,
891 4,
892 { MIPS_INST_LI_V0_N64_RT_SIGRETURN,
893 MIPS_INST_SYSCALL,
894 TRAMP_SENTINEL_INSN },
895 mips_linux_n32n64_sigframe_init
896 };
897
898 /* *INDENT-OFF* */
899 /* The unwinder for o32 signal frames. The legacy structures look
900 like this:
901
902 struct sigframe {
903 u32 sf_ass[4]; [argument save space for o32]
904 u32 sf_code[2]; [signal trampoline]
905 struct sigcontext sf_sc;
906 sigset_t sf_mask;
907 };
908
909 struct sigcontext {
910 unsigned int sc_regmask; [Unused]
911 unsigned int sc_status;
912 unsigned long long sc_pc;
913 unsigned long long sc_regs[32];
914 unsigned long long sc_fpregs[32];
915 unsigned int sc_ownedfp;
916 unsigned int sc_fpc_csr;
917 unsigned int sc_fpc_eir; [Unused]
918 unsigned int sc_used_math;
919 unsigned int sc_ssflags; [Unused]
920 [Alignment hole of four bytes]
921 unsigned long long sc_mdhi;
922 unsigned long long sc_mdlo;
923
924 unsigned int sc_cause; [Unused]
925 unsigned int sc_badvaddr; [Unused]
926
927 unsigned long sc_sigset[4]; [kernel's sigset_t]
928 };
929
930 The RT signal frames look like this:
931
932 struct rt_sigframe {
933 u32 rs_ass[4]; [argument save space for o32]
934 u32 rs_code[2] [signal trampoline]
935 struct siginfo rs_info;
936 struct ucontext rs_uc;
937 };
938
939 struct ucontext {
940 unsigned long uc_flags;
941 struct ucontext *uc_link;
942 stack_t uc_stack;
943 [Alignment hole of four bytes]
944 struct sigcontext uc_mcontext;
945 sigset_t uc_sigmask;
946 }; */
947 /* *INDENT-ON* */
948
949 #define SIGFRAME_CODE_OFFSET (4 * 4)
950 #define SIGFRAME_SIGCONTEXT_OFFSET (6 * 4)
951
952 #define RTSIGFRAME_SIGINFO_SIZE 128
953 #define STACK_T_SIZE (3 * 4)
954 #define UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + STACK_T_SIZE + 4)
955 #define RTSIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
956 + RTSIGFRAME_SIGINFO_SIZE \
957 + UCONTEXT_SIGCONTEXT_OFFSET)
958
959 #define SIGCONTEXT_PC (1 * 8)
960 #define SIGCONTEXT_REGS (2 * 8)
961 #define SIGCONTEXT_FPREGS (34 * 8)
962 #define SIGCONTEXT_FPCSR (66 * 8 + 4)
963 #define SIGCONTEXT_HI (69 * 8)
964 #define SIGCONTEXT_LO (70 * 8)
965 #define SIGCONTEXT_CAUSE (71 * 8 + 0)
966 #define SIGCONTEXT_BADVADDR (71 * 8 + 4)
967
968 #define SIGCONTEXT_REG_SIZE 8
969
970 static void
mips_linux_o32_sigframe_init(const struct tramp_frame * self,struct frame_info * next_frame,struct trad_frame_cache * this_cache,CORE_ADDR func)971 mips_linux_o32_sigframe_init (const struct tramp_frame *self,
972 struct frame_info *next_frame,
973 struct trad_frame_cache *this_cache,
974 CORE_ADDR func)
975 {
976 int ireg, reg_position;
977 CORE_ADDR sigcontext_base = func - SIGFRAME_CODE_OFFSET;
978 const struct mips_regnum *regs = mips_regnum (current_gdbarch);
979 CORE_ADDR regs_base;
980
981 if (self == &mips_linux_o32_sigframe)
982 sigcontext_base += SIGFRAME_SIGCONTEXT_OFFSET;
983 else
984 sigcontext_base += RTSIGFRAME_SIGCONTEXT_OFFSET;
985
986 /* I'm not proud of this hack. Eventually we will have the
987 infrastructure to indicate the size of saved registers on a
988 per-frame basis, but right now we don't; the kernel saves eight
989 bytes but we only want four. Use regs_base to access any
990 64-bit fields. */
991 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
992 regs_base = sigcontext_base + 4;
993 else
994 regs_base = sigcontext_base;
995
996 #if 0
997 trad_frame_set_reg_addr (this_cache, ORIG_ZERO_REGNUM + NUM_REGS,
998 regs_base + SIGCONTEXT_REGS);
999 #endif
1000
1001 for (ireg = 1; ireg < 32; ireg++)
1002 trad_frame_set_reg_addr (this_cache,
1003 ireg + MIPS_ZERO_REGNUM + NUM_REGS,
1004 regs_base + SIGCONTEXT_REGS
1005 + ireg * SIGCONTEXT_REG_SIZE);
1006
1007 /* The way that floating point registers are saved, unfortunately,
1008 depends on the architecture the kernel is built for. For the r3000 and
1009 tx39, four bytes of each register are at the beginning of each of the
1010 32 eight byte slots. For everything else, the registers are saved
1011 using double precision; only the even-numbered slots are initialized,
1012 and the high bits are the odd-numbered register. Assume the latter
1013 layout, since we can't tell, and it's much more common. Which bits are
1014 the "high" bits depends on endianness. */
1015 for (ireg = 0; ireg < 32; ireg++)
1016 if ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) != (ireg & 1))
1017 trad_frame_set_reg_addr (this_cache, ireg + regs->fp0 + NUM_REGS,
1018 sigcontext_base + SIGCONTEXT_FPREGS + 4
1019 + (ireg & ~1) * SIGCONTEXT_REG_SIZE);
1020 else
1021 trad_frame_set_reg_addr (this_cache, ireg + regs->fp0 + NUM_REGS,
1022 sigcontext_base + SIGCONTEXT_FPREGS
1023 + (ireg & ~1) * SIGCONTEXT_REG_SIZE);
1024
1025 trad_frame_set_reg_addr (this_cache, regs->pc + NUM_REGS,
1026 regs_base + SIGCONTEXT_PC);
1027
1028 trad_frame_set_reg_addr (this_cache,
1029 regs->fp_control_status + NUM_REGS,
1030 sigcontext_base + SIGCONTEXT_FPCSR);
1031 trad_frame_set_reg_addr (this_cache, regs->hi + NUM_REGS,
1032 regs_base + SIGCONTEXT_HI);
1033 trad_frame_set_reg_addr (this_cache, regs->lo + NUM_REGS,
1034 regs_base + SIGCONTEXT_LO);
1035 trad_frame_set_reg_addr (this_cache, regs->cause + NUM_REGS,
1036 sigcontext_base + SIGCONTEXT_CAUSE);
1037 trad_frame_set_reg_addr (this_cache, regs->badvaddr + NUM_REGS,
1038 sigcontext_base + SIGCONTEXT_BADVADDR);
1039
1040 /* Choice of the bottom of the sigframe is somewhat arbitrary. */
1041 trad_frame_set_id (this_cache,
1042 frame_id_build (func - SIGFRAME_CODE_OFFSET,
1043 func));
1044 }
1045
1046 /* *INDENT-OFF* */
1047 /* For N32/N64 things look different. There is no non-rt signal frame.
1048
1049 struct rt_sigframe_n32 {
1050 u32 rs_ass[4]; [ argument save space for o32 ]
1051 u32 rs_code[2]; [ signal trampoline ]
1052 struct siginfo rs_info;
1053 struct ucontextn32 rs_uc;
1054 };
1055
1056 struct ucontextn32 {
1057 u32 uc_flags;
1058 s32 uc_link;
1059 stack32_t uc_stack;
1060 struct sigcontext uc_mcontext;
1061 sigset_t uc_sigmask; [ mask last for extensibility ]
1062 };
1063
1064 struct rt_sigframe_n32 {
1065 u32 rs_ass[4]; [ argument save space for o32 ]
1066 u32 rs_code[2]; [ signal trampoline ]
1067 struct siginfo rs_info;
1068 struct ucontext rs_uc;
1069 };
1070
1071 struct ucontext {
1072 unsigned long uc_flags;
1073 struct ucontext *uc_link;
1074 stack_t uc_stack;
1075 struct sigcontext uc_mcontext;
1076 sigset_t uc_sigmask; [ mask last for extensibility ]
1077 };
1078
1079 And the sigcontext is different (this is for both n32 and n64):
1080
1081 struct sigcontext {
1082 unsigned long long sc_regs[32];
1083 unsigned long long sc_fpregs[32];
1084 unsigned long long sc_mdhi;
1085 unsigned long long sc_mdlo;
1086 unsigned long long sc_pc;
1087 unsigned int sc_status;
1088 unsigned int sc_fpc_csr;
1089 unsigned int sc_fpc_eir;
1090 unsigned int sc_used_math;
1091 unsigned int sc_cause;
1092 unsigned int sc_badvaddr;
1093 }; */
1094 /* *INDENT-ON* */
1095
1096 #define N32_STACK_T_SIZE STACK_T_SIZE
1097 #define N64_STACK_T_SIZE (2 * 8 + 4)
1098 #define N32_UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + N32_STACK_T_SIZE + 4)
1099 #define N64_UCONTEXT_SIGCONTEXT_OFFSET (2 * 8 + N64_STACK_T_SIZE + 4)
1100 #define N32_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
1101 + RTSIGFRAME_SIGINFO_SIZE \
1102 + N32_UCONTEXT_SIGCONTEXT_OFFSET)
1103 #define N64_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
1104 + RTSIGFRAME_SIGINFO_SIZE \
1105 + N64_UCONTEXT_SIGCONTEXT_OFFSET)
1106
1107 #define N64_SIGCONTEXT_REGS (0 * 8)
1108 #define N64_SIGCONTEXT_FPREGS (32 * 8)
1109 #define N64_SIGCONTEXT_HI (64 * 8)
1110 #define N64_SIGCONTEXT_LO (65 * 8)
1111 #define N64_SIGCONTEXT_PC (66 * 8)
1112 #define N64_SIGCONTEXT_FPCSR (67 * 8 + 1 * 4)
1113 #define N64_SIGCONTEXT_FIR (67 * 8 + 2 * 4)
1114 #define N64_SIGCONTEXT_CAUSE (67 * 8 + 4 * 4)
1115 #define N64_SIGCONTEXT_BADVADDR (67 * 8 + 5 * 4)
1116
1117 #define N64_SIGCONTEXT_REG_SIZE 8
1118
1119 static void
mips_linux_n32n64_sigframe_init(const struct tramp_frame * self,struct frame_info * next_frame,struct trad_frame_cache * this_cache,CORE_ADDR func)1120 mips_linux_n32n64_sigframe_init (const struct tramp_frame *self,
1121 struct frame_info *next_frame,
1122 struct trad_frame_cache *this_cache,
1123 CORE_ADDR func)
1124 {
1125 int ireg, reg_position;
1126 CORE_ADDR sigcontext_base = func - SIGFRAME_CODE_OFFSET;
1127 const struct mips_regnum *regs = mips_regnum (current_gdbarch);
1128
1129 if (self == &mips_linux_n32_rt_sigframe)
1130 sigcontext_base += N32_SIGFRAME_SIGCONTEXT_OFFSET;
1131 else
1132 sigcontext_base += N64_SIGFRAME_SIGCONTEXT_OFFSET;
1133
1134 #if 0
1135 trad_frame_set_reg_addr (this_cache, ORIG_ZERO_REGNUM + NUM_REGS,
1136 sigcontext_base + N64_SIGCONTEXT_REGS);
1137 #endif
1138
1139 for (ireg = 1; ireg < 32; ireg++)
1140 trad_frame_set_reg_addr (this_cache,
1141 ireg + MIPS_ZERO_REGNUM + NUM_REGS,
1142 sigcontext_base + N64_SIGCONTEXT_REGS
1143 + ireg * N64_SIGCONTEXT_REG_SIZE);
1144
1145 for (ireg = 0; ireg < 32; ireg++)
1146 trad_frame_set_reg_addr (this_cache, ireg + regs->fp0 + NUM_REGS,
1147 sigcontext_base + N64_SIGCONTEXT_FPREGS
1148 + ireg * N64_SIGCONTEXT_REG_SIZE);
1149
1150 trad_frame_set_reg_addr (this_cache, regs->pc + NUM_REGS,
1151 sigcontext_base + N64_SIGCONTEXT_PC);
1152
1153 trad_frame_set_reg_addr (this_cache,
1154 regs->fp_control_status + NUM_REGS,
1155 sigcontext_base + N64_SIGCONTEXT_FPCSR);
1156 trad_frame_set_reg_addr (this_cache, regs->hi + NUM_REGS,
1157 sigcontext_base + N64_SIGCONTEXT_HI);
1158 trad_frame_set_reg_addr (this_cache, regs->lo + NUM_REGS,
1159 sigcontext_base + N64_SIGCONTEXT_LO);
1160 trad_frame_set_reg_addr (this_cache, regs->cause + NUM_REGS,
1161 sigcontext_base + N64_SIGCONTEXT_CAUSE);
1162 trad_frame_set_reg_addr (this_cache, regs->badvaddr + NUM_REGS,
1163 sigcontext_base + N64_SIGCONTEXT_BADVADDR);
1164
1165 /* Choice of the bottom of the sigframe is somewhat arbitrary. */
1166 trad_frame_set_id (this_cache,
1167 frame_id_build (func - SIGFRAME_CODE_OFFSET,
1168 func));
1169 }
1170
1171 /* Initialize one of the GNU/Linux OS ABIs. */
1172
1173 static void
mips_linux_init_abi(struct gdbarch_info info,struct gdbarch * gdbarch)1174 mips_linux_init_abi (struct gdbarch_info info,
1175 struct gdbarch *gdbarch)
1176 {
1177 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1178 enum mips_abi abi = mips_abi (gdbarch);
1179
1180 switch (abi)
1181 {
1182 case MIPS_ABI_O32:
1183 set_gdbarch_get_longjmp_target (gdbarch,
1184 mips_linux_get_longjmp_target);
1185 set_solib_svr4_fetch_link_map_offsets
1186 (gdbarch, mips_linux_svr4_fetch_link_map_offsets);
1187 set_mips_linux_register_addr (gdbarch, mips_linux_register_addr);
1188 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_sigframe);
1189 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_rt_sigframe);
1190 break;
1191 case MIPS_ABI_N32:
1192 set_gdbarch_get_longjmp_target (gdbarch,
1193 mips_linux_get_longjmp_target);
1194 set_solib_svr4_fetch_link_map_offsets
1195 (gdbarch, mips_linux_svr4_fetch_link_map_offsets);
1196 set_mips_linux_register_addr (gdbarch, mips64_linux_register_addr);
1197 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n32_rt_sigframe);
1198 break;
1199 case MIPS_ABI_N64:
1200 set_gdbarch_get_longjmp_target (gdbarch,
1201 mips64_linux_get_longjmp_target);
1202 set_solib_svr4_fetch_link_map_offsets
1203 (gdbarch, mips64_linux_svr4_fetch_link_map_offsets);
1204 set_mips_linux_register_addr (gdbarch, mips64_linux_register_addr);
1205 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n64_rt_sigframe);
1206 break;
1207 default:
1208 internal_error (__FILE__, __LINE__, _("can't handle ABI"));
1209 break;
1210 }
1211
1212 set_gdbarch_skip_solib_resolver (gdbarch, mips_linux_skip_resolver);
1213
1214 set_gdbarch_software_single_step (gdbarch, mips_software_single_step);
1215
1216 /* Enable TLS support. */
1217 set_gdbarch_fetch_tls_load_module_address (gdbarch,
1218 svr4_fetch_objfile_link_map);
1219 }
1220
1221 void
_initialize_mips_linux_tdep(void)1222 _initialize_mips_linux_tdep (void)
1223 {
1224 const struct bfd_arch_info *arch_info;
1225
1226 register_addr_data =
1227 gdbarch_data_register_post_init (init_register_addr_data);
1228
1229 for (arch_info = bfd_lookup_arch (bfd_arch_mips, 0);
1230 arch_info != NULL;
1231 arch_info = arch_info->next)
1232 {
1233 gdbarch_register_osabi (bfd_arch_mips, arch_info->mach,
1234 GDB_OSABI_LINUX,
1235 mips_linux_init_abi);
1236 }
1237
1238 deprecated_add_core_fns (®set_core_fns);
1239 }
1240