1@section Relocations 2BFD maintains relocations in much the same way it maintains 3symbols: they are left alone until required, then read in 4en-masse and translated into an internal form. A common 5routine @code{bfd_perform_relocation} acts upon the 6canonical form to do the fixup. 7 8Relocations are maintained on a per section basis, 9while symbols are maintained on a per BFD basis. 10 11All that a back end has to do to fit the BFD interface is to create 12a @code{struct reloc_cache_entry} for each relocation 13in a particular section, and fill in the right bits of the structures. 14 15@menu 16* typedef arelent:: 17* howto manager:: 18@end menu 19 20 21@node typedef arelent, howto manager, Relocations, Relocations 22@subsection typedef arelent 23This is the structure of a relocation entry: 24 25 26@example 27 28typedef enum bfd_reloc_status 29@{ 30 /* No errors detected. */ 31 bfd_reloc_ok, 32 33 /* The relocation was performed, but there was an overflow. */ 34 bfd_reloc_overflow, 35 36 /* The address to relocate was not within the section supplied. */ 37 bfd_reloc_outofrange, 38 39 /* Used by special functions. */ 40 bfd_reloc_continue, 41 42 /* Unsupported relocation size requested. */ 43 bfd_reloc_notsupported, 44 45 /* Unused. */ 46 bfd_reloc_other, 47 48 /* The symbol to relocate against was undefined. */ 49 bfd_reloc_undefined, 50 51 /* The relocation was performed, but may not be ok - presently 52 generated only when linking i960 coff files with i960 b.out 53 symbols. If this type is returned, the error_message argument 54 to bfd_perform_relocation will be set. */ 55 bfd_reloc_dangerous 56 @} 57 bfd_reloc_status_type; 58 59 60typedef struct reloc_cache_entry 61@{ 62 /* A pointer into the canonical table of pointers. */ 63 struct bfd_symbol **sym_ptr_ptr; 64 65 /* offset in section. */ 66 bfd_size_type address; 67 68 /* addend for relocation value. */ 69 bfd_vma addend; 70 71 /* Pointer to how to perform the required relocation. */ 72 reloc_howto_type *howto; 73 74@} 75arelent; 76 77@end example 78@strong{Description}@* 79Here is a description of each of the fields within an @code{arelent}: 80 81@itemize @bullet 82 83@item 84@code{sym_ptr_ptr} 85@end itemize 86The symbol table pointer points to a pointer to the symbol 87associated with the relocation request. It is the pointer 88into the table returned by the back end's 89@code{canonicalize_symtab} action. @xref{Symbols}. The symbol is 90referenced through a pointer to a pointer so that tools like 91the linker can fix up all the symbols of the same name by 92modifying only one pointer. The relocation routine looks in 93the symbol and uses the base of the section the symbol is 94attached to and the value of the symbol as the initial 95relocation offset. If the symbol pointer is zero, then the 96section provided is looked up. 97 98@itemize @bullet 99 100@item 101@code{address} 102@end itemize 103The @code{address} field gives the offset in bytes from the base of 104the section data which owns the relocation record to the first 105byte of relocatable information. The actual data relocated 106will be relative to this point; for example, a relocation 107type which modifies the bottom two bytes of a four byte word 108would not touch the first byte pointed to in a big endian 109world. 110 111@itemize @bullet 112 113@item 114@code{addend} 115@end itemize 116The @code{addend} is a value provided by the back end to be added (!) 117to the relocation offset. Its interpretation is dependent upon 118the howto. For example, on the 68k the code: 119 120@example 121 char foo[]; 122 main() 123 @{ 124 return foo[0x12345678]; 125 @} 126@end example 127 128Could be compiled into: 129 130@example 131 linkw fp,#-4 132 moveb @@#12345678,d0 133 extbl d0 134 unlk fp 135 rts 136@end example 137 138This could create a reloc pointing to @code{foo}, but leave the 139offset in the data, something like: 140 141@example 142RELOCATION RECORDS FOR [.text]: 143offset type value 14400000006 32 _foo 145 14600000000 4e56 fffc ; linkw fp,#-4 14700000004 1039 1234 5678 ; moveb @@#12345678,d0 1480000000a 49c0 ; extbl d0 1490000000c 4e5e ; unlk fp 1500000000e 4e75 ; rts 151@end example 152 153Using coff and an 88k, some instructions don't have enough 154space in them to represent the full address range, and 155pointers have to be loaded in two parts. So you'd get something like: 156 157@example 158 or.u r13,r0,hi16(_foo+0x12345678) 159 ld.b r2,r13,lo16(_foo+0x12345678) 160 jmp r1 161@end example 162 163This should create two relocs, both pointing to @code{_foo}, and with 1640x12340000 in their addend field. The data would consist of: 165 166@example 167RELOCATION RECORDS FOR [.text]: 168offset type value 16900000002 HVRT16 _foo+0x12340000 17000000006 LVRT16 _foo+0x12340000 171 17200000000 5da05678 ; or.u r13,r0,0x5678 17300000004 1c4d5678 ; ld.b r2,r13,0x5678 17400000008 f400c001 ; jmp r1 175@end example 176 177The relocation routine digs out the value from the data, adds 178it to the addend to get the original offset, and then adds the 179value of @code{_foo}. Note that all 32 bits have to be kept around 180somewhere, to cope with carry from bit 15 to bit 16. 181 182One further example is the sparc and the a.out format. The 183sparc has a similar problem to the 88k, in that some 184instructions don't have room for an entire offset, but on the 185sparc the parts are created in odd sized lumps. The designers of 186the a.out format chose to not use the data within the section 187for storing part of the offset; all the offset is kept within 188the reloc. Anything in the data should be ignored. 189 190@example 191 save %sp,-112,%sp 192 sethi %hi(_foo+0x12345678),%g2 193 ldsb [%g2+%lo(_foo+0x12345678)],%i0 194 ret 195 restore 196@end example 197 198Both relocs contain a pointer to @code{foo}, and the offsets 199contain junk. 200 201@example 202RELOCATION RECORDS FOR [.text]: 203offset type value 20400000004 HI22 _foo+0x12345678 20500000008 LO10 _foo+0x12345678 206 20700000000 9de3bf90 ; save %sp,-112,%sp 20800000004 05000000 ; sethi %hi(_foo+0),%g2 20900000008 f048a000 ; ldsb [%g2+%lo(_foo+0)],%i0 2100000000c 81c7e008 ; ret 21100000010 81e80000 ; restore 212@end example 213 214@itemize @bullet 215 216@item 217@code{howto} 218@end itemize 219The @code{howto} field can be imagined as a 220relocation instruction. It is a pointer to a structure which 221contains information on what to do with all of the other 222information in the reloc record and data section. A back end 223would normally have a relocation instruction set and turn 224relocations into pointers to the correct structure on input - 225but it would be possible to create each howto field on demand. 226 227@subsubsection @code{enum complain_overflow} 228Indicates what sort of overflow checking should be done when 229performing a relocation. 230 231 232@example 233 234enum complain_overflow 235@{ 236 /* Do not complain on overflow. */ 237 complain_overflow_dont, 238 239 /* Complain if the bitfield overflows, whether it is considered 240 as signed or unsigned. */ 241 complain_overflow_bitfield, 242 243 /* Complain if the value overflows when considered as signed 244 number. */ 245 complain_overflow_signed, 246 247 /* Complain if the value overflows when considered as an 248 unsigned number. */ 249 complain_overflow_unsigned 250@}; 251@end example 252@subsubsection @code{reloc_howto_type} 253The @code{reloc_howto_type} is a structure which contains all the 254information that libbfd needs to know to tie up a back end's data. 255 256 257@example 258struct bfd_symbol; /* Forward declaration. */ 259 260struct reloc_howto_struct 261@{ 262 /* The type field has mainly a documentary use - the back end can 263 do what it wants with it, though normally the back end's 264 external idea of what a reloc number is stored 265 in this field. For example, a PC relative word relocation 266 in a coff environment has the type 023 - because that's 267 what the outside world calls a R_PCRWORD reloc. */ 268 unsigned int type; 269 270 /* The value the final relocation is shifted right by. This drops 271 unwanted data from the relocation. */ 272 unsigned int rightshift; 273 274 /* The size of the item to be relocated. This is *not* a 275 power-of-two measure. To get the number of bytes operated 276 on by a type of relocation, use bfd_get_reloc_size. */ 277 int size; 278 279 /* The number of bits in the item to be relocated. This is used 280 when doing overflow checking. */ 281 unsigned int bitsize; 282 283 /* Notes that the relocation is relative to the location in the 284 data section of the addend. The relocation function will 285 subtract from the relocation value the address of the location 286 being relocated. */ 287 bfd_boolean pc_relative; 288 289 /* The bit position of the reloc value in the destination. 290 The relocated value is left shifted by this amount. */ 291 unsigned int bitpos; 292 293 /* What type of overflow error should be checked for when 294 relocating. */ 295 enum complain_overflow complain_on_overflow; 296 297 /* If this field is non null, then the supplied function is 298 called rather than the normal function. This allows really 299 strange relocation methods to be accommodated (e.g., i960 callj 300 instructions). */ 301 bfd_reloc_status_type (*special_function) 302 (bfd *, arelent *, struct bfd_symbol *, void *, asection *, 303 bfd *, char **); 304 305 /* The textual name of the relocation type. */ 306 char *name; 307 308 /* Some formats record a relocation addend in the section contents 309 rather than with the relocation. For ELF formats this is the 310 distinction between USE_REL and USE_RELA (though the code checks 311 for USE_REL == 1/0). The value of this field is TRUE if the 312 addend is recorded with the section contents; when performing a 313 partial link (ld -r) the section contents (the data) will be 314 modified. The value of this field is FALSE if addends are 315 recorded with the relocation (in arelent.addend); when performing 316 a partial link the relocation will be modified. 317 All relocations for all ELF USE_RELA targets should set this field 318 to FALSE (values of TRUE should be looked on with suspicion). 319 However, the converse is not true: not all relocations of all ELF 320 USE_REL targets set this field to TRUE. Why this is so is peculiar 321 to each particular target. For relocs that aren't used in partial 322 links (e.g. GOT stuff) it doesn't matter what this is set to. */ 323 bfd_boolean partial_inplace; 324 325 /* src_mask selects the part of the instruction (or data) to be used 326 in the relocation sum. If the target relocations don't have an 327 addend in the reloc, eg. ELF USE_REL, src_mask will normally equal 328 dst_mask to extract the addend from the section contents. If 329 relocations do have an addend in the reloc, eg. ELF USE_RELA, this 330 field should be zero. Non-zero values for ELF USE_RELA targets are 331 bogus as in those cases the value in the dst_mask part of the 332 section contents should be treated as garbage. */ 333 bfd_vma src_mask; 334 335 /* dst_mask selects which parts of the instruction (or data) are 336 replaced with a relocated value. */ 337 bfd_vma dst_mask; 338 339 /* When some formats create PC relative instructions, they leave 340 the value of the pc of the place being relocated in the offset 341 slot of the instruction, so that a PC relative relocation can 342 be made just by adding in an ordinary offset (e.g., sun3 a.out). 343 Some formats leave the displacement part of an instruction 344 empty (e.g., m88k bcs); this flag signals the fact. */ 345 bfd_boolean pcrel_offset; 346@}; 347 348@end example 349@findex The HOWTO Macro 350@subsubsection @code{The HOWTO Macro} 351@strong{Description}@* 352The HOWTO define is horrible and will go away. 353@example 354#define HOWTO(C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC) \ 355 @{ (unsigned) C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC @} 356@end example 357 358@strong{Description}@* 359And will be replaced with the totally magic way. But for the 360moment, we are compatible, so do it this way. 361@example 362#define NEWHOWTO(FUNCTION, NAME, SIZE, REL, IN) \ 363 HOWTO (0, 0, SIZE, 0, REL, 0, complain_overflow_dont, FUNCTION, \ 364 NAME, FALSE, 0, 0, IN) 365 366@end example 367 368@strong{Description}@* 369This is used to fill in an empty howto entry in an array. 370@example 371#define EMPTY_HOWTO(C) \ 372 HOWTO ((C), 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL, \ 373 NULL, FALSE, 0, 0, FALSE) 374 375@end example 376 377@strong{Description}@* 378Helper routine to turn a symbol into a relocation value. 379@example 380#define HOWTO_PREPARE(relocation, symbol) \ 381 @{ \ 382 if (symbol != NULL) \ 383 @{ \ 384 if (bfd_is_com_section (symbol->section)) \ 385 @{ \ 386 relocation = 0; \ 387 @} \ 388 else \ 389 @{ \ 390 relocation = symbol->value; \ 391 @} \ 392 @} \ 393 @} 394 395@end example 396 397@findex bfd_get_reloc_size 398@subsubsection @code{bfd_get_reloc_size} 399@strong{Synopsis} 400@example 401unsigned int bfd_get_reloc_size (reloc_howto_type *); 402@end example 403@strong{Description}@* 404For a reloc_howto_type that operates on a fixed number of bytes, 405this returns the number of bytes operated on. 406 407@findex arelent_chain 408@subsubsection @code{arelent_chain} 409@strong{Description}@* 410How relocs are tied together in an @code{asection}: 411@example 412typedef struct relent_chain 413@{ 414 arelent relent; 415 struct relent_chain *next; 416@} 417arelent_chain; 418 419@end example 420 421@findex bfd_check_overflow 422@subsubsection @code{bfd_check_overflow} 423@strong{Synopsis} 424@example 425bfd_reloc_status_type bfd_check_overflow 426 (enum complain_overflow how, 427 unsigned int bitsize, 428 unsigned int rightshift, 429 unsigned int addrsize, 430 bfd_vma relocation); 431@end example 432@strong{Description}@* 433Perform overflow checking on @var{relocation} which has 434@var{bitsize} significant bits and will be shifted right by 435@var{rightshift} bits, on a machine with addresses containing 436@var{addrsize} significant bits. The result is either of 437@code{bfd_reloc_ok} or @code{bfd_reloc_overflow}. 438 439@findex bfd_perform_relocation 440@subsubsection @code{bfd_perform_relocation} 441@strong{Synopsis} 442@example 443bfd_reloc_status_type bfd_perform_relocation 444 (bfd *abfd, 445 arelent *reloc_entry, 446 void *data, 447 asection *input_section, 448 bfd *output_bfd, 449 char **error_message); 450@end example 451@strong{Description}@* 452If @var{output_bfd} is supplied to this function, the 453generated image will be relocatable; the relocations are 454copied to the output file after they have been changed to 455reflect the new state of the world. There are two ways of 456reflecting the results of partial linkage in an output file: 457by modifying the output data in place, and by modifying the 458relocation record. Some native formats (e.g., basic a.out and 459basic coff) have no way of specifying an addend in the 460relocation type, so the addend has to go in the output data. 461This is no big deal since in these formats the output data 462slot will always be big enough for the addend. Complex reloc 463types with addends were invented to solve just this problem. 464The @var{error_message} argument is set to an error message if 465this return @code{bfd_reloc_dangerous}. 466 467@findex bfd_install_relocation 468@subsubsection @code{bfd_install_relocation} 469@strong{Synopsis} 470@example 471bfd_reloc_status_type bfd_install_relocation 472 (bfd *abfd, 473 arelent *reloc_entry, 474 void *data, bfd_vma data_start, 475 asection *input_section, 476 char **error_message); 477@end example 478@strong{Description}@* 479This looks remarkably like @code{bfd_perform_relocation}, except it 480does not expect that the section contents have been filled in. 481I.e., it's suitable for use when creating, rather than applying 482a relocation. 483 484For now, this function should be considered reserved for the 485assembler. 486 487 488@node howto manager, , typedef arelent, Relocations 489@section The howto manager 490When an application wants to create a relocation, but doesn't 491know what the target machine might call it, it can find out by 492using this bit of code. 493 494@findex bfd_reloc_code_type 495@subsubsection @code{bfd_reloc_code_type} 496@strong{Description}@* 497The insides of a reloc code. The idea is that, eventually, there 498will be one enumerator for every type of relocation we ever do. 499Pass one of these values to @code{bfd_reloc_type_lookup}, and it'll 500return a howto pointer. 501 502This does mean that the application must determine the correct 503enumerator value; you can't get a howto pointer from a random set 504of attributes. 505 506Here are the possible values for @code{enum bfd_reloc_code_real}: 507 508@deffn {} BFD_RELOC_64 509@deffnx {} BFD_RELOC_32 510@deffnx {} BFD_RELOC_26 511@deffnx {} BFD_RELOC_24 512@deffnx {} BFD_RELOC_16 513@deffnx {} BFD_RELOC_14 514@deffnx {} BFD_RELOC_8 515Basic absolute relocations of N bits. 516@end deffn 517@deffn {} BFD_RELOC_64_PCREL 518@deffnx {} BFD_RELOC_32_PCREL 519@deffnx {} BFD_RELOC_24_PCREL 520@deffnx {} BFD_RELOC_16_PCREL 521@deffnx {} BFD_RELOC_12_PCREL 522@deffnx {} BFD_RELOC_8_PCREL 523PC-relative relocations. Sometimes these are relative to the address 524of the relocation itself; sometimes they are relative to the start of 525the section containing the relocation. It depends on the specific target. 526 527The 24-bit relocation is used in some Intel 960 configurations. 528@end deffn 529@deffn {} BFD_RELOC_32_SECREL 530Section relative relocations. Some targets need this for DWARF2. 531@end deffn 532@deffn {} BFD_RELOC_32_GOT_PCREL 533@deffnx {} BFD_RELOC_16_GOT_PCREL 534@deffnx {} BFD_RELOC_8_GOT_PCREL 535@deffnx {} BFD_RELOC_32_GOTOFF 536@deffnx {} BFD_RELOC_16_GOTOFF 537@deffnx {} BFD_RELOC_LO16_GOTOFF 538@deffnx {} BFD_RELOC_HI16_GOTOFF 539@deffnx {} BFD_RELOC_HI16_S_GOTOFF 540@deffnx {} BFD_RELOC_8_GOTOFF 541@deffnx {} BFD_RELOC_64_PLT_PCREL 542@deffnx {} BFD_RELOC_32_PLT_PCREL 543@deffnx {} BFD_RELOC_24_PLT_PCREL 544@deffnx {} BFD_RELOC_16_PLT_PCREL 545@deffnx {} BFD_RELOC_8_PLT_PCREL 546@deffnx {} BFD_RELOC_64_PLTOFF 547@deffnx {} BFD_RELOC_32_PLTOFF 548@deffnx {} BFD_RELOC_16_PLTOFF 549@deffnx {} BFD_RELOC_LO16_PLTOFF 550@deffnx {} BFD_RELOC_HI16_PLTOFF 551@deffnx {} BFD_RELOC_HI16_S_PLTOFF 552@deffnx {} BFD_RELOC_8_PLTOFF 553For ELF. 554@end deffn 555@deffn {} BFD_RELOC_68K_GLOB_DAT 556@deffnx {} BFD_RELOC_68K_JMP_SLOT 557@deffnx {} BFD_RELOC_68K_RELATIVE 558Relocations used by 68K ELF. 559@end deffn 560@deffn {} BFD_RELOC_32_BASEREL 561@deffnx {} BFD_RELOC_16_BASEREL 562@deffnx {} BFD_RELOC_LO16_BASEREL 563@deffnx {} BFD_RELOC_HI16_BASEREL 564@deffnx {} BFD_RELOC_HI16_S_BASEREL 565@deffnx {} BFD_RELOC_8_BASEREL 566@deffnx {} BFD_RELOC_RVA 567Linkage-table relative. 568@end deffn 569@deffn {} BFD_RELOC_8_FFnn 570Absolute 8-bit relocation, but used to form an address like 0xFFnn. 571@end deffn 572@deffn {} BFD_RELOC_32_PCREL_S2 573@deffnx {} BFD_RELOC_16_PCREL_S2 574@deffnx {} BFD_RELOC_23_PCREL_S2 575These PC-relative relocations are stored as word displacements -- 576i.e., byte displacements shifted right two bits. The 30-bit word 577displacement (<<32_PCREL_S2>> -- 32 bits, shifted 2) is used on the 578SPARC. (SPARC tools generally refer to this as <<WDISP30>>.) The 579signed 16-bit displacement is used on the MIPS, and the 23-bit 580displacement is used on the Alpha. 581@end deffn 582@deffn {} BFD_RELOC_HI22 583@deffnx {} BFD_RELOC_LO10 584High 22 bits and low 10 bits of 32-bit value, placed into lower bits of 585the target word. These are used on the SPARC. 586@end deffn 587@deffn {} BFD_RELOC_GPREL16 588@deffnx {} BFD_RELOC_GPREL32 589For systems that allocate a Global Pointer register, these are 590displacements off that register. These relocation types are 591handled specially, because the value the register will have is 592decided relatively late. 593@end deffn 594@deffn {} BFD_RELOC_I960_CALLJ 595Reloc types used for i960/b.out. 596@end deffn 597@deffn {} BFD_RELOC_NONE 598@deffnx {} BFD_RELOC_SPARC_WDISP22 599@deffnx {} BFD_RELOC_SPARC22 600@deffnx {} BFD_RELOC_SPARC13 601@deffnx {} BFD_RELOC_SPARC_GOT10 602@deffnx {} BFD_RELOC_SPARC_GOT13 603@deffnx {} BFD_RELOC_SPARC_GOT22 604@deffnx {} BFD_RELOC_SPARC_PC10 605@deffnx {} BFD_RELOC_SPARC_PC22 606@deffnx {} BFD_RELOC_SPARC_WPLT30 607@deffnx {} BFD_RELOC_SPARC_COPY 608@deffnx {} BFD_RELOC_SPARC_GLOB_DAT 609@deffnx {} BFD_RELOC_SPARC_JMP_SLOT 610@deffnx {} BFD_RELOC_SPARC_RELATIVE 611@deffnx {} BFD_RELOC_SPARC_UA16 612@deffnx {} BFD_RELOC_SPARC_UA32 613@deffnx {} BFD_RELOC_SPARC_UA64 614SPARC ELF relocations. There is probably some overlap with other 615relocation types already defined. 616@end deffn 617@deffn {} BFD_RELOC_SPARC_BASE13 618@deffnx {} BFD_RELOC_SPARC_BASE22 619I think these are specific to SPARC a.out (e.g., Sun 4). 620@end deffn 621@deffn {} BFD_RELOC_SPARC_64 622@deffnx {} BFD_RELOC_SPARC_10 623@deffnx {} BFD_RELOC_SPARC_11 624@deffnx {} BFD_RELOC_SPARC_OLO10 625@deffnx {} BFD_RELOC_SPARC_HH22 626@deffnx {} BFD_RELOC_SPARC_HM10 627@deffnx {} BFD_RELOC_SPARC_LM22 628@deffnx {} BFD_RELOC_SPARC_PC_HH22 629@deffnx {} BFD_RELOC_SPARC_PC_HM10 630@deffnx {} BFD_RELOC_SPARC_PC_LM22 631@deffnx {} BFD_RELOC_SPARC_WDISP16 632@deffnx {} BFD_RELOC_SPARC_WDISP19 633@deffnx {} BFD_RELOC_SPARC_7 634@deffnx {} BFD_RELOC_SPARC_6 635@deffnx {} BFD_RELOC_SPARC_5 636@deffnx {} BFD_RELOC_SPARC_DISP64 637@deffnx {} BFD_RELOC_SPARC_PLT32 638@deffnx {} BFD_RELOC_SPARC_PLT64 639@deffnx {} BFD_RELOC_SPARC_HIX22 640@deffnx {} BFD_RELOC_SPARC_LOX10 641@deffnx {} BFD_RELOC_SPARC_H44 642@deffnx {} BFD_RELOC_SPARC_M44 643@deffnx {} BFD_RELOC_SPARC_L44 644@deffnx {} BFD_RELOC_SPARC_REGISTER 645SPARC64 relocations 646@end deffn 647@deffn {} BFD_RELOC_SPARC_REV32 648SPARC little endian relocation 649@end deffn 650@deffn {} BFD_RELOC_SPARC_TLS_GD_HI22 651@deffnx {} BFD_RELOC_SPARC_TLS_GD_LO10 652@deffnx {} BFD_RELOC_SPARC_TLS_GD_ADD 653@deffnx {} BFD_RELOC_SPARC_TLS_GD_CALL 654@deffnx {} BFD_RELOC_SPARC_TLS_LDM_HI22 655@deffnx {} BFD_RELOC_SPARC_TLS_LDM_LO10 656@deffnx {} BFD_RELOC_SPARC_TLS_LDM_ADD 657@deffnx {} BFD_RELOC_SPARC_TLS_LDM_CALL 658@deffnx {} BFD_RELOC_SPARC_TLS_LDO_HIX22 659@deffnx {} BFD_RELOC_SPARC_TLS_LDO_LOX10 660@deffnx {} BFD_RELOC_SPARC_TLS_LDO_ADD 661@deffnx {} BFD_RELOC_SPARC_TLS_IE_HI22 662@deffnx {} BFD_RELOC_SPARC_TLS_IE_LO10 663@deffnx {} BFD_RELOC_SPARC_TLS_IE_LD 664@deffnx {} BFD_RELOC_SPARC_TLS_IE_LDX 665@deffnx {} BFD_RELOC_SPARC_TLS_IE_ADD 666@deffnx {} BFD_RELOC_SPARC_TLS_LE_HIX22 667@deffnx {} BFD_RELOC_SPARC_TLS_LE_LOX10 668@deffnx {} BFD_RELOC_SPARC_TLS_DTPMOD32 669@deffnx {} BFD_RELOC_SPARC_TLS_DTPMOD64 670@deffnx {} BFD_RELOC_SPARC_TLS_DTPOFF32 671@deffnx {} BFD_RELOC_SPARC_TLS_DTPOFF64 672@deffnx {} BFD_RELOC_SPARC_TLS_TPOFF32 673@deffnx {} BFD_RELOC_SPARC_TLS_TPOFF64 674SPARC TLS relocations 675@end deffn 676@deffn {} BFD_RELOC_ALPHA_GPDISP_HI16 677Alpha ECOFF and ELF relocations. Some of these treat the symbol or 678"addend" in some special way. 679For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when 680writing; when reading, it will be the absolute section symbol. The 681addend is the displacement in bytes of the "lda" instruction from 682the "ldah" instruction (which is at the address of this reloc). 683@end deffn 684@deffn {} BFD_RELOC_ALPHA_GPDISP_LO16 685For GPDISP_LO16 ("ignore") relocations, the symbol is handled as 686with GPDISP_HI16 relocs. The addend is ignored when writing the 687relocations out, and is filled in with the file's GP value on 688reading, for convenience. 689@end deffn 690@deffn {} BFD_RELOC_ALPHA_GPDISP 691The ELF GPDISP relocation is exactly the same as the GPDISP_HI16 692relocation except that there is no accompanying GPDISP_LO16 693relocation. 694@end deffn 695@deffn {} BFD_RELOC_ALPHA_LITERAL 696@deffnx {} BFD_RELOC_ALPHA_ELF_LITERAL 697@deffnx {} BFD_RELOC_ALPHA_LITUSE 698The Alpha LITERAL/LITUSE relocs are produced by a symbol reference; 699the assembler turns it into a LDQ instruction to load the address of 700the symbol, and then fills in a register in the real instruction. 701 702The LITERAL reloc, at the LDQ instruction, refers to the .lita 703section symbol. The addend is ignored when writing, but is filled 704in with the file's GP value on reading, for convenience, as with the 705GPDISP_LO16 reloc. 706 707The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16. 708It should refer to the symbol to be referenced, as with 16_GOTOFF, 709but it generates output not based on the position within the .got 710section, but relative to the GP value chosen for the file during the 711final link stage. 712 713The LITUSE reloc, on the instruction using the loaded address, gives 714information to the linker that it might be able to use to optimize 715away some literal section references. The symbol is ignored (read 716as the absolute section symbol), and the "addend" indicates the type 717of instruction using the register: 7181 - "memory" fmt insn 7192 - byte-manipulation (byte offset reg) 7203 - jsr (target of branch) 721@end deffn 722@deffn {} BFD_RELOC_ALPHA_HINT 723The HINT relocation indicates a value that should be filled into the 724"hint" field of a jmp/jsr/ret instruction, for possible branch- 725prediction logic which may be provided on some processors. 726@end deffn 727@deffn {} BFD_RELOC_ALPHA_LINKAGE 728The LINKAGE relocation outputs a linkage pair in the object file, 729which is filled by the linker. 730@end deffn 731@deffn {} BFD_RELOC_ALPHA_CODEADDR 732The CODEADDR relocation outputs a STO_CA in the object file, 733which is filled by the linker. 734@end deffn 735@deffn {} BFD_RELOC_ALPHA_GPREL_HI16 736@deffnx {} BFD_RELOC_ALPHA_GPREL_LO16 737The GPREL_HI/LO relocations together form a 32-bit offset from the 738GP register. 739@end deffn 740@deffn {} BFD_RELOC_ALPHA_BRSGP 741Like BFD_RELOC_23_PCREL_S2, except that the source and target must 742share a common GP, and the target address is adjusted for 743STO_ALPHA_STD_GPLOAD. 744@end deffn 745@deffn {} BFD_RELOC_ALPHA_TLSGD 746@deffnx {} BFD_RELOC_ALPHA_TLSLDM 747@deffnx {} BFD_RELOC_ALPHA_DTPMOD64 748@deffnx {} BFD_RELOC_ALPHA_GOTDTPREL16 749@deffnx {} BFD_RELOC_ALPHA_DTPREL64 750@deffnx {} BFD_RELOC_ALPHA_DTPREL_HI16 751@deffnx {} BFD_RELOC_ALPHA_DTPREL_LO16 752@deffnx {} BFD_RELOC_ALPHA_DTPREL16 753@deffnx {} BFD_RELOC_ALPHA_GOTTPREL16 754@deffnx {} BFD_RELOC_ALPHA_TPREL64 755@deffnx {} BFD_RELOC_ALPHA_TPREL_HI16 756@deffnx {} BFD_RELOC_ALPHA_TPREL_LO16 757@deffnx {} BFD_RELOC_ALPHA_TPREL16 758Alpha thread-local storage relocations. 759@end deffn 760@deffn {} BFD_RELOC_MIPS_JMP 761Bits 27..2 of the relocation address shifted right 2 bits; 762simple reloc otherwise. 763@end deffn 764@deffn {} BFD_RELOC_MIPS16_JMP 765The MIPS16 jump instruction. 766@end deffn 767@deffn {} BFD_RELOC_MIPS16_GPREL 768MIPS16 GP relative reloc. 769@end deffn 770@deffn {} BFD_RELOC_HI16 771High 16 bits of 32-bit value; simple reloc. 772@end deffn 773@deffn {} BFD_RELOC_HI16_S 774High 16 bits of 32-bit value but the low 16 bits will be sign 775extended and added to form the final result. If the low 16 776bits form a negative number, we need to add one to the high value 777to compensate for the borrow when the low bits are added. 778@end deffn 779@deffn {} BFD_RELOC_LO16 780Low 16 bits. 781@end deffn 782@deffn {} BFD_RELOC_HI16_PCREL 783High 16 bits of 32-bit pc-relative value 784@end deffn 785@deffn {} BFD_RELOC_HI16_S_PCREL 786High 16 bits of 32-bit pc-relative value, adjusted 787@end deffn 788@deffn {} BFD_RELOC_LO16_PCREL 789Low 16 bits of pc-relative value 790@end deffn 791@deffn {} BFD_RELOC_MIPS16_HI16 792MIPS16 high 16 bits of 32-bit value. 793@end deffn 794@deffn {} BFD_RELOC_MIPS16_HI16_S 795MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign 796extended and added to form the final result. If the low 16 797bits form a negative number, we need to add one to the high value 798to compensate for the borrow when the low bits are added. 799@end deffn 800@deffn {} BFD_RELOC_MIPS16_LO16 801MIPS16 low 16 bits. 802@end deffn 803@deffn {} BFD_RELOC_MIPS_LITERAL 804Relocation against a MIPS literal section. 805@end deffn 806@deffn {} BFD_RELOC_MIPS_GOT16 807@deffnx {} BFD_RELOC_MIPS_CALL16 808@deffnx {} BFD_RELOC_MIPS_GOT_HI16 809@deffnx {} BFD_RELOC_MIPS_GOT_LO16 810@deffnx {} BFD_RELOC_MIPS_CALL_HI16 811@deffnx {} BFD_RELOC_MIPS_CALL_LO16 812@deffnx {} BFD_RELOC_MIPS_SUB 813@deffnx {} BFD_RELOC_MIPS_GOT_PAGE 814@deffnx {} BFD_RELOC_MIPS_GOT_OFST 815@deffnx {} BFD_RELOC_MIPS_GOT_DISP 816@deffnx {} BFD_RELOC_MIPS_SHIFT5 817@deffnx {} BFD_RELOC_MIPS_SHIFT6 818@deffnx {} BFD_RELOC_MIPS_INSERT_A 819@deffnx {} BFD_RELOC_MIPS_INSERT_B 820@deffnx {} BFD_RELOC_MIPS_DELETE 821@deffnx {} BFD_RELOC_MIPS_HIGHEST 822@deffnx {} BFD_RELOC_MIPS_HIGHER 823@deffnx {} BFD_RELOC_MIPS_SCN_DISP 824@deffnx {} BFD_RELOC_MIPS_REL16 825@deffnx {} BFD_RELOC_MIPS_RELGOT 826@deffnx {} BFD_RELOC_MIPS_JALR 827@deffnx {} BFD_RELOC_MIPS_TLS_DTPMOD32 828@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL32 829@deffnx {} BFD_RELOC_MIPS_TLS_DTPMOD64 830@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL64 831@deffnx {} BFD_RELOC_MIPS_TLS_GD 832@deffnx {} BFD_RELOC_MIPS_TLS_LDM 833@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL_HI16 834@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL_LO16 835@deffnx {} BFD_RELOC_MIPS_TLS_GOTTPREL 836@deffnx {} BFD_RELOC_MIPS_TLS_TPREL32 837@deffnx {} BFD_RELOC_MIPS_TLS_TPREL64 838@deffnx {} BFD_RELOC_MIPS_TLS_TPREL_HI16 839@deffnx {} BFD_RELOC_MIPS_TLS_TPREL_LO16 840MIPS ELF relocations. 841@end deffn 842@deffn {} BFD_RELOC_FRV_LABEL16 843@deffnx {} BFD_RELOC_FRV_LABEL24 844@deffnx {} BFD_RELOC_FRV_LO16 845@deffnx {} BFD_RELOC_FRV_HI16 846@deffnx {} BFD_RELOC_FRV_GPREL12 847@deffnx {} BFD_RELOC_FRV_GPRELU12 848@deffnx {} BFD_RELOC_FRV_GPREL32 849@deffnx {} BFD_RELOC_FRV_GPRELHI 850@deffnx {} BFD_RELOC_FRV_GPRELLO 851@deffnx {} BFD_RELOC_FRV_GOT12 852@deffnx {} BFD_RELOC_FRV_GOTHI 853@deffnx {} BFD_RELOC_FRV_GOTLO 854@deffnx {} BFD_RELOC_FRV_FUNCDESC 855@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOT12 856@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTHI 857@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTLO 858@deffnx {} BFD_RELOC_FRV_FUNCDESC_VALUE 859@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFF12 860@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFFHI 861@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFFLO 862@deffnx {} BFD_RELOC_FRV_GOTOFF12 863@deffnx {} BFD_RELOC_FRV_GOTOFFHI 864@deffnx {} BFD_RELOC_FRV_GOTOFFLO 865@deffnx {} BFD_RELOC_FRV_GETTLSOFF 866@deffnx {} BFD_RELOC_FRV_TLSDESC_VALUE 867@deffnx {} BFD_RELOC_FRV_GOTTLSDESC12 868@deffnx {} BFD_RELOC_FRV_GOTTLSDESCHI 869@deffnx {} BFD_RELOC_FRV_GOTTLSDESCLO 870@deffnx {} BFD_RELOC_FRV_TLSMOFF12 871@deffnx {} BFD_RELOC_FRV_TLSMOFFHI 872@deffnx {} BFD_RELOC_FRV_TLSMOFFLO 873@deffnx {} BFD_RELOC_FRV_GOTTLSOFF12 874@deffnx {} BFD_RELOC_FRV_GOTTLSOFFHI 875@deffnx {} BFD_RELOC_FRV_GOTTLSOFFLO 876@deffnx {} BFD_RELOC_FRV_TLSOFF 877@deffnx {} BFD_RELOC_FRV_TLSDESC_RELAX 878@deffnx {} BFD_RELOC_FRV_GETTLSOFF_RELAX 879@deffnx {} BFD_RELOC_FRV_TLSOFF_RELAX 880@deffnx {} BFD_RELOC_FRV_TLSMOFF 881Fujitsu Frv Relocations. 882@end deffn 883@deffn {} BFD_RELOC_MN10300_GOTOFF24 884This is a 24bit GOT-relative reloc for the mn10300. 885@end deffn 886@deffn {} BFD_RELOC_MN10300_GOT32 887This is a 32bit GOT-relative reloc for the mn10300, offset by two bytes 888in the instruction. 889@end deffn 890@deffn {} BFD_RELOC_MN10300_GOT24 891This is a 24bit GOT-relative reloc for the mn10300, offset by two bytes 892in the instruction. 893@end deffn 894@deffn {} BFD_RELOC_MN10300_GOT16 895This is a 16bit GOT-relative reloc for the mn10300, offset by two bytes 896in the instruction. 897@end deffn 898@deffn {} BFD_RELOC_MN10300_COPY 899Copy symbol at runtime. 900@end deffn 901@deffn {} BFD_RELOC_MN10300_GLOB_DAT 902Create GOT entry. 903@end deffn 904@deffn {} BFD_RELOC_MN10300_JMP_SLOT 905Create PLT entry. 906@end deffn 907@deffn {} BFD_RELOC_MN10300_RELATIVE 908Adjust by program base. 909@end deffn 910@deffn {} BFD_RELOC_386_GOT32 911@deffnx {} BFD_RELOC_386_PLT32 912@deffnx {} BFD_RELOC_386_COPY 913@deffnx {} BFD_RELOC_386_GLOB_DAT 914@deffnx {} BFD_RELOC_386_JUMP_SLOT 915@deffnx {} BFD_RELOC_386_RELATIVE 916@deffnx {} BFD_RELOC_386_GOTOFF 917@deffnx {} BFD_RELOC_386_GOTPC 918@deffnx {} BFD_RELOC_386_TLS_TPOFF 919@deffnx {} BFD_RELOC_386_TLS_IE 920@deffnx {} BFD_RELOC_386_TLS_GOTIE 921@deffnx {} BFD_RELOC_386_TLS_LE 922@deffnx {} BFD_RELOC_386_TLS_GD 923@deffnx {} BFD_RELOC_386_TLS_LDM 924@deffnx {} BFD_RELOC_386_TLS_LDO_32 925@deffnx {} BFD_RELOC_386_TLS_IE_32 926@deffnx {} BFD_RELOC_386_TLS_LE_32 927@deffnx {} BFD_RELOC_386_TLS_DTPMOD32 928@deffnx {} BFD_RELOC_386_TLS_DTPOFF32 929@deffnx {} BFD_RELOC_386_TLS_TPOFF32 930i386/elf relocations 931@end deffn 932@deffn {} BFD_RELOC_X86_64_GOT32 933@deffnx {} BFD_RELOC_X86_64_PLT32 934@deffnx {} BFD_RELOC_X86_64_COPY 935@deffnx {} BFD_RELOC_X86_64_GLOB_DAT 936@deffnx {} BFD_RELOC_X86_64_JUMP_SLOT 937@deffnx {} BFD_RELOC_X86_64_RELATIVE 938@deffnx {} BFD_RELOC_X86_64_GOTPCREL 939@deffnx {} BFD_RELOC_X86_64_32S 940@deffnx {} BFD_RELOC_X86_64_DTPMOD64 941@deffnx {} BFD_RELOC_X86_64_DTPOFF64 942@deffnx {} BFD_RELOC_X86_64_TPOFF64 943@deffnx {} BFD_RELOC_X86_64_TLSGD 944@deffnx {} BFD_RELOC_X86_64_TLSLD 945@deffnx {} BFD_RELOC_X86_64_DTPOFF32 946@deffnx {} BFD_RELOC_X86_64_GOTTPOFF 947@deffnx {} BFD_RELOC_X86_64_TPOFF32 948@deffnx {} BFD_RELOC_X86_64_GOTOFF64 949@deffnx {} BFD_RELOC_X86_64_GOTPC32 950x86-64/elf relocations 951@end deffn 952@deffn {} BFD_RELOC_NS32K_IMM_8 953@deffnx {} BFD_RELOC_NS32K_IMM_16 954@deffnx {} BFD_RELOC_NS32K_IMM_32 955@deffnx {} BFD_RELOC_NS32K_IMM_8_PCREL 956@deffnx {} BFD_RELOC_NS32K_IMM_16_PCREL 957@deffnx {} BFD_RELOC_NS32K_IMM_32_PCREL 958@deffnx {} BFD_RELOC_NS32K_DISP_8 959@deffnx {} BFD_RELOC_NS32K_DISP_16 960@deffnx {} BFD_RELOC_NS32K_DISP_32 961@deffnx {} BFD_RELOC_NS32K_DISP_8_PCREL 962@deffnx {} BFD_RELOC_NS32K_DISP_16_PCREL 963@deffnx {} BFD_RELOC_NS32K_DISP_32_PCREL 964ns32k relocations 965@end deffn 966@deffn {} BFD_RELOC_PDP11_DISP_8_PCREL 967@deffnx {} BFD_RELOC_PDP11_DISP_6_PCREL 968PDP11 relocations 969@end deffn 970@deffn {} BFD_RELOC_PJ_CODE_HI16 971@deffnx {} BFD_RELOC_PJ_CODE_LO16 972@deffnx {} BFD_RELOC_PJ_CODE_DIR16 973@deffnx {} BFD_RELOC_PJ_CODE_DIR32 974@deffnx {} BFD_RELOC_PJ_CODE_REL16 975@deffnx {} BFD_RELOC_PJ_CODE_REL32 976Picojava relocs. Not all of these appear in object files. 977@end deffn 978@deffn {} BFD_RELOC_PPC_B26 979@deffnx {} BFD_RELOC_PPC_BA26 980@deffnx {} BFD_RELOC_PPC_TOC16 981@deffnx {} BFD_RELOC_PPC_B16 982@deffnx {} BFD_RELOC_PPC_B16_BRTAKEN 983@deffnx {} BFD_RELOC_PPC_B16_BRNTAKEN 984@deffnx {} BFD_RELOC_PPC_BA16 985@deffnx {} BFD_RELOC_PPC_BA16_BRTAKEN 986@deffnx {} BFD_RELOC_PPC_BA16_BRNTAKEN 987@deffnx {} BFD_RELOC_PPC_COPY 988@deffnx {} BFD_RELOC_PPC_GLOB_DAT 989@deffnx {} BFD_RELOC_PPC_JMP_SLOT 990@deffnx {} BFD_RELOC_PPC_RELATIVE 991@deffnx {} BFD_RELOC_PPC_LOCAL24PC 992@deffnx {} BFD_RELOC_PPC_EMB_NADDR32 993@deffnx {} BFD_RELOC_PPC_EMB_NADDR16 994@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_LO 995@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_HI 996@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_HA 997@deffnx {} BFD_RELOC_PPC_EMB_SDAI16 998@deffnx {} BFD_RELOC_PPC_EMB_SDA2I16 999@deffnx {} BFD_RELOC_PPC_EMB_SDA2REL 1000@deffnx {} BFD_RELOC_PPC_EMB_SDA21 1001@deffnx {} BFD_RELOC_PPC_EMB_MRKREF 1002@deffnx {} BFD_RELOC_PPC_EMB_RELSEC16 1003@deffnx {} BFD_RELOC_PPC_EMB_RELST_LO 1004@deffnx {} BFD_RELOC_PPC_EMB_RELST_HI 1005@deffnx {} BFD_RELOC_PPC_EMB_RELST_HA 1006@deffnx {} BFD_RELOC_PPC_EMB_BIT_FLD 1007@deffnx {} BFD_RELOC_PPC_EMB_RELSDA 1008@deffnx {} BFD_RELOC_PPC64_HIGHER 1009@deffnx {} BFD_RELOC_PPC64_HIGHER_S 1010@deffnx {} BFD_RELOC_PPC64_HIGHEST 1011@deffnx {} BFD_RELOC_PPC64_HIGHEST_S 1012@deffnx {} BFD_RELOC_PPC64_TOC16_LO 1013@deffnx {} BFD_RELOC_PPC64_TOC16_HI 1014@deffnx {} BFD_RELOC_PPC64_TOC16_HA 1015@deffnx {} BFD_RELOC_PPC64_TOC 1016@deffnx {} BFD_RELOC_PPC64_PLTGOT16 1017@deffnx {} BFD_RELOC_PPC64_PLTGOT16_LO 1018@deffnx {} BFD_RELOC_PPC64_PLTGOT16_HI 1019@deffnx {} BFD_RELOC_PPC64_PLTGOT16_HA 1020@deffnx {} BFD_RELOC_PPC64_ADDR16_DS 1021@deffnx {} BFD_RELOC_PPC64_ADDR16_LO_DS 1022@deffnx {} BFD_RELOC_PPC64_GOT16_DS 1023@deffnx {} BFD_RELOC_PPC64_GOT16_LO_DS 1024@deffnx {} BFD_RELOC_PPC64_PLT16_LO_DS 1025@deffnx {} BFD_RELOC_PPC64_SECTOFF_DS 1026@deffnx {} BFD_RELOC_PPC64_SECTOFF_LO_DS 1027@deffnx {} BFD_RELOC_PPC64_TOC16_DS 1028@deffnx {} BFD_RELOC_PPC64_TOC16_LO_DS 1029@deffnx {} BFD_RELOC_PPC64_PLTGOT16_DS 1030@deffnx {} BFD_RELOC_PPC64_PLTGOT16_LO_DS 1031Power(rs6000) and PowerPC relocations. 1032@end deffn 1033@deffn {} BFD_RELOC_PPC_TLS 1034@deffnx {} BFD_RELOC_PPC_DTPMOD 1035@deffnx {} BFD_RELOC_PPC_TPREL16 1036@deffnx {} BFD_RELOC_PPC_TPREL16_LO 1037@deffnx {} BFD_RELOC_PPC_TPREL16_HI 1038@deffnx {} BFD_RELOC_PPC_TPREL16_HA 1039@deffnx {} BFD_RELOC_PPC_TPREL 1040@deffnx {} BFD_RELOC_PPC_DTPREL16 1041@deffnx {} BFD_RELOC_PPC_DTPREL16_LO 1042@deffnx {} BFD_RELOC_PPC_DTPREL16_HI 1043@deffnx {} BFD_RELOC_PPC_DTPREL16_HA 1044@deffnx {} BFD_RELOC_PPC_DTPREL 1045@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16 1046@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_LO 1047@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_HI 1048@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_HA 1049@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16 1050@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_LO 1051@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_HI 1052@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_HA 1053@deffnx {} BFD_RELOC_PPC_GOT_TPREL16 1054@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_LO 1055@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_HI 1056@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_HA 1057@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16 1058@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_LO 1059@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_HI 1060@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_HA 1061@deffnx {} BFD_RELOC_PPC64_TPREL16_DS 1062@deffnx {} BFD_RELOC_PPC64_TPREL16_LO_DS 1063@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHER 1064@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHERA 1065@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHEST 1066@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHESTA 1067@deffnx {} BFD_RELOC_PPC64_DTPREL16_DS 1068@deffnx {} BFD_RELOC_PPC64_DTPREL16_LO_DS 1069@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHER 1070@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHERA 1071@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHEST 1072@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHESTA 1073PowerPC and PowerPC64 thread-local storage relocations. 1074@end deffn 1075@deffn {} BFD_RELOC_I370_D12 1076IBM 370/390 relocations 1077@end deffn 1078@deffn {} BFD_RELOC_CTOR 1079The type of reloc used to build a constructor table - at the moment 1080probably a 32 bit wide absolute relocation, but the target can choose. 1081It generally does map to one of the other relocation types. 1082@end deffn 1083@deffn {} BFD_RELOC_ARM_PCREL_BRANCH 1084ARM 26 bit pc-relative branch. The lowest two bits must be zero and are 1085not stored in the instruction. 1086@end deffn 1087@deffn {} BFD_RELOC_ARM_PCREL_BLX 1088ARM 26 bit pc-relative branch. The lowest bit must be zero and is 1089not stored in the instruction. The 2nd lowest bit comes from a 1 bit 1090field in the instruction. 1091@end deffn 1092@deffn {} BFD_RELOC_THUMB_PCREL_BLX 1093Thumb 22 bit pc-relative branch. The lowest bit must be zero and is 1094not stored in the instruction. The 2nd lowest bit comes from a 1 bit 1095field in the instruction. 1096@end deffn 1097@deffn {} BFD_RELOC_THUMB_PCREL_BRANCH7 1098@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH9 1099@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH12 1100@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH20 1101@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH23 1102@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH25 1103Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches. 1104The lowest bit must be zero and is not stored in the instruction. 1105Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an 1106"nn" one smaller in all cases. Note further that BRANCH23 1107corresponds to R_ARM_THM_CALL. 1108@end deffn 1109@deffn {} BFD_RELOC_ARM_OFFSET_IMM 111012-bit immediate offset, used in ARM-format ldr and str instructions. 1111@end deffn 1112@deffn {} BFD_RELOC_ARM_THUMB_OFFSET 11135-bit immediate offset, used in Thumb-format ldr and str instructions. 1114@end deffn 1115@deffn {} BFD_RELOC_ARM_TARGET1 1116Pc-relative or absolute relocation depending on target. Used for 1117entries in .init_array sections. 1118@end deffn 1119@deffn {} BFD_RELOC_ARM_ROSEGREL32 1120Read-only segment base relative address. 1121@end deffn 1122@deffn {} BFD_RELOC_ARM_SBREL32 1123Data segment base relative address. 1124@end deffn 1125@deffn {} BFD_RELOC_ARM_TARGET2 1126This reloc is used for references to RTTI data from exception handling 1127tables. The actual definition depends on the target. It may be a 1128pc-relative or some form of GOT-indirect relocation. 1129@end deffn 1130@deffn {} BFD_RELOC_ARM_PREL31 113131-bit PC relative address. 1132@end deffn 1133@deffn {} BFD_RELOC_ARM_JUMP_SLOT 1134@deffnx {} BFD_RELOC_ARM_GLOB_DAT 1135@deffnx {} BFD_RELOC_ARM_GOT32 1136@deffnx {} BFD_RELOC_ARM_PLT32 1137@deffnx {} BFD_RELOC_ARM_RELATIVE 1138@deffnx {} BFD_RELOC_ARM_GOTOFF 1139@deffnx {} BFD_RELOC_ARM_GOTPC 1140Relocations for setting up GOTs and PLTs for shared libraries. 1141@end deffn 1142@deffn {} BFD_RELOC_ARM_TLS_GD32 1143@deffnx {} BFD_RELOC_ARM_TLS_LDO32 1144@deffnx {} BFD_RELOC_ARM_TLS_LDM32 1145@deffnx {} BFD_RELOC_ARM_TLS_DTPOFF32 1146@deffnx {} BFD_RELOC_ARM_TLS_DTPMOD32 1147@deffnx {} BFD_RELOC_ARM_TLS_TPOFF32 1148@deffnx {} BFD_RELOC_ARM_TLS_IE32 1149@deffnx {} BFD_RELOC_ARM_TLS_LE32 1150ARM thread-local storage relocations. 1151@end deffn 1152@deffn {} BFD_RELOC_ARM_IMMEDIATE 1153@deffnx {} BFD_RELOC_ARM_ADRL_IMMEDIATE 1154@deffnx {} BFD_RELOC_ARM_T32_IMMEDIATE 1155@deffnx {} BFD_RELOC_ARM_SHIFT_IMM 1156@deffnx {} BFD_RELOC_ARM_SMI 1157@deffnx {} BFD_RELOC_ARM_SWI 1158@deffnx {} BFD_RELOC_ARM_MULTI 1159@deffnx {} BFD_RELOC_ARM_CP_OFF_IMM 1160@deffnx {} BFD_RELOC_ARM_CP_OFF_IMM_S2 1161@deffnx {} BFD_RELOC_ARM_ADR_IMM 1162@deffnx {} BFD_RELOC_ARM_LDR_IMM 1163@deffnx {} BFD_RELOC_ARM_LITERAL 1164@deffnx {} BFD_RELOC_ARM_IN_POOL 1165@deffnx {} BFD_RELOC_ARM_OFFSET_IMM8 1166@deffnx {} BFD_RELOC_ARM_T32_OFFSET_U8 1167@deffnx {} BFD_RELOC_ARM_T32_OFFSET_IMM 1168@deffnx {} BFD_RELOC_ARM_HWLITERAL 1169@deffnx {} BFD_RELOC_ARM_THUMB_ADD 1170@deffnx {} BFD_RELOC_ARM_THUMB_IMM 1171@deffnx {} BFD_RELOC_ARM_THUMB_SHIFT 1172These relocs are only used within the ARM assembler. They are not 1173(at present) written to any object files. 1174@end deffn 1175@deffn {} BFD_RELOC_SH_PCDISP8BY2 1176@deffnx {} BFD_RELOC_SH_PCDISP12BY2 1177@deffnx {} BFD_RELOC_SH_IMM3 1178@deffnx {} BFD_RELOC_SH_IMM3U 1179@deffnx {} BFD_RELOC_SH_DISP12 1180@deffnx {} BFD_RELOC_SH_DISP12BY2 1181@deffnx {} BFD_RELOC_SH_DISP12BY4 1182@deffnx {} BFD_RELOC_SH_DISP12BY8 1183@deffnx {} BFD_RELOC_SH_DISP20 1184@deffnx {} BFD_RELOC_SH_DISP20BY8 1185@deffnx {} BFD_RELOC_SH_IMM4 1186@deffnx {} BFD_RELOC_SH_IMM4BY2 1187@deffnx {} BFD_RELOC_SH_IMM4BY4 1188@deffnx {} BFD_RELOC_SH_IMM8 1189@deffnx {} BFD_RELOC_SH_IMM8BY2 1190@deffnx {} BFD_RELOC_SH_IMM8BY4 1191@deffnx {} BFD_RELOC_SH_PCRELIMM8BY2 1192@deffnx {} BFD_RELOC_SH_PCRELIMM8BY4 1193@deffnx {} BFD_RELOC_SH_SWITCH16 1194@deffnx {} BFD_RELOC_SH_SWITCH32 1195@deffnx {} BFD_RELOC_SH_USES 1196@deffnx {} BFD_RELOC_SH_COUNT 1197@deffnx {} BFD_RELOC_SH_ALIGN 1198@deffnx {} BFD_RELOC_SH_CODE 1199@deffnx {} BFD_RELOC_SH_DATA 1200@deffnx {} BFD_RELOC_SH_LABEL 1201@deffnx {} BFD_RELOC_SH_LOOP_START 1202@deffnx {} BFD_RELOC_SH_LOOP_END 1203@deffnx {} BFD_RELOC_SH_COPY 1204@deffnx {} BFD_RELOC_SH_GLOB_DAT 1205@deffnx {} BFD_RELOC_SH_JMP_SLOT 1206@deffnx {} BFD_RELOC_SH_RELATIVE 1207@deffnx {} BFD_RELOC_SH_GOTPC 1208@deffnx {} BFD_RELOC_SH_GOT_LOW16 1209@deffnx {} BFD_RELOC_SH_GOT_MEDLOW16 1210@deffnx {} BFD_RELOC_SH_GOT_MEDHI16 1211@deffnx {} BFD_RELOC_SH_GOT_HI16 1212@deffnx {} BFD_RELOC_SH_GOTPLT_LOW16 1213@deffnx {} BFD_RELOC_SH_GOTPLT_MEDLOW16 1214@deffnx {} BFD_RELOC_SH_GOTPLT_MEDHI16 1215@deffnx {} BFD_RELOC_SH_GOTPLT_HI16 1216@deffnx {} BFD_RELOC_SH_PLT_LOW16 1217@deffnx {} BFD_RELOC_SH_PLT_MEDLOW16 1218@deffnx {} BFD_RELOC_SH_PLT_MEDHI16 1219@deffnx {} BFD_RELOC_SH_PLT_HI16 1220@deffnx {} BFD_RELOC_SH_GOTOFF_LOW16 1221@deffnx {} BFD_RELOC_SH_GOTOFF_MEDLOW16 1222@deffnx {} BFD_RELOC_SH_GOTOFF_MEDHI16 1223@deffnx {} BFD_RELOC_SH_GOTOFF_HI16 1224@deffnx {} BFD_RELOC_SH_GOTPC_LOW16 1225@deffnx {} BFD_RELOC_SH_GOTPC_MEDLOW16 1226@deffnx {} BFD_RELOC_SH_GOTPC_MEDHI16 1227@deffnx {} BFD_RELOC_SH_GOTPC_HI16 1228@deffnx {} BFD_RELOC_SH_COPY64 1229@deffnx {} BFD_RELOC_SH_GLOB_DAT64 1230@deffnx {} BFD_RELOC_SH_JMP_SLOT64 1231@deffnx {} BFD_RELOC_SH_RELATIVE64 1232@deffnx {} BFD_RELOC_SH_GOT10BY4 1233@deffnx {} BFD_RELOC_SH_GOT10BY8 1234@deffnx {} BFD_RELOC_SH_GOTPLT10BY4 1235@deffnx {} BFD_RELOC_SH_GOTPLT10BY8 1236@deffnx {} BFD_RELOC_SH_GOTPLT32 1237@deffnx {} BFD_RELOC_SH_SHMEDIA_CODE 1238@deffnx {} BFD_RELOC_SH_IMMU5 1239@deffnx {} BFD_RELOC_SH_IMMS6 1240@deffnx {} BFD_RELOC_SH_IMMS6BY32 1241@deffnx {} BFD_RELOC_SH_IMMU6 1242@deffnx {} BFD_RELOC_SH_IMMS10 1243@deffnx {} BFD_RELOC_SH_IMMS10BY2 1244@deffnx {} BFD_RELOC_SH_IMMS10BY4 1245@deffnx {} BFD_RELOC_SH_IMMS10BY8 1246@deffnx {} BFD_RELOC_SH_IMMS16 1247@deffnx {} BFD_RELOC_SH_IMMU16 1248@deffnx {} BFD_RELOC_SH_IMM_LOW16 1249@deffnx {} BFD_RELOC_SH_IMM_LOW16_PCREL 1250@deffnx {} BFD_RELOC_SH_IMM_MEDLOW16 1251@deffnx {} BFD_RELOC_SH_IMM_MEDLOW16_PCREL 1252@deffnx {} BFD_RELOC_SH_IMM_MEDHI16 1253@deffnx {} BFD_RELOC_SH_IMM_MEDHI16_PCREL 1254@deffnx {} BFD_RELOC_SH_IMM_HI16 1255@deffnx {} BFD_RELOC_SH_IMM_HI16_PCREL 1256@deffnx {} BFD_RELOC_SH_PT_16 1257@deffnx {} BFD_RELOC_SH_TLS_GD_32 1258@deffnx {} BFD_RELOC_SH_TLS_LD_32 1259@deffnx {} BFD_RELOC_SH_TLS_LDO_32 1260@deffnx {} BFD_RELOC_SH_TLS_IE_32 1261@deffnx {} BFD_RELOC_SH_TLS_LE_32 1262@deffnx {} BFD_RELOC_SH_TLS_DTPMOD32 1263@deffnx {} BFD_RELOC_SH_TLS_DTPOFF32 1264@deffnx {} BFD_RELOC_SH_TLS_TPOFF32 1265Renesas / SuperH SH relocs. Not all of these appear in object files. 1266@end deffn 1267@deffn {} BFD_RELOC_ARC_B22_PCREL 1268ARC Cores relocs. 1269ARC 22 bit pc-relative branch. The lowest two bits must be zero and are 1270not stored in the instruction. The high 20 bits are installed in bits 26 1271through 7 of the instruction. 1272@end deffn 1273@deffn {} BFD_RELOC_ARC_B26 1274ARC 26 bit absolute branch. The lowest two bits must be zero and are not 1275stored in the instruction. The high 24 bits are installed in bits 23 1276through 0. 1277@end deffn 1278@deffn {} BFD_RELOC_D10V_10_PCREL_R 1279Mitsubishi D10V relocs. 1280This is a 10-bit reloc with the right 2 bits 1281assumed to be 0. 1282@end deffn 1283@deffn {} BFD_RELOC_D10V_10_PCREL_L 1284Mitsubishi D10V relocs. 1285This is a 10-bit reloc with the right 2 bits 1286assumed to be 0. This is the same as the previous reloc 1287except it is in the left container, i.e., 1288shifted left 15 bits. 1289@end deffn 1290@deffn {} BFD_RELOC_D10V_18 1291This is an 18-bit reloc with the right 2 bits 1292assumed to be 0. 1293@end deffn 1294@deffn {} BFD_RELOC_D10V_18_PCREL 1295This is an 18-bit reloc with the right 2 bits 1296assumed to be 0. 1297@end deffn 1298@deffn {} BFD_RELOC_D30V_6 1299Mitsubishi D30V relocs. 1300This is a 6-bit absolute reloc. 1301@end deffn 1302@deffn {} BFD_RELOC_D30V_9_PCREL 1303This is a 6-bit pc-relative reloc with 1304the right 3 bits assumed to be 0. 1305@end deffn 1306@deffn {} BFD_RELOC_D30V_9_PCREL_R 1307This is a 6-bit pc-relative reloc with 1308the right 3 bits assumed to be 0. Same 1309as the previous reloc but on the right side 1310of the container. 1311@end deffn 1312@deffn {} BFD_RELOC_D30V_15 1313This is a 12-bit absolute reloc with the 1314right 3 bitsassumed to be 0. 1315@end deffn 1316@deffn {} BFD_RELOC_D30V_15_PCREL 1317This is a 12-bit pc-relative reloc with 1318the right 3 bits assumed to be 0. 1319@end deffn 1320@deffn {} BFD_RELOC_D30V_15_PCREL_R 1321This is a 12-bit pc-relative reloc with 1322the right 3 bits assumed to be 0. Same 1323as the previous reloc but on the right side 1324of the container. 1325@end deffn 1326@deffn {} BFD_RELOC_D30V_21 1327This is an 18-bit absolute reloc with 1328the right 3 bits assumed to be 0. 1329@end deffn 1330@deffn {} BFD_RELOC_D30V_21_PCREL 1331This is an 18-bit pc-relative reloc with 1332the right 3 bits assumed to be 0. 1333@end deffn 1334@deffn {} BFD_RELOC_D30V_21_PCREL_R 1335This is an 18-bit pc-relative reloc with 1336the right 3 bits assumed to be 0. Same 1337as the previous reloc but on the right side 1338of the container. 1339@end deffn 1340@deffn {} BFD_RELOC_D30V_32 1341This is a 32-bit absolute reloc. 1342@end deffn 1343@deffn {} BFD_RELOC_D30V_32_PCREL 1344This is a 32-bit pc-relative reloc. 1345@end deffn 1346@deffn {} BFD_RELOC_DLX_HI16_S 1347DLX relocs 1348@end deffn 1349@deffn {} BFD_RELOC_DLX_LO16 1350DLX relocs 1351@end deffn 1352@deffn {} BFD_RELOC_DLX_JMP26 1353DLX relocs 1354@end deffn 1355@deffn {} BFD_RELOC_M32R_24 1356Renesas M32R (formerly Mitsubishi M32R) relocs. 1357This is a 24 bit absolute address. 1358@end deffn 1359@deffn {} BFD_RELOC_M32R_10_PCREL 1360This is a 10-bit pc-relative reloc with the right 2 bits assumed to be 0. 1361@end deffn 1362@deffn {} BFD_RELOC_M32R_18_PCREL 1363This is an 18-bit reloc with the right 2 bits assumed to be 0. 1364@end deffn 1365@deffn {} BFD_RELOC_M32R_26_PCREL 1366This is a 26-bit reloc with the right 2 bits assumed to be 0. 1367@end deffn 1368@deffn {} BFD_RELOC_M32R_HI16_ULO 1369This is a 16-bit reloc containing the high 16 bits of an address 1370used when the lower 16 bits are treated as unsigned. 1371@end deffn 1372@deffn {} BFD_RELOC_M32R_HI16_SLO 1373This is a 16-bit reloc containing the high 16 bits of an address 1374used when the lower 16 bits are treated as signed. 1375@end deffn 1376@deffn {} BFD_RELOC_M32R_LO16 1377This is a 16-bit reloc containing the lower 16 bits of an address. 1378@end deffn 1379@deffn {} BFD_RELOC_M32R_SDA16 1380This is a 16-bit reloc containing the small data area offset for use in 1381add3, load, and store instructions. 1382@end deffn 1383@deffn {} BFD_RELOC_M32R_GOT24 1384@deffnx {} BFD_RELOC_M32R_26_PLTREL 1385@deffnx {} BFD_RELOC_M32R_COPY 1386@deffnx {} BFD_RELOC_M32R_GLOB_DAT 1387@deffnx {} BFD_RELOC_M32R_JMP_SLOT 1388@deffnx {} BFD_RELOC_M32R_RELATIVE 1389@deffnx {} BFD_RELOC_M32R_GOTOFF 1390@deffnx {} BFD_RELOC_M32R_GOTOFF_HI_ULO 1391@deffnx {} BFD_RELOC_M32R_GOTOFF_HI_SLO 1392@deffnx {} BFD_RELOC_M32R_GOTOFF_LO 1393@deffnx {} BFD_RELOC_M32R_GOTPC24 1394@deffnx {} BFD_RELOC_M32R_GOT16_HI_ULO 1395@deffnx {} BFD_RELOC_M32R_GOT16_HI_SLO 1396@deffnx {} BFD_RELOC_M32R_GOT16_LO 1397@deffnx {} BFD_RELOC_M32R_GOTPC_HI_ULO 1398@deffnx {} BFD_RELOC_M32R_GOTPC_HI_SLO 1399@deffnx {} BFD_RELOC_M32R_GOTPC_LO 1400For PIC. 1401@end deffn 1402@deffn {} BFD_RELOC_V850_9_PCREL 1403This is a 9-bit reloc 1404@end deffn 1405@deffn {} BFD_RELOC_V850_22_PCREL 1406This is a 22-bit reloc 1407@end deffn 1408@deffn {} BFD_RELOC_V850_SDA_16_16_OFFSET 1409This is a 16 bit offset from the short data area pointer. 1410@end deffn 1411@deffn {} BFD_RELOC_V850_SDA_15_16_OFFSET 1412This is a 16 bit offset (of which only 15 bits are used) from the 1413short data area pointer. 1414@end deffn 1415@deffn {} BFD_RELOC_V850_ZDA_16_16_OFFSET 1416This is a 16 bit offset from the zero data area pointer. 1417@end deffn 1418@deffn {} BFD_RELOC_V850_ZDA_15_16_OFFSET 1419This is a 16 bit offset (of which only 15 bits are used) from the 1420zero data area pointer. 1421@end deffn 1422@deffn {} BFD_RELOC_V850_TDA_6_8_OFFSET 1423This is an 8 bit offset (of which only 6 bits are used) from the 1424tiny data area pointer. 1425@end deffn 1426@deffn {} BFD_RELOC_V850_TDA_7_8_OFFSET 1427This is an 8bit offset (of which only 7 bits are used) from the tiny 1428data area pointer. 1429@end deffn 1430@deffn {} BFD_RELOC_V850_TDA_7_7_OFFSET 1431This is a 7 bit offset from the tiny data area pointer. 1432@end deffn 1433@deffn {} BFD_RELOC_V850_TDA_16_16_OFFSET 1434This is a 16 bit offset from the tiny data area pointer. 1435@end deffn 1436@deffn {} BFD_RELOC_V850_TDA_4_5_OFFSET 1437This is a 5 bit offset (of which only 4 bits are used) from the tiny 1438data area pointer. 1439@end deffn 1440@deffn {} BFD_RELOC_V850_TDA_4_4_OFFSET 1441This is a 4 bit offset from the tiny data area pointer. 1442@end deffn 1443@deffn {} BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET 1444This is a 16 bit offset from the short data area pointer, with the 1445bits placed non-contiguously in the instruction. 1446@end deffn 1447@deffn {} BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET 1448This is a 16 bit offset from the zero data area pointer, with the 1449bits placed non-contiguously in the instruction. 1450@end deffn 1451@deffn {} BFD_RELOC_V850_CALLT_6_7_OFFSET 1452This is a 6 bit offset from the call table base pointer. 1453@end deffn 1454@deffn {} BFD_RELOC_V850_CALLT_16_16_OFFSET 1455This is a 16 bit offset from the call table base pointer. 1456@end deffn 1457@deffn {} BFD_RELOC_V850_LONGCALL 1458Used for relaxing indirect function calls. 1459@end deffn 1460@deffn {} BFD_RELOC_V850_LONGJUMP 1461Used for relaxing indirect jumps. 1462@end deffn 1463@deffn {} BFD_RELOC_V850_ALIGN 1464Used to maintain alignment whilst relaxing. 1465@end deffn 1466@deffn {} BFD_RELOC_V850_LO16_SPLIT_OFFSET 1467This is a variation of BFD_RELOC_LO16 that can be used in v850e ld.bu 1468instructions. 1469@end deffn 1470@deffn {} BFD_RELOC_MN10300_32_PCREL 1471This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the 1472instruction. 1473@end deffn 1474@deffn {} BFD_RELOC_MN10300_16_PCREL 1475This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the 1476instruction. 1477@end deffn 1478@deffn {} BFD_RELOC_TIC30_LDP 1479This is a 8bit DP reloc for the tms320c30, where the most 1480significant 8 bits of a 24 bit word are placed into the least 1481significant 8 bits of the opcode. 1482@end deffn 1483@deffn {} BFD_RELOC_TIC54X_PARTLS7 1484This is a 7bit reloc for the tms320c54x, where the least 1485significant 7 bits of a 16 bit word are placed into the least 1486significant 7 bits of the opcode. 1487@end deffn 1488@deffn {} BFD_RELOC_TIC54X_PARTMS9 1489This is a 9bit DP reloc for the tms320c54x, where the most 1490significant 9 bits of a 16 bit word are placed into the least 1491significant 9 bits of the opcode. 1492@end deffn 1493@deffn {} BFD_RELOC_TIC54X_23 1494This is an extended address 23-bit reloc for the tms320c54x. 1495@end deffn 1496@deffn {} BFD_RELOC_TIC54X_16_OF_23 1497This is a 16-bit reloc for the tms320c54x, where the least 1498significant 16 bits of a 23-bit extended address are placed into 1499the opcode. 1500@end deffn 1501@deffn {} BFD_RELOC_TIC54X_MS7_OF_23 1502This is a reloc for the tms320c54x, where the most 1503significant 7 bits of a 23-bit extended address are placed into 1504the opcode. 1505@end deffn 1506@deffn {} BFD_RELOC_FR30_48 1507This is a 48 bit reloc for the FR30 that stores 32 bits. 1508@end deffn 1509@deffn {} BFD_RELOC_FR30_20 1510This is a 32 bit reloc for the FR30 that stores 20 bits split up into 1511two sections. 1512@end deffn 1513@deffn {} BFD_RELOC_FR30_6_IN_4 1514This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in 15154 bits. 1516@end deffn 1517@deffn {} BFD_RELOC_FR30_8_IN_8 1518This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset 1519into 8 bits. 1520@end deffn 1521@deffn {} BFD_RELOC_FR30_9_IN_8 1522This is a 16 bit reloc for the FR30 that stores a 9 bit short offset 1523into 8 bits. 1524@end deffn 1525@deffn {} BFD_RELOC_FR30_10_IN_8 1526This is a 16 bit reloc for the FR30 that stores a 10 bit word offset 1527into 8 bits. 1528@end deffn 1529@deffn {} BFD_RELOC_FR30_9_PCREL 1530This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative 1531short offset into 8 bits. 1532@end deffn 1533@deffn {} BFD_RELOC_FR30_12_PCREL 1534This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative 1535short offset into 11 bits. 1536@end deffn 1537@deffn {} BFD_RELOC_MCORE_PCREL_IMM8BY4 1538@deffnx {} BFD_RELOC_MCORE_PCREL_IMM11BY2 1539@deffnx {} BFD_RELOC_MCORE_PCREL_IMM4BY2 1540@deffnx {} BFD_RELOC_MCORE_PCREL_32 1541@deffnx {} BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2 1542@deffnx {} BFD_RELOC_MCORE_RVA 1543Motorola Mcore relocations. 1544@end deffn 1545@deffn {} BFD_RELOC_MMIX_GETA 1546@deffnx {} BFD_RELOC_MMIX_GETA_1 1547@deffnx {} BFD_RELOC_MMIX_GETA_2 1548@deffnx {} BFD_RELOC_MMIX_GETA_3 1549These are relocations for the GETA instruction. 1550@end deffn 1551@deffn {} BFD_RELOC_MMIX_CBRANCH 1552@deffnx {} BFD_RELOC_MMIX_CBRANCH_J 1553@deffnx {} BFD_RELOC_MMIX_CBRANCH_1 1554@deffnx {} BFD_RELOC_MMIX_CBRANCH_2 1555@deffnx {} BFD_RELOC_MMIX_CBRANCH_3 1556These are relocations for a conditional branch instruction. 1557@end deffn 1558@deffn {} BFD_RELOC_MMIX_PUSHJ 1559@deffnx {} BFD_RELOC_MMIX_PUSHJ_1 1560@deffnx {} BFD_RELOC_MMIX_PUSHJ_2 1561@deffnx {} BFD_RELOC_MMIX_PUSHJ_3 1562@deffnx {} BFD_RELOC_MMIX_PUSHJ_STUBBABLE 1563These are relocations for the PUSHJ instruction. 1564@end deffn 1565@deffn {} BFD_RELOC_MMIX_JMP 1566@deffnx {} BFD_RELOC_MMIX_JMP_1 1567@deffnx {} BFD_RELOC_MMIX_JMP_2 1568@deffnx {} BFD_RELOC_MMIX_JMP_3 1569These are relocations for the JMP instruction. 1570@end deffn 1571@deffn {} BFD_RELOC_MMIX_ADDR19 1572This is a relocation for a relative address as in a GETA instruction or 1573a branch. 1574@end deffn 1575@deffn {} BFD_RELOC_MMIX_ADDR27 1576This is a relocation for a relative address as in a JMP instruction. 1577@end deffn 1578@deffn {} BFD_RELOC_MMIX_REG_OR_BYTE 1579This is a relocation for an instruction field that may be a general 1580register or a value 0..255. 1581@end deffn 1582@deffn {} BFD_RELOC_MMIX_REG 1583This is a relocation for an instruction field that may be a general 1584register. 1585@end deffn 1586@deffn {} BFD_RELOC_MMIX_BASE_PLUS_OFFSET 1587This is a relocation for two instruction fields holding a register and 1588an offset, the equivalent of the relocation. 1589@end deffn 1590@deffn {} BFD_RELOC_MMIX_LOCAL 1591This relocation is an assertion that the expression is not allocated as 1592a global register. It does not modify contents. 1593@end deffn 1594@deffn {} BFD_RELOC_AVR_7_PCREL 1595This is a 16 bit reloc for the AVR that stores 8 bit pc relative 1596short offset into 7 bits. 1597@end deffn 1598@deffn {} BFD_RELOC_AVR_13_PCREL 1599This is a 16 bit reloc for the AVR that stores 13 bit pc relative 1600short offset into 12 bits. 1601@end deffn 1602@deffn {} BFD_RELOC_AVR_16_PM 1603This is a 16 bit reloc for the AVR that stores 17 bit value (usually 1604program memory address) into 16 bits. 1605@end deffn 1606@deffn {} BFD_RELOC_AVR_LO8_LDI 1607This is a 16 bit reloc for the AVR that stores 8 bit value (usually 1608data memory address) into 8 bit immediate value of LDI insn. 1609@end deffn 1610@deffn {} BFD_RELOC_AVR_HI8_LDI 1611This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit 1612of data memory address) into 8 bit immediate value of LDI insn. 1613@end deffn 1614@deffn {} BFD_RELOC_AVR_HH8_LDI 1615This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit 1616of program memory address) into 8 bit immediate value of LDI insn. 1617@end deffn 1618@deffn {} BFD_RELOC_AVR_LO8_LDI_NEG 1619This is a 16 bit reloc for the AVR that stores negated 8 bit value 1620(usually data memory address) into 8 bit immediate value of SUBI insn. 1621@end deffn 1622@deffn {} BFD_RELOC_AVR_HI8_LDI_NEG 1623This is a 16 bit reloc for the AVR that stores negated 8 bit value 1624(high 8 bit of data memory address) into 8 bit immediate value of 1625SUBI insn. 1626@end deffn 1627@deffn {} BFD_RELOC_AVR_HH8_LDI_NEG 1628This is a 16 bit reloc for the AVR that stores negated 8 bit value 1629(most high 8 bit of program memory address) into 8 bit immediate value 1630of LDI or SUBI insn. 1631@end deffn 1632@deffn {} BFD_RELOC_AVR_LO8_LDI_PM 1633This is a 16 bit reloc for the AVR that stores 8 bit value (usually 1634command address) into 8 bit immediate value of LDI insn. 1635@end deffn 1636@deffn {} BFD_RELOC_AVR_HI8_LDI_PM 1637This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit 1638of command address) into 8 bit immediate value of LDI insn. 1639@end deffn 1640@deffn {} BFD_RELOC_AVR_HH8_LDI_PM 1641This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit 1642of command address) into 8 bit immediate value of LDI insn. 1643@end deffn 1644@deffn {} BFD_RELOC_AVR_LO8_LDI_PM_NEG 1645This is a 16 bit reloc for the AVR that stores negated 8 bit value 1646(usually command address) into 8 bit immediate value of SUBI insn. 1647@end deffn 1648@deffn {} BFD_RELOC_AVR_HI8_LDI_PM_NEG 1649This is a 16 bit reloc for the AVR that stores negated 8 bit value 1650(high 8 bit of 16 bit command address) into 8 bit immediate value 1651of SUBI insn. 1652@end deffn 1653@deffn {} BFD_RELOC_AVR_HH8_LDI_PM_NEG 1654This is a 16 bit reloc for the AVR that stores negated 8 bit value 1655(high 6 bit of 22 bit command address) into 8 bit immediate 1656value of SUBI insn. 1657@end deffn 1658@deffn {} BFD_RELOC_AVR_CALL 1659This is a 32 bit reloc for the AVR that stores 23 bit value 1660into 22 bits. 1661@end deffn 1662@deffn {} BFD_RELOC_AVR_LDI 1663This is a 16 bit reloc for the AVR that stores all needed bits 1664for absolute addressing with ldi with overflow check to linktime 1665@end deffn 1666@deffn {} BFD_RELOC_AVR_6 1667This is a 6 bit reloc for the AVR that stores offset for ldd/std 1668instructions 1669@end deffn 1670@deffn {} BFD_RELOC_AVR_6_ADIW 1671This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw 1672instructions 1673@end deffn 1674@deffn {} BFD_RELOC_390_12 1675Direct 12 bit. 1676@end deffn 1677@deffn {} BFD_RELOC_390_GOT12 167812 bit GOT offset. 1679@end deffn 1680@deffn {} BFD_RELOC_390_PLT32 168132 bit PC relative PLT address. 1682@end deffn 1683@deffn {} BFD_RELOC_390_COPY 1684Copy symbol at runtime. 1685@end deffn 1686@deffn {} BFD_RELOC_390_GLOB_DAT 1687Create GOT entry. 1688@end deffn 1689@deffn {} BFD_RELOC_390_JMP_SLOT 1690Create PLT entry. 1691@end deffn 1692@deffn {} BFD_RELOC_390_RELATIVE 1693Adjust by program base. 1694@end deffn 1695@deffn {} BFD_RELOC_390_GOTPC 169632 bit PC relative offset to GOT. 1697@end deffn 1698@deffn {} BFD_RELOC_390_GOT16 169916 bit GOT offset. 1700@end deffn 1701@deffn {} BFD_RELOC_390_PC16DBL 1702PC relative 16 bit shifted by 1. 1703@end deffn 1704@deffn {} BFD_RELOC_390_PLT16DBL 170516 bit PC rel. PLT shifted by 1. 1706@end deffn 1707@deffn {} BFD_RELOC_390_PC32DBL 1708PC relative 32 bit shifted by 1. 1709@end deffn 1710@deffn {} BFD_RELOC_390_PLT32DBL 171132 bit PC rel. PLT shifted by 1. 1712@end deffn 1713@deffn {} BFD_RELOC_390_GOTPCDBL 171432 bit PC rel. GOT shifted by 1. 1715@end deffn 1716@deffn {} BFD_RELOC_390_GOT64 171764 bit GOT offset. 1718@end deffn 1719@deffn {} BFD_RELOC_390_PLT64 172064 bit PC relative PLT address. 1721@end deffn 1722@deffn {} BFD_RELOC_390_GOTENT 172332 bit rel. offset to GOT entry. 1724@end deffn 1725@deffn {} BFD_RELOC_390_GOTOFF64 172664 bit offset to GOT. 1727@end deffn 1728@deffn {} BFD_RELOC_390_GOTPLT12 172912-bit offset to symbol-entry within GOT, with PLT handling. 1730@end deffn 1731@deffn {} BFD_RELOC_390_GOTPLT16 173216-bit offset to symbol-entry within GOT, with PLT handling. 1733@end deffn 1734@deffn {} BFD_RELOC_390_GOTPLT32 173532-bit offset to symbol-entry within GOT, with PLT handling. 1736@end deffn 1737@deffn {} BFD_RELOC_390_GOTPLT64 173864-bit offset to symbol-entry within GOT, with PLT handling. 1739@end deffn 1740@deffn {} BFD_RELOC_390_GOTPLTENT 174132-bit rel. offset to symbol-entry within GOT, with PLT handling. 1742@end deffn 1743@deffn {} BFD_RELOC_390_PLTOFF16 174416-bit rel. offset from the GOT to a PLT entry. 1745@end deffn 1746@deffn {} BFD_RELOC_390_PLTOFF32 174732-bit rel. offset from the GOT to a PLT entry. 1748@end deffn 1749@deffn {} BFD_RELOC_390_PLTOFF64 175064-bit rel. offset from the GOT to a PLT entry. 1751@end deffn 1752@deffn {} BFD_RELOC_390_TLS_LOAD 1753@deffnx {} BFD_RELOC_390_TLS_GDCALL 1754@deffnx {} BFD_RELOC_390_TLS_LDCALL 1755@deffnx {} BFD_RELOC_390_TLS_GD32 1756@deffnx {} BFD_RELOC_390_TLS_GD64 1757@deffnx {} BFD_RELOC_390_TLS_GOTIE12 1758@deffnx {} BFD_RELOC_390_TLS_GOTIE32 1759@deffnx {} BFD_RELOC_390_TLS_GOTIE64 1760@deffnx {} BFD_RELOC_390_TLS_LDM32 1761@deffnx {} BFD_RELOC_390_TLS_LDM64 1762@deffnx {} BFD_RELOC_390_TLS_IE32 1763@deffnx {} BFD_RELOC_390_TLS_IE64 1764@deffnx {} BFD_RELOC_390_TLS_IEENT 1765@deffnx {} BFD_RELOC_390_TLS_LE32 1766@deffnx {} BFD_RELOC_390_TLS_LE64 1767@deffnx {} BFD_RELOC_390_TLS_LDO32 1768@deffnx {} BFD_RELOC_390_TLS_LDO64 1769@deffnx {} BFD_RELOC_390_TLS_DTPMOD 1770@deffnx {} BFD_RELOC_390_TLS_DTPOFF 1771@deffnx {} BFD_RELOC_390_TLS_TPOFF 1772s390 tls relocations. 1773@end deffn 1774@deffn {} BFD_RELOC_390_20 1775@deffnx {} BFD_RELOC_390_GOT20 1776@deffnx {} BFD_RELOC_390_GOTPLT20 1777@deffnx {} BFD_RELOC_390_TLS_GOTIE20 1778Long displacement extension. 1779@end deffn 1780@deffn {} BFD_RELOC_IP2K_FR9 1781Scenix IP2K - 9-bit register number / data address 1782@end deffn 1783@deffn {} BFD_RELOC_IP2K_BANK 1784Scenix IP2K - 4-bit register/data bank number 1785@end deffn 1786@deffn {} BFD_RELOC_IP2K_ADDR16CJP 1787Scenix IP2K - low 13 bits of instruction word address 1788@end deffn 1789@deffn {} BFD_RELOC_IP2K_PAGE3 1790Scenix IP2K - high 3 bits of instruction word address 1791@end deffn 1792@deffn {} BFD_RELOC_IP2K_LO8DATA 1793@deffnx {} BFD_RELOC_IP2K_HI8DATA 1794@deffnx {} BFD_RELOC_IP2K_EX8DATA 1795Scenix IP2K - ext/low/high 8 bits of data address 1796@end deffn 1797@deffn {} BFD_RELOC_IP2K_LO8INSN 1798@deffnx {} BFD_RELOC_IP2K_HI8INSN 1799Scenix IP2K - low/high 8 bits of instruction word address 1800@end deffn 1801@deffn {} BFD_RELOC_IP2K_PC_SKIP 1802Scenix IP2K - even/odd PC modifier to modify snb pcl.0 1803@end deffn 1804@deffn {} BFD_RELOC_IP2K_TEXT 1805Scenix IP2K - 16 bit word address in text section. 1806@end deffn 1807@deffn {} BFD_RELOC_IP2K_FR_OFFSET 1808Scenix IP2K - 7-bit sp or dp offset 1809@end deffn 1810@deffn {} BFD_RELOC_VPE4KMATH_DATA 1811@deffnx {} BFD_RELOC_VPE4KMATH_INSN 1812Scenix VPE4K coprocessor - data/insn-space addressing 1813@end deffn 1814@deffn {} BFD_RELOC_VTABLE_INHERIT 1815@deffnx {} BFD_RELOC_VTABLE_ENTRY 1816These two relocations are used by the linker to determine which of 1817the entries in a C++ virtual function table are actually used. When 1818the --gc-sections option is given, the linker will zero out the entries 1819that are not used, so that the code for those functions need not be 1820included in the output. 1821 1822VTABLE_INHERIT is a zero-space relocation used to describe to the 1823linker the inheritance tree of a C++ virtual function table. The 1824relocation's symbol should be the parent class' vtable, and the 1825relocation should be located at the child vtable. 1826 1827VTABLE_ENTRY is a zero-space relocation that describes the use of a 1828virtual function table entry. The reloc's symbol should refer to the 1829table of the class mentioned in the code. Off of that base, an offset 1830describes the entry that is being used. For Rela hosts, this offset 1831is stored in the reloc's addend. For Rel hosts, we are forced to put 1832this offset in the reloc's section offset. 1833@end deffn 1834@deffn {} BFD_RELOC_IA64_IMM14 1835@deffnx {} BFD_RELOC_IA64_IMM22 1836@deffnx {} BFD_RELOC_IA64_IMM64 1837@deffnx {} BFD_RELOC_IA64_DIR32MSB 1838@deffnx {} BFD_RELOC_IA64_DIR32LSB 1839@deffnx {} BFD_RELOC_IA64_DIR64MSB 1840@deffnx {} BFD_RELOC_IA64_DIR64LSB 1841@deffnx {} BFD_RELOC_IA64_GPREL22 1842@deffnx {} BFD_RELOC_IA64_GPREL64I 1843@deffnx {} BFD_RELOC_IA64_GPREL32MSB 1844@deffnx {} BFD_RELOC_IA64_GPREL32LSB 1845@deffnx {} BFD_RELOC_IA64_GPREL64MSB 1846@deffnx {} BFD_RELOC_IA64_GPREL64LSB 1847@deffnx {} BFD_RELOC_IA64_LTOFF22 1848@deffnx {} BFD_RELOC_IA64_LTOFF64I 1849@deffnx {} BFD_RELOC_IA64_PLTOFF22 1850@deffnx {} BFD_RELOC_IA64_PLTOFF64I 1851@deffnx {} BFD_RELOC_IA64_PLTOFF64MSB 1852@deffnx {} BFD_RELOC_IA64_PLTOFF64LSB 1853@deffnx {} BFD_RELOC_IA64_FPTR64I 1854@deffnx {} BFD_RELOC_IA64_FPTR32MSB 1855@deffnx {} BFD_RELOC_IA64_FPTR32LSB 1856@deffnx {} BFD_RELOC_IA64_FPTR64MSB 1857@deffnx {} BFD_RELOC_IA64_FPTR64LSB 1858@deffnx {} BFD_RELOC_IA64_PCREL21B 1859@deffnx {} BFD_RELOC_IA64_PCREL21BI 1860@deffnx {} BFD_RELOC_IA64_PCREL21M 1861@deffnx {} BFD_RELOC_IA64_PCREL21F 1862@deffnx {} BFD_RELOC_IA64_PCREL22 1863@deffnx {} BFD_RELOC_IA64_PCREL60B 1864@deffnx {} BFD_RELOC_IA64_PCREL64I 1865@deffnx {} BFD_RELOC_IA64_PCREL32MSB 1866@deffnx {} BFD_RELOC_IA64_PCREL32LSB 1867@deffnx {} BFD_RELOC_IA64_PCREL64MSB 1868@deffnx {} BFD_RELOC_IA64_PCREL64LSB 1869@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR22 1870@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64I 1871@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR32MSB 1872@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR32LSB 1873@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64MSB 1874@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64LSB 1875@deffnx {} BFD_RELOC_IA64_SEGREL32MSB 1876@deffnx {} BFD_RELOC_IA64_SEGREL32LSB 1877@deffnx {} BFD_RELOC_IA64_SEGREL64MSB 1878@deffnx {} BFD_RELOC_IA64_SEGREL64LSB 1879@deffnx {} BFD_RELOC_IA64_SECREL32MSB 1880@deffnx {} BFD_RELOC_IA64_SECREL32LSB 1881@deffnx {} BFD_RELOC_IA64_SECREL64MSB 1882@deffnx {} BFD_RELOC_IA64_SECREL64LSB 1883@deffnx {} BFD_RELOC_IA64_REL32MSB 1884@deffnx {} BFD_RELOC_IA64_REL32LSB 1885@deffnx {} BFD_RELOC_IA64_REL64MSB 1886@deffnx {} BFD_RELOC_IA64_REL64LSB 1887@deffnx {} BFD_RELOC_IA64_LTV32MSB 1888@deffnx {} BFD_RELOC_IA64_LTV32LSB 1889@deffnx {} BFD_RELOC_IA64_LTV64MSB 1890@deffnx {} BFD_RELOC_IA64_LTV64LSB 1891@deffnx {} BFD_RELOC_IA64_IPLTMSB 1892@deffnx {} BFD_RELOC_IA64_IPLTLSB 1893@deffnx {} BFD_RELOC_IA64_COPY 1894@deffnx {} BFD_RELOC_IA64_LTOFF22X 1895@deffnx {} BFD_RELOC_IA64_LDXMOV 1896@deffnx {} BFD_RELOC_IA64_TPREL14 1897@deffnx {} BFD_RELOC_IA64_TPREL22 1898@deffnx {} BFD_RELOC_IA64_TPREL64I 1899@deffnx {} BFD_RELOC_IA64_TPREL64MSB 1900@deffnx {} BFD_RELOC_IA64_TPREL64LSB 1901@deffnx {} BFD_RELOC_IA64_LTOFF_TPREL22 1902@deffnx {} BFD_RELOC_IA64_DTPMOD64MSB 1903@deffnx {} BFD_RELOC_IA64_DTPMOD64LSB 1904@deffnx {} BFD_RELOC_IA64_LTOFF_DTPMOD22 1905@deffnx {} BFD_RELOC_IA64_DTPREL14 1906@deffnx {} BFD_RELOC_IA64_DTPREL22 1907@deffnx {} BFD_RELOC_IA64_DTPREL64I 1908@deffnx {} BFD_RELOC_IA64_DTPREL32MSB 1909@deffnx {} BFD_RELOC_IA64_DTPREL32LSB 1910@deffnx {} BFD_RELOC_IA64_DTPREL64MSB 1911@deffnx {} BFD_RELOC_IA64_DTPREL64LSB 1912@deffnx {} BFD_RELOC_IA64_LTOFF_DTPREL22 1913Intel IA64 Relocations. 1914@end deffn 1915@deffn {} BFD_RELOC_M68HC11_HI8 1916Motorola 68HC11 reloc. 1917This is the 8 bit high part of an absolute address. 1918@end deffn 1919@deffn {} BFD_RELOC_M68HC11_LO8 1920Motorola 68HC11 reloc. 1921This is the 8 bit low part of an absolute address. 1922@end deffn 1923@deffn {} BFD_RELOC_M68HC11_3B 1924Motorola 68HC11 reloc. 1925This is the 3 bit of a value. 1926@end deffn 1927@deffn {} BFD_RELOC_M68HC11_RL_JUMP 1928Motorola 68HC11 reloc. 1929This reloc marks the beginning of a jump/call instruction. 1930It is used for linker relaxation to correctly identify beginning 1931of instruction and change some branches to use PC-relative 1932addressing mode. 1933@end deffn 1934@deffn {} BFD_RELOC_M68HC11_RL_GROUP 1935Motorola 68HC11 reloc. 1936This reloc marks a group of several instructions that gcc generates 1937and for which the linker relaxation pass can modify and/or remove 1938some of them. 1939@end deffn 1940@deffn {} BFD_RELOC_M68HC11_LO16 1941Motorola 68HC11 reloc. 1942This is the 16-bit lower part of an address. It is used for 'call' 1943instruction to specify the symbol address without any special 1944transformation (due to memory bank window). 1945@end deffn 1946@deffn {} BFD_RELOC_M68HC11_PAGE 1947Motorola 68HC11 reloc. 1948This is a 8-bit reloc that specifies the page number of an address. 1949It is used by 'call' instruction to specify the page number of 1950the symbol. 1951@end deffn 1952@deffn {} BFD_RELOC_M68HC11_24 1953Motorola 68HC11 reloc. 1954This is a 24-bit reloc that represents the address with a 16-bit 1955value and a 8-bit page number. The symbol address is transformed 1956to follow the 16K memory bank of 68HC12 (seen as mapped in the window). 1957@end deffn 1958@deffn {} BFD_RELOC_M68HC12_5B 1959Motorola 68HC12 reloc. 1960This is the 5 bits of a value. 1961@end deffn 1962@deffn {} BFD_RELOC_16C_NUM08 1963@deffnx {} BFD_RELOC_16C_NUM08_C 1964@deffnx {} BFD_RELOC_16C_NUM16 1965@deffnx {} BFD_RELOC_16C_NUM16_C 1966@deffnx {} BFD_RELOC_16C_NUM32 1967@deffnx {} BFD_RELOC_16C_NUM32_C 1968@deffnx {} BFD_RELOC_16C_DISP04 1969@deffnx {} BFD_RELOC_16C_DISP04_C 1970@deffnx {} BFD_RELOC_16C_DISP08 1971@deffnx {} BFD_RELOC_16C_DISP08_C 1972@deffnx {} BFD_RELOC_16C_DISP16 1973@deffnx {} BFD_RELOC_16C_DISP16_C 1974@deffnx {} BFD_RELOC_16C_DISP24 1975@deffnx {} BFD_RELOC_16C_DISP24_C 1976@deffnx {} BFD_RELOC_16C_DISP24a 1977@deffnx {} BFD_RELOC_16C_DISP24a_C 1978@deffnx {} BFD_RELOC_16C_REG04 1979@deffnx {} BFD_RELOC_16C_REG04_C 1980@deffnx {} BFD_RELOC_16C_REG04a 1981@deffnx {} BFD_RELOC_16C_REG04a_C 1982@deffnx {} BFD_RELOC_16C_REG14 1983@deffnx {} BFD_RELOC_16C_REG14_C 1984@deffnx {} BFD_RELOC_16C_REG16 1985@deffnx {} BFD_RELOC_16C_REG16_C 1986@deffnx {} BFD_RELOC_16C_REG20 1987@deffnx {} BFD_RELOC_16C_REG20_C 1988@deffnx {} BFD_RELOC_16C_ABS20 1989@deffnx {} BFD_RELOC_16C_ABS20_C 1990@deffnx {} BFD_RELOC_16C_ABS24 1991@deffnx {} BFD_RELOC_16C_ABS24_C 1992@deffnx {} BFD_RELOC_16C_IMM04 1993@deffnx {} BFD_RELOC_16C_IMM04_C 1994@deffnx {} BFD_RELOC_16C_IMM16 1995@deffnx {} BFD_RELOC_16C_IMM16_C 1996@deffnx {} BFD_RELOC_16C_IMM20 1997@deffnx {} BFD_RELOC_16C_IMM20_C 1998@deffnx {} BFD_RELOC_16C_IMM24 1999@deffnx {} BFD_RELOC_16C_IMM24_C 2000@deffnx {} BFD_RELOC_16C_IMM32 2001@deffnx {} BFD_RELOC_16C_IMM32_C 2002NS CR16C Relocations. 2003@end deffn 2004@deffn {} BFD_RELOC_CRX_REL4 2005@deffnx {} BFD_RELOC_CRX_REL8 2006@deffnx {} BFD_RELOC_CRX_REL8_CMP 2007@deffnx {} BFD_RELOC_CRX_REL16 2008@deffnx {} BFD_RELOC_CRX_REL24 2009@deffnx {} BFD_RELOC_CRX_REL32 2010@deffnx {} BFD_RELOC_CRX_REGREL12 2011@deffnx {} BFD_RELOC_CRX_REGREL22 2012@deffnx {} BFD_RELOC_CRX_REGREL28 2013@deffnx {} BFD_RELOC_CRX_REGREL32 2014@deffnx {} BFD_RELOC_CRX_ABS16 2015@deffnx {} BFD_RELOC_CRX_ABS32 2016@deffnx {} BFD_RELOC_CRX_NUM8 2017@deffnx {} BFD_RELOC_CRX_NUM16 2018@deffnx {} BFD_RELOC_CRX_NUM32 2019@deffnx {} BFD_RELOC_CRX_IMM16 2020@deffnx {} BFD_RELOC_CRX_IMM32 2021@deffnx {} BFD_RELOC_CRX_SWITCH8 2022@deffnx {} BFD_RELOC_CRX_SWITCH16 2023@deffnx {} BFD_RELOC_CRX_SWITCH32 2024NS CRX Relocations. 2025@end deffn 2026@deffn {} BFD_RELOC_CRIS_BDISP8 2027@deffnx {} BFD_RELOC_CRIS_UNSIGNED_5 2028@deffnx {} BFD_RELOC_CRIS_SIGNED_6 2029@deffnx {} BFD_RELOC_CRIS_UNSIGNED_6 2030@deffnx {} BFD_RELOC_CRIS_SIGNED_8 2031@deffnx {} BFD_RELOC_CRIS_UNSIGNED_8 2032@deffnx {} BFD_RELOC_CRIS_SIGNED_16 2033@deffnx {} BFD_RELOC_CRIS_UNSIGNED_16 2034@deffnx {} BFD_RELOC_CRIS_LAPCQ_OFFSET 2035@deffnx {} BFD_RELOC_CRIS_UNSIGNED_4 2036These relocs are only used within the CRIS assembler. They are not 2037(at present) written to any object files. 2038@end deffn 2039@deffn {} BFD_RELOC_CRIS_COPY 2040@deffnx {} BFD_RELOC_CRIS_GLOB_DAT 2041@deffnx {} BFD_RELOC_CRIS_JUMP_SLOT 2042@deffnx {} BFD_RELOC_CRIS_RELATIVE 2043Relocs used in ELF shared libraries for CRIS. 2044@end deffn 2045@deffn {} BFD_RELOC_CRIS_32_GOT 204632-bit offset to symbol-entry within GOT. 2047@end deffn 2048@deffn {} BFD_RELOC_CRIS_16_GOT 204916-bit offset to symbol-entry within GOT. 2050@end deffn 2051@deffn {} BFD_RELOC_CRIS_32_GOTPLT 205232-bit offset to symbol-entry within GOT, with PLT handling. 2053@end deffn 2054@deffn {} BFD_RELOC_CRIS_16_GOTPLT 205516-bit offset to symbol-entry within GOT, with PLT handling. 2056@end deffn 2057@deffn {} BFD_RELOC_CRIS_32_GOTREL 205832-bit offset to symbol, relative to GOT. 2059@end deffn 2060@deffn {} BFD_RELOC_CRIS_32_PLT_GOTREL 206132-bit offset to symbol with PLT entry, relative to GOT. 2062@end deffn 2063@deffn {} BFD_RELOC_CRIS_32_PLT_PCREL 206432-bit offset to symbol with PLT entry, relative to this relocation. 2065@end deffn 2066@deffn {} BFD_RELOC_860_COPY 2067@deffnx {} BFD_RELOC_860_GLOB_DAT 2068@deffnx {} BFD_RELOC_860_JUMP_SLOT 2069@deffnx {} BFD_RELOC_860_RELATIVE 2070@deffnx {} BFD_RELOC_860_PC26 2071@deffnx {} BFD_RELOC_860_PLT26 2072@deffnx {} BFD_RELOC_860_PC16 2073@deffnx {} BFD_RELOC_860_LOW0 2074@deffnx {} BFD_RELOC_860_SPLIT0 2075@deffnx {} BFD_RELOC_860_LOW1 2076@deffnx {} BFD_RELOC_860_SPLIT1 2077@deffnx {} BFD_RELOC_860_LOW2 2078@deffnx {} BFD_RELOC_860_SPLIT2 2079@deffnx {} BFD_RELOC_860_LOW3 2080@deffnx {} BFD_RELOC_860_LOGOT0 2081@deffnx {} BFD_RELOC_860_SPGOT0 2082@deffnx {} BFD_RELOC_860_LOGOT1 2083@deffnx {} BFD_RELOC_860_SPGOT1 2084@deffnx {} BFD_RELOC_860_LOGOTOFF0 2085@deffnx {} BFD_RELOC_860_SPGOTOFF0 2086@deffnx {} BFD_RELOC_860_LOGOTOFF1 2087@deffnx {} BFD_RELOC_860_SPGOTOFF1 2088@deffnx {} BFD_RELOC_860_LOGOTOFF2 2089@deffnx {} BFD_RELOC_860_LOGOTOFF3 2090@deffnx {} BFD_RELOC_860_LOPC 2091@deffnx {} BFD_RELOC_860_HIGHADJ 2092@deffnx {} BFD_RELOC_860_HAGOT 2093@deffnx {} BFD_RELOC_860_HAGOTOFF 2094@deffnx {} BFD_RELOC_860_HAPC 2095@deffnx {} BFD_RELOC_860_HIGH 2096@deffnx {} BFD_RELOC_860_HIGOT 2097@deffnx {} BFD_RELOC_860_HIGOTOFF 2098Intel i860 Relocations. 2099@end deffn 2100@deffn {} BFD_RELOC_OPENRISC_ABS_26 2101@deffnx {} BFD_RELOC_OPENRISC_REL_26 2102OpenRISC Relocations. 2103@end deffn 2104@deffn {} BFD_RELOC_H8_DIR16A8 2105@deffnx {} BFD_RELOC_H8_DIR16R8 2106@deffnx {} BFD_RELOC_H8_DIR24A8 2107@deffnx {} BFD_RELOC_H8_DIR24R8 2108@deffnx {} BFD_RELOC_H8_DIR32A16 2109H8 elf Relocations. 2110@end deffn 2111@deffn {} BFD_RELOC_XSTORMY16_REL_12 2112@deffnx {} BFD_RELOC_XSTORMY16_12 2113@deffnx {} BFD_RELOC_XSTORMY16_24 2114@deffnx {} BFD_RELOC_XSTORMY16_FPTR16 2115Sony Xstormy16 Relocations. 2116@end deffn 2117@deffn {} BFD_RELOC_VAX_GLOB_DAT 2118@deffnx {} BFD_RELOC_VAX_JMP_SLOT 2119@deffnx {} BFD_RELOC_VAX_RELATIVE 2120Relocations used by VAX ELF. 2121@end deffn 2122@deffn {} BFD_RELOC_MSP430_10_PCREL 2123@deffnx {} BFD_RELOC_MSP430_16_PCREL 2124@deffnx {} BFD_RELOC_MSP430_16 2125@deffnx {} BFD_RELOC_MSP430_16_PCREL_BYTE 2126@deffnx {} BFD_RELOC_MSP430_16_BYTE 2127@deffnx {} BFD_RELOC_MSP430_2X_PCREL 2128@deffnx {} BFD_RELOC_MSP430_RL_PCREL 2129msp430 specific relocation codes 2130@end deffn 2131@deffn {} BFD_RELOC_IQ2000_OFFSET_16 2132@deffnx {} BFD_RELOC_IQ2000_OFFSET_21 2133@deffnx {} BFD_RELOC_IQ2000_UHI16 2134IQ2000 Relocations. 2135@end deffn 2136@deffn {} BFD_RELOC_XTENSA_RTLD 2137Special Xtensa relocation used only by PLT entries in ELF shared 2138objects to indicate that the runtime linker should set the value 2139to one of its own internal functions or data structures. 2140@end deffn 2141@deffn {} BFD_RELOC_XTENSA_GLOB_DAT 2142@deffnx {} BFD_RELOC_XTENSA_JMP_SLOT 2143@deffnx {} BFD_RELOC_XTENSA_RELATIVE 2144Xtensa relocations for ELF shared objects. 2145@end deffn 2146@deffn {} BFD_RELOC_XTENSA_PLT 2147Xtensa relocation used in ELF object files for symbols that may require 2148PLT entries. Otherwise, this is just a generic 32-bit relocation. 2149@end deffn 2150@deffn {} BFD_RELOC_XTENSA_DIFF8 2151@deffnx {} BFD_RELOC_XTENSA_DIFF16 2152@deffnx {} BFD_RELOC_XTENSA_DIFF32 2153Xtensa relocations to mark the difference of two local symbols. 2154These are only needed to support linker relaxation and can be ignored 2155when not relaxing. The field is set to the value of the difference 2156assuming no relaxation. The relocation encodes the position of the 2157first symbol so the linker can determine whether to adjust the field 2158value. 2159@end deffn 2160@deffn {} BFD_RELOC_XTENSA_SLOT0_OP 2161@deffnx {} BFD_RELOC_XTENSA_SLOT1_OP 2162@deffnx {} BFD_RELOC_XTENSA_SLOT2_OP 2163@deffnx {} BFD_RELOC_XTENSA_SLOT3_OP 2164@deffnx {} BFD_RELOC_XTENSA_SLOT4_OP 2165@deffnx {} BFD_RELOC_XTENSA_SLOT5_OP 2166@deffnx {} BFD_RELOC_XTENSA_SLOT6_OP 2167@deffnx {} BFD_RELOC_XTENSA_SLOT7_OP 2168@deffnx {} BFD_RELOC_XTENSA_SLOT8_OP 2169@deffnx {} BFD_RELOC_XTENSA_SLOT9_OP 2170@deffnx {} BFD_RELOC_XTENSA_SLOT10_OP 2171@deffnx {} BFD_RELOC_XTENSA_SLOT11_OP 2172@deffnx {} BFD_RELOC_XTENSA_SLOT12_OP 2173@deffnx {} BFD_RELOC_XTENSA_SLOT13_OP 2174@deffnx {} BFD_RELOC_XTENSA_SLOT14_OP 2175Generic Xtensa relocations for instruction operands. Only the slot 2176number is encoded in the relocation. The relocation applies to the 2177last PC-relative immediate operand, or if there are no PC-relative 2178immediates, to the last immediate operand. 2179@end deffn 2180@deffn {} BFD_RELOC_XTENSA_SLOT0_ALT 2181@deffnx {} BFD_RELOC_XTENSA_SLOT1_ALT 2182@deffnx {} BFD_RELOC_XTENSA_SLOT2_ALT 2183@deffnx {} BFD_RELOC_XTENSA_SLOT3_ALT 2184@deffnx {} BFD_RELOC_XTENSA_SLOT4_ALT 2185@deffnx {} BFD_RELOC_XTENSA_SLOT5_ALT 2186@deffnx {} BFD_RELOC_XTENSA_SLOT6_ALT 2187@deffnx {} BFD_RELOC_XTENSA_SLOT7_ALT 2188@deffnx {} BFD_RELOC_XTENSA_SLOT8_ALT 2189@deffnx {} BFD_RELOC_XTENSA_SLOT9_ALT 2190@deffnx {} BFD_RELOC_XTENSA_SLOT10_ALT 2191@deffnx {} BFD_RELOC_XTENSA_SLOT11_ALT 2192@deffnx {} BFD_RELOC_XTENSA_SLOT12_ALT 2193@deffnx {} BFD_RELOC_XTENSA_SLOT13_ALT 2194@deffnx {} BFD_RELOC_XTENSA_SLOT14_ALT 2195Alternate Xtensa relocations. Only the slot is encoded in the 2196relocation. The meaning of these relocations is opcode-specific. 2197@end deffn 2198@deffn {} BFD_RELOC_XTENSA_OP0 2199@deffnx {} BFD_RELOC_XTENSA_OP1 2200@deffnx {} BFD_RELOC_XTENSA_OP2 2201Xtensa relocations for backward compatibility. These have all been 2202replaced by BFD_RELOC_XTENSA_SLOT0_OP. 2203@end deffn 2204@deffn {} BFD_RELOC_XTENSA_ASM_EXPAND 2205Xtensa relocation to mark that the assembler expanded the 2206instructions from an original target. The expansion size is 2207encoded in the reloc size. 2208@end deffn 2209@deffn {} BFD_RELOC_XTENSA_ASM_SIMPLIFY 2210Xtensa relocation to mark that the linker should simplify 2211assembler-expanded instructions. This is commonly used 2212internally by the linker after analysis of a 2213BFD_RELOC_XTENSA_ASM_EXPAND. 2214@end deffn 2215 2216@example 2217 2218typedef enum bfd_reloc_code_real bfd_reloc_code_real_type; 2219@end example 2220@findex bfd_reloc_type_lookup 2221@subsubsection @code{bfd_reloc_type_lookup} 2222@strong{Synopsis} 2223@example 2224reloc_howto_type *bfd_reloc_type_lookup 2225 (bfd *abfd, bfd_reloc_code_real_type code); 2226@end example 2227@strong{Description}@* 2228Return a pointer to a howto structure which, when 2229invoked, will perform the relocation @var{code} on data from the 2230architecture noted. 2231 2232@findex bfd_default_reloc_type_lookup 2233@subsubsection @code{bfd_default_reloc_type_lookup} 2234@strong{Synopsis} 2235@example 2236reloc_howto_type *bfd_default_reloc_type_lookup 2237 (bfd *abfd, bfd_reloc_code_real_type code); 2238@end example 2239@strong{Description}@* 2240Provides a default relocation lookup routine for any architecture. 2241 2242@findex bfd_get_reloc_code_name 2243@subsubsection @code{bfd_get_reloc_code_name} 2244@strong{Synopsis} 2245@example 2246const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code); 2247@end example 2248@strong{Description}@* 2249Provides a printable name for the supplied relocation code. 2250Useful mainly for printing error messages. 2251 2252@findex bfd_generic_relax_section 2253@subsubsection @code{bfd_generic_relax_section} 2254@strong{Synopsis} 2255@example 2256bfd_boolean bfd_generic_relax_section 2257 (bfd *abfd, 2258 asection *section, 2259 struct bfd_link_info *, 2260 bfd_boolean *); 2261@end example 2262@strong{Description}@* 2263Provides default handling for relaxing for back ends which 2264don't do relaxing. 2265 2266@findex bfd_generic_gc_sections 2267@subsubsection @code{bfd_generic_gc_sections} 2268@strong{Synopsis} 2269@example 2270bfd_boolean bfd_generic_gc_sections 2271 (bfd *, struct bfd_link_info *); 2272@end example 2273@strong{Description}@* 2274Provides default handling for relaxing for back ends which 2275don't do section gc -- i.e., does nothing besides the special 2276case for marking sections having global symbols. 2277 2278@findex bfd_generic_merge_sections 2279@subsubsection @code{bfd_generic_merge_sections} 2280@strong{Synopsis} 2281@example 2282bfd_boolean bfd_generic_merge_sections 2283 (bfd *, struct bfd_link_info *); 2284@end example 2285@strong{Description}@* 2286Provides default handling for SEC_MERGE section merging for back ends 2287which don't have SEC_MERGE support -- i.e., does nothing. 2288 2289@findex bfd_generic_get_relocated_section_contents 2290@subsubsection @code{bfd_generic_get_relocated_section_contents} 2291@strong{Synopsis} 2292@example 2293bfd_byte *bfd_generic_get_relocated_section_contents 2294 (bfd *abfd, 2295 struct bfd_link_info *link_info, 2296 struct bfd_link_order *link_order, 2297 bfd_byte *data, 2298 bfd_boolean relocatable, 2299 asymbol **symbols); 2300@end example 2301@strong{Description}@* 2302Provides default handling of relocation effort for back ends 2303which can't be bothered to do it efficiently. 2304 2305