1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /*
3 * Copyright (C) 2017 Intel Deutschland GmbH
4 * Copyright (C) 2018-2024 Intel Corporation
5 */
6 #if defined(__FreeBSD__)
7 #include <linux/delay.h>
8 #endif
9 #include "iwl-trans.h"
10 #include "iwl-prph.h"
11 #include "iwl-context-info.h"
12 #include "iwl-context-info-gen3.h"
13 #include "internal.h"
14 #include "fw/dbg.h"
15
16 #define FW_RESET_TIMEOUT (HZ / 5)
17
18 /*
19 * Start up NIC's basic functionality after it has been reset
20 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
21 * NOTE: This does not load uCode nor start the embedded processor
22 */
iwl_pcie_gen2_apm_init(struct iwl_trans * trans)23 int iwl_pcie_gen2_apm_init(struct iwl_trans *trans)
24 {
25 int ret = 0;
26
27 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
28
29 /*
30 * Use "set_bit" below rather than "write", to preserve any hardware
31 * bits already set by default after reset.
32 */
33
34 /*
35 * Disable L0s without affecting L1;
36 * don't wait for ICH L0s (ICH bug W/A)
37 */
38 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
39 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
40
41 /* Set FH wait threshold to maximum (HW error during stress W/A) */
42 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
43
44 /*
45 * Enable HAP INTA (interrupt from management bus) to
46 * wake device's PCI Express link L1a -> L0s
47 */
48 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
49 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
50
51 iwl_pcie_apm_config(trans);
52
53 ret = iwl_finish_nic_init(trans);
54 if (ret)
55 return ret;
56
57 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
58
59 return 0;
60 }
61
iwl_pcie_gen2_apm_stop(struct iwl_trans * trans,bool op_mode_leave)62 static void iwl_pcie_gen2_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
63 {
64 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
65
66 if (op_mode_leave) {
67 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
68 iwl_pcie_gen2_apm_init(trans);
69
70 /* inform ME that we are leaving */
71 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
72 CSR_RESET_LINK_PWR_MGMT_DISABLED);
73 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
74 CSR_HW_IF_CONFIG_REG_PREPARE |
75 CSR_HW_IF_CONFIG_REG_ENABLE_PME);
76 mdelay(1);
77 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
78 CSR_RESET_LINK_PWR_MGMT_DISABLED);
79 mdelay(5);
80 }
81
82 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
83
84 /* Stop device's DMA activity */
85 iwl_pcie_apm_stop_master(trans);
86
87 iwl_trans_sw_reset(trans, false);
88
89 /*
90 * Clear "initialization complete" bit to move adapter from
91 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
92 */
93 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
94 iwl_clear_bit(trans, CSR_GP_CNTRL,
95 CSR_GP_CNTRL_REG_FLAG_MAC_INIT);
96 else
97 iwl_clear_bit(trans, CSR_GP_CNTRL,
98 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
99 }
100
iwl_trans_pcie_fw_reset_handshake(struct iwl_trans * trans)101 static void iwl_trans_pcie_fw_reset_handshake(struct iwl_trans *trans)
102 {
103 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
104 int ret;
105
106 trans_pcie->fw_reset_state = FW_RESET_REQUESTED;
107
108 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
109 iwl_write_umac_prph(trans, UREG_NIC_SET_NMI_DRIVER,
110 UREG_NIC_SET_NMI_DRIVER_RESET_HANDSHAKE);
111 else if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210)
112 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
113 UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE);
114 else
115 iwl_write32(trans, CSR_DOORBELL_VECTOR,
116 UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE);
117
118 /* wait 200ms */
119 ret = wait_event_timeout(trans_pcie->fw_reset_waitq,
120 trans_pcie->fw_reset_state != FW_RESET_REQUESTED,
121 FW_RESET_TIMEOUT);
122 if (!ret || trans_pcie->fw_reset_state == FW_RESET_ERROR) {
123 u32 inta_hw = iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD);
124
125 IWL_ERR(trans,
126 "timeout waiting for FW reset ACK (inta_hw=0x%x)\n",
127 inta_hw);
128
129 if (!(inta_hw & MSIX_HW_INT_CAUSES_REG_RESET_DONE))
130 iwl_trans_fw_error(trans, true);
131 }
132
133 trans_pcie->fw_reset_state = FW_RESET_IDLE;
134 }
135
_iwl_trans_pcie_gen2_stop_device(struct iwl_trans * trans)136 void _iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans)
137 {
138 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
139
140 lockdep_assert_held(&trans_pcie->mutex);
141
142 if (trans_pcie->is_down)
143 return;
144
145 if (trans->state >= IWL_TRANS_FW_STARTED)
146 if (trans_pcie->fw_reset_handshake)
147 iwl_trans_pcie_fw_reset_handshake(trans);
148
149 trans_pcie->is_down = true;
150
151 /* tell the device to stop sending interrupts */
152 iwl_disable_interrupts(trans);
153
154 /* device going down, Stop using ICT table */
155 iwl_pcie_disable_ict(trans);
156
157 /*
158 * If a HW restart happens during firmware loading,
159 * then the firmware loading might call this function
160 * and later it might be called again due to the
161 * restart. So don't process again if the device is
162 * already dead.
163 */
164 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
165 IWL_DEBUG_INFO(trans,
166 "DEVICE_ENABLED bit was set and is now cleared\n");
167 iwl_pcie_synchronize_irqs(trans);
168 iwl_pcie_rx_napi_sync(trans);
169 iwl_txq_gen2_tx_free(trans);
170 iwl_pcie_rx_stop(trans);
171 }
172
173 iwl_pcie_ctxt_info_free_paging(trans);
174 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
175 iwl_pcie_ctxt_info_gen3_free(trans, false);
176 else
177 iwl_pcie_ctxt_info_free(trans);
178
179 /* Stop the device, and put it in low power state */
180 iwl_pcie_gen2_apm_stop(trans, false);
181
182 /* re-take ownership to prevent other users from stealing the device */
183 iwl_trans_sw_reset(trans, true);
184
185 /*
186 * Upon stop, the IVAR table gets erased, so msi-x won't
187 * work. This causes a bug in RF-KILL flows, since the interrupt
188 * that enables radio won't fire on the correct irq, and the
189 * driver won't be able to handle the interrupt.
190 * Configure the IVAR table again after reset.
191 */
192 iwl_pcie_conf_msix_hw(trans_pcie);
193
194 /*
195 * Upon stop, the APM issues an interrupt if HW RF kill is set.
196 * This is a bug in certain verions of the hardware.
197 * Certain devices also keep sending HW RF kill interrupt all
198 * the time, unless the interrupt is ACKed even if the interrupt
199 * should be masked. Re-ACK all the interrupts here.
200 */
201 iwl_disable_interrupts(trans);
202
203 /* clear all status bits */
204 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
205 clear_bit(STATUS_INT_ENABLED, &trans->status);
206 clear_bit(STATUS_TPOWER_PMI, &trans->status);
207
208 /*
209 * Even if we stop the HW, we still want the RF kill
210 * interrupt
211 */
212 iwl_enable_rfkill_int(trans);
213 }
214
iwl_trans_pcie_gen2_stop_device(struct iwl_trans * trans)215 void iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans)
216 {
217 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
218 bool was_in_rfkill;
219
220 iwl_op_mode_time_point(trans->op_mode,
221 IWL_FW_INI_TIME_POINT_HOST_DEVICE_DISABLE,
222 NULL);
223
224 mutex_lock(&trans_pcie->mutex);
225 trans_pcie->opmode_down = true;
226 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
227 _iwl_trans_pcie_gen2_stop_device(trans);
228 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill);
229 mutex_unlock(&trans_pcie->mutex);
230 }
231
iwl_pcie_gen2_nic_init(struct iwl_trans * trans)232 static int iwl_pcie_gen2_nic_init(struct iwl_trans *trans)
233 {
234 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
235 int queue_size = max_t(u32, IWL_CMD_QUEUE_SIZE,
236 trans->cfg->min_txq_size);
237 int ret;
238
239 /* TODO: most of the logic can be removed in A0 - but not in Z0 */
240 spin_lock_bh(&trans_pcie->irq_lock);
241 ret = iwl_pcie_gen2_apm_init(trans);
242 spin_unlock_bh(&trans_pcie->irq_lock);
243 if (ret)
244 return ret;
245
246 iwl_op_mode_nic_config(trans->op_mode);
247
248 /* Allocate the RX queue, or reset if it is already allocated */
249 if (iwl_pcie_gen2_rx_init(trans))
250 return -ENOMEM;
251
252 /* Allocate or reset and init all Tx and Command queues */
253 if (iwl_txq_gen2_init(trans, trans_pcie->txqs.cmd.q_id, queue_size))
254 return -ENOMEM;
255
256 /* enable shadow regs in HW */
257 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
258 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
259
260 return 0;
261 }
262
iwl_pcie_get_rf_name(struct iwl_trans * trans)263 static void iwl_pcie_get_rf_name(struct iwl_trans *trans)
264 {
265 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
266 char *buf = trans_pcie->rf_name;
267 size_t buflen = sizeof(trans_pcie->rf_name);
268 size_t pos;
269 u32 version;
270
271 if (buf[0])
272 return;
273
274 switch (CSR_HW_RFID_TYPE(trans->hw_rf_id)) {
275 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_JF):
276 pos = scnprintf(buf, buflen, "JF");
277 break;
278 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_GF):
279 pos = scnprintf(buf, buflen, "GF");
280 break;
281 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_GF4):
282 pos = scnprintf(buf, buflen, "GF4");
283 break;
284 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR):
285 pos = scnprintf(buf, buflen, "HR");
286 break;
287 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR1):
288 pos = scnprintf(buf, buflen, "HR1");
289 break;
290 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HRCDB):
291 pos = scnprintf(buf, buflen, "HRCDB");
292 break;
293 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_MS):
294 pos = scnprintf(buf, buflen, "MS");
295 break;
296 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_FM):
297 pos = scnprintf(buf, buflen, "FM");
298 break;
299 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_WP):
300 if (SILICON_Z_STEP ==
301 CSR_HW_RFID_STEP(trans->hw_rf_id))
302 pos = scnprintf(buf, buflen, "WHTC");
303 else
304 pos = scnprintf(buf, buflen, "WH");
305 break;
306 default:
307 return;
308 }
309
310 switch (CSR_HW_RFID_TYPE(trans->hw_rf_id)) {
311 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR):
312 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR1):
313 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HRCDB):
314 version = iwl_read_prph(trans, CNVI_MBOX_C);
315 switch (version) {
316 case 0x20000:
317 pos += scnprintf(buf + pos, buflen - pos, " B3");
318 break;
319 case 0x120000:
320 pos += scnprintf(buf + pos, buflen - pos, " B5");
321 break;
322 default:
323 pos += scnprintf(buf + pos, buflen - pos,
324 " (0x%x)", version);
325 break;
326 }
327 break;
328 default:
329 break;
330 }
331
332 pos += scnprintf(buf + pos, buflen - pos, ", rfid=0x%x",
333 trans->hw_rf_id);
334
335 IWL_INFO(trans, "Detected RF %s\n", buf);
336
337 /*
338 * also add a \n for debugfs - need to do it after printing
339 * since our IWL_INFO machinery wants to see a static \n at
340 * the end of the string
341 */
342 pos += scnprintf(buf + pos, buflen - pos, "\n");
343 }
344
iwl_trans_pcie_gen2_fw_alive(struct iwl_trans * trans)345 void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans *trans)
346 {
347 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
348
349 iwl_pcie_reset_ict(trans);
350
351 /* make sure all queue are not stopped/used */
352 memset(trans_pcie->txqs.queue_stopped, 0,
353 sizeof(trans_pcie->txqs.queue_stopped));
354 memset(trans_pcie->txqs.queue_used, 0,
355 sizeof(trans_pcie->txqs.queue_used));
356
357 /* now that we got alive we can free the fw image & the context info.
358 * paging memory cannot be freed included since FW will still use it
359 */
360 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
361 iwl_pcie_ctxt_info_gen3_free(trans, true);
362 else
363 iwl_pcie_ctxt_info_free(trans);
364
365 /*
366 * Re-enable all the interrupts, including the RF-Kill one, now that
367 * the firmware is alive.
368 */
369 iwl_enable_interrupts(trans);
370 mutex_lock(&trans_pcie->mutex);
371 iwl_pcie_check_hw_rf_kill(trans);
372
373 iwl_pcie_get_rf_name(trans);
374 mutex_unlock(&trans_pcie->mutex);
375 }
376
iwl_pcie_set_ltr(struct iwl_trans * trans)377 static bool iwl_pcie_set_ltr(struct iwl_trans *trans)
378 {
379 u32 ltr_val = CSR_LTR_LONG_VAL_AD_NO_SNOOP_REQ |
380 u32_encode_bits(CSR_LTR_LONG_VAL_AD_SCALE_USEC,
381 CSR_LTR_LONG_VAL_AD_NO_SNOOP_SCALE) |
382 u32_encode_bits(250,
383 CSR_LTR_LONG_VAL_AD_NO_SNOOP_VAL) |
384 CSR_LTR_LONG_VAL_AD_SNOOP_REQ |
385 u32_encode_bits(CSR_LTR_LONG_VAL_AD_SCALE_USEC,
386 CSR_LTR_LONG_VAL_AD_SNOOP_SCALE) |
387 u32_encode_bits(250, CSR_LTR_LONG_VAL_AD_SNOOP_VAL);
388
389 /*
390 * To workaround hardware latency issues during the boot process,
391 * initialize the LTR to ~250 usec (see ltr_val above).
392 * The firmware initializes this again later (to a smaller value).
393 */
394 if ((trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210 ||
395 trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000) &&
396 !trans->trans_cfg->integrated) {
397 iwl_write32(trans, CSR_LTR_LONG_VAL_AD, ltr_val);
398 return true;
399 }
400
401 if (trans->trans_cfg->integrated &&
402 trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000) {
403 iwl_write_prph(trans, HPM_MAC_LTR_CSR, HPM_MAC_LRT_ENABLE_ALL);
404 iwl_write_prph(trans, HPM_UMAC_LTR, ltr_val);
405 return true;
406 }
407
408 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210) {
409 /* First clear the interrupt, just in case */
410 iwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD,
411 MSIX_HW_INT_CAUSES_REG_IML);
412 /* In this case, unfortunately the same ROM bug exists in the
413 * device (not setting LTR correctly), but we don't have control
414 * over the settings from the host due to some hardware security
415 * features. The only workaround we've been able to come up with
416 * so far is to try to keep the CPU and device busy by polling
417 * it and the IML (image loader) completed interrupt.
418 */
419 return false;
420 }
421
422 /* nothing needs to be done on other devices */
423 return true;
424 }
425
iwl_pcie_spin_for_iml(struct iwl_trans * trans)426 static void iwl_pcie_spin_for_iml(struct iwl_trans *trans)
427 {
428 /* in practice, this seems to complete in around 20-30ms at most, wait 100 */
429 #define IML_WAIT_TIMEOUT (HZ / 10)
430 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
431 unsigned long end_time = jiffies + IML_WAIT_TIMEOUT;
432 u32 value, loops = 0;
433 bool irq = false;
434
435 if (WARN_ON(!trans_pcie->iml))
436 return;
437
438 value = iwl_read32(trans, CSR_LTR_LAST_MSG);
439 IWL_DEBUG_INFO(trans, "Polling for IML load - CSR_LTR_LAST_MSG=0x%x\n",
440 value);
441
442 while (time_before(jiffies, end_time)) {
443 if (iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD) &
444 MSIX_HW_INT_CAUSES_REG_IML) {
445 irq = true;
446 break;
447 }
448 /* Keep the CPU and device busy. */
449 value = iwl_read32(trans, CSR_LTR_LAST_MSG);
450 loops++;
451 }
452
453 IWL_DEBUG_INFO(trans,
454 "Polled for IML load: irq=%d, loops=%d, CSR_LTR_LAST_MSG=0x%x\n",
455 irq, loops, value);
456
457 /* We don't fail here even if we timed out - maybe we get lucky and the
458 * interrupt comes in later (and we get alive from firmware) and then
459 * we're all happy - but if not we'll fail on alive timeout or get some
460 * other error out.
461 */
462 }
463
iwl_trans_pcie_gen2_start_fw(struct iwl_trans * trans,const struct fw_img * fw,bool run_in_rfkill)464 int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans,
465 const struct fw_img *fw, bool run_in_rfkill)
466 {
467 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
468 bool hw_rfkill, keep_ram_busy;
469 int ret;
470
471 /* This may fail if AMT took ownership of the device */
472 if (iwl_pcie_prepare_card_hw(trans)) {
473 IWL_WARN(trans, "Exit HW not ready\n");
474 return -EIO;
475 }
476
477 iwl_enable_rfkill_int(trans);
478
479 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
480
481 /*
482 * We enabled the RF-Kill interrupt and the handler may very
483 * well be running. Disable the interrupts to make sure no other
484 * interrupt can be fired.
485 */
486 iwl_disable_interrupts(trans);
487
488 /* Make sure it finished running */
489 iwl_pcie_synchronize_irqs(trans);
490
491 mutex_lock(&trans_pcie->mutex);
492
493 /* If platform's RF_KILL switch is NOT set to KILL */
494 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
495 if (hw_rfkill && !run_in_rfkill) {
496 ret = -ERFKILL;
497 goto out;
498 }
499
500 /* Someone called stop_device, don't try to start_fw */
501 if (trans_pcie->is_down) {
502 IWL_WARN(trans,
503 "Can't start_fw since the HW hasn't been started\n");
504 ret = -EIO;
505 goto out;
506 }
507
508 /* make sure rfkill handshake bits are cleared */
509 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
510 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
511 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
512
513 /* clear (again), then enable host interrupts */
514 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
515
516 ret = iwl_pcie_gen2_nic_init(trans);
517 if (ret) {
518 IWL_ERR(trans, "Unable to init nic\n");
519 goto out;
520 }
521
522 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
523 ret = iwl_pcie_ctxt_info_gen3_init(trans, fw);
524 else
525 ret = iwl_pcie_ctxt_info_init(trans, fw);
526 if (ret)
527 goto out;
528
529 keep_ram_busy = !iwl_pcie_set_ltr(trans);
530
531 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {
532 iwl_write32(trans, CSR_FUNC_SCRATCH, CSR_FUNC_SCRATCH_INIT_VALUE);
533 iwl_set_bit(trans, CSR_GP_CNTRL,
534 CSR_GP_CNTRL_REG_FLAG_ROM_START);
535 } else if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
536 iwl_write_umac_prph(trans, UREG_CPU_INIT_RUN, 1);
537 } else {
538 iwl_write_prph(trans, UREG_CPU_INIT_RUN, 1);
539 }
540
541 if (keep_ram_busy)
542 iwl_pcie_spin_for_iml(trans);
543
544 /* re-check RF-Kill state since we may have missed the interrupt */
545 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
546 if (hw_rfkill && !run_in_rfkill)
547 ret = -ERFKILL;
548
549 out:
550 mutex_unlock(&trans_pcie->mutex);
551 return ret;
552 }
553