1 /*-
2 * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
3 * reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in
13 * the documentation and/or other materials provided with the
14 * distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
26 * THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * NETLOGIC_BSD
29 * $FreeBSD: stable/9/sys/mips/nlm/hal/cpucontrol.h 225394 2011-09-05 10:45:29Z jchandra $
30 */
31
32 #ifndef __NLM_HAL_CPUCONTROL_H__
33 #define __NLM_HAL_CPUCONTROL_H__
34
35 #define CPU_BLOCKID_IFU 0
36 #define CPU_BLOCKID_ICU 1
37 #define CPU_BLOCKID_IEU 2
38 #define CPU_BLOCKID_LSU 3
39 #define CPU_BLOCKID_MMU 4
40 #define CPU_BLOCKID_PRF 5
41 #define CPU_BLOCKID_SCH 7
42 #define CPU_BLOCKID_SCU 8
43 #define CPU_BLOCKID_FPU 9
44 #define CPU_BLOCKID_MAP 10
45
46 #define LSU_DEFEATURE 0x304
47 #define LSU_CERRLOG_REGID 0x09
48 #define SCHED_DEFEATURE 0x700
49
50 /* Offsets of interest from the 'MAP' Block */
51 #define MAP_THREADMODE 0x00
52 #define MAP_EXT_EBASE_ENABLE 0x04
53 #define MAP_CCDI_CONFIG 0x08
54 #define MAP_THRD0_CCDI_STATUS 0x0c
55 #define MAP_THRD1_CCDI_STATUS 0x10
56 #define MAP_THRD2_CCDI_STATUS 0x14
57 #define MAP_THRD3_CCDI_STATUS 0x18
58 #define MAP_THRD0_DEBUG_MODE 0x1c
59 #define MAP_THRD1_DEBUG_MODE 0x20
60 #define MAP_THRD2_DEBUG_MODE 0x24
61 #define MAP_THRD3_DEBUG_MODE 0x28
62 #define MAP_MISC_STATE 0x60
63 #define MAP_DEBUG_READ_CTL 0x64
64 #define MAP_DEBUG_READ_REG0 0x68
65 #define MAP_DEBUG_READ_REG1 0x6c
66
67 #define MMU_SETUP 0x400
68 #define MMU_LFSRSEED 0x401
69 #define MMU_HPW_NUM_PAGE_LVL 0x410
70 #define MMU_PGWKR_PGDBASE 0x411
71 #define MMU_PGWKR_PGDSHFT 0x412
72 #define MMU_PGWKR_PGDMASK 0x413
73 #define MMU_PGWKR_PUDSHFT 0x414
74 #define MMU_PGWKR_PUDMASK 0x415
75 #define MMU_PGWKR_PMDSHFT 0x416
76 #define MMU_PGWKR_PMDMASK 0x417
77 #define MMU_PGWKR_PTESHFT 0x418
78 #define MMU_PGWKR_PTEMASK 0x419
79
80
81 #if !defined(LOCORE) && !defined(__ASSEMBLY__)
82 #if defined(__mips_n64) || defined(__mips_n32)
83 static __inline uint64_t
nlm_mfcr(uint32_t reg)84 nlm_mfcr(uint32_t reg)
85 {
86 uint64_t res;
87
88 __asm__ __volatile__(
89 ".set push\n\t"
90 ".set noreorder\n\t"
91 "move $9, %1\n\t"
92 ".word 0x71280018\n\t" /* mfcr $8, $9 */
93 "move %0, $8\n\t"
94 ".set pop\n"
95 : "=r" (res) : "r"(reg)
96 : "$8", "$9"
97 );
98 return (res);
99 }
100
101 static __inline void
nlm_mtcr(uint32_t reg,uint64_t value)102 nlm_mtcr(uint32_t reg, uint64_t value)
103 {
104 __asm__ __volatile__(
105 ".set push\n\t"
106 ".set noreorder\n\t"
107 "move $8, %0\n"
108 "move $9, %1\n"
109 ".word 0x71280019\n" /* mtcr $8, $9 */
110 ".set pop\n"
111 :
112 : "r" (value), "r" (reg)
113 : "$8", "$9"
114 );
115 }
116
117 #else /* !(defined(__mips_n64) || defined(__mips_n32)) */
118
119 static __inline__ uint64_t
nlm_mfcr(uint32_t reg)120 nlm_mfcr(uint32_t reg)
121 {
122 uint32_t hi, lo;
123
124 __asm__ __volatile__ (
125 ".set push\n"
126 ".set mips64\n"
127 "move $8, %2\n"
128 ".word 0x71090018\n"
129 "nop \n"
130 "dsra32 %0, $9, 0\n"
131 "sll %1, $9, 0\n"
132 ".set pop\n"
133 : "=r"(hi), "=r"(lo)
134 : "r"(reg) : "$8", "$9");
135
136 return (((uint64_t)hi) << 32) | lo;
137 }
138
139 static __inline__ void
nlm_mtcr(uint32_t reg,uint64_t val)140 nlm_mtcr(uint32_t reg, uint64_t val)
141 {
142 uint32_t hi, lo;
143
144 hi = val >> 32;
145 lo = val & 0xffffffff;
146
147 __asm__ __volatile__ (
148 ".set push\n"
149 ".set mips64\n"
150 "move $9, %0\n"
151 "dsll32 $9, %1, 0\n"
152 "dsll32 $8, %0, 0\n"
153 "dsrl32 $9, $9, 0\n"
154 "or $9, $9, $8\n"
155 "move $8, %2\n"
156 ".word 0x71090019\n"
157 "nop \n"
158 ".set pop\n"
159 : :"r"(hi), "r"(lo), "r"(reg)
160 : "$8", "$9");
161 }
162 #endif /* (defined(__mips_n64) || defined(__mips_n32)) */
163
164 /* hashindex_en = 1 to enable hash mode, hashindex_en=0 to disable
165 * global_mode = 1 to enable global mode, global_mode=0 to disable
166 * clk_gating = 0 to enable clock gating, clk_gating=1 to disable
167 */
nlm_mmu_setup(int hashindex_en,int global_mode,int clk_gating)168 static __inline__ void nlm_mmu_setup(int hashindex_en, int global_mode,
169 int clk_gating)
170 {
171 uint32_t mmusetup = 0;
172
173 mmusetup |= (hashindex_en << 13);
174 mmusetup |= (clk_gating << 3);
175 mmusetup |= (global_mode << 0);
176 nlm_mtcr(MMU_SETUP, mmusetup);
177 }
178
nlm_mmu_lfsr_seed(int thr0_seed,int thr1_seed,int thr2_seed,int thr3_seed)179 static __inline__ void nlm_mmu_lfsr_seed (int thr0_seed, int thr1_seed,
180 int thr2_seed, int thr3_seed)
181 {
182 uint32_t seed = nlm_mfcr(MMU_LFSRSEED);
183
184 seed |= ((thr3_seed & 0x7f) << 23);
185 seed |= ((thr2_seed & 0x7f) << 16);
186 seed |= ((thr1_seed & 0x7f) << 7);
187 seed |= ((thr0_seed & 0x7f) << 0);
188 nlm_mtcr(MMU_LFSRSEED, seed);
189 }
190
191 #endif /* __ASSEMBLY__ */
192 #endif /* __NLM_CPUCONTROL_H__ */
193