1 /*- 2 * Copyright (c) 2010 Adrian Chadd 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* $FreeBSD: stable/9/sys/mips/atheros/ar724xreg.h 221518 2011-05-06 02:45:02Z adrian $ */ 28 29 #ifndef __AR72XX_REG_H__ 30 #define __AR72XX_REG_H__ 31 32 #define AR724X_PLL_REG_CPU_CONFIG AR71XX_PLL_CPU_BASE + 0x00 33 #define AR724X_PLL_REG_PCIE_CONFIG AR71XX_PLL_CPU_BASE + 0x18 34 35 #define AR724X_PLL_DIV_SHIFT 0 36 #define AR724X_PLL_DIV_MASK 0x3ff 37 #define AR724X_PLL_REF_DIV_SHIFT 10 38 #define AR724X_PLL_REF_DIV_MASK 0xf 39 #define AR724X_AHB_DIV_SHIFT 19 40 #define AR724X_AHB_DIV_MASK 0x1 41 #define AR724X_DDR_DIV_SHIFT 22 42 #define AR724X_DDR_DIV_MASK 0x3 43 44 #define AR724X_PLL_VAL_1000 0x00110000 45 #define AR724X_PLL_VAL_100 0x00001099 46 #define AR724X_PLL_VAL_10 0x00991099 47 48 #define AR724X_BASE_FREQ 5000000 49 50 #define AR724X_DDR_REG_FLUSH_GE0 (AR71XX_DDR_CONFIG + 0x7c) 51 #define AR724X_DDR_REG_FLUSH_GE1 (AR71XX_DDR_CONFIG + 0x80) 52 #define AR724X_DDR_REG_FLUSH_USB (AR71XX_DDR_CONFIG + 0x84) 53 #define AR724X_DDR_REG_FLUSH_PCIE (AR71XX_DDR_CONFIG + 0x88) 54 55 #define AR724X_RESET_REG_RESET_MODULE AR71XX_RST_BLOCK_BASE + 0x1c 56 #define AR724X_RESET_USB_HOST (1 << 5) 57 #define AR724X_RESET_USB_PHY (1 << 4) 58 #define AR724X_RESET_MODULE_USB_OHCI_DLL (1 << 3) 59 60 #define AR724X_RESET_GE1_MDIO (1 << 23) 61 #define AR724X_RESET_GE0_MDIO (1 << 22) 62 #define AR724X_RESET_PCIE_PHY_SERIAL (1 << 10) 63 #define AR724X_RESET_PCIE_PHY (1 << 7) 64 #define AR724X_RESET_PCIE (1 << 6) 65 #define AR724X_RESET_USB_HOST (1 << 5) 66 #define AR724X_RESET_USB_PHY (1 << 4) 67 #define AR724X_RESET_USBSUS_OVERRIDE (1 << 3) 68 69 /* XXX so USB requires different init code? -adrian */ 70 #define AR7240_OHCI_BASE 0x1b000000 71 #define AR7240_OHCI_SIZE 0x01000000 72 73 #define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000C0000) 74 #define AR724X_PCI_CRP_SIZE 0x100 75 #define AR724X_PCI_CFG_BASE 0x14000000 76 #define AR724X_PCI_CFG_SIZE 0x1000 77 78 #define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000F0000) 79 #define AR724X_PCI_CTRL_SIZE 0x100 80 81 /* PCI config registers */ 82 #define AR724X_PCI_APP 0x180f0000 83 #define AR724X_PCI_APP_LTSSM_ENABLE (1 << 0) 84 #define AR724X_PCI_RESET 0x180f0018 85 #define AR724X_PCI_RESET_LINK_UP (1 << 0) 86 #define AR724X_PCI_INTR_STATUS 0x180f004c 87 #define AR724X_PCI_INTR_MASK 0x180f0050 88 #define AR724X_PCI_INTR_DEV0 (1 << 14) 89 90 #define AR724X_GPIO_FUNC_GE0_MII_CLK_EN (1 >> 19) 91 #define AR724X_GPIO_FUNC_SPI_EN (1 >> 18) 92 #define AR724X_GPIO_FUNC_SPI_CS_EN2 (1 >> 14) 93 #define AR724X_GPIO_FUNC_SPI_CS_EN1 (1 >> 13) 94 #define AR724X_GPIO_FUNC_CLK_OBS5_EN (1 >> 12) 95 #define AR724X_GPIO_FUNC_CLK_OBS4_EN (1 >> 11) 96 #define AR724X_GPIO_FUNC_CLK_OBS3_EN (1 >> 10) 97 #define AR724X_GPIO_FUNC_CLK_OBS2_EN (1 >> 9) 98 #define AR724X_GPIO_FUNC_CLK_OBS1_EN (1 >> 8) 99 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN (1 >> 7) 100 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN (1 >> 6) 101 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN (1 >> 5) 102 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN (1 >> 4) 103 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN (1 >> 3) 104 #define AR724X_GPIO_FUNC_UART_RTS_CTS_EN (1 >> 2) 105 #define AR724X_GPIO_FUNC_UART_EN (1 >> 1) 106 #define AR724X_GPIO_FUNC_JTAG_DISABLE (1 >> 0) 107 108 #endif 109