1 /*- 2 * Copyright (c) 1997 Semen Ustimenko 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: stable/9/sys/dev/tx/if_txreg.h 119690 2003-09-02 17:30:40Z jhb $ 27 */ 28 29 #define EPIC_MAX_MTU 1600 /* This is experiment-derived value */ 30 31 /* PCI aux configuration registers */ 32 #define PCIR_BASEIO PCIR_BAR(0) /* Base IO Address */ 33 #define PCIR_BASEMEM PCIR_BAR(1) /* Base Memory Address */ 34 35 /* PCI identification */ 36 #define SMC_VENDORID 0x10B8 37 #define SMC_DEVICEID_83C170 0x0005 38 39 /* EPIC's registers */ 40 #define COMMAND 0x0000 41 #define INTSTAT 0x0004 /* Interrupt status. See below */ 42 #define INTMASK 0x0008 /* Interrupt mask. See below */ 43 #define GENCTL 0x000C 44 #define NVCTL 0x0010 45 #define EECTL 0x0014 /* EEPROM control **/ 46 #define TEST1 0x001C /* XXXXX */ 47 #define CRCCNT 0x0020 /* CRC error counter */ 48 #define ALICNT 0x0024 /* FrameTooLang error counter */ 49 #define MPCNT 0x0028 /* MissedFrames error counters */ 50 #define MIICTL 0x0030 51 #define MIIDATA 0x0034 52 #define MIICFG 0x0038 53 #define IPG 0x003C 54 #define LAN0 0x0040 /* MAC address */ 55 #define LAN1 0x0044 /* MAC address */ 56 #define LAN2 0x0048 /* MAC address */ 57 #define ID_CHK 0x004C 58 #define MC0 0x0050 /* Multicast filter table */ 59 #define MC1 0x0054 /* Multicast filter table */ 60 #define MC2 0x0058 /* Multicast filter table */ 61 #define MC3 0x005C /* Multicast filter table */ 62 #define RXCON 0x0060 /* Rx control register */ 63 #define TXCON 0x0070 /* Tx control register */ 64 #define TXSTAT 0x0074 65 #define PRCDAR 0x0084 /* RxRing bus address */ 66 #define PRSTAT 0x00A4 67 #define PRCPTHR 0x00B0 68 #define PTCDAR 0x00C4 /* TxRing bus address */ 69 #define ETXTHR 0x00DC 70 71 #define COMMAND_STOP_RX 0x01 72 #define COMMAND_START_RX 0x02 73 #define COMMAND_TXQUEUED 0x04 74 #define COMMAND_RXQUEUED 0x08 75 #define COMMAND_NEXTFRAME 0x10 76 #define COMMAND_STOP_TDMA 0x20 77 #define COMMAND_STOP_RDMA 0x40 78 #define COMMAND_TXUGO 0x80 79 80 /* Interrupt register bits */ 81 #define INTSTAT_RCC 0x00000001 82 #define INTSTAT_HCC 0x00000002 83 #define INTSTAT_RQE 0x00000004 84 #define INTSTAT_OVW 0x00000008 85 #define INTSTAT_RXE 0x00000010 86 #define INTSTAT_TXC 0x00000020 87 #define INTSTAT_TCC 0x00000040 88 #define INTSTAT_TQE 0x00000080 89 #define INTSTAT_TXU 0x00000100 90 #define INTSTAT_CNT 0x00000200 91 #define INTSTAT_PREI 0x00000400 92 #define INTSTAT_RCT 0x00000800 93 #define INTSTAT_FATAL 0x00001000 /* One of DPE,APE,PMA,PTA happend */ 94 #define INTSTAT_UNUSED1 0x00002000 95 #define INTSTAT_UNUSED2 0x00004000 96 #define INTSTAT_GP2 0x00008000 /* PHY Event */ 97 #define INTSTAT_INT_ACTV 0x00010000 98 #define INTSTAT_RXIDLE 0x00020000 99 #define INTSTAT_TXIDLE 0x00040000 100 #define INTSTAT_RCIP 0x00080000 101 #define INTSTAT_TCIP 0x00100000 102 #define INTSTAT_RBE 0x00200000 103 #define INTSTAT_RCTS 0x00400000 104 #define INTSTAT_RSV 0x00800000 105 #define INTSTAT_DPE 0x01000000 /* PCI Fatal error */ 106 #define INTSTAT_APE 0x02000000 /* PCI Fatal error */ 107 #define INTSTAT_PMA 0x04000000 /* PCI Fatal error */ 108 #define INTSTAT_PTA 0x08000000 /* PCI Fatal error */ 109 110 #define GENCTL_SOFT_RESET 0x00000001 111 #define GENCTL_ENABLE_INTERRUPT 0x00000002 112 #define GENCTL_SOFTWARE_INTERRUPT 0x00000004 113 #define GENCTL_POWER_DOWN 0x00000008 114 #define GENCTL_ONECOPY 0x00000010 115 #define GENCTL_BIG_ENDIAN 0x00000020 116 #define GENCTL_RECEIVE_DMA_PRIORITY 0x00000040 117 #define GENCTL_TRANSMIT_DMA_PRIORITY 0x00000080 118 #define GENCTL_RECEIVE_FIFO_THRESHOLD128 0x00000300 119 #define GENCTL_RECEIVE_FIFO_THRESHOLD96 0x00000200 120 #define GENCTL_RECEIVE_FIFO_THRESHOLD64 0x00000100 121 #define GENCTL_RECEIVE_FIFO_THRESHOLD32 0x00000000 122 #define GENCTL_MEMORY_READ_LINE 0x00000400 123 #define GENCTL_MEMORY_READ_MULTIPLE 0x00000800 124 #define GENCTL_SOFTWARE1 0x00001000 125 #define GENCTL_SOFTWARE2 0x00002000 126 #define GENCTL_RESET_PHY 0x00004000 127 128 #define NVCTL_ENABLE_MEMORY_MAP 0x00000001 129 #define NVCTL_CLOCK_RUN_SUPPORTED 0x00000002 130 #define NVCTL_GP1_OUTPUT_ENABLE 0x00000004 131 #define NVCTL_GP2_OUTPUT_ENABLE 0x00000008 132 #define NVCTL_GP1 0x00000010 133 #define NVCTL_GP2 0x00000020 134 #define NVCTL_CARDBUS_MODE 0x00000040 135 #define NVCTL_IPG_DELAY_MASK(x) ((x&0xF)<<7) 136 137 #define RXCON_SAVE_ERRORED_PACKETS 0x00000001 138 #define RXCON_RECEIVE_RUNT_FRAMES 0x00000002 139 #define RXCON_RECEIVE_BROADCAST_FRAMES 0x00000004 140 #define RXCON_RECEIVE_MULTICAST_FRAMES 0x00000008 141 #define RXCON_RECEIVE_INVERSE_INDIVIDUAL_ADDRESS_FRAMES 0x00000010 142 #define RXCON_PROMISCUOUS_MODE 0x00000020 143 #define RXCON_MONITOR_MODE 0x00000040 144 #define RXCON_EARLY_RECEIVE_ENABLE 0x00000080 145 #define RXCON_EXTERNAL_BUFFER_DISABLE 0x00000000 146 #define RXCON_EXTERNAL_BUFFER_16K 0x00000100 147 #define RXCON_EXTERNAL_BUFFER_32K 0x00000200 148 #define RXCON_EXTERNAL_BUFFER_128K 0x00000300 149 150 #define TXCON_EARLY_TRANSMIT_ENABLE 0x00000001 151 #define TXCON_LOOPBACK_DISABLE 0x00000000 152 #define TXCON_LOOPBACK_MODE_INT 0x00000002 153 #define TXCON_LOOPBACK_MODE_PHY 0x00000004 154 #define TXCON_LOOPBACK_MODE 0x00000006 155 #define TXCON_FULL_DUPLEX 0x00000006 156 #define TXCON_SLOT_TIME 0x00000078 157 158 #define MIICFG_SERIAL_ENABLE 0x00000001 159 #define MIICFG_694_ENABLE 0x00000002 160 #define MIICFG_694_STATUS 0x00000004 161 #define MIICFG_PHY_PRESENT 0x00000008 162 #define MIICFG_SMI_ENABLE 0x00000010 163 164 #define TEST1_CLOCK_TEST 0x00000008 165 166 /* 167 * Some default values 168 */ 169 #define TXCON_DEFAULT (TXCON_SLOT_TIME | TXCON_EARLY_TRANSMIT_ENABLE) 170 #define TRANSMIT_THRESHOLD 0x300 171 #define TRANSMIT_THRESHOLD_MAX 0x600 172 173 #define RXCON_DEFAULT (RXCON_RECEIVE_MULTICAST_FRAMES | \ 174 RXCON_RECEIVE_BROADCAST_FRAMES) 175 176 #define RXCON_EARLY_RX (RXCON_EARLY_RECEIVE_ENABLE | \ 177 RXCON_SAVE_ERRORED_PACKETS) 178 /* 179 * EEPROM structure 180 * SMC9432* eeprom is organized by words and only first 8 words 181 * have distinctive meaning (according to datasheet) 182 */ 183 #define EEPROM_MAC0 0x0000 /* Byte 0 / Byte 1 */ 184 #define EEPROM_MAC1 0x0001 /* Byte 2 / Byte 3 */ 185 #define EEPROM_MAC2 0x0002 /* Byte 4 / Byte 5 */ 186 #define EEPROM_BID_CSUM 0x0003 /* Board Id / Check Sum */ 187 #define EEPROM_NVCTL 0x0004 /* NVCTL (bits 0-5) / nothing */ 188 #define EEPROM_PCI_MGD_MLD 0x0005 /* PCI MinGrant / MaxLatency. Desired */ 189 #define EEPROM_SSVENDID 0x0006 /* Subsystem Vendor Id */ 190 #define EEPROM_SSID 0x0006 /* Subsystem Id */ 191 192 /* 193 * Hardware structures. 194 */ 195 196 /* 197 * EPIC's hardware descriptors, must be aligned on dword in memory. 198 * NB: to make driver happy, this two structures MUST have their sizes 199 * be divisor of PAGE_SIZE. 200 */ 201 struct epic_tx_desc { 202 volatile u_int16_t status; 203 volatile u_int16_t txlength; 204 volatile u_int32_t bufaddr; 205 volatile u_int16_t buflength; 206 volatile u_int16_t control; 207 volatile u_int32_t next; 208 }; 209 struct epic_rx_desc { 210 volatile u_int16_t status; 211 volatile u_int16_t rxlength; 212 volatile u_int32_t bufaddr; 213 volatile u_int32_t buflength; 214 volatile u_int32_t next; 215 }; 216 217 /* 218 * This structure defines EPIC's fragment list, maximum number of frags 219 * is 63. Let's use the maximum, because size of struct MUST be divisor 220 * of PAGE_SIZE, and sometimes come mbufs with more then 30 frags. 221 */ 222 #define EPIC_MAX_FRAGS 63 223 struct epic_frag_list { 224 volatile u_int32_t numfrags; 225 struct { 226 volatile u_int32_t fragaddr; 227 volatile u_int32_t fraglen; 228 } frag[EPIC_MAX_FRAGS]; 229 volatile u_int32_t pad; /* align on 256 bytes */ 230 }; 231 232 /* 233 * NB: ALIGN OF ABOVE STRUCTURES 234 * epic_rx_desc, epic_tx_desc, epic_frag_list - must be aligned on dword 235 */ 236 237 #define SMC9432DMT 0xA010 238 #define SMC9432TX 0xA011 239 #define SMC9032TXM 0xA012 240 #define SMC9032TX 0xA013 241 #define SMC9432TXPWR 0xA014 242 #define SMC9432BTX 0xA015 243 #define SMC9432FTX 0xA016 244 #define SMC9432FTX_SC 0xA017 245 #define SMC9432TX_XG_ADHOC 0xA020 246 #define SMC9434TX_XG_ADHOC 0xA021 247 #define SMC9432FTX_ADHOC 0xA022 248 #define SMC9432BTX1 0xA024 249