1 /*-
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD: stable/9/sys/dev/sf/if_sf.c 248078 2013-03-09 00:39:54Z marius $");
35
36 /*
37 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD.
38 * Programming manual is available from:
39 * http://download.adaptec.com/pdfs/user_guides/aic6915_pg.pdf.
40 *
41 * Written by Bill Paul <wpaul@ctr.columbia.edu>
42 * Department of Electical Engineering
43 * Columbia University, New York City
44 */
45 /*
46 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet
47 * controller designed with flexibility and reducing CPU load in mind.
48 * The Starfire offers high and low priority buffer queues, a
49 * producer/consumer index mechanism and several different buffer
50 * queue and completion queue descriptor types. Any one of a number
51 * of different driver designs can be used, depending on system and
52 * OS requirements. This driver makes use of type2 transmit frame
53 * descriptors to take full advantage of fragmented packets buffers
54 * and two RX buffer queues prioritized on size (one queue for small
55 * frames that will fit into a single mbuf, another with full size
56 * mbuf clusters for everything else). The producer/consumer indexes
57 * and completion queues are also used.
58 *
59 * One downside to the Starfire has to do with alignment: buffer
60 * queues must be aligned on 256-byte boundaries, and receive buffers
61 * must be aligned on longword boundaries. The receive buffer alignment
62 * causes problems on the strict alignment architecture, where the
63 * packet payload should be longword aligned. There is no simple way
64 * around this.
65 *
66 * For receive filtering, the Starfire offers 16 perfect filter slots
67 * and a 512-bit hash table.
68 *
69 * The Starfire has no internal transceiver, relying instead on an
70 * external MII-based transceiver. Accessing registers on external
71 * PHYs is done through a special register map rather than with the
72 * usual bitbang MDIO method.
73 *
74 * Acesssing the registers on the Starfire is a little tricky. The
75 * Starfire has a 512K internal register space. When programmed for
76 * PCI memory mapped mode, the entire register space can be accessed
77 * directly. However in I/O space mode, only 256 bytes are directly
78 * mapped into PCI I/O space. The other registers can be accessed
79 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA
80 * registers inside the 256-byte I/O window.
81 */
82
83 #ifdef HAVE_KERNEL_OPTION_HEADERS
84 #include "opt_device_polling.h"
85 #endif
86
87 #include <sys/param.h>
88 #include <sys/systm.h>
89 #include <sys/bus.h>
90 #include <sys/endian.h>
91 #include <sys/kernel.h>
92 #include <sys/malloc.h>
93 #include <sys/mbuf.h>
94 #include <sys/rman.h>
95 #include <sys/module.h>
96 #include <sys/socket.h>
97 #include <sys/sockio.h>
98 #include <sys/sysctl.h>
99
100 #include <net/bpf.h>
101 #include <net/if.h>
102 #include <net/if_arp.h>
103 #include <net/ethernet.h>
104 #include <net/if_dl.h>
105 #include <net/if_media.h>
106 #include <net/if_types.h>
107 #include <net/if_vlan_var.h>
108
109 #include <dev/mii/mii.h>
110 #include <dev/mii/miivar.h>
111
112 #include <dev/pci/pcireg.h>
113 #include <dev/pci/pcivar.h>
114
115 #include <machine/bus.h>
116
117 #include <dev/sf/if_sfreg.h>
118 #include <dev/sf/starfire_rx.h>
119 #include <dev/sf/starfire_tx.h>
120
121 /* "device miibus" required. See GENERIC if you get errors here. */
122 #include "miibus_if.h"
123
124 MODULE_DEPEND(sf, pci, 1, 1, 1);
125 MODULE_DEPEND(sf, ether, 1, 1, 1);
126 MODULE_DEPEND(sf, miibus, 1, 1, 1);
127
128 #undef SF_GFP_DEBUG
129 #define SF_CSUM_FEATURES (CSUM_TCP | CSUM_UDP)
130 /* Define this to activate partial TCP/UDP checksum offload. */
131 #undef SF_PARTIAL_CSUM_SUPPORT
132
133 static struct sf_type sf_devs[] = {
134 { AD_VENDORID, AD_DEVICEID_STARFIRE, "Adaptec AIC-6915 10/100BaseTX",
135 AD_SUBSYSID_62011_REV0, "Adaptec ANA-62011 (rev 0) 10/100BaseTX" },
136 { AD_VENDORID, AD_DEVICEID_STARFIRE, "Adaptec AIC-6915 10/100BaseTX",
137 AD_SUBSYSID_62011_REV1, "Adaptec ANA-62011 (rev 1) 10/100BaseTX" },
138 { AD_VENDORID, AD_DEVICEID_STARFIRE, "Adaptec AIC-6915 10/100BaseTX",
139 AD_SUBSYSID_62022, "Adaptec ANA-62022 10/100BaseTX" },
140 { AD_VENDORID, AD_DEVICEID_STARFIRE, "Adaptec AIC-6915 10/100BaseTX",
141 AD_SUBSYSID_62044_REV0, "Adaptec ANA-62044 (rev 0) 10/100BaseTX" },
142 { AD_VENDORID, AD_DEVICEID_STARFIRE, "Adaptec AIC-6915 10/100BaseTX",
143 AD_SUBSYSID_62044_REV1, "Adaptec ANA-62044 (rev 1) 10/100BaseTX" },
144 { AD_VENDORID, AD_DEVICEID_STARFIRE, "Adaptec AIC-6915 10/100BaseTX",
145 AD_SUBSYSID_62020, "Adaptec ANA-62020 10/100BaseFX" },
146 { AD_VENDORID, AD_DEVICEID_STARFIRE, "Adaptec AIC-6915 10/100BaseTX",
147 AD_SUBSYSID_69011, "Adaptec ANA-69011 10/100BaseTX" },
148 };
149
150 static int sf_probe(device_t);
151 static int sf_attach(device_t);
152 static int sf_detach(device_t);
153 static int sf_shutdown(device_t);
154 static int sf_suspend(device_t);
155 static int sf_resume(device_t);
156 static void sf_intr(void *);
157 static void sf_tick(void *);
158 static void sf_stats_update(struct sf_softc *);
159 #ifndef __NO_STRICT_ALIGNMENT
160 static __inline void sf_fixup_rx(struct mbuf *);
161 #endif
162 static int sf_rxeof(struct sf_softc *);
163 static void sf_txeof(struct sf_softc *);
164 static int sf_encap(struct sf_softc *, struct mbuf **);
165 static void sf_start(struct ifnet *);
166 static void sf_start_locked(struct ifnet *);
167 static int sf_ioctl(struct ifnet *, u_long, caddr_t);
168 static void sf_download_fw(struct sf_softc *);
169 static void sf_init(void *);
170 static void sf_init_locked(struct sf_softc *);
171 static void sf_stop(struct sf_softc *);
172 static void sf_watchdog(struct sf_softc *);
173 static int sf_ifmedia_upd(struct ifnet *);
174 static int sf_ifmedia_upd_locked(struct ifnet *);
175 static void sf_ifmedia_sts(struct ifnet *, struct ifmediareq *);
176 static void sf_reset(struct sf_softc *);
177 static int sf_dma_alloc(struct sf_softc *);
178 static void sf_dma_free(struct sf_softc *);
179 static int sf_init_rx_ring(struct sf_softc *);
180 static void sf_init_tx_ring(struct sf_softc *);
181 static int sf_newbuf(struct sf_softc *, int);
182 static void sf_rxfilter(struct sf_softc *);
183 static int sf_setperf(struct sf_softc *, int, uint8_t *);
184 static int sf_sethash(struct sf_softc *, caddr_t, int);
185 #ifdef notdef
186 static int sf_setvlan(struct sf_softc *, int, uint32_t);
187 #endif
188
189 static uint8_t sf_read_eeprom(struct sf_softc *, int);
190
191 static int sf_miibus_readreg(device_t, int, int);
192 static int sf_miibus_writereg(device_t, int, int, int);
193 static void sf_miibus_statchg(device_t);
194 #ifdef DEVICE_POLLING
195 static int sf_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
196 #endif
197
198 static uint32_t csr_read_4(struct sf_softc *, int);
199 static void csr_write_4(struct sf_softc *, int, uint32_t);
200 static void sf_txthresh_adjust(struct sf_softc *);
201 static int sf_sysctl_stats(SYSCTL_HANDLER_ARGS);
202 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
203 static int sysctl_hw_sf_int_mod(SYSCTL_HANDLER_ARGS);
204
205 static device_method_t sf_methods[] = {
206 /* Device interface */
207 DEVMETHOD(device_probe, sf_probe),
208 DEVMETHOD(device_attach, sf_attach),
209 DEVMETHOD(device_detach, sf_detach),
210 DEVMETHOD(device_shutdown, sf_shutdown),
211 DEVMETHOD(device_suspend, sf_suspend),
212 DEVMETHOD(device_resume, sf_resume),
213
214 /* MII interface */
215 DEVMETHOD(miibus_readreg, sf_miibus_readreg),
216 DEVMETHOD(miibus_writereg, sf_miibus_writereg),
217 DEVMETHOD(miibus_statchg, sf_miibus_statchg),
218
219 DEVMETHOD_END
220 };
221
222 static driver_t sf_driver = {
223 "sf",
224 sf_methods,
225 sizeof(struct sf_softc),
226 };
227
228 static devclass_t sf_devclass;
229
230 DRIVER_MODULE(sf, pci, sf_driver, sf_devclass, 0, 0);
231 DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0);
232
233 #define SF_SETBIT(sc, reg, x) \
234 csr_write_4(sc, reg, csr_read_4(sc, reg) | (x))
235
236 #define SF_CLRBIT(sc, reg, x) \
237 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~(x))
238
239 static uint32_t
csr_read_4(struct sf_softc * sc,int reg)240 csr_read_4(struct sf_softc *sc, int reg)
241 {
242 uint32_t val;
243
244 if (sc->sf_restype == SYS_RES_MEMORY)
245 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE));
246 else {
247 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE);
248 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA);
249 }
250
251 return (val);
252 }
253
254 static uint8_t
sf_read_eeprom(struct sf_softc * sc,int reg)255 sf_read_eeprom(struct sf_softc *sc, int reg)
256 {
257 uint8_t val;
258
259 val = (csr_read_4(sc, SF_EEADDR_BASE +
260 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF;
261
262 return (val);
263 }
264
265 static void
csr_write_4(struct sf_softc * sc,int reg,uint32_t val)266 csr_write_4(struct sf_softc *sc, int reg, uint32_t val)
267 {
268
269 if (sc->sf_restype == SYS_RES_MEMORY)
270 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val);
271 else {
272 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE);
273 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val);
274 }
275 }
276
277 /*
278 * Copy the address 'mac' into the perfect RX filter entry at
279 * offset 'idx.' The perfect filter only has 16 entries so do
280 * some sanity tests.
281 */
282 static int
sf_setperf(struct sf_softc * sc,int idx,uint8_t * mac)283 sf_setperf(struct sf_softc *sc, int idx, uint8_t *mac)
284 {
285
286 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT)
287 return (EINVAL);
288
289 if (mac == NULL)
290 return (EINVAL);
291
292 csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
293 (idx * SF_RXFILT_PERFECT_SKIP) + 0, mac[5] | (mac[4] << 8));
294 csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
295 (idx * SF_RXFILT_PERFECT_SKIP) + 4, mac[3] | (mac[2] << 8));
296 csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
297 (idx * SF_RXFILT_PERFECT_SKIP) + 8, mac[1] | (mac[0] << 8));
298
299 return (0);
300 }
301
302 /*
303 * Set the bit in the 512-bit hash table that corresponds to the
304 * specified mac address 'mac.' If 'prio' is nonzero, update the
305 * priority hash table instead of the filter hash table.
306 */
307 static int
sf_sethash(struct sf_softc * sc,caddr_t mac,int prio)308 sf_sethash(struct sf_softc *sc, caddr_t mac, int prio)
309 {
310 uint32_t h;
311
312 if (mac == NULL)
313 return (EINVAL);
314
315 h = ether_crc32_be(mac, ETHER_ADDR_LEN) >> 23;
316
317 if (prio) {
318 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF +
319 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF)));
320 } else {
321 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF +
322 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF)));
323 }
324
325 return (0);
326 }
327
328 #ifdef notdef
329 /*
330 * Set a VLAN tag in the receive filter.
331 */
332 static int
sf_setvlan(struct sf_softc * sc,int idx,uint32_t vlan)333 sf_setvlan(struct sf_softc *sc, int idx, uint32_t vlan)
334 {
335
336 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT)
337 return (EINVAL);
338
339 csr_write_4(sc, SF_RXFILT_HASH_BASE +
340 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan);
341
342 return (0);
343 }
344 #endif
345
346 static int
sf_miibus_readreg(device_t dev,int phy,int reg)347 sf_miibus_readreg(device_t dev, int phy, int reg)
348 {
349 struct sf_softc *sc;
350 int i;
351 uint32_t val = 0;
352
353 sc = device_get_softc(dev);
354
355 for (i = 0; i < SF_TIMEOUT; i++) {
356 val = csr_read_4(sc, SF_PHY_REG(phy, reg));
357 if ((val & SF_MII_DATAVALID) != 0)
358 break;
359 }
360
361 if (i == SF_TIMEOUT)
362 return (0);
363
364 val &= SF_MII_DATAPORT;
365 if (val == 0xffff)
366 return (0);
367
368 return (val);
369 }
370
371 static int
sf_miibus_writereg(device_t dev,int phy,int reg,int val)372 sf_miibus_writereg(device_t dev, int phy, int reg, int val)
373 {
374 struct sf_softc *sc;
375 int i;
376 int busy;
377
378 sc = device_get_softc(dev);
379
380 csr_write_4(sc, SF_PHY_REG(phy, reg), val);
381
382 for (i = 0; i < SF_TIMEOUT; i++) {
383 busy = csr_read_4(sc, SF_PHY_REG(phy, reg));
384 if ((busy & SF_MII_BUSY) == 0)
385 break;
386 }
387
388 return (0);
389 }
390
391 static void
sf_miibus_statchg(device_t dev)392 sf_miibus_statchg(device_t dev)
393 {
394 struct sf_softc *sc;
395 struct mii_data *mii;
396 struct ifnet *ifp;
397 uint32_t val;
398
399 sc = device_get_softc(dev);
400 mii = device_get_softc(sc->sf_miibus);
401 ifp = sc->sf_ifp;
402 if (mii == NULL || ifp == NULL ||
403 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
404 return;
405
406 sc->sf_link = 0;
407 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
408 (IFM_ACTIVE | IFM_AVALID)) {
409 switch (IFM_SUBTYPE(mii->mii_media_active)) {
410 case IFM_10_T:
411 case IFM_100_TX:
412 case IFM_100_FX:
413 sc->sf_link = 1;
414 break;
415 }
416 }
417 if (sc->sf_link == 0)
418 return;
419
420 val = csr_read_4(sc, SF_MACCFG_1);
421 val &= ~SF_MACCFG1_FULLDUPLEX;
422 val &= ~(SF_MACCFG1_RX_FLOWENB | SF_MACCFG1_TX_FLOWENB);
423 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
424 val |= SF_MACCFG1_FULLDUPLEX;
425 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX);
426 #ifdef notyet
427 /* Configure flow-control bits. */
428 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) &
429 IFM_ETH_RXPAUSE) != 0)
430 val |= SF_MACCFG1_RX_FLOWENB;
431 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) &
432 IFM_ETH_TXPAUSE) != 0)
433 val |= SF_MACCFG1_TX_FLOWENB;
434 #endif
435 } else
436 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX);
437
438 /* Make sure to reset MAC to take changes effect. */
439 csr_write_4(sc, SF_MACCFG_1, val | SF_MACCFG1_SOFTRESET);
440 DELAY(1000);
441 csr_write_4(sc, SF_MACCFG_1, val);
442
443 val = csr_read_4(sc, SF_TIMER_CTL);
444 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX)
445 val |= SF_TIMER_TIMES_TEN;
446 else
447 val &= ~SF_TIMER_TIMES_TEN;
448 csr_write_4(sc, SF_TIMER_CTL, val);
449 }
450
451 static void
sf_rxfilter(struct sf_softc * sc)452 sf_rxfilter(struct sf_softc *sc)
453 {
454 struct ifnet *ifp;
455 int i;
456 struct ifmultiaddr *ifma;
457 uint8_t dummy[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
458 uint32_t rxfilt;
459
460 ifp = sc->sf_ifp;
461
462 /* First zot all the existing filters. */
463 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++)
464 sf_setperf(sc, i, dummy);
465 for (i = SF_RXFILT_HASH_BASE; i < (SF_RXFILT_HASH_MAX + 1);
466 i += sizeof(uint32_t))
467 csr_write_4(sc, i, 0);
468
469 rxfilt = csr_read_4(sc, SF_RXFILT);
470 rxfilt &= ~(SF_RXFILT_PROMISC | SF_RXFILT_ALLMULTI | SF_RXFILT_BROAD);
471 if ((ifp->if_flags & IFF_BROADCAST) != 0)
472 rxfilt |= SF_RXFILT_BROAD;
473 if ((ifp->if_flags & IFF_ALLMULTI) != 0 ||
474 (ifp->if_flags & IFF_PROMISC) != 0) {
475 if ((ifp->if_flags & IFF_PROMISC) != 0)
476 rxfilt |= SF_RXFILT_PROMISC;
477 if ((ifp->if_flags & IFF_ALLMULTI) != 0)
478 rxfilt |= SF_RXFILT_ALLMULTI;
479 goto done;
480 }
481
482 /* Now program new ones. */
483 i = 1;
484 if_maddr_rlock(ifp);
485 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead,
486 ifma_link) {
487 if (ifma->ifma_addr->sa_family != AF_LINK)
488 continue;
489 /*
490 * Program the first 15 multicast groups
491 * into the perfect filter. For all others,
492 * use the hash table.
493 */
494 if (i < SF_RXFILT_PERFECT_CNT) {
495 sf_setperf(sc, i,
496 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
497 i++;
498 continue;
499 }
500
501 sf_sethash(sc,
502 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0);
503 }
504 if_maddr_runlock(ifp);
505
506 done:
507 csr_write_4(sc, SF_RXFILT, rxfilt);
508 }
509
510 /*
511 * Set media options.
512 */
513 static int
sf_ifmedia_upd(struct ifnet * ifp)514 sf_ifmedia_upd(struct ifnet *ifp)
515 {
516 struct sf_softc *sc;
517 int error;
518
519 sc = ifp->if_softc;
520 SF_LOCK(sc);
521 error = sf_ifmedia_upd_locked(ifp);
522 SF_UNLOCK(sc);
523 return (error);
524 }
525
526 static int
sf_ifmedia_upd_locked(struct ifnet * ifp)527 sf_ifmedia_upd_locked(struct ifnet *ifp)
528 {
529 struct sf_softc *sc;
530 struct mii_data *mii;
531 struct mii_softc *miisc;
532
533 sc = ifp->if_softc;
534 mii = device_get_softc(sc->sf_miibus);
535 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
536 PHY_RESET(miisc);
537 return (mii_mediachg(mii));
538 }
539
540 /*
541 * Report current media status.
542 */
543 static void
sf_ifmedia_sts(struct ifnet * ifp,struct ifmediareq * ifmr)544 sf_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
545 {
546 struct sf_softc *sc;
547 struct mii_data *mii;
548
549 sc = ifp->if_softc;
550 SF_LOCK(sc);
551 if ((ifp->if_flags & IFF_UP) == 0) {
552 SF_UNLOCK(sc);
553 return;
554 }
555
556 mii = device_get_softc(sc->sf_miibus);
557 mii_pollstat(mii);
558 ifmr->ifm_active = mii->mii_media_active;
559 ifmr->ifm_status = mii->mii_media_status;
560 SF_UNLOCK(sc);
561 }
562
563 static int
sf_ioctl(struct ifnet * ifp,u_long command,caddr_t data)564 sf_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
565 {
566 struct sf_softc *sc;
567 struct ifreq *ifr;
568 struct mii_data *mii;
569 int error, mask;
570
571 sc = ifp->if_softc;
572 ifr = (struct ifreq *)data;
573 error = 0;
574
575 switch (command) {
576 case SIOCSIFFLAGS:
577 SF_LOCK(sc);
578 if (ifp->if_flags & IFF_UP) {
579 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
580 if ((ifp->if_flags ^ sc->sf_if_flags) &
581 (IFF_PROMISC | IFF_ALLMULTI))
582 sf_rxfilter(sc);
583 } else {
584 if (sc->sf_detach == 0)
585 sf_init_locked(sc);
586 }
587 } else {
588 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
589 sf_stop(sc);
590 }
591 sc->sf_if_flags = ifp->if_flags;
592 SF_UNLOCK(sc);
593 break;
594 case SIOCADDMULTI:
595 case SIOCDELMULTI:
596 SF_LOCK(sc);
597 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
598 sf_rxfilter(sc);
599 SF_UNLOCK(sc);
600 break;
601 case SIOCGIFMEDIA:
602 case SIOCSIFMEDIA:
603 mii = device_get_softc(sc->sf_miibus);
604 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
605 break;
606 case SIOCSIFCAP:
607 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
608 #ifdef DEVICE_POLLING
609 if ((mask & IFCAP_POLLING) != 0) {
610 if ((ifr->ifr_reqcap & IFCAP_POLLING) != 0) {
611 error = ether_poll_register(sf_poll, ifp);
612 if (error != 0)
613 break;
614 SF_LOCK(sc);
615 /* Disable interrupts. */
616 csr_write_4(sc, SF_IMR, 0);
617 ifp->if_capenable |= IFCAP_POLLING;
618 SF_UNLOCK(sc);
619 } else {
620 error = ether_poll_deregister(ifp);
621 /* Enable interrupts. */
622 SF_LOCK(sc);
623 csr_write_4(sc, SF_IMR, SF_INTRS);
624 ifp->if_capenable &= ~IFCAP_POLLING;
625 SF_UNLOCK(sc);
626 }
627 }
628 #endif /* DEVICE_POLLING */
629 if ((mask & IFCAP_TXCSUM) != 0) {
630 if ((IFCAP_TXCSUM & ifp->if_capabilities) != 0) {
631 SF_LOCK(sc);
632 ifp->if_capenable ^= IFCAP_TXCSUM;
633 if ((IFCAP_TXCSUM & ifp->if_capenable) != 0) {
634 ifp->if_hwassist |= SF_CSUM_FEATURES;
635 SF_SETBIT(sc, SF_GEN_ETH_CTL,
636 SF_ETHCTL_TXGFP_ENB);
637 } else {
638 ifp->if_hwassist &= ~SF_CSUM_FEATURES;
639 SF_CLRBIT(sc, SF_GEN_ETH_CTL,
640 SF_ETHCTL_TXGFP_ENB);
641 }
642 SF_UNLOCK(sc);
643 }
644 }
645 if ((mask & IFCAP_RXCSUM) != 0) {
646 if ((IFCAP_RXCSUM & ifp->if_capabilities) != 0) {
647 SF_LOCK(sc);
648 ifp->if_capenable ^= IFCAP_RXCSUM;
649 if ((IFCAP_RXCSUM & ifp->if_capenable) != 0)
650 SF_SETBIT(sc, SF_GEN_ETH_CTL,
651 SF_ETHCTL_RXGFP_ENB);
652 else
653 SF_CLRBIT(sc, SF_GEN_ETH_CTL,
654 SF_ETHCTL_RXGFP_ENB);
655 SF_UNLOCK(sc);
656 }
657 }
658 break;
659 default:
660 error = ether_ioctl(ifp, command, data);
661 break;
662 }
663
664 return (error);
665 }
666
667 static void
sf_reset(struct sf_softc * sc)668 sf_reset(struct sf_softc *sc)
669 {
670 int i;
671
672 csr_write_4(sc, SF_GEN_ETH_CTL, 0);
673 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET);
674 DELAY(1000);
675 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET);
676
677 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET);
678
679 for (i = 0; i < SF_TIMEOUT; i++) {
680 DELAY(10);
681 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET))
682 break;
683 }
684
685 if (i == SF_TIMEOUT)
686 device_printf(sc->sf_dev, "reset never completed!\n");
687
688 /* Wait a little while for the chip to get its brains in order. */
689 DELAY(1000);
690 }
691
692 /*
693 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device
694 * IDs against our list and return a device name if we find a match.
695 * We also check the subsystem ID so that we can identify exactly which
696 * NIC has been found, if possible.
697 */
698 static int
sf_probe(device_t dev)699 sf_probe(device_t dev)
700 {
701 struct sf_type *t;
702 uint16_t vid;
703 uint16_t did;
704 uint16_t sdid;
705 int i;
706
707 vid = pci_get_vendor(dev);
708 did = pci_get_device(dev);
709 sdid = pci_get_subdevice(dev);
710
711 t = sf_devs;
712 for (i = 0; i < sizeof(sf_devs) / sizeof(sf_devs[0]); i++, t++) {
713 if (vid == t->sf_vid && did == t->sf_did) {
714 if (sdid == t->sf_sdid) {
715 device_set_desc(dev, t->sf_sname);
716 return (BUS_PROBE_DEFAULT);
717 }
718 }
719 }
720
721 if (vid == AD_VENDORID && did == AD_DEVICEID_STARFIRE) {
722 /* unkown subdevice */
723 device_set_desc(dev, sf_devs[0].sf_name);
724 return (BUS_PROBE_DEFAULT);
725 }
726
727 return (ENXIO);
728 }
729
730 /*
731 * Attach the interface. Allocate softc structures, do ifmedia
732 * setup and ethernet/BPF attach.
733 */
734 static int
sf_attach(device_t dev)735 sf_attach(device_t dev)
736 {
737 int i;
738 struct sf_softc *sc;
739 struct ifnet *ifp;
740 uint32_t reg;
741 int rid, error = 0;
742 uint8_t eaddr[ETHER_ADDR_LEN];
743
744 sc = device_get_softc(dev);
745 sc->sf_dev = dev;
746
747 mtx_init(&sc->sf_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
748 MTX_DEF);
749 callout_init_mtx(&sc->sf_co, &sc->sf_mtx, 0);
750
751 /*
752 * Map control/status registers.
753 */
754 pci_enable_busmaster(dev);
755
756 /*
757 * Prefer memory space register mapping over I/O space as the
758 * hardware requires lots of register access to get various
759 * producer/consumer index during Tx/Rx operation. However this
760 * requires large memory space(512K) to map the entire register
761 * space.
762 */
763 sc->sf_rid = PCIR_BAR(0);
764 sc->sf_restype = SYS_RES_MEMORY;
765 sc->sf_res = bus_alloc_resource_any(dev, sc->sf_restype, &sc->sf_rid,
766 RF_ACTIVE);
767 if (sc->sf_res == NULL) {
768 reg = pci_read_config(dev, PCIR_BAR(0), 4);
769 if ((reg & PCIM_BAR_MEM_64) == PCIM_BAR_MEM_64)
770 sc->sf_rid = PCIR_BAR(2);
771 else
772 sc->sf_rid = PCIR_BAR(1);
773 sc->sf_restype = SYS_RES_IOPORT;
774 sc->sf_res = bus_alloc_resource_any(dev, sc->sf_restype,
775 &sc->sf_rid, RF_ACTIVE);
776 if (sc->sf_res == NULL) {
777 device_printf(dev, "couldn't allocate resources\n");
778 mtx_destroy(&sc->sf_mtx);
779 return (ENXIO);
780 }
781 }
782 if (bootverbose)
783 device_printf(dev, "using %s space register mapping\n",
784 sc->sf_restype == SYS_RES_MEMORY ? "memory" : "I/O");
785
786 reg = pci_read_config(dev, PCIR_CACHELNSZ, 1);
787 if (reg == 0) {
788 /*
789 * If cache line size is 0, MWI is not used at all, so set
790 * reasonable default. AIC-6915 supports 0, 4, 8, 16, 32
791 * and 64.
792 */
793 reg = 16;
794 device_printf(dev, "setting PCI cache line size to %u\n", reg);
795 pci_write_config(dev, PCIR_CACHELNSZ, reg, 1);
796 } else {
797 if (bootverbose)
798 device_printf(dev, "PCI cache line size : %u\n", reg);
799 }
800 /* Enable MWI. */
801 reg = pci_read_config(dev, PCIR_COMMAND, 2);
802 reg |= PCIM_CMD_MWRICEN;
803 pci_write_config(dev, PCIR_COMMAND, reg, 2);
804
805 /* Allocate interrupt. */
806 rid = 0;
807 sc->sf_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
808 RF_SHAREABLE | RF_ACTIVE);
809
810 if (sc->sf_irq == NULL) {
811 device_printf(dev, "couldn't map interrupt\n");
812 error = ENXIO;
813 goto fail;
814 }
815
816 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
817 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
818 OID_AUTO, "stats", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
819 sf_sysctl_stats, "I", "Statistics");
820
821 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
822 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
823 OID_AUTO, "int_mod", CTLTYPE_INT | CTLFLAG_RW,
824 &sc->sf_int_mod, 0, sysctl_hw_sf_int_mod, "I",
825 "sf interrupt moderation");
826 /* Pull in device tunables. */
827 sc->sf_int_mod = SF_IM_DEFAULT;
828 error = resource_int_value(device_get_name(dev), device_get_unit(dev),
829 "int_mod", &sc->sf_int_mod);
830 if (error == 0) {
831 if (sc->sf_int_mod < SF_IM_MIN ||
832 sc->sf_int_mod > SF_IM_MAX) {
833 device_printf(dev, "int_mod value out of range; "
834 "using default: %d\n", SF_IM_DEFAULT);
835 sc->sf_int_mod = SF_IM_DEFAULT;
836 }
837 }
838
839 /* Reset the adapter. */
840 sf_reset(sc);
841
842 /*
843 * Get station address from the EEPROM.
844 */
845 for (i = 0; i < ETHER_ADDR_LEN; i++)
846 eaddr[i] =
847 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i);
848
849 /* Allocate DMA resources. */
850 if (sf_dma_alloc(sc) != 0) {
851 error = ENOSPC;
852 goto fail;
853 }
854
855 sc->sf_txthresh = SF_MIN_TX_THRESHOLD;
856
857 ifp = sc->sf_ifp = if_alloc(IFT_ETHER);
858 if (ifp == NULL) {
859 device_printf(dev, "can not allocate ifnet structure\n");
860 error = ENOSPC;
861 goto fail;
862 }
863
864 /* Do MII setup. */
865 error = mii_attach(dev, &sc->sf_miibus, ifp, sf_ifmedia_upd,
866 sf_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
867 if (error != 0) {
868 device_printf(dev, "attaching PHYs failed\n");
869 goto fail;
870 }
871
872 ifp->if_softc = sc;
873 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
874 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
875 ifp->if_ioctl = sf_ioctl;
876 ifp->if_start = sf_start;
877 ifp->if_init = sf_init;
878 IFQ_SET_MAXLEN(&ifp->if_snd, SF_TX_DLIST_CNT - 1);
879 ifp->if_snd.ifq_drv_maxlen = SF_TX_DLIST_CNT - 1;
880 IFQ_SET_READY(&ifp->if_snd);
881 /*
882 * With the help of firmware, AIC-6915 supports
883 * Tx/Rx TCP/UDP checksum offload.
884 */
885 ifp->if_hwassist = SF_CSUM_FEATURES;
886 ifp->if_capabilities = IFCAP_HWCSUM;
887
888 /*
889 * Call MI attach routine.
890 */
891 ether_ifattach(ifp, eaddr);
892
893 /* VLAN capability setup. */
894 ifp->if_capabilities |= IFCAP_VLAN_MTU;
895 ifp->if_capenable = ifp->if_capabilities;
896 #ifdef DEVICE_POLLING
897 ifp->if_capabilities |= IFCAP_POLLING;
898 #endif
899 /*
900 * Tell the upper layer(s) we support long frames.
901 * Must appear after the call to ether_ifattach() because
902 * ether_ifattach() sets ifi_hdrlen to the default value.
903 */
904 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
905
906 /* Hook interrupt last to avoid having to lock softc */
907 error = bus_setup_intr(dev, sc->sf_irq, INTR_TYPE_NET | INTR_MPSAFE,
908 NULL, sf_intr, sc, &sc->sf_intrhand);
909
910 if (error) {
911 device_printf(dev, "couldn't set up irq\n");
912 ether_ifdetach(ifp);
913 goto fail;
914 }
915
916 fail:
917 if (error)
918 sf_detach(dev);
919
920 return (error);
921 }
922
923 /*
924 * Shutdown hardware and free up resources. This can be called any
925 * time after the mutex has been initialized. It is called in both
926 * the error case in attach and the normal detach case so it needs
927 * to be careful about only freeing resources that have actually been
928 * allocated.
929 */
930 static int
sf_detach(device_t dev)931 sf_detach(device_t dev)
932 {
933 struct sf_softc *sc;
934 struct ifnet *ifp;
935
936 sc = device_get_softc(dev);
937 ifp = sc->sf_ifp;
938
939 #ifdef DEVICE_POLLING
940 if (ifp != NULL && ifp->if_capenable & IFCAP_POLLING)
941 ether_poll_deregister(ifp);
942 #endif
943
944 /* These should only be active if attach succeeded */
945 if (device_is_attached(dev)) {
946 SF_LOCK(sc);
947 sc->sf_detach = 1;
948 sf_stop(sc);
949 SF_UNLOCK(sc);
950 callout_drain(&sc->sf_co);
951 if (ifp != NULL)
952 ether_ifdetach(ifp);
953 }
954 if (sc->sf_miibus) {
955 device_delete_child(dev, sc->sf_miibus);
956 sc->sf_miibus = NULL;
957 }
958 bus_generic_detach(dev);
959
960 if (sc->sf_intrhand != NULL)
961 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand);
962 if (sc->sf_irq != NULL)
963 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq);
964 if (sc->sf_res != NULL)
965 bus_release_resource(dev, sc->sf_restype, sc->sf_rid,
966 sc->sf_res);
967
968 sf_dma_free(sc);
969 if (ifp != NULL)
970 if_free(ifp);
971
972 mtx_destroy(&sc->sf_mtx);
973
974 return (0);
975 }
976
977 struct sf_dmamap_arg {
978 bus_addr_t sf_busaddr;
979 };
980
981 static void
sf_dmamap_cb(void * arg,bus_dma_segment_t * segs,int nseg,int error)982 sf_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
983 {
984 struct sf_dmamap_arg *ctx;
985
986 if (error != 0)
987 return;
988 ctx = arg;
989 ctx->sf_busaddr = segs[0].ds_addr;
990 }
991
992 static int
sf_dma_alloc(struct sf_softc * sc)993 sf_dma_alloc(struct sf_softc *sc)
994 {
995 struct sf_dmamap_arg ctx;
996 struct sf_txdesc *txd;
997 struct sf_rxdesc *rxd;
998 bus_addr_t lowaddr;
999 bus_addr_t rx_ring_end, rx_cring_end;
1000 bus_addr_t tx_ring_end, tx_cring_end;
1001 int error, i;
1002
1003 lowaddr = BUS_SPACE_MAXADDR;
1004
1005 again:
1006 /* Create parent DMA tag. */
1007 error = bus_dma_tag_create(
1008 bus_get_dma_tag(sc->sf_dev), /* parent */
1009 1, 0, /* alignment, boundary */
1010 lowaddr, /* lowaddr */
1011 BUS_SPACE_MAXADDR, /* highaddr */
1012 NULL, NULL, /* filter, filterarg */
1013 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1014 0, /* nsegments */
1015 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1016 0, /* flags */
1017 NULL, NULL, /* lockfunc, lockarg */
1018 &sc->sf_cdata.sf_parent_tag);
1019 if (error != 0) {
1020 device_printf(sc->sf_dev, "failed to create parent DMA tag\n");
1021 goto fail;
1022 }
1023 /* Create tag for Tx ring. */
1024 error = bus_dma_tag_create(sc->sf_cdata.sf_parent_tag,/* parent */
1025 SF_RING_ALIGN, 0, /* alignment, boundary */
1026 BUS_SPACE_MAXADDR, /* lowaddr */
1027 BUS_SPACE_MAXADDR, /* highaddr */
1028 NULL, NULL, /* filter, filterarg */
1029 SF_TX_DLIST_SIZE, /* maxsize */
1030 1, /* nsegments */
1031 SF_TX_DLIST_SIZE, /* maxsegsize */
1032 0, /* flags */
1033 NULL, NULL, /* lockfunc, lockarg */
1034 &sc->sf_cdata.sf_tx_ring_tag);
1035 if (error != 0) {
1036 device_printf(sc->sf_dev, "failed to create Tx ring DMA tag\n");
1037 goto fail;
1038 }
1039
1040 /* Create tag for Tx completion ring. */
1041 error = bus_dma_tag_create(sc->sf_cdata.sf_parent_tag,/* parent */
1042 SF_RING_ALIGN, 0, /* alignment, boundary */
1043 BUS_SPACE_MAXADDR, /* lowaddr */
1044 BUS_SPACE_MAXADDR, /* highaddr */
1045 NULL, NULL, /* filter, filterarg */
1046 SF_TX_CLIST_SIZE, /* maxsize */
1047 1, /* nsegments */
1048 SF_TX_CLIST_SIZE, /* maxsegsize */
1049 0, /* flags */
1050 NULL, NULL, /* lockfunc, lockarg */
1051 &sc->sf_cdata.sf_tx_cring_tag);
1052 if (error != 0) {
1053 device_printf(sc->sf_dev,
1054 "failed to create Tx completion ring DMA tag\n");
1055 goto fail;
1056 }
1057
1058 /* Create tag for Rx ring. */
1059 error = bus_dma_tag_create(sc->sf_cdata.sf_parent_tag,/* parent */
1060 SF_RING_ALIGN, 0, /* alignment, boundary */
1061 BUS_SPACE_MAXADDR, /* lowaddr */
1062 BUS_SPACE_MAXADDR, /* highaddr */
1063 NULL, NULL, /* filter, filterarg */
1064 SF_RX_DLIST_SIZE, /* maxsize */
1065 1, /* nsegments */
1066 SF_RX_DLIST_SIZE, /* maxsegsize */
1067 0, /* flags */
1068 NULL, NULL, /* lockfunc, lockarg */
1069 &sc->sf_cdata.sf_rx_ring_tag);
1070 if (error != 0) {
1071 device_printf(sc->sf_dev,
1072 "failed to create Rx ring DMA tag\n");
1073 goto fail;
1074 }
1075
1076 /* Create tag for Rx completion ring. */
1077 error = bus_dma_tag_create(sc->sf_cdata.sf_parent_tag,/* parent */
1078 SF_RING_ALIGN, 0, /* alignment, boundary */
1079 BUS_SPACE_MAXADDR, /* lowaddr */
1080 BUS_SPACE_MAXADDR, /* highaddr */
1081 NULL, NULL, /* filter, filterarg */
1082 SF_RX_CLIST_SIZE, /* maxsize */
1083 1, /* nsegments */
1084 SF_RX_CLIST_SIZE, /* maxsegsize */
1085 0, /* flags */
1086 NULL, NULL, /* lockfunc, lockarg */
1087 &sc->sf_cdata.sf_rx_cring_tag);
1088 if (error != 0) {
1089 device_printf(sc->sf_dev,
1090 "failed to create Rx completion ring DMA tag\n");
1091 goto fail;
1092 }
1093
1094 /* Create tag for Tx buffers. */
1095 error = bus_dma_tag_create(sc->sf_cdata.sf_parent_tag,/* parent */
1096 1, 0, /* alignment, boundary */
1097 BUS_SPACE_MAXADDR, /* lowaddr */
1098 BUS_SPACE_MAXADDR, /* highaddr */
1099 NULL, NULL, /* filter, filterarg */
1100 MCLBYTES * SF_MAXTXSEGS, /* maxsize */
1101 SF_MAXTXSEGS, /* nsegments */
1102 MCLBYTES, /* maxsegsize */
1103 0, /* flags */
1104 NULL, NULL, /* lockfunc, lockarg */
1105 &sc->sf_cdata.sf_tx_tag);
1106 if (error != 0) {
1107 device_printf(sc->sf_dev, "failed to create Tx DMA tag\n");
1108 goto fail;
1109 }
1110
1111 /* Create tag for Rx buffers. */
1112 error = bus_dma_tag_create(sc->sf_cdata.sf_parent_tag,/* parent */
1113 SF_RX_ALIGN, 0, /* alignment, boundary */
1114 BUS_SPACE_MAXADDR, /* lowaddr */
1115 BUS_SPACE_MAXADDR, /* highaddr */
1116 NULL, NULL, /* filter, filterarg */
1117 MCLBYTES, /* maxsize */
1118 1, /* nsegments */
1119 MCLBYTES, /* maxsegsize */
1120 0, /* flags */
1121 NULL, NULL, /* lockfunc, lockarg */
1122 &sc->sf_cdata.sf_rx_tag);
1123 if (error != 0) {
1124 device_printf(sc->sf_dev, "failed to create Rx DMA tag\n");
1125 goto fail;
1126 }
1127
1128 /* Allocate DMA'able memory and load the DMA map for Tx ring. */
1129 error = bus_dmamem_alloc(sc->sf_cdata.sf_tx_ring_tag,
1130 (void **)&sc->sf_rdata.sf_tx_ring, BUS_DMA_WAITOK |
1131 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->sf_cdata.sf_tx_ring_map);
1132 if (error != 0) {
1133 device_printf(sc->sf_dev,
1134 "failed to allocate DMA'able memory for Tx ring\n");
1135 goto fail;
1136 }
1137
1138 ctx.sf_busaddr = 0;
1139 error = bus_dmamap_load(sc->sf_cdata.sf_tx_ring_tag,
1140 sc->sf_cdata.sf_tx_ring_map, sc->sf_rdata.sf_tx_ring,
1141 SF_TX_DLIST_SIZE, sf_dmamap_cb, &ctx, 0);
1142 if (error != 0 || ctx.sf_busaddr == 0) {
1143 device_printf(sc->sf_dev,
1144 "failed to load DMA'able memory for Tx ring\n");
1145 goto fail;
1146 }
1147 sc->sf_rdata.sf_tx_ring_paddr = ctx.sf_busaddr;
1148
1149 /*
1150 * Allocate DMA'able memory and load the DMA map for Tx completion ring.
1151 */
1152 error = bus_dmamem_alloc(sc->sf_cdata.sf_tx_cring_tag,
1153 (void **)&sc->sf_rdata.sf_tx_cring, BUS_DMA_WAITOK |
1154 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->sf_cdata.sf_tx_cring_map);
1155 if (error != 0) {
1156 device_printf(sc->sf_dev,
1157 "failed to allocate DMA'able memory for "
1158 "Tx completion ring\n");
1159 goto fail;
1160 }
1161
1162 ctx.sf_busaddr = 0;
1163 error = bus_dmamap_load(sc->sf_cdata.sf_tx_cring_tag,
1164 sc->sf_cdata.sf_tx_cring_map, sc->sf_rdata.sf_tx_cring,
1165 SF_TX_CLIST_SIZE, sf_dmamap_cb, &ctx, 0);
1166 if (error != 0 || ctx.sf_busaddr == 0) {
1167 device_printf(sc->sf_dev,
1168 "failed to load DMA'able memory for Tx completion ring\n");
1169 goto fail;
1170 }
1171 sc->sf_rdata.sf_tx_cring_paddr = ctx.sf_busaddr;
1172
1173 /* Allocate DMA'able memory and load the DMA map for Rx ring. */
1174 error = bus_dmamem_alloc(sc->sf_cdata.sf_rx_ring_tag,
1175 (void **)&sc->sf_rdata.sf_rx_ring, BUS_DMA_WAITOK |
1176 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->sf_cdata.sf_rx_ring_map);
1177 if (error != 0) {
1178 device_printf(sc->sf_dev,
1179 "failed to allocate DMA'able memory for Rx ring\n");
1180 goto fail;
1181 }
1182
1183 ctx.sf_busaddr = 0;
1184 error = bus_dmamap_load(sc->sf_cdata.sf_rx_ring_tag,
1185 sc->sf_cdata.sf_rx_ring_map, sc->sf_rdata.sf_rx_ring,
1186 SF_RX_DLIST_SIZE, sf_dmamap_cb, &ctx, 0);
1187 if (error != 0 || ctx.sf_busaddr == 0) {
1188 device_printf(sc->sf_dev,
1189 "failed to load DMA'able memory for Rx ring\n");
1190 goto fail;
1191 }
1192 sc->sf_rdata.sf_rx_ring_paddr = ctx.sf_busaddr;
1193
1194 /*
1195 * Allocate DMA'able memory and load the DMA map for Rx completion ring.
1196 */
1197 error = bus_dmamem_alloc(sc->sf_cdata.sf_rx_cring_tag,
1198 (void **)&sc->sf_rdata.sf_rx_cring, BUS_DMA_WAITOK |
1199 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->sf_cdata.sf_rx_cring_map);
1200 if (error != 0) {
1201 device_printf(sc->sf_dev,
1202 "failed to allocate DMA'able memory for "
1203 "Rx completion ring\n");
1204 goto fail;
1205 }
1206
1207 ctx.sf_busaddr = 0;
1208 error = bus_dmamap_load(sc->sf_cdata.sf_rx_cring_tag,
1209 sc->sf_cdata.sf_rx_cring_map, sc->sf_rdata.sf_rx_cring,
1210 SF_RX_CLIST_SIZE, sf_dmamap_cb, &ctx, 0);
1211 if (error != 0 || ctx.sf_busaddr == 0) {
1212 device_printf(sc->sf_dev,
1213 "failed to load DMA'able memory for Rx completion ring\n");
1214 goto fail;
1215 }
1216 sc->sf_rdata.sf_rx_cring_paddr = ctx.sf_busaddr;
1217
1218 /*
1219 * Tx desciptor ring and Tx completion ring should be addressed in
1220 * the same 4GB space. The same rule applys to Rx ring and Rx
1221 * completion ring. Unfortunately there is no way to specify this
1222 * boundary restriction with bus_dma(9). So just try to allocate
1223 * without the restriction and check the restriction was satisfied.
1224 * If not, fall back to 32bit dma addressing mode which always
1225 * guarantees the restriction.
1226 */
1227 tx_ring_end = sc->sf_rdata.sf_tx_ring_paddr + SF_TX_DLIST_SIZE;
1228 tx_cring_end = sc->sf_rdata.sf_tx_cring_paddr + SF_TX_CLIST_SIZE;
1229 rx_ring_end = sc->sf_rdata.sf_rx_ring_paddr + SF_RX_DLIST_SIZE;
1230 rx_cring_end = sc->sf_rdata.sf_rx_cring_paddr + SF_RX_CLIST_SIZE;
1231 if ((SF_ADDR_HI(sc->sf_rdata.sf_tx_ring_paddr) !=
1232 SF_ADDR_HI(tx_cring_end)) ||
1233 (SF_ADDR_HI(sc->sf_rdata.sf_tx_cring_paddr) !=
1234 SF_ADDR_HI(tx_ring_end)) ||
1235 (SF_ADDR_HI(sc->sf_rdata.sf_rx_ring_paddr) !=
1236 SF_ADDR_HI(rx_cring_end)) ||
1237 (SF_ADDR_HI(sc->sf_rdata.sf_rx_cring_paddr) !=
1238 SF_ADDR_HI(rx_ring_end))) {
1239 device_printf(sc->sf_dev,
1240 "switching to 32bit DMA mode\n");
1241 sf_dma_free(sc);
1242 /* Limit DMA address space to 32bit and try again. */
1243 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1244 goto again;
1245 }
1246
1247 /* Create DMA maps for Tx buffers. */
1248 for (i = 0; i < SF_TX_DLIST_CNT; i++) {
1249 txd = &sc->sf_cdata.sf_txdesc[i];
1250 txd->tx_m = NULL;
1251 txd->ndesc = 0;
1252 txd->tx_dmamap = NULL;
1253 error = bus_dmamap_create(sc->sf_cdata.sf_tx_tag, 0,
1254 &txd->tx_dmamap);
1255 if (error != 0) {
1256 device_printf(sc->sf_dev,
1257 "failed to create Tx dmamap\n");
1258 goto fail;
1259 }
1260 }
1261 /* Create DMA maps for Rx buffers. */
1262 if ((error = bus_dmamap_create(sc->sf_cdata.sf_rx_tag, 0,
1263 &sc->sf_cdata.sf_rx_sparemap)) != 0) {
1264 device_printf(sc->sf_dev,
1265 "failed to create spare Rx dmamap\n");
1266 goto fail;
1267 }
1268 for (i = 0; i < SF_RX_DLIST_CNT; i++) {
1269 rxd = &sc->sf_cdata.sf_rxdesc[i];
1270 rxd->rx_m = NULL;
1271 rxd->rx_dmamap = NULL;
1272 error = bus_dmamap_create(sc->sf_cdata.sf_rx_tag, 0,
1273 &rxd->rx_dmamap);
1274 if (error != 0) {
1275 device_printf(sc->sf_dev,
1276 "failed to create Rx dmamap\n");
1277 goto fail;
1278 }
1279 }
1280
1281 fail:
1282 return (error);
1283 }
1284
1285 static void
sf_dma_free(struct sf_softc * sc)1286 sf_dma_free(struct sf_softc *sc)
1287 {
1288 struct sf_txdesc *txd;
1289 struct sf_rxdesc *rxd;
1290 int i;
1291
1292 /* Tx ring. */
1293 if (sc->sf_cdata.sf_tx_ring_tag) {
1294 if (sc->sf_cdata.sf_tx_ring_map)
1295 bus_dmamap_unload(sc->sf_cdata.sf_tx_ring_tag,
1296 sc->sf_cdata.sf_tx_ring_map);
1297 if (sc->sf_cdata.sf_tx_ring_map &&
1298 sc->sf_rdata.sf_tx_ring)
1299 bus_dmamem_free(sc->sf_cdata.sf_tx_ring_tag,
1300 sc->sf_rdata.sf_tx_ring,
1301 sc->sf_cdata.sf_tx_ring_map);
1302 sc->sf_rdata.sf_tx_ring = NULL;
1303 sc->sf_cdata.sf_tx_ring_map = NULL;
1304 bus_dma_tag_destroy(sc->sf_cdata.sf_tx_ring_tag);
1305 sc->sf_cdata.sf_tx_ring_tag = NULL;
1306 }
1307 /* Tx completion ring. */
1308 if (sc->sf_cdata.sf_tx_cring_tag) {
1309 if (sc->sf_cdata.sf_tx_cring_map)
1310 bus_dmamap_unload(sc->sf_cdata.sf_tx_cring_tag,
1311 sc->sf_cdata.sf_tx_cring_map);
1312 if (sc->sf_cdata.sf_tx_cring_map &&
1313 sc->sf_rdata.sf_tx_cring)
1314 bus_dmamem_free(sc->sf_cdata.sf_tx_cring_tag,
1315 sc->sf_rdata.sf_tx_cring,
1316 sc->sf_cdata.sf_tx_cring_map);
1317 sc->sf_rdata.sf_tx_cring = NULL;
1318 sc->sf_cdata.sf_tx_cring_map = NULL;
1319 bus_dma_tag_destroy(sc->sf_cdata.sf_tx_cring_tag);
1320 sc->sf_cdata.sf_tx_cring_tag = NULL;
1321 }
1322 /* Rx ring. */
1323 if (sc->sf_cdata.sf_rx_ring_tag) {
1324 if (sc->sf_cdata.sf_rx_ring_map)
1325 bus_dmamap_unload(sc->sf_cdata.sf_rx_ring_tag,
1326 sc->sf_cdata.sf_rx_ring_map);
1327 if (sc->sf_cdata.sf_rx_ring_map &&
1328 sc->sf_rdata.sf_rx_ring)
1329 bus_dmamem_free(sc->sf_cdata.sf_rx_ring_tag,
1330 sc->sf_rdata.sf_rx_ring,
1331 sc->sf_cdata.sf_rx_ring_map);
1332 sc->sf_rdata.sf_rx_ring = NULL;
1333 sc->sf_cdata.sf_rx_ring_map = NULL;
1334 bus_dma_tag_destroy(sc->sf_cdata.sf_rx_ring_tag);
1335 sc->sf_cdata.sf_rx_ring_tag = NULL;
1336 }
1337 /* Rx completion ring. */
1338 if (sc->sf_cdata.sf_rx_cring_tag) {
1339 if (sc->sf_cdata.sf_rx_cring_map)
1340 bus_dmamap_unload(sc->sf_cdata.sf_rx_cring_tag,
1341 sc->sf_cdata.sf_rx_cring_map);
1342 if (sc->sf_cdata.sf_rx_cring_map &&
1343 sc->sf_rdata.sf_rx_cring)
1344 bus_dmamem_free(sc->sf_cdata.sf_rx_cring_tag,
1345 sc->sf_rdata.sf_rx_cring,
1346 sc->sf_cdata.sf_rx_cring_map);
1347 sc->sf_rdata.sf_rx_cring = NULL;
1348 sc->sf_cdata.sf_rx_cring_map = NULL;
1349 bus_dma_tag_destroy(sc->sf_cdata.sf_rx_cring_tag);
1350 sc->sf_cdata.sf_rx_cring_tag = NULL;
1351 }
1352 /* Tx buffers. */
1353 if (sc->sf_cdata.sf_tx_tag) {
1354 for (i = 0; i < SF_TX_DLIST_CNT; i++) {
1355 txd = &sc->sf_cdata.sf_txdesc[i];
1356 if (txd->tx_dmamap) {
1357 bus_dmamap_destroy(sc->sf_cdata.sf_tx_tag,
1358 txd->tx_dmamap);
1359 txd->tx_dmamap = NULL;
1360 }
1361 }
1362 bus_dma_tag_destroy(sc->sf_cdata.sf_tx_tag);
1363 sc->sf_cdata.sf_tx_tag = NULL;
1364 }
1365 /* Rx buffers. */
1366 if (sc->sf_cdata.sf_rx_tag) {
1367 for (i = 0; i < SF_RX_DLIST_CNT; i++) {
1368 rxd = &sc->sf_cdata.sf_rxdesc[i];
1369 if (rxd->rx_dmamap) {
1370 bus_dmamap_destroy(sc->sf_cdata.sf_rx_tag,
1371 rxd->rx_dmamap);
1372 rxd->rx_dmamap = NULL;
1373 }
1374 }
1375 if (sc->sf_cdata.sf_rx_sparemap) {
1376 bus_dmamap_destroy(sc->sf_cdata.sf_rx_tag,
1377 sc->sf_cdata.sf_rx_sparemap);
1378 sc->sf_cdata.sf_rx_sparemap = 0;
1379 }
1380 bus_dma_tag_destroy(sc->sf_cdata.sf_rx_tag);
1381 sc->sf_cdata.sf_rx_tag = NULL;
1382 }
1383
1384 if (sc->sf_cdata.sf_parent_tag) {
1385 bus_dma_tag_destroy(sc->sf_cdata.sf_parent_tag);
1386 sc->sf_cdata.sf_parent_tag = NULL;
1387 }
1388 }
1389
1390 static int
sf_init_rx_ring(struct sf_softc * sc)1391 sf_init_rx_ring(struct sf_softc *sc)
1392 {
1393 struct sf_ring_data *rd;
1394 int i;
1395
1396 sc->sf_cdata.sf_rxc_cons = 0;
1397
1398 rd = &sc->sf_rdata;
1399 bzero(rd->sf_rx_ring, SF_RX_DLIST_SIZE);
1400 bzero(rd->sf_rx_cring, SF_RX_CLIST_SIZE);
1401
1402 for (i = 0; i < SF_RX_DLIST_CNT; i++) {
1403 if (sf_newbuf(sc, i) != 0)
1404 return (ENOBUFS);
1405 }
1406
1407 bus_dmamap_sync(sc->sf_cdata.sf_rx_cring_tag,
1408 sc->sf_cdata.sf_rx_cring_map,
1409 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1410 bus_dmamap_sync(sc->sf_cdata.sf_rx_ring_tag,
1411 sc->sf_cdata.sf_rx_ring_map,
1412 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1413
1414 return (0);
1415 }
1416
1417 static void
sf_init_tx_ring(struct sf_softc * sc)1418 sf_init_tx_ring(struct sf_softc *sc)
1419 {
1420 struct sf_ring_data *rd;
1421 int i;
1422
1423 sc->sf_cdata.sf_tx_prod = 0;
1424 sc->sf_cdata.sf_tx_cnt = 0;
1425 sc->sf_cdata.sf_txc_cons = 0;
1426
1427 rd = &sc->sf_rdata;
1428 bzero(rd->sf_tx_ring, SF_TX_DLIST_SIZE);
1429 bzero(rd->sf_tx_cring, SF_TX_CLIST_SIZE);
1430 for (i = 0; i < SF_TX_DLIST_CNT; i++) {
1431 rd->sf_tx_ring[i].sf_tx_ctrl = htole32(SF_TX_DESC_ID);
1432 sc->sf_cdata.sf_txdesc[i].tx_m = NULL;
1433 sc->sf_cdata.sf_txdesc[i].ndesc = 0;
1434 }
1435 rd->sf_tx_ring[i].sf_tx_ctrl |= htole32(SF_TX_DESC_END);
1436
1437 bus_dmamap_sync(sc->sf_cdata.sf_tx_ring_tag,
1438 sc->sf_cdata.sf_tx_ring_map,
1439 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1440 bus_dmamap_sync(sc->sf_cdata.sf_tx_cring_tag,
1441 sc->sf_cdata.sf_tx_cring_map,
1442 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1443 }
1444
1445 /*
1446 * Initialize an RX descriptor and attach an MBUF cluster.
1447 */
1448 static int
sf_newbuf(struct sf_softc * sc,int idx)1449 sf_newbuf(struct sf_softc *sc, int idx)
1450 {
1451 struct sf_rx_rdesc *desc;
1452 struct sf_rxdesc *rxd;
1453 struct mbuf *m;
1454 bus_dma_segment_t segs[1];
1455 bus_dmamap_t map;
1456 int nsegs;
1457
1458 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1459 if (m == NULL)
1460 return (ENOBUFS);
1461 m->m_len = m->m_pkthdr.len = MCLBYTES;
1462 m_adj(m, sizeof(uint32_t));
1463
1464 if (bus_dmamap_load_mbuf_sg(sc->sf_cdata.sf_rx_tag,
1465 sc->sf_cdata.sf_rx_sparemap, m, segs, &nsegs, 0) != 0) {
1466 m_freem(m);
1467 return (ENOBUFS);
1468 }
1469 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1470
1471 rxd = &sc->sf_cdata.sf_rxdesc[idx];
1472 if (rxd->rx_m != NULL) {
1473 bus_dmamap_sync(sc->sf_cdata.sf_rx_tag, rxd->rx_dmamap,
1474 BUS_DMASYNC_POSTREAD);
1475 bus_dmamap_unload(sc->sf_cdata.sf_rx_tag, rxd->rx_dmamap);
1476 }
1477 map = rxd->rx_dmamap;
1478 rxd->rx_dmamap = sc->sf_cdata.sf_rx_sparemap;
1479 sc->sf_cdata.sf_rx_sparemap = map;
1480 bus_dmamap_sync(sc->sf_cdata.sf_rx_tag, rxd->rx_dmamap,
1481 BUS_DMASYNC_PREREAD);
1482 rxd->rx_m = m;
1483 desc = &sc->sf_rdata.sf_rx_ring[idx];
1484 desc->sf_addr = htole64(segs[0].ds_addr);
1485
1486 return (0);
1487 }
1488
1489 #ifndef __NO_STRICT_ALIGNMENT
1490 static __inline void
sf_fixup_rx(struct mbuf * m)1491 sf_fixup_rx(struct mbuf *m)
1492 {
1493 int i;
1494 uint16_t *src, *dst;
1495
1496 src = mtod(m, uint16_t *);
1497 dst = src - 1;
1498
1499 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
1500 *dst++ = *src++;
1501
1502 m->m_data -= ETHER_ALIGN;
1503 }
1504 #endif
1505
1506 /*
1507 * The starfire is programmed to use 'normal' mode for packet reception,
1508 * which means we use the consumer/producer model for both the buffer
1509 * descriptor queue and the completion descriptor queue. The only problem
1510 * with this is that it involves a lot of register accesses: we have to
1511 * read the RX completion consumer and producer indexes and the RX buffer
1512 * producer index, plus the RX completion consumer and RX buffer producer
1513 * indexes have to be updated. It would have been easier if Adaptec had
1514 * put each index in a separate register, especially given that the damn
1515 * NIC has a 512K register space.
1516 *
1517 * In spite of all the lovely features that Adaptec crammed into the 6915,
1518 * it is marred by one truly stupid design flaw, which is that receive
1519 * buffer addresses must be aligned on a longword boundary. This forces
1520 * the packet payload to be unaligned, which is suboptimal on the x86 and
1521 * completely unuseable on the Alpha. Our only recourse is to copy received
1522 * packets into properly aligned buffers before handing them off.
1523 */
1524 static int
sf_rxeof(struct sf_softc * sc)1525 sf_rxeof(struct sf_softc *sc)
1526 {
1527 struct mbuf *m;
1528 struct ifnet *ifp;
1529 struct sf_rxdesc *rxd;
1530 struct sf_rx_rcdesc *cur_cmp;
1531 int cons, eidx, prog, rx_npkts;
1532 uint32_t status, status2;
1533
1534 SF_LOCK_ASSERT(sc);
1535
1536 ifp = sc->sf_ifp;
1537 rx_npkts = 0;
1538
1539 bus_dmamap_sync(sc->sf_cdata.sf_rx_ring_tag,
1540 sc->sf_cdata.sf_rx_ring_map,
1541 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1542 bus_dmamap_sync(sc->sf_cdata.sf_rx_cring_tag,
1543 sc->sf_cdata.sf_rx_cring_map,
1544 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1545
1546 /*
1547 * To reduce register access, directly read Receive completion
1548 * queue entry.
1549 */
1550 eidx = 0;
1551 prog = 0;
1552 for (cons = sc->sf_cdata.sf_rxc_cons;
1553 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0;
1554 SF_INC(cons, SF_RX_CLIST_CNT)) {
1555 cur_cmp = &sc->sf_rdata.sf_rx_cring[cons];
1556 status = le32toh(cur_cmp->sf_rx_status1);
1557 if (status == 0)
1558 break;
1559 #ifdef DEVICE_POLLING
1560 if ((ifp->if_capenable & IFCAP_POLLING) != 0) {
1561 if (sc->rxcycles <= 0)
1562 break;
1563 sc->rxcycles--;
1564 }
1565 #endif
1566 prog++;
1567 eidx = (status & SF_RX_CMPDESC_EIDX) >> 16;
1568 rxd = &sc->sf_cdata.sf_rxdesc[eidx];
1569 m = rxd->rx_m;
1570
1571 /*
1572 * Note, if_ipackets and if_ierrors counters
1573 * are handled in sf_stats_update().
1574 */
1575 if ((status & SF_RXSTAT1_OK) == 0) {
1576 cur_cmp->sf_rx_status1 = 0;
1577 continue;
1578 }
1579
1580 if (sf_newbuf(sc, eidx) != 0) {
1581 ifp->if_iqdrops++;
1582 cur_cmp->sf_rx_status1 = 0;
1583 continue;
1584 }
1585
1586 /* AIC-6915 supports TCP/UDP checksum offload. */
1587 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) {
1588 status2 = le32toh(cur_cmp->sf_rx_status2);
1589 /*
1590 * Sometimes AIC-6915 generates an interrupt to
1591 * warn RxGFP stall with bad checksum bit set
1592 * in status word. I'm not sure what conditioan
1593 * triggers it but recevied packet's checksum
1594 * was correct even though AIC-6915 does not
1595 * agree on this. This may be an indication of
1596 * firmware bug. To fix the issue, do not rely
1597 * on bad checksum bit in status word and let
1598 * upper layer verify integrity of received
1599 * frame.
1600 * Another nice feature of AIC-6915 is hardware
1601 * assistance of checksum calculation by
1602 * providing partial checksum value for received
1603 * frame. The partial checksum value can be used
1604 * to accelerate checksum computation for
1605 * fragmented TCP/UDP packets. Upper network
1606 * stack already takes advantage of the partial
1607 * checksum value in IP reassembly stage. But
1608 * I'm not sure the correctness of the partial
1609 * hardware checksum assistance as frequent
1610 * RxGFP stalls are seen on non-fragmented
1611 * frames. Due to the nature of the complexity
1612 * of checksum computation code in firmware it's
1613 * possible to see another bug in RxGFP so
1614 * ignore checksum assistance for fragmented
1615 * frames. This can be changed in future.
1616 */
1617 if ((status2 & SF_RXSTAT2_FRAG) == 0) {
1618 if ((status2 & (SF_RXSTAT2_TCP |
1619 SF_RXSTAT2_UDP)) != 0) {
1620 if ((status2 & SF_RXSTAT2_CSUM_OK)) {
1621 m->m_pkthdr.csum_flags =
1622 CSUM_DATA_VALID |
1623 CSUM_PSEUDO_HDR;
1624 m->m_pkthdr.csum_data = 0xffff;
1625 }
1626 }
1627 }
1628 #ifdef SF_PARTIAL_CSUM_SUPPORT
1629 else if ((status2 & SF_RXSTAT2_FRAG) != 0) {
1630 if ((status2 & (SF_RXSTAT2_TCP |
1631 SF_RXSTAT2_UDP)) != 0) {
1632 if ((status2 & SF_RXSTAT2_PCSUM_OK)) {
1633 m->m_pkthdr.csum_flags =
1634 CSUM_DATA_VALID;
1635 m->m_pkthdr.csum_data =
1636 (status &
1637 SF_RX_CMPDESC_CSUM2);
1638 }
1639 }
1640 }
1641 #endif
1642 }
1643
1644 m->m_pkthdr.len = m->m_len = status & SF_RX_CMPDESC_LEN;
1645 #ifndef __NO_STRICT_ALIGNMENT
1646 sf_fixup_rx(m);
1647 #endif
1648 m->m_pkthdr.rcvif = ifp;
1649
1650 SF_UNLOCK(sc);
1651 (*ifp->if_input)(ifp, m);
1652 SF_LOCK(sc);
1653 rx_npkts++;
1654
1655 /* Clear completion status. */
1656 cur_cmp->sf_rx_status1 = 0;
1657 }
1658
1659 if (prog > 0) {
1660 sc->sf_cdata.sf_rxc_cons = cons;
1661 bus_dmamap_sync(sc->sf_cdata.sf_rx_ring_tag,
1662 sc->sf_cdata.sf_rx_ring_map,
1663 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1664 bus_dmamap_sync(sc->sf_cdata.sf_rx_cring_tag,
1665 sc->sf_cdata.sf_rx_cring_map,
1666 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1667
1668 /* Update Rx completion Q1 consumer index. */
1669 csr_write_4(sc, SF_CQ_CONSIDX,
1670 (csr_read_4(sc, SF_CQ_CONSIDX) & ~SF_CQ_CONSIDX_RXQ1) |
1671 (cons & SF_CQ_CONSIDX_RXQ1));
1672 /* Update Rx descriptor Q1 ptr. */
1673 csr_write_4(sc, SF_RXDQ_PTR_Q1,
1674 (csr_read_4(sc, SF_RXDQ_PTR_Q1) & ~SF_RXDQ_PRODIDX) |
1675 (eidx & SF_RXDQ_PRODIDX));
1676 }
1677 return (rx_npkts);
1678 }
1679
1680 /*
1681 * Read the transmit status from the completion queue and release
1682 * mbufs. Note that the buffer descriptor index in the completion
1683 * descriptor is an offset from the start of the transmit buffer
1684 * descriptor list in bytes. This is important because the manual
1685 * gives the impression that it should match the producer/consumer
1686 * index, which is the offset in 8 byte blocks.
1687 */
1688 static void
sf_txeof(struct sf_softc * sc)1689 sf_txeof(struct sf_softc *sc)
1690 {
1691 struct sf_txdesc *txd;
1692 struct sf_tx_rcdesc *cur_cmp;
1693 struct ifnet *ifp;
1694 uint32_t status;
1695 int cons, idx, prod;
1696
1697 SF_LOCK_ASSERT(sc);
1698
1699 ifp = sc->sf_ifp;
1700
1701 bus_dmamap_sync(sc->sf_cdata.sf_tx_cring_tag,
1702 sc->sf_cdata.sf_tx_cring_map,
1703 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1704
1705 cons = sc->sf_cdata.sf_txc_cons;
1706 prod = (csr_read_4(sc, SF_CQ_PRODIDX) & SF_TXDQ_PRODIDX_HIPRIO) >> 16;
1707 if (prod == cons)
1708 return;
1709
1710 for (; cons != prod; SF_INC(cons, SF_TX_CLIST_CNT)) {
1711 cur_cmp = &sc->sf_rdata.sf_tx_cring[cons];
1712 status = le32toh(cur_cmp->sf_tx_status1);
1713 if (status == 0)
1714 break;
1715 switch (status & SF_TX_CMPDESC_TYPE) {
1716 case SF_TXCMPTYPE_TX:
1717 /* Tx complete entry. */
1718 break;
1719 case SF_TXCMPTYPE_DMA:
1720 /* DMA complete entry. */
1721 idx = status & SF_TX_CMPDESC_IDX;
1722 idx = idx / sizeof(struct sf_tx_rdesc);
1723 /*
1724 * We don't need to check Tx status here.
1725 * SF_ISR_TX_LOFIFO intr would handle this.
1726 * Note, if_opackets, if_collisions and if_oerrors
1727 * counters are handled in sf_stats_update().
1728 */
1729 txd = &sc->sf_cdata.sf_txdesc[idx];
1730 if (txd->tx_m != NULL) {
1731 bus_dmamap_sync(sc->sf_cdata.sf_tx_tag,
1732 txd->tx_dmamap,
1733 BUS_DMASYNC_POSTWRITE);
1734 bus_dmamap_unload(sc->sf_cdata.sf_tx_tag,
1735 txd->tx_dmamap);
1736 m_freem(txd->tx_m);
1737 txd->tx_m = NULL;
1738 }
1739 sc->sf_cdata.sf_tx_cnt -= txd->ndesc;
1740 KASSERT(sc->sf_cdata.sf_tx_cnt >= 0,
1741 ("%s: Active Tx desc counter was garbled\n",
1742 __func__));
1743 txd->ndesc = 0;
1744 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1745 break;
1746 default:
1747 /* It should not happen. */
1748 device_printf(sc->sf_dev,
1749 "unknown Tx completion type : 0x%08x : %d : %d\n",
1750 status, cons, prod);
1751 break;
1752 }
1753 cur_cmp->sf_tx_status1 = 0;
1754 }
1755
1756 sc->sf_cdata.sf_txc_cons = cons;
1757 bus_dmamap_sync(sc->sf_cdata.sf_tx_cring_tag,
1758 sc->sf_cdata.sf_tx_cring_map,
1759 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1760
1761 if (sc->sf_cdata.sf_tx_cnt == 0)
1762 sc->sf_watchdog_timer = 0;
1763
1764 /* Update Tx completion consumer index. */
1765 csr_write_4(sc, SF_CQ_CONSIDX,
1766 (csr_read_4(sc, SF_CQ_CONSIDX) & 0xffff) |
1767 ((cons << 16) & 0xffff0000));
1768 }
1769
1770 static void
sf_txthresh_adjust(struct sf_softc * sc)1771 sf_txthresh_adjust(struct sf_softc *sc)
1772 {
1773 uint32_t txfctl;
1774
1775 device_printf(sc->sf_dev, "Tx underrun -- ");
1776 if (sc->sf_txthresh < SF_MAX_TX_THRESHOLD) {
1777 txfctl = csr_read_4(sc, SF_TX_FRAMCTL);
1778 /* Increase Tx threshold 256 bytes. */
1779 sc->sf_txthresh += 16;
1780 if (sc->sf_txthresh > SF_MAX_TX_THRESHOLD)
1781 sc->sf_txthresh = SF_MAX_TX_THRESHOLD;
1782 txfctl &= ~SF_TXFRMCTL_TXTHRESH;
1783 txfctl |= sc->sf_txthresh;
1784 printf("increasing Tx threshold to %d bytes\n",
1785 sc->sf_txthresh * SF_TX_THRESHOLD_UNIT);
1786 csr_write_4(sc, SF_TX_FRAMCTL, txfctl);
1787 } else
1788 printf("\n");
1789 }
1790
1791 #ifdef DEVICE_POLLING
1792 static int
sf_poll(struct ifnet * ifp,enum poll_cmd cmd,int count)1793 sf_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1794 {
1795 struct sf_softc *sc;
1796 uint32_t status;
1797 int rx_npkts;
1798
1799 sc = ifp->if_softc;
1800 rx_npkts = 0;
1801 SF_LOCK(sc);
1802
1803 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1804 SF_UNLOCK(sc);
1805 return (rx_npkts);
1806 }
1807
1808 sc->rxcycles = count;
1809 rx_npkts = sf_rxeof(sc);
1810 sf_txeof(sc);
1811 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1812 sf_start_locked(ifp);
1813
1814 if (cmd == POLL_AND_CHECK_STATUS) {
1815 /* Reading the ISR register clears all interrrupts. */
1816 status = csr_read_4(sc, SF_ISR);
1817
1818 if ((status & SF_ISR_ABNORMALINTR) != 0) {
1819 if ((status & SF_ISR_STATSOFLOW) != 0)
1820 sf_stats_update(sc);
1821 else if ((status & SF_ISR_TX_LOFIFO) != 0)
1822 sf_txthresh_adjust(sc);
1823 else if ((status & SF_ISR_DMAERR) != 0) {
1824 device_printf(sc->sf_dev,
1825 "DMA error, resetting\n");
1826 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1827 sf_init_locked(sc);
1828 SF_UNLOCK(sc);
1829 return (rx_npkts);
1830 } else if ((status & SF_ISR_NO_TX_CSUM) != 0) {
1831 sc->sf_statistics.sf_tx_gfp_stall++;
1832 #ifdef SF_GFP_DEBUG
1833 device_printf(sc->sf_dev,
1834 "TxGFP is not responding!\n");
1835 #endif
1836 } else if ((status & SF_ISR_RXGFP_NORESP) != 0) {
1837 sc->sf_statistics.sf_rx_gfp_stall++;
1838 #ifdef SF_GFP_DEBUG
1839 device_printf(sc->sf_dev,
1840 "RxGFP is not responding!\n");
1841 #endif
1842 }
1843 }
1844 }
1845
1846 SF_UNLOCK(sc);
1847 return (rx_npkts);
1848 }
1849 #endif /* DEVICE_POLLING */
1850
1851 static void
sf_intr(void * arg)1852 sf_intr(void *arg)
1853 {
1854 struct sf_softc *sc;
1855 struct ifnet *ifp;
1856 uint32_t status;
1857 int cnt;
1858
1859 sc = (struct sf_softc *)arg;
1860 SF_LOCK(sc);
1861
1862 if (sc->sf_suspended != 0)
1863 goto done_locked;
1864
1865 /* Reading the ISR register clears all interrrupts. */
1866 status = csr_read_4(sc, SF_ISR);
1867 if (status == 0 || status == 0xffffffff ||
1868 (status & SF_ISR_PCIINT_ASSERTED) == 0)
1869 goto done_locked;
1870
1871 ifp = sc->sf_ifp;
1872 #ifdef DEVICE_POLLING
1873 if ((ifp->if_capenable & IFCAP_POLLING) != 0)
1874 goto done_locked;
1875 #endif
1876
1877 /* Disable interrupts. */
1878 csr_write_4(sc, SF_IMR, 0x00000000);
1879
1880 for (cnt = 32; (status & SF_INTRS) != 0;) {
1881 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1882 break;
1883 if ((status & SF_ISR_RXDQ1_DMADONE) != 0)
1884 sf_rxeof(sc);
1885
1886 if ((status & (SF_ISR_TX_TXDONE | SF_ISR_TX_DMADONE |
1887 SF_ISR_TX_QUEUEDONE)) != 0)
1888 sf_txeof(sc);
1889
1890 if ((status & SF_ISR_ABNORMALINTR) != 0) {
1891 if ((status & SF_ISR_STATSOFLOW) != 0)
1892 sf_stats_update(sc);
1893 else if ((status & SF_ISR_TX_LOFIFO) != 0)
1894 sf_txthresh_adjust(sc);
1895 else if ((status & SF_ISR_DMAERR) != 0) {
1896 device_printf(sc->sf_dev,
1897 "DMA error, resetting\n");
1898 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1899 sf_init_locked(sc);
1900 SF_UNLOCK(sc);
1901 return;
1902 } else if ((status & SF_ISR_NO_TX_CSUM) != 0) {
1903 sc->sf_statistics.sf_tx_gfp_stall++;
1904 #ifdef SF_GFP_DEBUG
1905 device_printf(sc->sf_dev,
1906 "TxGFP is not responding!\n");
1907 #endif
1908 }
1909 else if ((status & SF_ISR_RXGFP_NORESP) != 0) {
1910 sc->sf_statistics.sf_rx_gfp_stall++;
1911 #ifdef SF_GFP_DEBUG
1912 device_printf(sc->sf_dev,
1913 "RxGFP is not responding!\n");
1914 #endif
1915 }
1916 }
1917 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1918 sf_start_locked(ifp);
1919 if (--cnt <= 0)
1920 break;
1921 /* Reading the ISR register clears all interrrupts. */
1922 status = csr_read_4(sc, SF_ISR);
1923 }
1924
1925 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1926 /* Re-enable interrupts. */
1927 csr_write_4(sc, SF_IMR, SF_INTRS);
1928 }
1929
1930 done_locked:
1931 SF_UNLOCK(sc);
1932 }
1933
1934 static void
sf_download_fw(struct sf_softc * sc)1935 sf_download_fw(struct sf_softc *sc)
1936 {
1937 uint32_t gfpinst;
1938 int i, ndx;
1939 uint8_t *p;
1940
1941 /*
1942 * A FP instruction is composed of 48bits so we have to
1943 * write it with two parts.
1944 */
1945 p = txfwdata;
1946 ndx = 0;
1947 for (i = 0; i < sizeof(txfwdata) / SF_GFP_INST_BYTES; i++) {
1948 gfpinst = p[2] << 24 | p[3] << 16 | p[4] << 8 | p[5];
1949 csr_write_4(sc, SF_TXGFP_MEM_BASE + ndx * 4, gfpinst);
1950 gfpinst = p[0] << 8 | p[1];
1951 csr_write_4(sc, SF_TXGFP_MEM_BASE + (ndx + 1) * 4, gfpinst);
1952 p += SF_GFP_INST_BYTES;
1953 ndx += 2;
1954 }
1955 if (bootverbose)
1956 device_printf(sc->sf_dev, "%d Tx instructions downloaded\n", i);
1957
1958 p = rxfwdata;
1959 ndx = 0;
1960 for (i = 0; i < sizeof(rxfwdata) / SF_GFP_INST_BYTES; i++) {
1961 gfpinst = p[2] << 24 | p[3] << 16 | p[4] << 8 | p[5];
1962 csr_write_4(sc, SF_RXGFP_MEM_BASE + (ndx * 4), gfpinst);
1963 gfpinst = p[0] << 8 | p[1];
1964 csr_write_4(sc, SF_RXGFP_MEM_BASE + (ndx + 1) * 4, gfpinst);
1965 p += SF_GFP_INST_BYTES;
1966 ndx += 2;
1967 }
1968 if (bootverbose)
1969 device_printf(sc->sf_dev, "%d Rx instructions downloaded\n", i);
1970 }
1971
1972 static void
sf_init(void * xsc)1973 sf_init(void *xsc)
1974 {
1975 struct sf_softc *sc;
1976
1977 sc = (struct sf_softc *)xsc;
1978 SF_LOCK(sc);
1979 sf_init_locked(sc);
1980 SF_UNLOCK(sc);
1981 }
1982
1983 static void
sf_init_locked(struct sf_softc * sc)1984 sf_init_locked(struct sf_softc *sc)
1985 {
1986 struct ifnet *ifp;
1987 struct mii_data *mii;
1988 uint8_t eaddr[ETHER_ADDR_LEN];
1989 bus_addr_t addr;
1990 int i;
1991
1992 SF_LOCK_ASSERT(sc);
1993 ifp = sc->sf_ifp;
1994 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1995 return;
1996 mii = device_get_softc(sc->sf_miibus);
1997
1998 sf_stop(sc);
1999 /* Reset the hardware to a known state. */
2000 sf_reset(sc);
2001
2002 /* Init all the receive filter registers */
2003 for (i = SF_RXFILT_PERFECT_BASE;
2004 i < (SF_RXFILT_HASH_MAX + 1); i += sizeof(uint32_t))
2005 csr_write_4(sc, i, 0);
2006
2007 /* Empty stats counter registers. */
2008 for (i = SF_STATS_BASE; i < (SF_STATS_END + 1); i += sizeof(uint32_t))
2009 csr_write_4(sc, i, 0);
2010
2011 /* Init our MAC address. */
2012 bcopy(IF_LLADDR(sc->sf_ifp), eaddr, sizeof(eaddr));
2013 csr_write_4(sc, SF_PAR0,
2014 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]);
2015 csr_write_4(sc, SF_PAR1, eaddr[0] << 8 | eaddr[1]);
2016 sf_setperf(sc, 0, eaddr);
2017
2018 if (sf_init_rx_ring(sc) == ENOBUFS) {
2019 device_printf(sc->sf_dev,
2020 "initialization failed: no memory for rx buffers\n");
2021 sf_stop(sc);
2022 return;
2023 }
2024
2025 sf_init_tx_ring(sc);
2026
2027 /*
2028 * 16 perfect address filtering.
2029 * Hash only multicast destination address, Accept matching
2030 * frames regardless of VLAN ID.
2031 */
2032 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL | SF_HASHMODE_ANYVLAN);
2033
2034 /*
2035 * Set Rx filter.
2036 */
2037 sf_rxfilter(sc);
2038
2039 /* Init the completion queue indexes. */
2040 csr_write_4(sc, SF_CQ_CONSIDX, 0);
2041 csr_write_4(sc, SF_CQ_PRODIDX, 0);
2042
2043 /* Init the RX completion queue. */
2044 addr = sc->sf_rdata.sf_rx_cring_paddr;
2045 csr_write_4(sc, SF_CQ_ADDR_HI, SF_ADDR_HI(addr));
2046 csr_write_4(sc, SF_RXCQ_CTL_1, SF_ADDR_LO(addr) & SF_RXCQ_ADDR);
2047 if (SF_ADDR_HI(addr) != 0)
2048 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQ_USE_64BIT);
2049 /* Set RX completion queue type 2. */
2050 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_2);
2051 csr_write_4(sc, SF_RXCQ_CTL_2, 0);
2052
2053 /*
2054 * Init RX DMA control.
2055 * default RxHighPriority Threshold,
2056 * default RxBurstSize, 128bytes.
2057 */
2058 SF_SETBIT(sc, SF_RXDMA_CTL,
2059 SF_RXDMA_REPORTBADPKTS |
2060 (SF_RXDMA_HIGHPRIO_THRESH << 8) |
2061 SF_RXDMA_BURST);
2062
2063 /* Init the RX buffer descriptor queue. */
2064 addr = sc->sf_rdata.sf_rx_ring_paddr;
2065 csr_write_4(sc, SF_RXDQ_ADDR_HI, SF_ADDR_HI(addr));
2066 csr_write_4(sc, SF_RXDQ_ADDR_Q1, SF_ADDR_LO(addr));
2067
2068 /* Set RX queue buffer length. */
2069 csr_write_4(sc, SF_RXDQ_CTL_1,
2070 ((MCLBYTES - sizeof(uint32_t)) << 16) |
2071 SF_RXDQCTL_64BITBADDR | SF_RXDQCTL_VARIABLE);
2072
2073 if (SF_ADDR_HI(addr) != 0)
2074 SF_SETBIT(sc, SF_RXDQ_CTL_1, SF_RXDQCTL_64BITDADDR);
2075 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1);
2076 csr_write_4(sc, SF_RXDQ_CTL_2, 0);
2077
2078 /* Init the TX completion queue */
2079 addr = sc->sf_rdata.sf_tx_cring_paddr;
2080 csr_write_4(sc, SF_TXCQ_CTL, SF_ADDR_LO(addr) & SF_TXCQ_ADDR);
2081 if (SF_ADDR_HI(addr) != 0)
2082 SF_SETBIT(sc, SF_TXCQ_CTL, SF_TXCQ_USE_64BIT);
2083
2084 /* Init the TX buffer descriptor queue. */
2085 addr = sc->sf_rdata.sf_tx_ring_paddr;
2086 csr_write_4(sc, SF_TXDQ_ADDR_HI, SF_ADDR_HI(addr));
2087 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0);
2088 csr_write_4(sc, SF_TXDQ_ADDR_LOPRIO, SF_ADDR_LO(addr));
2089 csr_write_4(sc, SF_TX_FRAMCTL,
2090 SF_TXFRMCTL_CPLAFTERTX | sc->sf_txthresh);
2091 csr_write_4(sc, SF_TXDQ_CTL,
2092 SF_TXDMA_HIPRIO_THRESH << 24 |
2093 SF_TXSKIPLEN_0BYTES << 16 |
2094 SF_TXDDMA_BURST << 8 |
2095 SF_TXBUFDESC_TYPE2 | SF_TXMINSPACE_UNLIMIT);
2096 if (SF_ADDR_HI(addr) != 0)
2097 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_64BITADDR);
2098
2099 /* Set VLAN Type register. */
2100 csr_write_4(sc, SF_VLANTYPE, ETHERTYPE_VLAN);
2101
2102 /* Set TxPause Timer. */
2103 csr_write_4(sc, SF_TXPAUSETIMER, 0xffff);
2104
2105 /* Enable autopadding of short TX frames. */
2106 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD);
2107 SF_SETBIT(sc, SF_MACCFG_2, SF_MACCFG2_AUTOVLANPAD);
2108 /* Make sure to reset MAC to take changes effect. */
2109 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET);
2110 DELAY(1000);
2111 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET);
2112
2113 /* Enable PCI bus master. */
2114 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_PCIMEN);
2115
2116 /* Load StarFire firmware. */
2117 sf_download_fw(sc);
2118
2119 /* Intialize interrupt moderation. */
2120 csr_write_4(sc, SF_TIMER_CTL, SF_TIMER_IMASK_MODE | SF_TIMER_TIMES_TEN |
2121 (sc->sf_int_mod & SF_TIMER_IMASK_INTERVAL));
2122
2123 #ifdef DEVICE_POLLING
2124 /* Disable interrupts if we are polling. */
2125 if ((ifp->if_capenable & IFCAP_POLLING) != 0)
2126 csr_write_4(sc, SF_IMR, 0x00000000);
2127 else
2128 #endif
2129 /* Enable interrupts. */
2130 csr_write_4(sc, SF_IMR, SF_INTRS);
2131 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB);
2132
2133 /* Enable the RX and TX engines. */
2134 csr_write_4(sc, SF_GEN_ETH_CTL,
2135 SF_ETHCTL_RX_ENB | SF_ETHCTL_RXDMA_ENB |
2136 SF_ETHCTL_TX_ENB | SF_ETHCTL_TXDMA_ENB);
2137
2138 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
2139 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TXGFP_ENB);
2140 else
2141 SF_CLRBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TXGFP_ENB);
2142 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
2143 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RXGFP_ENB);
2144 else
2145 SF_CLRBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RXGFP_ENB);
2146
2147 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2148 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2149
2150 sc->sf_link = 0;
2151 sf_ifmedia_upd_locked(ifp);
2152
2153 callout_reset(&sc->sf_co, hz, sf_tick, sc);
2154 }
2155
2156 static int
sf_encap(struct sf_softc * sc,struct mbuf ** m_head)2157 sf_encap(struct sf_softc *sc, struct mbuf **m_head)
2158 {
2159 struct sf_txdesc *txd;
2160 struct sf_tx_rdesc *desc;
2161 struct mbuf *m;
2162 bus_dmamap_t map;
2163 bus_dma_segment_t txsegs[SF_MAXTXSEGS];
2164 int error, i, nsegs, prod, si;
2165 int avail, nskip;
2166
2167 SF_LOCK_ASSERT(sc);
2168
2169 m = *m_head;
2170 prod = sc->sf_cdata.sf_tx_prod;
2171 txd = &sc->sf_cdata.sf_txdesc[prod];
2172 map = txd->tx_dmamap;
2173 error = bus_dmamap_load_mbuf_sg(sc->sf_cdata.sf_tx_tag, map,
2174 *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT);
2175 if (error == EFBIG) {
2176 m = m_collapse(*m_head, M_NOWAIT, SF_MAXTXSEGS);
2177 if (m == NULL) {
2178 m_freem(*m_head);
2179 *m_head = NULL;
2180 return (ENOBUFS);
2181 }
2182 *m_head = m;
2183 error = bus_dmamap_load_mbuf_sg(sc->sf_cdata.sf_tx_tag,
2184 map, *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT);
2185 if (error != 0) {
2186 m_freem(*m_head);
2187 *m_head = NULL;
2188 return (error);
2189 }
2190 } else if (error != 0)
2191 return (error);
2192 if (nsegs == 0) {
2193 m_freem(*m_head);
2194 *m_head = NULL;
2195 return (EIO);
2196 }
2197
2198 /* Check number of available descriptors. */
2199 avail = (SF_TX_DLIST_CNT - 1) - sc->sf_cdata.sf_tx_cnt;
2200 if (avail < nsegs) {
2201 bus_dmamap_unload(sc->sf_cdata.sf_tx_tag, map);
2202 return (ENOBUFS);
2203 }
2204 nskip = 0;
2205 if (prod + nsegs >= SF_TX_DLIST_CNT) {
2206 nskip = SF_TX_DLIST_CNT - prod - 1;
2207 if (avail < nsegs + nskip) {
2208 bus_dmamap_unload(sc->sf_cdata.sf_tx_tag, map);
2209 return (ENOBUFS);
2210 }
2211 }
2212
2213 bus_dmamap_sync(sc->sf_cdata.sf_tx_tag, map, BUS_DMASYNC_PREWRITE);
2214
2215 si = prod;
2216 for (i = 0; i < nsegs; i++) {
2217 desc = &sc->sf_rdata.sf_tx_ring[prod];
2218 desc->sf_tx_ctrl = htole32(SF_TX_DESC_ID |
2219 (txsegs[i].ds_len & SF_TX_DESC_FRAGLEN));
2220 desc->sf_tx_reserved = 0;
2221 desc->sf_addr = htole64(txsegs[i].ds_addr);
2222 if (i == 0 && prod + nsegs >= SF_TX_DLIST_CNT) {
2223 /* Queue wraps! */
2224 desc->sf_tx_ctrl |= htole32(SF_TX_DESC_END);
2225 prod = 0;
2226 } else
2227 SF_INC(prod, SF_TX_DLIST_CNT);
2228 }
2229 /* Update producer index. */
2230 sc->sf_cdata.sf_tx_prod = prod;
2231 sc->sf_cdata.sf_tx_cnt += nsegs + nskip;
2232
2233 desc = &sc->sf_rdata.sf_tx_ring[si];
2234 /* Check TDP/UDP checksum offload request. */
2235 if ((m->m_pkthdr.csum_flags & SF_CSUM_FEATURES) != 0)
2236 desc->sf_tx_ctrl |= htole32(SF_TX_DESC_CALTCP);
2237 desc->sf_tx_ctrl |=
2238 htole32(SF_TX_DESC_CRCEN | SF_TX_DESC_INTR | (nsegs << 16));
2239
2240 txd->tx_dmamap = map;
2241 txd->tx_m = m;
2242 txd->ndesc = nsegs + nskip;
2243
2244 return (0);
2245 }
2246
2247 static void
sf_start(struct ifnet * ifp)2248 sf_start(struct ifnet *ifp)
2249 {
2250 struct sf_softc *sc;
2251
2252 sc = ifp->if_softc;
2253 SF_LOCK(sc);
2254 sf_start_locked(ifp);
2255 SF_UNLOCK(sc);
2256 }
2257
2258 static void
sf_start_locked(struct ifnet * ifp)2259 sf_start_locked(struct ifnet *ifp)
2260 {
2261 struct sf_softc *sc;
2262 struct mbuf *m_head;
2263 int enq;
2264
2265 sc = ifp->if_softc;
2266 SF_LOCK_ASSERT(sc);
2267
2268 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2269 IFF_DRV_RUNNING || sc->sf_link == 0)
2270 return;
2271
2272 /*
2273 * Since we don't know when descriptor wrap occurrs in advance
2274 * limit available number of active Tx descriptor counter to be
2275 * higher than maximum number of DMA segments allowed in driver.
2276 */
2277 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2278 sc->sf_cdata.sf_tx_cnt < SF_TX_DLIST_CNT - SF_MAXTXSEGS; ) {
2279 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2280 if (m_head == NULL)
2281 break;
2282 /*
2283 * Pack the data into the transmit ring. If we
2284 * don't have room, set the OACTIVE flag and wait
2285 * for the NIC to drain the ring.
2286 */
2287 if (sf_encap(sc, &m_head)) {
2288 if (m_head == NULL)
2289 break;
2290 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2291 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2292 break;
2293 }
2294
2295 enq++;
2296 /*
2297 * If there's a BPF listener, bounce a copy of this frame
2298 * to him.
2299 */
2300 ETHER_BPF_MTAP(ifp, m_head);
2301 }
2302
2303 if (enq > 0) {
2304 bus_dmamap_sync(sc->sf_cdata.sf_tx_ring_tag,
2305 sc->sf_cdata.sf_tx_ring_map,
2306 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2307 /* Kick transmit. */
2308 csr_write_4(sc, SF_TXDQ_PRODIDX,
2309 sc->sf_cdata.sf_tx_prod * (sizeof(struct sf_tx_rdesc) / 8));
2310
2311 /* Set a timeout in case the chip goes out to lunch. */
2312 sc->sf_watchdog_timer = 5;
2313 }
2314 }
2315
2316 static void
sf_stop(struct sf_softc * sc)2317 sf_stop(struct sf_softc *sc)
2318 {
2319 struct sf_txdesc *txd;
2320 struct sf_rxdesc *rxd;
2321 struct ifnet *ifp;
2322 int i;
2323
2324 SF_LOCK_ASSERT(sc);
2325
2326 ifp = sc->sf_ifp;
2327
2328 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2329 sc->sf_link = 0;
2330 callout_stop(&sc->sf_co);
2331 sc->sf_watchdog_timer = 0;
2332
2333 /* Reading the ISR register clears all interrrupts. */
2334 csr_read_4(sc, SF_ISR);
2335 /* Disable further interrupts. */
2336 csr_write_4(sc, SF_IMR, 0);
2337
2338 /* Disable Tx/Rx egine. */
2339 csr_write_4(sc, SF_GEN_ETH_CTL, 0);
2340
2341 /* Give hardware chance to drain active DMA cycles. */
2342 DELAY(1000);
2343
2344 csr_write_4(sc, SF_CQ_CONSIDX, 0);
2345 csr_write_4(sc, SF_CQ_PRODIDX, 0);
2346 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0);
2347 csr_write_4(sc, SF_RXDQ_CTL_1, 0);
2348 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0);
2349 csr_write_4(sc, SF_TXCQ_CTL, 0);
2350 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0);
2351 csr_write_4(sc, SF_TXDQ_CTL, 0);
2352
2353 /*
2354 * Free RX and TX mbufs still in the queues.
2355 */
2356 for (i = 0; i < SF_RX_DLIST_CNT; i++) {
2357 rxd = &sc->sf_cdata.sf_rxdesc[i];
2358 if (rxd->rx_m != NULL) {
2359 bus_dmamap_sync(sc->sf_cdata.sf_rx_tag,
2360 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
2361 bus_dmamap_unload(sc->sf_cdata.sf_rx_tag,
2362 rxd->rx_dmamap);
2363 m_freem(rxd->rx_m);
2364 rxd->rx_m = NULL;
2365 }
2366 }
2367 for (i = 0; i < SF_TX_DLIST_CNT; i++) {
2368 txd = &sc->sf_cdata.sf_txdesc[i];
2369 if (txd->tx_m != NULL) {
2370 bus_dmamap_sync(sc->sf_cdata.sf_tx_tag,
2371 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2372 bus_dmamap_unload(sc->sf_cdata.sf_tx_tag,
2373 txd->tx_dmamap);
2374 m_freem(txd->tx_m);
2375 txd->tx_m = NULL;
2376 txd->ndesc = 0;
2377 }
2378 }
2379 }
2380
2381 static void
sf_tick(void * xsc)2382 sf_tick(void *xsc)
2383 {
2384 struct sf_softc *sc;
2385 struct mii_data *mii;
2386
2387 sc = xsc;
2388 SF_LOCK_ASSERT(sc);
2389 mii = device_get_softc(sc->sf_miibus);
2390 mii_tick(mii);
2391 sf_stats_update(sc);
2392 sf_watchdog(sc);
2393 callout_reset(&sc->sf_co, hz, sf_tick, sc);
2394 }
2395
2396 /*
2397 * Note: it is important that this function not be interrupted. We
2398 * use a two-stage register access scheme: if we are interrupted in
2399 * between setting the indirect address register and reading from the
2400 * indirect data register, the contents of the address register could
2401 * be changed out from under us.
2402 */
2403 static void
sf_stats_update(struct sf_softc * sc)2404 sf_stats_update(struct sf_softc *sc)
2405 {
2406 struct ifnet *ifp;
2407 struct sf_stats now, *stats, *nstats;
2408 int i;
2409
2410 SF_LOCK_ASSERT(sc);
2411
2412 ifp = sc->sf_ifp;
2413 stats = &now;
2414
2415 stats->sf_tx_frames =
2416 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_FRAMES);
2417 stats->sf_tx_single_colls =
2418 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_SINGLE_COL);
2419 stats->sf_tx_multi_colls =
2420 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_MULTI_COL);
2421 stats->sf_tx_crcerrs =
2422 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_CRC_ERRS);
2423 stats->sf_tx_bytes =
2424 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_BYTES);
2425 stats->sf_tx_deferred =
2426 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_DEFERRED);
2427 stats->sf_tx_late_colls =
2428 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_LATE_COL);
2429 stats->sf_tx_pause_frames =
2430 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_PAUSE);
2431 stats->sf_tx_control_frames =
2432 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_CTL_FRAME);
2433 stats->sf_tx_excess_colls =
2434 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_EXCESS_COL);
2435 stats->sf_tx_excess_defer =
2436 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_EXCESS_DEF);
2437 stats->sf_tx_mcast_frames =
2438 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_MULTI);
2439 stats->sf_tx_bcast_frames =
2440 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_BCAST);
2441 stats->sf_tx_frames_lost =
2442 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_FRAME_LOST);
2443 stats->sf_rx_frames =
2444 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_FRAMES);
2445 stats->sf_rx_crcerrs =
2446 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_CRC_ERRS);
2447 stats->sf_rx_alignerrs =
2448 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_ALIGN_ERRS);
2449 stats->sf_rx_bytes =
2450 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_BYTES);
2451 stats->sf_rx_pause_frames =
2452 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_PAUSE);
2453 stats->sf_rx_control_frames =
2454 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_CTL_FRAME);
2455 stats->sf_rx_unsup_control_frames =
2456 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_UNSUP_FRAME);
2457 stats->sf_rx_giants =
2458 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_GIANTS);
2459 stats->sf_rx_runts =
2460 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_RUNTS);
2461 stats->sf_rx_jabbererrs =
2462 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_JABBER);
2463 stats->sf_rx_fragments =
2464 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_FRAGMENTS);
2465 stats->sf_rx_pkts_64 =
2466 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_64);
2467 stats->sf_rx_pkts_65_127 =
2468 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_65_127);
2469 stats->sf_rx_pkts_128_255 =
2470 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_128_255);
2471 stats->sf_rx_pkts_256_511 =
2472 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_256_511);
2473 stats->sf_rx_pkts_512_1023 =
2474 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_512_1023);
2475 stats->sf_rx_pkts_1024_1518 =
2476 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_1024_1518);
2477 stats->sf_rx_frames_lost =
2478 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_FRAME_LOST);
2479 /* Lower 16bits are valid. */
2480 stats->sf_tx_underruns =
2481 (csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_UNDERRUN) & 0xffff);
2482
2483 /* Empty stats counter registers. */
2484 for (i = SF_STATS_BASE; i < (SF_STATS_END + 1); i += sizeof(uint32_t))
2485 csr_write_4(sc, i, 0);
2486
2487 ifp->if_opackets += (u_long)stats->sf_tx_frames;
2488
2489 ifp->if_collisions += (u_long)stats->sf_tx_single_colls +
2490 (u_long)stats->sf_tx_multi_colls;
2491
2492 ifp->if_oerrors += (u_long)stats->sf_tx_excess_colls +
2493 (u_long)stats->sf_tx_excess_defer +
2494 (u_long)stats->sf_tx_frames_lost;
2495
2496 ifp->if_ipackets += (u_long)stats->sf_rx_frames;
2497
2498 ifp->if_ierrors += (u_long)stats->sf_rx_crcerrs +
2499 (u_long)stats->sf_rx_alignerrs +
2500 (u_long)stats->sf_rx_giants +
2501 (u_long)stats->sf_rx_runts +
2502 (u_long)stats->sf_rx_jabbererrs +
2503 (u_long)stats->sf_rx_frames_lost;
2504
2505 nstats = &sc->sf_statistics;
2506
2507 nstats->sf_tx_frames += stats->sf_tx_frames;
2508 nstats->sf_tx_single_colls += stats->sf_tx_single_colls;
2509 nstats->sf_tx_multi_colls += stats->sf_tx_multi_colls;
2510 nstats->sf_tx_crcerrs += stats->sf_tx_crcerrs;
2511 nstats->sf_tx_bytes += stats->sf_tx_bytes;
2512 nstats->sf_tx_deferred += stats->sf_tx_deferred;
2513 nstats->sf_tx_late_colls += stats->sf_tx_late_colls;
2514 nstats->sf_tx_pause_frames += stats->sf_tx_pause_frames;
2515 nstats->sf_tx_control_frames += stats->sf_tx_control_frames;
2516 nstats->sf_tx_excess_colls += stats->sf_tx_excess_colls;
2517 nstats->sf_tx_excess_defer += stats->sf_tx_excess_defer;
2518 nstats->sf_tx_mcast_frames += stats->sf_tx_mcast_frames;
2519 nstats->sf_tx_bcast_frames += stats->sf_tx_bcast_frames;
2520 nstats->sf_tx_frames_lost += stats->sf_tx_frames_lost;
2521 nstats->sf_rx_frames += stats->sf_rx_frames;
2522 nstats->sf_rx_crcerrs += stats->sf_rx_crcerrs;
2523 nstats->sf_rx_alignerrs += stats->sf_rx_alignerrs;
2524 nstats->sf_rx_bytes += stats->sf_rx_bytes;
2525 nstats->sf_rx_pause_frames += stats->sf_rx_pause_frames;
2526 nstats->sf_rx_control_frames += stats->sf_rx_control_frames;
2527 nstats->sf_rx_unsup_control_frames += stats->sf_rx_unsup_control_frames;
2528 nstats->sf_rx_giants += stats->sf_rx_giants;
2529 nstats->sf_rx_runts += stats->sf_rx_runts;
2530 nstats->sf_rx_jabbererrs += stats->sf_rx_jabbererrs;
2531 nstats->sf_rx_fragments += stats->sf_rx_fragments;
2532 nstats->sf_rx_pkts_64 += stats->sf_rx_pkts_64;
2533 nstats->sf_rx_pkts_65_127 += stats->sf_rx_pkts_65_127;
2534 nstats->sf_rx_pkts_128_255 += stats->sf_rx_pkts_128_255;
2535 nstats->sf_rx_pkts_256_511 += stats->sf_rx_pkts_256_511;
2536 nstats->sf_rx_pkts_512_1023 += stats->sf_rx_pkts_512_1023;
2537 nstats->sf_rx_pkts_1024_1518 += stats->sf_rx_pkts_1024_1518;
2538 nstats->sf_rx_frames_lost += stats->sf_rx_frames_lost;
2539 nstats->sf_tx_underruns += stats->sf_tx_underruns;
2540 }
2541
2542 static void
sf_watchdog(struct sf_softc * sc)2543 sf_watchdog(struct sf_softc *sc)
2544 {
2545 struct ifnet *ifp;
2546
2547 SF_LOCK_ASSERT(sc);
2548
2549 if (sc->sf_watchdog_timer == 0 || --sc->sf_watchdog_timer)
2550 return;
2551
2552 ifp = sc->sf_ifp;
2553
2554 ifp->if_oerrors++;
2555 if (sc->sf_link == 0) {
2556 if (bootverbose)
2557 if_printf(sc->sf_ifp, "watchdog timeout "
2558 "(missed link)\n");
2559 } else
2560 if_printf(ifp, "watchdog timeout, %d Tx descs are active\n",
2561 sc->sf_cdata.sf_tx_cnt);
2562
2563 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2564 sf_init_locked(sc);
2565
2566 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2567 sf_start_locked(ifp);
2568 }
2569
2570 static int
sf_shutdown(device_t dev)2571 sf_shutdown(device_t dev)
2572 {
2573 struct sf_softc *sc;
2574
2575 sc = device_get_softc(dev);
2576
2577 SF_LOCK(sc);
2578 sf_stop(sc);
2579 SF_UNLOCK(sc);
2580
2581 return (0);
2582 }
2583
2584 static int
sf_suspend(device_t dev)2585 sf_suspend(device_t dev)
2586 {
2587 struct sf_softc *sc;
2588
2589 sc = device_get_softc(dev);
2590
2591 SF_LOCK(sc);
2592 sf_stop(sc);
2593 sc->sf_suspended = 1;
2594 bus_generic_suspend(dev);
2595 SF_UNLOCK(sc);
2596
2597 return (0);
2598 }
2599
2600 static int
sf_resume(device_t dev)2601 sf_resume(device_t dev)
2602 {
2603 struct sf_softc *sc;
2604 struct ifnet *ifp;
2605
2606 sc = device_get_softc(dev);
2607
2608 SF_LOCK(sc);
2609 bus_generic_resume(dev);
2610 ifp = sc->sf_ifp;
2611 if ((ifp->if_flags & IFF_UP) != 0)
2612 sf_init_locked(sc);
2613
2614 sc->sf_suspended = 0;
2615 SF_UNLOCK(sc);
2616
2617 return (0);
2618 }
2619
2620 static int
sf_sysctl_stats(SYSCTL_HANDLER_ARGS)2621 sf_sysctl_stats(SYSCTL_HANDLER_ARGS)
2622 {
2623 struct sf_softc *sc;
2624 struct sf_stats *stats;
2625 int error;
2626 int result;
2627
2628 result = -1;
2629 error = sysctl_handle_int(oidp, &result, 0, req);
2630
2631 if (error != 0 || req->newptr == NULL)
2632 return (error);
2633
2634 if (result != 1)
2635 return (error);
2636
2637 sc = (struct sf_softc *)arg1;
2638 stats = &sc->sf_statistics;
2639
2640 printf("%s statistics:\n", device_get_nameunit(sc->sf_dev));
2641 printf("Transmit good frames : %ju\n",
2642 (uintmax_t)stats->sf_tx_frames);
2643 printf("Transmit good octets : %ju\n",
2644 (uintmax_t)stats->sf_tx_bytes);
2645 printf("Transmit single collisions : %u\n",
2646 stats->sf_tx_single_colls);
2647 printf("Transmit multiple collisions : %u\n",
2648 stats->sf_tx_multi_colls);
2649 printf("Transmit late collisions : %u\n",
2650 stats->sf_tx_late_colls);
2651 printf("Transmit abort due to excessive collisions : %u\n",
2652 stats->sf_tx_excess_colls);
2653 printf("Transmit CRC errors : %u\n",
2654 stats->sf_tx_crcerrs);
2655 printf("Transmit deferrals : %u\n",
2656 stats->sf_tx_deferred);
2657 printf("Transmit abort due to excessive deferrals : %u\n",
2658 stats->sf_tx_excess_defer);
2659 printf("Transmit pause control frames : %u\n",
2660 stats->sf_tx_pause_frames);
2661 printf("Transmit control frames : %u\n",
2662 stats->sf_tx_control_frames);
2663 printf("Transmit good multicast frames : %u\n",
2664 stats->sf_tx_mcast_frames);
2665 printf("Transmit good broadcast frames : %u\n",
2666 stats->sf_tx_bcast_frames);
2667 printf("Transmit frames lost due to internal transmit errors : %u\n",
2668 stats->sf_tx_frames_lost);
2669 printf("Transmit FIFO underflows : %u\n",
2670 stats->sf_tx_underruns);
2671 printf("Transmit GFP stalls : %u\n", stats->sf_tx_gfp_stall);
2672 printf("Receive good frames : %ju\n",
2673 (uint64_t)stats->sf_rx_frames);
2674 printf("Receive good octets : %ju\n",
2675 (uint64_t)stats->sf_rx_bytes);
2676 printf("Receive CRC errors : %u\n",
2677 stats->sf_rx_crcerrs);
2678 printf("Receive alignment errors : %u\n",
2679 stats->sf_rx_alignerrs);
2680 printf("Receive pause frames : %u\n",
2681 stats->sf_rx_pause_frames);
2682 printf("Receive control frames : %u\n",
2683 stats->sf_rx_control_frames);
2684 printf("Receive control frames with unsupported opcode : %u\n",
2685 stats->sf_rx_unsup_control_frames);
2686 printf("Receive frames too long : %u\n",
2687 stats->sf_rx_giants);
2688 printf("Receive frames too short : %u\n",
2689 stats->sf_rx_runts);
2690 printf("Receive frames jabber errors : %u\n",
2691 stats->sf_rx_jabbererrs);
2692 printf("Receive frames fragments : %u\n",
2693 stats->sf_rx_fragments);
2694 printf("Receive packets 64 bytes : %ju\n",
2695 (uint64_t)stats->sf_rx_pkts_64);
2696 printf("Receive packets 65 to 127 bytes : %ju\n",
2697 (uint64_t)stats->sf_rx_pkts_65_127);
2698 printf("Receive packets 128 to 255 bytes : %ju\n",
2699 (uint64_t)stats->sf_rx_pkts_128_255);
2700 printf("Receive packets 256 to 511 bytes : %ju\n",
2701 (uint64_t)stats->sf_rx_pkts_256_511);
2702 printf("Receive packets 512 to 1023 bytes : %ju\n",
2703 (uint64_t)stats->sf_rx_pkts_512_1023);
2704 printf("Receive packets 1024 to 1518 bytes : %ju\n",
2705 (uint64_t)stats->sf_rx_pkts_1024_1518);
2706 printf("Receive frames lost due to internal receive errors : %u\n",
2707 stats->sf_rx_frames_lost);
2708 printf("Receive GFP stalls : %u\n", stats->sf_rx_gfp_stall);
2709
2710 return (error);
2711 }
2712
2713 static int
sysctl_int_range(SYSCTL_HANDLER_ARGS,int low,int high)2714 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
2715 {
2716 int error, value;
2717
2718 if (!arg1)
2719 return (EINVAL);
2720 value = *(int *)arg1;
2721 error = sysctl_handle_int(oidp, &value, 0, req);
2722 if (error || !req->newptr)
2723 return (error);
2724 if (value < low || value > high)
2725 return (EINVAL);
2726 *(int *)arg1 = value;
2727
2728 return (0);
2729 }
2730
2731 static int
sysctl_hw_sf_int_mod(SYSCTL_HANDLER_ARGS)2732 sysctl_hw_sf_int_mod(SYSCTL_HANDLER_ARGS)
2733 {
2734
2735 return (sysctl_int_range(oidp, arg1, arg2, req, SF_IM_MIN, SF_IM_MAX));
2736 }
2737