1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD: stable/9/sys/dev/drm2/radeon/radeon_asic.c 254885 2013-08-25 19:37:15Z dumbbell $");
31
32 #include <dev/drm2/drmP.h>
33 #include <dev/drm2/drm_crtc_helper.h>
34 #include <dev/drm2/radeon/radeon_drm.h>
35 #include "radeon_reg.h"
36 #include "radeon.h"
37 #include "radeon_asic.h"
38 #include "atom.h"
39
40 /*
41 * Registers accessors functions.
42 */
43 /**
44 * radeon_invalid_rreg - dummy reg read function
45 *
46 * @rdev: radeon device pointer
47 * @reg: offset of register
48 *
49 * Dummy register read function. Used for register blocks
50 * that certain asics don't have (all asics).
51 * Returns the value in the register.
52 */
radeon_invalid_rreg(struct radeon_device * rdev,uint32_t reg)53 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
54 {
55 panic("Invalid callback to read register 0x%04X\n", reg);
56 return 0;
57 }
58
59 /**
60 * radeon_invalid_wreg - dummy reg write function
61 *
62 * @rdev: radeon device pointer
63 * @reg: offset of register
64 * @v: value to write to the register
65 *
66 * Dummy register read function. Used for register blocks
67 * that certain asics don't have (all asics).
68 */
radeon_invalid_wreg(struct radeon_device * rdev,uint32_t reg,uint32_t v)69 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
70 {
71 panic("Invalid callback to write register 0x%04X with 0x%08X\n",
72 reg, v);
73 }
74
75 /**
76 * radeon_register_accessor_init - sets up the register accessor callbacks
77 *
78 * @rdev: radeon device pointer
79 *
80 * Sets up the register accessor callbacks for various register
81 * apertures. Not all asics have all apertures (all asics).
82 */
radeon_register_accessor_init(struct radeon_device * rdev)83 static void radeon_register_accessor_init(struct radeon_device *rdev)
84 {
85 rdev->mc_rreg = &radeon_invalid_rreg;
86 rdev->mc_wreg = &radeon_invalid_wreg;
87 rdev->pll_rreg = &radeon_invalid_rreg;
88 rdev->pll_wreg = &radeon_invalid_wreg;
89 rdev->pciep_rreg = &radeon_invalid_rreg;
90 rdev->pciep_wreg = &radeon_invalid_wreg;
91
92 /* Don't change order as we are overridding accessor. */
93 if (rdev->family < CHIP_RV515) {
94 rdev->pcie_reg_mask = 0xff;
95 } else {
96 rdev->pcie_reg_mask = 0x7ff;
97 }
98 /* FIXME: not sure here */
99 if (rdev->family <= CHIP_R580) {
100 rdev->pll_rreg = &r100_pll_rreg;
101 rdev->pll_wreg = &r100_pll_wreg;
102 }
103 if (rdev->family >= CHIP_R420) {
104 rdev->mc_rreg = &r420_mc_rreg;
105 rdev->mc_wreg = &r420_mc_wreg;
106 }
107 if (rdev->family >= CHIP_RV515) {
108 rdev->mc_rreg = &rv515_mc_rreg;
109 rdev->mc_wreg = &rv515_mc_wreg;
110 }
111 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
112 rdev->mc_rreg = &rs400_mc_rreg;
113 rdev->mc_wreg = &rs400_mc_wreg;
114 }
115 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
116 rdev->mc_rreg = &rs690_mc_rreg;
117 rdev->mc_wreg = &rs690_mc_wreg;
118 }
119 if (rdev->family == CHIP_RS600) {
120 rdev->mc_rreg = &rs600_mc_rreg;
121 rdev->mc_wreg = &rs600_mc_wreg;
122 }
123 if (rdev->family >= CHIP_R600) {
124 rdev->pciep_rreg = &r600_pciep_rreg;
125 rdev->pciep_wreg = &r600_pciep_wreg;
126 }
127 }
128
129
130 /* helper to disable agp */
131 /**
132 * radeon_agp_disable - AGP disable helper function
133 *
134 * @rdev: radeon device pointer
135 *
136 * Removes AGP flags and changes the gart callbacks on AGP
137 * cards when using the internal gart rather than AGP (all asics).
138 */
radeon_agp_disable(struct radeon_device * rdev)139 void radeon_agp_disable(struct radeon_device *rdev)
140 {
141 rdev->flags &= ~RADEON_IS_AGP;
142 if (rdev->family >= CHIP_R600) {
143 DRM_INFO("Forcing AGP to PCIE mode\n");
144 rdev->flags |= RADEON_IS_PCIE;
145 } else if (rdev->family >= CHIP_RV515 ||
146 rdev->family == CHIP_RV380 ||
147 rdev->family == CHIP_RV410 ||
148 rdev->family == CHIP_R423) {
149 DRM_INFO("Forcing AGP to PCIE mode\n");
150 rdev->flags |= RADEON_IS_PCIE;
151 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
152 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
153 } else {
154 DRM_INFO("Forcing AGP to PCI mode\n");
155 rdev->flags |= RADEON_IS_PCI;
156 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
157 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
158 }
159 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
160 }
161
162 /*
163 * ASIC
164 */
165 static struct radeon_asic r100_asic = {
166 .init = &r100_init,
167 .fini = &r100_fini,
168 .suspend = &r100_suspend,
169 .resume = &r100_resume,
170 .vga_set_state = &r100_vga_set_state,
171 .asic_reset = &r100_asic_reset,
172 .ioctl_wait_idle = NULL,
173 .gui_idle = &r100_gui_idle,
174 .mc_wait_for_idle = &r100_mc_wait_for_idle,
175 .gart = {
176 .tlb_flush = &r100_pci_gart_tlb_flush,
177 .set_page = &r100_pci_gart_set_page,
178 },
179 .ring = {
180 [RADEON_RING_TYPE_GFX_INDEX] = {
181 .ib_execute = &r100_ring_ib_execute,
182 .emit_fence = &r100_fence_ring_emit,
183 .emit_semaphore = &r100_semaphore_ring_emit,
184 .cs_parse = &r100_cs_parse,
185 .ring_start = &r100_ring_start,
186 .ring_test = &r100_ring_test,
187 .ib_test = &r100_ib_test,
188 .is_lockup = &r100_gpu_is_lockup,
189 }
190 },
191 .irq = {
192 .set = &r100_irq_set,
193 .process = &r100_irq_process,
194 },
195 .display = {
196 .bandwidth_update = &r100_bandwidth_update,
197 .get_vblank_counter = &r100_get_vblank_counter,
198 .wait_for_vblank = &r100_wait_for_vblank,
199 .set_backlight_level = &radeon_legacy_set_backlight_level,
200 .get_backlight_level = &radeon_legacy_get_backlight_level,
201 },
202 .copy = {
203 .blit = &r100_copy_blit,
204 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
205 .dma = NULL,
206 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
207 .copy = &r100_copy_blit,
208 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
209 },
210 .surface = {
211 .set_reg = r100_set_surface_reg,
212 .clear_reg = r100_clear_surface_reg,
213 },
214 .hpd = {
215 .init = &r100_hpd_init,
216 .fini = &r100_hpd_fini,
217 .sense = &r100_hpd_sense,
218 .set_polarity = &r100_hpd_set_polarity,
219 },
220 .pm = {
221 .misc = &r100_pm_misc,
222 .prepare = &r100_pm_prepare,
223 .finish = &r100_pm_finish,
224 .init_profile = &r100_pm_init_profile,
225 .get_dynpm_state = &r100_pm_get_dynpm_state,
226 .get_engine_clock = &radeon_legacy_get_engine_clock,
227 .set_engine_clock = &radeon_legacy_set_engine_clock,
228 .get_memory_clock = &radeon_legacy_get_memory_clock,
229 .set_memory_clock = NULL,
230 .get_pcie_lanes = NULL,
231 .set_pcie_lanes = NULL,
232 .set_clock_gating = &radeon_legacy_set_clock_gating,
233 },
234 .pflip = {
235 .pre_page_flip = &r100_pre_page_flip,
236 .page_flip = &r100_page_flip,
237 .post_page_flip = &r100_post_page_flip,
238 },
239 };
240
241 static struct radeon_asic r200_asic = {
242 .init = &r100_init,
243 .fini = &r100_fini,
244 .suspend = &r100_suspend,
245 .resume = &r100_resume,
246 .vga_set_state = &r100_vga_set_state,
247 .asic_reset = &r100_asic_reset,
248 .ioctl_wait_idle = NULL,
249 .gui_idle = &r100_gui_idle,
250 .mc_wait_for_idle = &r100_mc_wait_for_idle,
251 .gart = {
252 .tlb_flush = &r100_pci_gart_tlb_flush,
253 .set_page = &r100_pci_gart_set_page,
254 },
255 .ring = {
256 [RADEON_RING_TYPE_GFX_INDEX] = {
257 .ib_execute = &r100_ring_ib_execute,
258 .emit_fence = &r100_fence_ring_emit,
259 .emit_semaphore = &r100_semaphore_ring_emit,
260 .cs_parse = &r100_cs_parse,
261 .ring_start = &r100_ring_start,
262 .ring_test = &r100_ring_test,
263 .ib_test = &r100_ib_test,
264 .is_lockup = &r100_gpu_is_lockup,
265 }
266 },
267 .irq = {
268 .set = &r100_irq_set,
269 .process = &r100_irq_process,
270 },
271 .display = {
272 .bandwidth_update = &r100_bandwidth_update,
273 .get_vblank_counter = &r100_get_vblank_counter,
274 .wait_for_vblank = &r100_wait_for_vblank,
275 .set_backlight_level = &radeon_legacy_set_backlight_level,
276 .get_backlight_level = &radeon_legacy_get_backlight_level,
277 },
278 .copy = {
279 .blit = &r100_copy_blit,
280 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
281 .dma = &r200_copy_dma,
282 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
283 .copy = &r100_copy_blit,
284 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
285 },
286 .surface = {
287 .set_reg = r100_set_surface_reg,
288 .clear_reg = r100_clear_surface_reg,
289 },
290 .hpd = {
291 .init = &r100_hpd_init,
292 .fini = &r100_hpd_fini,
293 .sense = &r100_hpd_sense,
294 .set_polarity = &r100_hpd_set_polarity,
295 },
296 .pm = {
297 .misc = &r100_pm_misc,
298 .prepare = &r100_pm_prepare,
299 .finish = &r100_pm_finish,
300 .init_profile = &r100_pm_init_profile,
301 .get_dynpm_state = &r100_pm_get_dynpm_state,
302 .get_engine_clock = &radeon_legacy_get_engine_clock,
303 .set_engine_clock = &radeon_legacy_set_engine_clock,
304 .get_memory_clock = &radeon_legacy_get_memory_clock,
305 .set_memory_clock = NULL,
306 .get_pcie_lanes = NULL,
307 .set_pcie_lanes = NULL,
308 .set_clock_gating = &radeon_legacy_set_clock_gating,
309 },
310 .pflip = {
311 .pre_page_flip = &r100_pre_page_flip,
312 .page_flip = &r100_page_flip,
313 .post_page_flip = &r100_post_page_flip,
314 },
315 };
316
317 static struct radeon_asic r300_asic = {
318 .init = &r300_init,
319 .fini = &r300_fini,
320 .suspend = &r300_suspend,
321 .resume = &r300_resume,
322 .vga_set_state = &r100_vga_set_state,
323 .asic_reset = &r300_asic_reset,
324 .ioctl_wait_idle = NULL,
325 .gui_idle = &r100_gui_idle,
326 .mc_wait_for_idle = &r300_mc_wait_for_idle,
327 .gart = {
328 .tlb_flush = &r100_pci_gart_tlb_flush,
329 .set_page = &r100_pci_gart_set_page,
330 },
331 .ring = {
332 [RADEON_RING_TYPE_GFX_INDEX] = {
333 .ib_execute = &r100_ring_ib_execute,
334 .emit_fence = &r300_fence_ring_emit,
335 .emit_semaphore = &r100_semaphore_ring_emit,
336 .cs_parse = &r300_cs_parse,
337 .ring_start = &r300_ring_start,
338 .ring_test = &r100_ring_test,
339 .ib_test = &r100_ib_test,
340 .is_lockup = &r100_gpu_is_lockup,
341 }
342 },
343 .irq = {
344 .set = &r100_irq_set,
345 .process = &r100_irq_process,
346 },
347 .display = {
348 .bandwidth_update = &r100_bandwidth_update,
349 .get_vblank_counter = &r100_get_vblank_counter,
350 .wait_for_vblank = &r100_wait_for_vblank,
351 .set_backlight_level = &radeon_legacy_set_backlight_level,
352 .get_backlight_level = &radeon_legacy_get_backlight_level,
353 },
354 .copy = {
355 .blit = &r100_copy_blit,
356 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
357 .dma = &r200_copy_dma,
358 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
359 .copy = &r100_copy_blit,
360 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
361 },
362 .surface = {
363 .set_reg = r100_set_surface_reg,
364 .clear_reg = r100_clear_surface_reg,
365 },
366 .hpd = {
367 .init = &r100_hpd_init,
368 .fini = &r100_hpd_fini,
369 .sense = &r100_hpd_sense,
370 .set_polarity = &r100_hpd_set_polarity,
371 },
372 .pm = {
373 .misc = &r100_pm_misc,
374 .prepare = &r100_pm_prepare,
375 .finish = &r100_pm_finish,
376 .init_profile = &r100_pm_init_profile,
377 .get_dynpm_state = &r100_pm_get_dynpm_state,
378 .get_engine_clock = &radeon_legacy_get_engine_clock,
379 .set_engine_clock = &radeon_legacy_set_engine_clock,
380 .get_memory_clock = &radeon_legacy_get_memory_clock,
381 .set_memory_clock = NULL,
382 .get_pcie_lanes = &rv370_get_pcie_lanes,
383 .set_pcie_lanes = &rv370_set_pcie_lanes,
384 .set_clock_gating = &radeon_legacy_set_clock_gating,
385 },
386 .pflip = {
387 .pre_page_flip = &r100_pre_page_flip,
388 .page_flip = &r100_page_flip,
389 .post_page_flip = &r100_post_page_flip,
390 },
391 };
392
393 static struct radeon_asic r300_asic_pcie = {
394 .init = &r300_init,
395 .fini = &r300_fini,
396 .suspend = &r300_suspend,
397 .resume = &r300_resume,
398 .vga_set_state = &r100_vga_set_state,
399 .asic_reset = &r300_asic_reset,
400 .ioctl_wait_idle = NULL,
401 .gui_idle = &r100_gui_idle,
402 .mc_wait_for_idle = &r300_mc_wait_for_idle,
403 .gart = {
404 .tlb_flush = &rv370_pcie_gart_tlb_flush,
405 .set_page = &rv370_pcie_gart_set_page,
406 },
407 .ring = {
408 [RADEON_RING_TYPE_GFX_INDEX] = {
409 .ib_execute = &r100_ring_ib_execute,
410 .emit_fence = &r300_fence_ring_emit,
411 .emit_semaphore = &r100_semaphore_ring_emit,
412 .cs_parse = &r300_cs_parse,
413 .ring_start = &r300_ring_start,
414 .ring_test = &r100_ring_test,
415 .ib_test = &r100_ib_test,
416 .is_lockup = &r100_gpu_is_lockup,
417 }
418 },
419 .irq = {
420 .set = &r100_irq_set,
421 .process = &r100_irq_process,
422 },
423 .display = {
424 .bandwidth_update = &r100_bandwidth_update,
425 .get_vblank_counter = &r100_get_vblank_counter,
426 .wait_for_vblank = &r100_wait_for_vblank,
427 .set_backlight_level = &radeon_legacy_set_backlight_level,
428 .get_backlight_level = &radeon_legacy_get_backlight_level,
429 },
430 .copy = {
431 .blit = &r100_copy_blit,
432 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
433 .dma = &r200_copy_dma,
434 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
435 .copy = &r100_copy_blit,
436 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
437 },
438 .surface = {
439 .set_reg = r100_set_surface_reg,
440 .clear_reg = r100_clear_surface_reg,
441 },
442 .hpd = {
443 .init = &r100_hpd_init,
444 .fini = &r100_hpd_fini,
445 .sense = &r100_hpd_sense,
446 .set_polarity = &r100_hpd_set_polarity,
447 },
448 .pm = {
449 .misc = &r100_pm_misc,
450 .prepare = &r100_pm_prepare,
451 .finish = &r100_pm_finish,
452 .init_profile = &r100_pm_init_profile,
453 .get_dynpm_state = &r100_pm_get_dynpm_state,
454 .get_engine_clock = &radeon_legacy_get_engine_clock,
455 .set_engine_clock = &radeon_legacy_set_engine_clock,
456 .get_memory_clock = &radeon_legacy_get_memory_clock,
457 .set_memory_clock = NULL,
458 .get_pcie_lanes = &rv370_get_pcie_lanes,
459 .set_pcie_lanes = &rv370_set_pcie_lanes,
460 .set_clock_gating = &radeon_legacy_set_clock_gating,
461 },
462 .pflip = {
463 .pre_page_flip = &r100_pre_page_flip,
464 .page_flip = &r100_page_flip,
465 .post_page_flip = &r100_post_page_flip,
466 },
467 };
468
469 static struct radeon_asic r420_asic = {
470 .init = &r420_init,
471 .fini = &r420_fini,
472 .suspend = &r420_suspend,
473 .resume = &r420_resume,
474 .vga_set_state = &r100_vga_set_state,
475 .asic_reset = &r300_asic_reset,
476 .ioctl_wait_idle = NULL,
477 .gui_idle = &r100_gui_idle,
478 .mc_wait_for_idle = &r300_mc_wait_for_idle,
479 .gart = {
480 .tlb_flush = &rv370_pcie_gart_tlb_flush,
481 .set_page = &rv370_pcie_gart_set_page,
482 },
483 .ring = {
484 [RADEON_RING_TYPE_GFX_INDEX] = {
485 .ib_execute = &r100_ring_ib_execute,
486 .emit_fence = &r300_fence_ring_emit,
487 .emit_semaphore = &r100_semaphore_ring_emit,
488 .cs_parse = &r300_cs_parse,
489 .ring_start = &r300_ring_start,
490 .ring_test = &r100_ring_test,
491 .ib_test = &r100_ib_test,
492 .is_lockup = &r100_gpu_is_lockup,
493 }
494 },
495 .irq = {
496 .set = &r100_irq_set,
497 .process = &r100_irq_process,
498 },
499 .display = {
500 .bandwidth_update = &r100_bandwidth_update,
501 .get_vblank_counter = &r100_get_vblank_counter,
502 .wait_for_vblank = &r100_wait_for_vblank,
503 .set_backlight_level = &atombios_set_backlight_level,
504 .get_backlight_level = &atombios_get_backlight_level,
505 },
506 .copy = {
507 .blit = &r100_copy_blit,
508 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
509 .dma = &r200_copy_dma,
510 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
511 .copy = &r100_copy_blit,
512 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
513 },
514 .surface = {
515 .set_reg = r100_set_surface_reg,
516 .clear_reg = r100_clear_surface_reg,
517 },
518 .hpd = {
519 .init = &r100_hpd_init,
520 .fini = &r100_hpd_fini,
521 .sense = &r100_hpd_sense,
522 .set_polarity = &r100_hpd_set_polarity,
523 },
524 .pm = {
525 .misc = &r100_pm_misc,
526 .prepare = &r100_pm_prepare,
527 .finish = &r100_pm_finish,
528 .init_profile = &r420_pm_init_profile,
529 .get_dynpm_state = &r100_pm_get_dynpm_state,
530 .get_engine_clock = &radeon_atom_get_engine_clock,
531 .set_engine_clock = &radeon_atom_set_engine_clock,
532 .get_memory_clock = &radeon_atom_get_memory_clock,
533 .set_memory_clock = &radeon_atom_set_memory_clock,
534 .get_pcie_lanes = &rv370_get_pcie_lanes,
535 .set_pcie_lanes = &rv370_set_pcie_lanes,
536 .set_clock_gating = &radeon_atom_set_clock_gating,
537 },
538 .pflip = {
539 .pre_page_flip = &r100_pre_page_flip,
540 .page_flip = &r100_page_flip,
541 .post_page_flip = &r100_post_page_flip,
542 },
543 };
544
545 static struct radeon_asic rs400_asic = {
546 .init = &rs400_init,
547 .fini = &rs400_fini,
548 .suspend = &rs400_suspend,
549 .resume = &rs400_resume,
550 .vga_set_state = &r100_vga_set_state,
551 .asic_reset = &r300_asic_reset,
552 .ioctl_wait_idle = NULL,
553 .gui_idle = &r100_gui_idle,
554 .mc_wait_for_idle = &rs400_mc_wait_for_idle,
555 .gart = {
556 .tlb_flush = &rs400_gart_tlb_flush,
557 .set_page = &rs400_gart_set_page,
558 },
559 .ring = {
560 [RADEON_RING_TYPE_GFX_INDEX] = {
561 .ib_execute = &r100_ring_ib_execute,
562 .emit_fence = &r300_fence_ring_emit,
563 .emit_semaphore = &r100_semaphore_ring_emit,
564 .cs_parse = &r300_cs_parse,
565 .ring_start = &r300_ring_start,
566 .ring_test = &r100_ring_test,
567 .ib_test = &r100_ib_test,
568 .is_lockup = &r100_gpu_is_lockup,
569 }
570 },
571 .irq = {
572 .set = &r100_irq_set,
573 .process = &r100_irq_process,
574 },
575 .display = {
576 .bandwidth_update = &r100_bandwidth_update,
577 .get_vblank_counter = &r100_get_vblank_counter,
578 .wait_for_vblank = &r100_wait_for_vblank,
579 .set_backlight_level = &radeon_legacy_set_backlight_level,
580 .get_backlight_level = &radeon_legacy_get_backlight_level,
581 },
582 .copy = {
583 .blit = &r100_copy_blit,
584 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
585 .dma = &r200_copy_dma,
586 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
587 .copy = &r100_copy_blit,
588 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
589 },
590 .surface = {
591 .set_reg = r100_set_surface_reg,
592 .clear_reg = r100_clear_surface_reg,
593 },
594 .hpd = {
595 .init = &r100_hpd_init,
596 .fini = &r100_hpd_fini,
597 .sense = &r100_hpd_sense,
598 .set_polarity = &r100_hpd_set_polarity,
599 },
600 .pm = {
601 .misc = &r100_pm_misc,
602 .prepare = &r100_pm_prepare,
603 .finish = &r100_pm_finish,
604 .init_profile = &r100_pm_init_profile,
605 .get_dynpm_state = &r100_pm_get_dynpm_state,
606 .get_engine_clock = &radeon_legacy_get_engine_clock,
607 .set_engine_clock = &radeon_legacy_set_engine_clock,
608 .get_memory_clock = &radeon_legacy_get_memory_clock,
609 .set_memory_clock = NULL,
610 .get_pcie_lanes = NULL,
611 .set_pcie_lanes = NULL,
612 .set_clock_gating = &radeon_legacy_set_clock_gating,
613 },
614 .pflip = {
615 .pre_page_flip = &r100_pre_page_flip,
616 .page_flip = &r100_page_flip,
617 .post_page_flip = &r100_post_page_flip,
618 },
619 };
620
621 static struct radeon_asic rs600_asic = {
622 .init = &rs600_init,
623 .fini = &rs600_fini,
624 .suspend = &rs600_suspend,
625 .resume = &rs600_resume,
626 .vga_set_state = &r100_vga_set_state,
627 .asic_reset = &rs600_asic_reset,
628 .ioctl_wait_idle = NULL,
629 .gui_idle = &r100_gui_idle,
630 .mc_wait_for_idle = &rs600_mc_wait_for_idle,
631 .gart = {
632 .tlb_flush = &rs600_gart_tlb_flush,
633 .set_page = &rs600_gart_set_page,
634 },
635 .ring = {
636 [RADEON_RING_TYPE_GFX_INDEX] = {
637 .ib_execute = &r100_ring_ib_execute,
638 .emit_fence = &r300_fence_ring_emit,
639 .emit_semaphore = &r100_semaphore_ring_emit,
640 .cs_parse = &r300_cs_parse,
641 .ring_start = &r300_ring_start,
642 .ring_test = &r100_ring_test,
643 .ib_test = &r100_ib_test,
644 .is_lockup = &r100_gpu_is_lockup,
645 }
646 },
647 .irq = {
648 .set = &rs600_irq_set,
649 .process = &rs600_irq_process,
650 },
651 .display = {
652 .bandwidth_update = &rs600_bandwidth_update,
653 .get_vblank_counter = &rs600_get_vblank_counter,
654 .wait_for_vblank = &avivo_wait_for_vblank,
655 .set_backlight_level = &atombios_set_backlight_level,
656 .get_backlight_level = &atombios_get_backlight_level,
657 },
658 .copy = {
659 .blit = &r100_copy_blit,
660 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
661 .dma = &r200_copy_dma,
662 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
663 .copy = &r100_copy_blit,
664 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
665 },
666 .surface = {
667 .set_reg = r100_set_surface_reg,
668 .clear_reg = r100_clear_surface_reg,
669 },
670 .hpd = {
671 .init = &rs600_hpd_init,
672 .fini = &rs600_hpd_fini,
673 .sense = &rs600_hpd_sense,
674 .set_polarity = &rs600_hpd_set_polarity,
675 },
676 .pm = {
677 .misc = &rs600_pm_misc,
678 .prepare = &rs600_pm_prepare,
679 .finish = &rs600_pm_finish,
680 .init_profile = &r420_pm_init_profile,
681 .get_dynpm_state = &r100_pm_get_dynpm_state,
682 .get_engine_clock = &radeon_atom_get_engine_clock,
683 .set_engine_clock = &radeon_atom_set_engine_clock,
684 .get_memory_clock = &radeon_atom_get_memory_clock,
685 .set_memory_clock = &radeon_atom_set_memory_clock,
686 .get_pcie_lanes = NULL,
687 .set_pcie_lanes = NULL,
688 .set_clock_gating = &radeon_atom_set_clock_gating,
689 },
690 .pflip = {
691 .pre_page_flip = &rs600_pre_page_flip,
692 .page_flip = &rs600_page_flip,
693 .post_page_flip = &rs600_post_page_flip,
694 },
695 };
696
697 static struct radeon_asic rs690_asic = {
698 .init = &rs690_init,
699 .fini = &rs690_fini,
700 .suspend = &rs690_suspend,
701 .resume = &rs690_resume,
702 .vga_set_state = &r100_vga_set_state,
703 .asic_reset = &rs600_asic_reset,
704 .ioctl_wait_idle = NULL,
705 .gui_idle = &r100_gui_idle,
706 .mc_wait_for_idle = &rs690_mc_wait_for_idle,
707 .gart = {
708 .tlb_flush = &rs400_gart_tlb_flush,
709 .set_page = &rs400_gart_set_page,
710 },
711 .ring = {
712 [RADEON_RING_TYPE_GFX_INDEX] = {
713 .ib_execute = &r100_ring_ib_execute,
714 .emit_fence = &r300_fence_ring_emit,
715 .emit_semaphore = &r100_semaphore_ring_emit,
716 .cs_parse = &r300_cs_parse,
717 .ring_start = &r300_ring_start,
718 .ring_test = &r100_ring_test,
719 .ib_test = &r100_ib_test,
720 .is_lockup = &r100_gpu_is_lockup,
721 }
722 },
723 .irq = {
724 .set = &rs600_irq_set,
725 .process = &rs600_irq_process,
726 },
727 .display = {
728 .get_vblank_counter = &rs600_get_vblank_counter,
729 .bandwidth_update = &rs690_bandwidth_update,
730 .wait_for_vblank = &avivo_wait_for_vblank,
731 .set_backlight_level = &atombios_set_backlight_level,
732 .get_backlight_level = &atombios_get_backlight_level,
733 },
734 .copy = {
735 .blit = &r100_copy_blit,
736 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
737 .dma = &r200_copy_dma,
738 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
739 .copy = &r200_copy_dma,
740 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
741 },
742 .surface = {
743 .set_reg = r100_set_surface_reg,
744 .clear_reg = r100_clear_surface_reg,
745 },
746 .hpd = {
747 .init = &rs600_hpd_init,
748 .fini = &rs600_hpd_fini,
749 .sense = &rs600_hpd_sense,
750 .set_polarity = &rs600_hpd_set_polarity,
751 },
752 .pm = {
753 .misc = &rs600_pm_misc,
754 .prepare = &rs600_pm_prepare,
755 .finish = &rs600_pm_finish,
756 .init_profile = &r420_pm_init_profile,
757 .get_dynpm_state = &r100_pm_get_dynpm_state,
758 .get_engine_clock = &radeon_atom_get_engine_clock,
759 .set_engine_clock = &radeon_atom_set_engine_clock,
760 .get_memory_clock = &radeon_atom_get_memory_clock,
761 .set_memory_clock = &radeon_atom_set_memory_clock,
762 .get_pcie_lanes = NULL,
763 .set_pcie_lanes = NULL,
764 .set_clock_gating = &radeon_atom_set_clock_gating,
765 },
766 .pflip = {
767 .pre_page_flip = &rs600_pre_page_flip,
768 .page_flip = &rs600_page_flip,
769 .post_page_flip = &rs600_post_page_flip,
770 },
771 };
772
773 static struct radeon_asic rv515_asic = {
774 .init = &rv515_init,
775 .fini = &rv515_fini,
776 .suspend = &rv515_suspend,
777 .resume = &rv515_resume,
778 .vga_set_state = &r100_vga_set_state,
779 .asic_reset = &rs600_asic_reset,
780 .ioctl_wait_idle = NULL,
781 .gui_idle = &r100_gui_idle,
782 .mc_wait_for_idle = &rv515_mc_wait_for_idle,
783 .gart = {
784 .tlb_flush = &rv370_pcie_gart_tlb_flush,
785 .set_page = &rv370_pcie_gart_set_page,
786 },
787 .ring = {
788 [RADEON_RING_TYPE_GFX_INDEX] = {
789 .ib_execute = &r100_ring_ib_execute,
790 .emit_fence = &r300_fence_ring_emit,
791 .emit_semaphore = &r100_semaphore_ring_emit,
792 .cs_parse = &r300_cs_parse,
793 .ring_start = &rv515_ring_start,
794 .ring_test = &r100_ring_test,
795 .ib_test = &r100_ib_test,
796 .is_lockup = &r100_gpu_is_lockup,
797 }
798 },
799 .irq = {
800 .set = &rs600_irq_set,
801 .process = &rs600_irq_process,
802 },
803 .display = {
804 .get_vblank_counter = &rs600_get_vblank_counter,
805 .bandwidth_update = &rv515_bandwidth_update,
806 .wait_for_vblank = &avivo_wait_for_vblank,
807 .set_backlight_level = &atombios_set_backlight_level,
808 .get_backlight_level = &atombios_get_backlight_level,
809 },
810 .copy = {
811 .blit = &r100_copy_blit,
812 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
813 .dma = &r200_copy_dma,
814 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
815 .copy = &r100_copy_blit,
816 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
817 },
818 .surface = {
819 .set_reg = r100_set_surface_reg,
820 .clear_reg = r100_clear_surface_reg,
821 },
822 .hpd = {
823 .init = &rs600_hpd_init,
824 .fini = &rs600_hpd_fini,
825 .sense = &rs600_hpd_sense,
826 .set_polarity = &rs600_hpd_set_polarity,
827 },
828 .pm = {
829 .misc = &rs600_pm_misc,
830 .prepare = &rs600_pm_prepare,
831 .finish = &rs600_pm_finish,
832 .init_profile = &r420_pm_init_profile,
833 .get_dynpm_state = &r100_pm_get_dynpm_state,
834 .get_engine_clock = &radeon_atom_get_engine_clock,
835 .set_engine_clock = &radeon_atom_set_engine_clock,
836 .get_memory_clock = &radeon_atom_get_memory_clock,
837 .set_memory_clock = &radeon_atom_set_memory_clock,
838 .get_pcie_lanes = &rv370_get_pcie_lanes,
839 .set_pcie_lanes = &rv370_set_pcie_lanes,
840 .set_clock_gating = &radeon_atom_set_clock_gating,
841 },
842 .pflip = {
843 .pre_page_flip = &rs600_pre_page_flip,
844 .page_flip = &rs600_page_flip,
845 .post_page_flip = &rs600_post_page_flip,
846 },
847 };
848
849 static struct radeon_asic r520_asic = {
850 .init = &r520_init,
851 .fini = &rv515_fini,
852 .suspend = &rv515_suspend,
853 .resume = &r520_resume,
854 .vga_set_state = &r100_vga_set_state,
855 .asic_reset = &rs600_asic_reset,
856 .ioctl_wait_idle = NULL,
857 .gui_idle = &r100_gui_idle,
858 .mc_wait_for_idle = &r520_mc_wait_for_idle,
859 .gart = {
860 .tlb_flush = &rv370_pcie_gart_tlb_flush,
861 .set_page = &rv370_pcie_gart_set_page,
862 },
863 .ring = {
864 [RADEON_RING_TYPE_GFX_INDEX] = {
865 .ib_execute = &r100_ring_ib_execute,
866 .emit_fence = &r300_fence_ring_emit,
867 .emit_semaphore = &r100_semaphore_ring_emit,
868 .cs_parse = &r300_cs_parse,
869 .ring_start = &rv515_ring_start,
870 .ring_test = &r100_ring_test,
871 .ib_test = &r100_ib_test,
872 .is_lockup = &r100_gpu_is_lockup,
873 }
874 },
875 .irq = {
876 .set = &rs600_irq_set,
877 .process = &rs600_irq_process,
878 },
879 .display = {
880 .bandwidth_update = &rv515_bandwidth_update,
881 .get_vblank_counter = &rs600_get_vblank_counter,
882 .wait_for_vblank = &avivo_wait_for_vblank,
883 .set_backlight_level = &atombios_set_backlight_level,
884 .get_backlight_level = &atombios_get_backlight_level,
885 },
886 .copy = {
887 .blit = &r100_copy_blit,
888 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
889 .dma = &r200_copy_dma,
890 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
891 .copy = &r100_copy_blit,
892 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
893 },
894 .surface = {
895 .set_reg = r100_set_surface_reg,
896 .clear_reg = r100_clear_surface_reg,
897 },
898 .hpd = {
899 .init = &rs600_hpd_init,
900 .fini = &rs600_hpd_fini,
901 .sense = &rs600_hpd_sense,
902 .set_polarity = &rs600_hpd_set_polarity,
903 },
904 .pm = {
905 .misc = &rs600_pm_misc,
906 .prepare = &rs600_pm_prepare,
907 .finish = &rs600_pm_finish,
908 .init_profile = &r420_pm_init_profile,
909 .get_dynpm_state = &r100_pm_get_dynpm_state,
910 .get_engine_clock = &radeon_atom_get_engine_clock,
911 .set_engine_clock = &radeon_atom_set_engine_clock,
912 .get_memory_clock = &radeon_atom_get_memory_clock,
913 .set_memory_clock = &radeon_atom_set_memory_clock,
914 .get_pcie_lanes = &rv370_get_pcie_lanes,
915 .set_pcie_lanes = &rv370_set_pcie_lanes,
916 .set_clock_gating = &radeon_atom_set_clock_gating,
917 },
918 .pflip = {
919 .pre_page_flip = &rs600_pre_page_flip,
920 .page_flip = &rs600_page_flip,
921 .post_page_flip = &rs600_post_page_flip,
922 },
923 };
924
925 static struct radeon_asic r600_asic = {
926 .init = &r600_init,
927 .fini = &r600_fini,
928 .suspend = &r600_suspend,
929 .resume = &r600_resume,
930 .vga_set_state = &r600_vga_set_state,
931 .asic_reset = &r600_asic_reset,
932 .ioctl_wait_idle = r600_ioctl_wait_idle,
933 .gui_idle = &r600_gui_idle,
934 .mc_wait_for_idle = &r600_mc_wait_for_idle,
935 .gart = {
936 .tlb_flush = &r600_pcie_gart_tlb_flush,
937 .set_page = &rs600_gart_set_page,
938 },
939 .ring = {
940 [RADEON_RING_TYPE_GFX_INDEX] = {
941 .ib_execute = &r600_ring_ib_execute,
942 .emit_fence = &r600_fence_ring_emit,
943 .emit_semaphore = &r600_semaphore_ring_emit,
944 .cs_parse = &r600_cs_parse,
945 .ring_test = &r600_ring_test,
946 .ib_test = &r600_ib_test,
947 .is_lockup = &r600_gpu_is_lockup,
948 },
949 [R600_RING_TYPE_DMA_INDEX] = {
950 .ib_execute = &r600_dma_ring_ib_execute,
951 .emit_fence = &r600_dma_fence_ring_emit,
952 .emit_semaphore = &r600_dma_semaphore_ring_emit,
953 .cs_parse = &r600_dma_cs_parse,
954 .ring_test = &r600_dma_ring_test,
955 .ib_test = &r600_dma_ib_test,
956 .is_lockup = &r600_dma_is_lockup,
957 }
958 },
959 .irq = {
960 .set = &r600_irq_set,
961 .process = &r600_irq_process,
962 },
963 .display = {
964 .bandwidth_update = &rv515_bandwidth_update,
965 .get_vblank_counter = &rs600_get_vblank_counter,
966 .wait_for_vblank = &avivo_wait_for_vblank,
967 .set_backlight_level = &atombios_set_backlight_level,
968 .get_backlight_level = &atombios_get_backlight_level,
969 },
970 .copy = {
971 .blit = &r600_copy_blit,
972 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
973 .dma = &r600_copy_dma,
974 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
975 .copy = &r600_copy_dma,
976 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
977 },
978 .surface = {
979 .set_reg = r600_set_surface_reg,
980 .clear_reg = r600_clear_surface_reg,
981 },
982 .hpd = {
983 .init = &r600_hpd_init,
984 .fini = &r600_hpd_fini,
985 .sense = &r600_hpd_sense,
986 .set_polarity = &r600_hpd_set_polarity,
987 },
988 .pm = {
989 .misc = &r600_pm_misc,
990 .prepare = &rs600_pm_prepare,
991 .finish = &rs600_pm_finish,
992 .init_profile = &r600_pm_init_profile,
993 .get_dynpm_state = &r600_pm_get_dynpm_state,
994 .get_engine_clock = &radeon_atom_get_engine_clock,
995 .set_engine_clock = &radeon_atom_set_engine_clock,
996 .get_memory_clock = &radeon_atom_get_memory_clock,
997 .set_memory_clock = &radeon_atom_set_memory_clock,
998 .get_pcie_lanes = &r600_get_pcie_lanes,
999 .set_pcie_lanes = &r600_set_pcie_lanes,
1000 .set_clock_gating = NULL,
1001 },
1002 .pflip = {
1003 .pre_page_flip = &rs600_pre_page_flip,
1004 .page_flip = &rs600_page_flip,
1005 .post_page_flip = &rs600_post_page_flip,
1006 },
1007 };
1008
1009 static struct radeon_asic rs780_asic = {
1010 .init = &r600_init,
1011 .fini = &r600_fini,
1012 .suspend = &r600_suspend,
1013 .resume = &r600_resume,
1014 .vga_set_state = &r600_vga_set_state,
1015 .asic_reset = &r600_asic_reset,
1016 .ioctl_wait_idle = r600_ioctl_wait_idle,
1017 .gui_idle = &r600_gui_idle,
1018 .mc_wait_for_idle = &r600_mc_wait_for_idle,
1019 .gart = {
1020 .tlb_flush = &r600_pcie_gart_tlb_flush,
1021 .set_page = &rs600_gart_set_page,
1022 },
1023 .ring = {
1024 [RADEON_RING_TYPE_GFX_INDEX] = {
1025 .ib_execute = &r600_ring_ib_execute,
1026 .emit_fence = &r600_fence_ring_emit,
1027 .emit_semaphore = &r600_semaphore_ring_emit,
1028 .cs_parse = &r600_cs_parse,
1029 .ring_test = &r600_ring_test,
1030 .ib_test = &r600_ib_test,
1031 .is_lockup = &r600_gpu_is_lockup,
1032 },
1033 [R600_RING_TYPE_DMA_INDEX] = {
1034 .ib_execute = &r600_dma_ring_ib_execute,
1035 .emit_fence = &r600_dma_fence_ring_emit,
1036 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1037 .cs_parse = &r600_dma_cs_parse,
1038 .ring_test = &r600_dma_ring_test,
1039 .ib_test = &r600_dma_ib_test,
1040 .is_lockup = &r600_dma_is_lockup,
1041 }
1042 },
1043 .irq = {
1044 .set = &r600_irq_set,
1045 .process = &r600_irq_process,
1046 },
1047 .display = {
1048 .bandwidth_update = &rs690_bandwidth_update,
1049 .get_vblank_counter = &rs600_get_vblank_counter,
1050 .wait_for_vblank = &avivo_wait_for_vblank,
1051 .set_backlight_level = &atombios_set_backlight_level,
1052 .get_backlight_level = &atombios_get_backlight_level,
1053 },
1054 .copy = {
1055 .blit = &r600_copy_blit,
1056 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1057 .dma = &r600_copy_dma,
1058 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1059 .copy = &r600_copy_dma,
1060 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1061 },
1062 .surface = {
1063 .set_reg = r600_set_surface_reg,
1064 .clear_reg = r600_clear_surface_reg,
1065 },
1066 .hpd = {
1067 .init = &r600_hpd_init,
1068 .fini = &r600_hpd_fini,
1069 .sense = &r600_hpd_sense,
1070 .set_polarity = &r600_hpd_set_polarity,
1071 },
1072 .pm = {
1073 .misc = &r600_pm_misc,
1074 .prepare = &rs600_pm_prepare,
1075 .finish = &rs600_pm_finish,
1076 .init_profile = &rs780_pm_init_profile,
1077 .get_dynpm_state = &r600_pm_get_dynpm_state,
1078 .get_engine_clock = &radeon_atom_get_engine_clock,
1079 .set_engine_clock = &radeon_atom_set_engine_clock,
1080 .get_memory_clock = NULL,
1081 .set_memory_clock = NULL,
1082 .get_pcie_lanes = NULL,
1083 .set_pcie_lanes = NULL,
1084 .set_clock_gating = NULL,
1085 },
1086 .pflip = {
1087 .pre_page_flip = &rs600_pre_page_flip,
1088 .page_flip = &rs600_page_flip,
1089 .post_page_flip = &rs600_post_page_flip,
1090 },
1091 };
1092
1093 static struct radeon_asic rv770_asic = {
1094 .init = &rv770_init,
1095 .fini = &rv770_fini,
1096 .suspend = &rv770_suspend,
1097 .resume = &rv770_resume,
1098 .asic_reset = &r600_asic_reset,
1099 .vga_set_state = &r600_vga_set_state,
1100 .ioctl_wait_idle = r600_ioctl_wait_idle,
1101 .gui_idle = &r600_gui_idle,
1102 .mc_wait_for_idle = &r600_mc_wait_for_idle,
1103 .gart = {
1104 .tlb_flush = &r600_pcie_gart_tlb_flush,
1105 .set_page = &rs600_gart_set_page,
1106 },
1107 .ring = {
1108 [RADEON_RING_TYPE_GFX_INDEX] = {
1109 .ib_execute = &r600_ring_ib_execute,
1110 .emit_fence = &r600_fence_ring_emit,
1111 .emit_semaphore = &r600_semaphore_ring_emit,
1112 .cs_parse = &r600_cs_parse,
1113 .ring_test = &r600_ring_test,
1114 .ib_test = &r600_ib_test,
1115 .is_lockup = &r600_gpu_is_lockup,
1116 },
1117 [R600_RING_TYPE_DMA_INDEX] = {
1118 .ib_execute = &r600_dma_ring_ib_execute,
1119 .emit_fence = &r600_dma_fence_ring_emit,
1120 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1121 .cs_parse = &r600_dma_cs_parse,
1122 .ring_test = &r600_dma_ring_test,
1123 .ib_test = &r600_dma_ib_test,
1124 .is_lockup = &r600_dma_is_lockup,
1125 }
1126 },
1127 .irq = {
1128 .set = &r600_irq_set,
1129 .process = &r600_irq_process,
1130 },
1131 .display = {
1132 .bandwidth_update = &rv515_bandwidth_update,
1133 .get_vblank_counter = &rs600_get_vblank_counter,
1134 .wait_for_vblank = &avivo_wait_for_vblank,
1135 .set_backlight_level = &atombios_set_backlight_level,
1136 .get_backlight_level = &atombios_get_backlight_level,
1137 },
1138 .copy = {
1139 .blit = &r600_copy_blit,
1140 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1141 .dma = &rv770_copy_dma,
1142 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1143 .copy = &rv770_copy_dma,
1144 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1145 },
1146 .surface = {
1147 .set_reg = r600_set_surface_reg,
1148 .clear_reg = r600_clear_surface_reg,
1149 },
1150 .hpd = {
1151 .init = &r600_hpd_init,
1152 .fini = &r600_hpd_fini,
1153 .sense = &r600_hpd_sense,
1154 .set_polarity = &r600_hpd_set_polarity,
1155 },
1156 .pm = {
1157 .misc = &rv770_pm_misc,
1158 .prepare = &rs600_pm_prepare,
1159 .finish = &rs600_pm_finish,
1160 .init_profile = &r600_pm_init_profile,
1161 .get_dynpm_state = &r600_pm_get_dynpm_state,
1162 .get_engine_clock = &radeon_atom_get_engine_clock,
1163 .set_engine_clock = &radeon_atom_set_engine_clock,
1164 .get_memory_clock = &radeon_atom_get_memory_clock,
1165 .set_memory_clock = &radeon_atom_set_memory_clock,
1166 .get_pcie_lanes = &r600_get_pcie_lanes,
1167 .set_pcie_lanes = &r600_set_pcie_lanes,
1168 .set_clock_gating = &radeon_atom_set_clock_gating,
1169 },
1170 .pflip = {
1171 .pre_page_flip = &rs600_pre_page_flip,
1172 .page_flip = &rv770_page_flip,
1173 .post_page_flip = &rs600_post_page_flip,
1174 },
1175 };
1176
1177 static struct radeon_asic evergreen_asic = {
1178 .init = &evergreen_init,
1179 .fini = &evergreen_fini,
1180 .suspend = &evergreen_suspend,
1181 .resume = &evergreen_resume,
1182 .asic_reset = &evergreen_asic_reset,
1183 .vga_set_state = &r600_vga_set_state,
1184 .ioctl_wait_idle = r600_ioctl_wait_idle,
1185 .gui_idle = &r600_gui_idle,
1186 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1187 .gart = {
1188 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1189 .set_page = &rs600_gart_set_page,
1190 },
1191 .ring = {
1192 [RADEON_RING_TYPE_GFX_INDEX] = {
1193 .ib_execute = &evergreen_ring_ib_execute,
1194 .emit_fence = &r600_fence_ring_emit,
1195 .emit_semaphore = &r600_semaphore_ring_emit,
1196 .cs_parse = &evergreen_cs_parse,
1197 .ring_test = &r600_ring_test,
1198 .ib_test = &r600_ib_test,
1199 .is_lockup = &evergreen_gpu_is_lockup,
1200 },
1201 [R600_RING_TYPE_DMA_INDEX] = {
1202 .ib_execute = &evergreen_dma_ring_ib_execute,
1203 .emit_fence = &evergreen_dma_fence_ring_emit,
1204 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1205 .cs_parse = &evergreen_dma_cs_parse,
1206 .ring_test = &r600_dma_ring_test,
1207 .ib_test = &r600_dma_ib_test,
1208 .is_lockup = &r600_dma_is_lockup,
1209 }
1210 },
1211 .irq = {
1212 .set = &evergreen_irq_set,
1213 .process = &evergreen_irq_process,
1214 },
1215 .display = {
1216 .bandwidth_update = &evergreen_bandwidth_update,
1217 .get_vblank_counter = &evergreen_get_vblank_counter,
1218 .wait_for_vblank = &dce4_wait_for_vblank,
1219 .set_backlight_level = &atombios_set_backlight_level,
1220 .get_backlight_level = &atombios_get_backlight_level,
1221 },
1222 .copy = {
1223 .blit = &r600_copy_blit,
1224 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1225 .dma = &evergreen_copy_dma,
1226 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1227 .copy = &evergreen_copy_dma,
1228 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1229 },
1230 .surface = {
1231 .set_reg = r600_set_surface_reg,
1232 .clear_reg = r600_clear_surface_reg,
1233 },
1234 .hpd = {
1235 .init = &evergreen_hpd_init,
1236 .fini = &evergreen_hpd_fini,
1237 .sense = &evergreen_hpd_sense,
1238 .set_polarity = &evergreen_hpd_set_polarity,
1239 },
1240 .pm = {
1241 .misc = &evergreen_pm_misc,
1242 .prepare = &evergreen_pm_prepare,
1243 .finish = &evergreen_pm_finish,
1244 .init_profile = &r600_pm_init_profile,
1245 .get_dynpm_state = &r600_pm_get_dynpm_state,
1246 .get_engine_clock = &radeon_atom_get_engine_clock,
1247 .set_engine_clock = &radeon_atom_set_engine_clock,
1248 .get_memory_clock = &radeon_atom_get_memory_clock,
1249 .set_memory_clock = &radeon_atom_set_memory_clock,
1250 .get_pcie_lanes = &r600_get_pcie_lanes,
1251 .set_pcie_lanes = &r600_set_pcie_lanes,
1252 .set_clock_gating = NULL,
1253 },
1254 .pflip = {
1255 .pre_page_flip = &evergreen_pre_page_flip,
1256 .page_flip = &evergreen_page_flip,
1257 .post_page_flip = &evergreen_post_page_flip,
1258 },
1259 };
1260
1261 static struct radeon_asic sumo_asic = {
1262 .init = &evergreen_init,
1263 .fini = &evergreen_fini,
1264 .suspend = &evergreen_suspend,
1265 .resume = &evergreen_resume,
1266 .asic_reset = &evergreen_asic_reset,
1267 .vga_set_state = &r600_vga_set_state,
1268 .ioctl_wait_idle = r600_ioctl_wait_idle,
1269 .gui_idle = &r600_gui_idle,
1270 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1271 .gart = {
1272 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1273 .set_page = &rs600_gart_set_page,
1274 },
1275 .ring = {
1276 [RADEON_RING_TYPE_GFX_INDEX] = {
1277 .ib_execute = &evergreen_ring_ib_execute,
1278 .emit_fence = &r600_fence_ring_emit,
1279 .emit_semaphore = &r600_semaphore_ring_emit,
1280 .cs_parse = &evergreen_cs_parse,
1281 .ring_test = &r600_ring_test,
1282 .ib_test = &r600_ib_test,
1283 .is_lockup = &evergreen_gpu_is_lockup,
1284 },
1285 [R600_RING_TYPE_DMA_INDEX] = {
1286 .ib_execute = &evergreen_dma_ring_ib_execute,
1287 .emit_fence = &evergreen_dma_fence_ring_emit,
1288 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1289 .cs_parse = &evergreen_dma_cs_parse,
1290 .ring_test = &r600_dma_ring_test,
1291 .ib_test = &r600_dma_ib_test,
1292 .is_lockup = &r600_dma_is_lockup,
1293 }
1294 },
1295 .irq = {
1296 .set = &evergreen_irq_set,
1297 .process = &evergreen_irq_process,
1298 },
1299 .display = {
1300 .bandwidth_update = &evergreen_bandwidth_update,
1301 .get_vblank_counter = &evergreen_get_vblank_counter,
1302 .wait_for_vblank = &dce4_wait_for_vblank,
1303 .set_backlight_level = &atombios_set_backlight_level,
1304 .get_backlight_level = &atombios_get_backlight_level,
1305 },
1306 .copy = {
1307 .blit = &r600_copy_blit,
1308 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1309 .dma = &evergreen_copy_dma,
1310 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1311 .copy = &evergreen_copy_dma,
1312 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1313 },
1314 .surface = {
1315 .set_reg = r600_set_surface_reg,
1316 .clear_reg = r600_clear_surface_reg,
1317 },
1318 .hpd = {
1319 .init = &evergreen_hpd_init,
1320 .fini = &evergreen_hpd_fini,
1321 .sense = &evergreen_hpd_sense,
1322 .set_polarity = &evergreen_hpd_set_polarity,
1323 },
1324 .pm = {
1325 .misc = &evergreen_pm_misc,
1326 .prepare = &evergreen_pm_prepare,
1327 .finish = &evergreen_pm_finish,
1328 .init_profile = &sumo_pm_init_profile,
1329 .get_dynpm_state = &r600_pm_get_dynpm_state,
1330 .get_engine_clock = &radeon_atom_get_engine_clock,
1331 .set_engine_clock = &radeon_atom_set_engine_clock,
1332 .get_memory_clock = NULL,
1333 .set_memory_clock = NULL,
1334 .get_pcie_lanes = NULL,
1335 .set_pcie_lanes = NULL,
1336 .set_clock_gating = NULL,
1337 },
1338 .pflip = {
1339 .pre_page_flip = &evergreen_pre_page_flip,
1340 .page_flip = &evergreen_page_flip,
1341 .post_page_flip = &evergreen_post_page_flip,
1342 },
1343 };
1344
1345 static struct radeon_asic btc_asic = {
1346 .init = &evergreen_init,
1347 .fini = &evergreen_fini,
1348 .suspend = &evergreen_suspend,
1349 .resume = &evergreen_resume,
1350 .asic_reset = &evergreen_asic_reset,
1351 .vga_set_state = &r600_vga_set_state,
1352 .ioctl_wait_idle = r600_ioctl_wait_idle,
1353 .gui_idle = &r600_gui_idle,
1354 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1355 .gart = {
1356 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1357 .set_page = &rs600_gart_set_page,
1358 },
1359 .ring = {
1360 [RADEON_RING_TYPE_GFX_INDEX] = {
1361 .ib_execute = &evergreen_ring_ib_execute,
1362 .emit_fence = &r600_fence_ring_emit,
1363 .emit_semaphore = &r600_semaphore_ring_emit,
1364 .cs_parse = &evergreen_cs_parse,
1365 .ring_test = &r600_ring_test,
1366 .ib_test = &r600_ib_test,
1367 .is_lockup = &evergreen_gpu_is_lockup,
1368 },
1369 [R600_RING_TYPE_DMA_INDEX] = {
1370 .ib_execute = &evergreen_dma_ring_ib_execute,
1371 .emit_fence = &evergreen_dma_fence_ring_emit,
1372 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1373 .cs_parse = &evergreen_dma_cs_parse,
1374 .ring_test = &r600_dma_ring_test,
1375 .ib_test = &r600_dma_ib_test,
1376 .is_lockup = &r600_dma_is_lockup,
1377 }
1378 },
1379 .irq = {
1380 .set = &evergreen_irq_set,
1381 .process = &evergreen_irq_process,
1382 },
1383 .display = {
1384 .bandwidth_update = &evergreen_bandwidth_update,
1385 .get_vblank_counter = &evergreen_get_vblank_counter,
1386 .wait_for_vblank = &dce4_wait_for_vblank,
1387 .set_backlight_level = &atombios_set_backlight_level,
1388 .get_backlight_level = &atombios_get_backlight_level,
1389 },
1390 .copy = {
1391 .blit = &r600_copy_blit,
1392 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1393 .dma = &evergreen_copy_dma,
1394 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1395 .copy = &evergreen_copy_dma,
1396 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1397 },
1398 .surface = {
1399 .set_reg = r600_set_surface_reg,
1400 .clear_reg = r600_clear_surface_reg,
1401 },
1402 .hpd = {
1403 .init = &evergreen_hpd_init,
1404 .fini = &evergreen_hpd_fini,
1405 .sense = &evergreen_hpd_sense,
1406 .set_polarity = &evergreen_hpd_set_polarity,
1407 },
1408 .pm = {
1409 .misc = &evergreen_pm_misc,
1410 .prepare = &evergreen_pm_prepare,
1411 .finish = &evergreen_pm_finish,
1412 .init_profile = &btc_pm_init_profile,
1413 .get_dynpm_state = &r600_pm_get_dynpm_state,
1414 .get_engine_clock = &radeon_atom_get_engine_clock,
1415 .set_engine_clock = &radeon_atom_set_engine_clock,
1416 .get_memory_clock = &radeon_atom_get_memory_clock,
1417 .set_memory_clock = &radeon_atom_set_memory_clock,
1418 .get_pcie_lanes = NULL,
1419 .set_pcie_lanes = NULL,
1420 .set_clock_gating = NULL,
1421 },
1422 .pflip = {
1423 .pre_page_flip = &evergreen_pre_page_flip,
1424 .page_flip = &evergreen_page_flip,
1425 .post_page_flip = &evergreen_post_page_flip,
1426 },
1427 };
1428
1429 static struct radeon_asic cayman_asic = {
1430 .init = &cayman_init,
1431 .fini = &cayman_fini,
1432 .suspend = &cayman_suspend,
1433 .resume = &cayman_resume,
1434 .asic_reset = &cayman_asic_reset,
1435 .vga_set_state = &r600_vga_set_state,
1436 .ioctl_wait_idle = r600_ioctl_wait_idle,
1437 .gui_idle = &r600_gui_idle,
1438 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1439 .gart = {
1440 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1441 .set_page = &rs600_gart_set_page,
1442 },
1443 .vm = {
1444 .init = &cayman_vm_init,
1445 .fini = &cayman_vm_fini,
1446 .pt_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1447 .set_page = &cayman_vm_set_page,
1448 },
1449 .ring = {
1450 [RADEON_RING_TYPE_GFX_INDEX] = {
1451 .ib_execute = &cayman_ring_ib_execute,
1452 .ib_parse = &evergreen_ib_parse,
1453 .emit_fence = &cayman_fence_ring_emit,
1454 .emit_semaphore = &r600_semaphore_ring_emit,
1455 .cs_parse = &evergreen_cs_parse,
1456 .ring_test = &r600_ring_test,
1457 .ib_test = &r600_ib_test,
1458 .is_lockup = &evergreen_gpu_is_lockup,
1459 .vm_flush = &cayman_vm_flush,
1460 },
1461 [CAYMAN_RING_TYPE_CP1_INDEX] = {
1462 .ib_execute = &cayman_ring_ib_execute,
1463 .ib_parse = &evergreen_ib_parse,
1464 .emit_fence = &cayman_fence_ring_emit,
1465 .emit_semaphore = &r600_semaphore_ring_emit,
1466 .cs_parse = &evergreen_cs_parse,
1467 .ring_test = &r600_ring_test,
1468 .ib_test = &r600_ib_test,
1469 .is_lockup = &evergreen_gpu_is_lockup,
1470 .vm_flush = &cayman_vm_flush,
1471 },
1472 [CAYMAN_RING_TYPE_CP2_INDEX] = {
1473 .ib_execute = &cayman_ring_ib_execute,
1474 .ib_parse = &evergreen_ib_parse,
1475 .emit_fence = &cayman_fence_ring_emit,
1476 .emit_semaphore = &r600_semaphore_ring_emit,
1477 .cs_parse = &evergreen_cs_parse,
1478 .ring_test = &r600_ring_test,
1479 .ib_test = &r600_ib_test,
1480 .is_lockup = &evergreen_gpu_is_lockup,
1481 .vm_flush = &cayman_vm_flush,
1482 },
1483 [R600_RING_TYPE_DMA_INDEX] = {
1484 .ib_execute = &cayman_dma_ring_ib_execute,
1485 .ib_parse = &evergreen_dma_ib_parse,
1486 .emit_fence = &evergreen_dma_fence_ring_emit,
1487 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1488 .cs_parse = &evergreen_dma_cs_parse,
1489 .ring_test = &r600_dma_ring_test,
1490 .ib_test = &r600_dma_ib_test,
1491 .is_lockup = &cayman_dma_is_lockup,
1492 .vm_flush = &cayman_dma_vm_flush,
1493 },
1494 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
1495 .ib_execute = &cayman_dma_ring_ib_execute,
1496 .ib_parse = &evergreen_dma_ib_parse,
1497 .emit_fence = &evergreen_dma_fence_ring_emit,
1498 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1499 .cs_parse = &evergreen_dma_cs_parse,
1500 .ring_test = &r600_dma_ring_test,
1501 .ib_test = &r600_dma_ib_test,
1502 .is_lockup = &cayman_dma_is_lockup,
1503 .vm_flush = &cayman_dma_vm_flush,
1504 }
1505 },
1506 .irq = {
1507 .set = &evergreen_irq_set,
1508 .process = &evergreen_irq_process,
1509 },
1510 .display = {
1511 .bandwidth_update = &evergreen_bandwidth_update,
1512 .get_vblank_counter = &evergreen_get_vblank_counter,
1513 .wait_for_vblank = &dce4_wait_for_vblank,
1514 .set_backlight_level = &atombios_set_backlight_level,
1515 .get_backlight_level = &atombios_get_backlight_level,
1516 },
1517 .copy = {
1518 .blit = &r600_copy_blit,
1519 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1520 .dma = &evergreen_copy_dma,
1521 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1522 .copy = &evergreen_copy_dma,
1523 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1524 },
1525 .surface = {
1526 .set_reg = r600_set_surface_reg,
1527 .clear_reg = r600_clear_surface_reg,
1528 },
1529 .hpd = {
1530 .init = &evergreen_hpd_init,
1531 .fini = &evergreen_hpd_fini,
1532 .sense = &evergreen_hpd_sense,
1533 .set_polarity = &evergreen_hpd_set_polarity,
1534 },
1535 .pm = {
1536 .misc = &evergreen_pm_misc,
1537 .prepare = &evergreen_pm_prepare,
1538 .finish = &evergreen_pm_finish,
1539 .init_profile = &btc_pm_init_profile,
1540 .get_dynpm_state = &r600_pm_get_dynpm_state,
1541 .get_engine_clock = &radeon_atom_get_engine_clock,
1542 .set_engine_clock = &radeon_atom_set_engine_clock,
1543 .get_memory_clock = &radeon_atom_get_memory_clock,
1544 .set_memory_clock = &radeon_atom_set_memory_clock,
1545 .get_pcie_lanes = NULL,
1546 .set_pcie_lanes = NULL,
1547 .set_clock_gating = NULL,
1548 },
1549 .pflip = {
1550 .pre_page_flip = &evergreen_pre_page_flip,
1551 .page_flip = &evergreen_page_flip,
1552 .post_page_flip = &evergreen_post_page_flip,
1553 },
1554 };
1555
1556 static struct radeon_asic trinity_asic = {
1557 .init = &cayman_init,
1558 .fini = &cayman_fini,
1559 .suspend = &cayman_suspend,
1560 .resume = &cayman_resume,
1561 .asic_reset = &cayman_asic_reset,
1562 .vga_set_state = &r600_vga_set_state,
1563 .ioctl_wait_idle = r600_ioctl_wait_idle,
1564 .gui_idle = &r600_gui_idle,
1565 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1566 .gart = {
1567 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1568 .set_page = &rs600_gart_set_page,
1569 },
1570 .vm = {
1571 .init = &cayman_vm_init,
1572 .fini = &cayman_vm_fini,
1573 .pt_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1574 .set_page = &cayman_vm_set_page,
1575 },
1576 .ring = {
1577 [RADEON_RING_TYPE_GFX_INDEX] = {
1578 .ib_execute = &cayman_ring_ib_execute,
1579 .ib_parse = &evergreen_ib_parse,
1580 .emit_fence = &cayman_fence_ring_emit,
1581 .emit_semaphore = &r600_semaphore_ring_emit,
1582 .cs_parse = &evergreen_cs_parse,
1583 .ring_test = &r600_ring_test,
1584 .ib_test = &r600_ib_test,
1585 .is_lockup = &evergreen_gpu_is_lockup,
1586 .vm_flush = &cayman_vm_flush,
1587 },
1588 [CAYMAN_RING_TYPE_CP1_INDEX] = {
1589 .ib_execute = &cayman_ring_ib_execute,
1590 .ib_parse = &evergreen_ib_parse,
1591 .emit_fence = &cayman_fence_ring_emit,
1592 .emit_semaphore = &r600_semaphore_ring_emit,
1593 .cs_parse = &evergreen_cs_parse,
1594 .ring_test = &r600_ring_test,
1595 .ib_test = &r600_ib_test,
1596 .is_lockup = &evergreen_gpu_is_lockup,
1597 .vm_flush = &cayman_vm_flush,
1598 },
1599 [CAYMAN_RING_TYPE_CP2_INDEX] = {
1600 .ib_execute = &cayman_ring_ib_execute,
1601 .ib_parse = &evergreen_ib_parse,
1602 .emit_fence = &cayman_fence_ring_emit,
1603 .emit_semaphore = &r600_semaphore_ring_emit,
1604 .cs_parse = &evergreen_cs_parse,
1605 .ring_test = &r600_ring_test,
1606 .ib_test = &r600_ib_test,
1607 .is_lockup = &evergreen_gpu_is_lockup,
1608 .vm_flush = &cayman_vm_flush,
1609 },
1610 [R600_RING_TYPE_DMA_INDEX] = {
1611 .ib_execute = &cayman_dma_ring_ib_execute,
1612 .ib_parse = &evergreen_dma_ib_parse,
1613 .emit_fence = &evergreen_dma_fence_ring_emit,
1614 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1615 .cs_parse = &evergreen_dma_cs_parse,
1616 .ring_test = &r600_dma_ring_test,
1617 .ib_test = &r600_dma_ib_test,
1618 .is_lockup = &cayman_dma_is_lockup,
1619 .vm_flush = &cayman_dma_vm_flush,
1620 },
1621 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
1622 .ib_execute = &cayman_dma_ring_ib_execute,
1623 .ib_parse = &evergreen_dma_ib_parse,
1624 .emit_fence = &evergreen_dma_fence_ring_emit,
1625 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1626 .cs_parse = &evergreen_dma_cs_parse,
1627 .ring_test = &r600_dma_ring_test,
1628 .ib_test = &r600_dma_ib_test,
1629 .is_lockup = &cayman_dma_is_lockup,
1630 .vm_flush = &cayman_dma_vm_flush,
1631 }
1632 },
1633 .irq = {
1634 .set = &evergreen_irq_set,
1635 .process = &evergreen_irq_process,
1636 },
1637 .display = {
1638 .bandwidth_update = &dce6_bandwidth_update,
1639 .get_vblank_counter = &evergreen_get_vblank_counter,
1640 .wait_for_vblank = &dce4_wait_for_vblank,
1641 .set_backlight_level = &atombios_set_backlight_level,
1642 .get_backlight_level = &atombios_get_backlight_level,
1643 },
1644 .copy = {
1645 .blit = &r600_copy_blit,
1646 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1647 .dma = &evergreen_copy_dma,
1648 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1649 .copy = &evergreen_copy_dma,
1650 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1651 },
1652 .surface = {
1653 .set_reg = r600_set_surface_reg,
1654 .clear_reg = r600_clear_surface_reg,
1655 },
1656 .hpd = {
1657 .init = &evergreen_hpd_init,
1658 .fini = &evergreen_hpd_fini,
1659 .sense = &evergreen_hpd_sense,
1660 .set_polarity = &evergreen_hpd_set_polarity,
1661 },
1662 .pm = {
1663 .misc = &evergreen_pm_misc,
1664 .prepare = &evergreen_pm_prepare,
1665 .finish = &evergreen_pm_finish,
1666 .init_profile = &sumo_pm_init_profile,
1667 .get_dynpm_state = &r600_pm_get_dynpm_state,
1668 .get_engine_clock = &radeon_atom_get_engine_clock,
1669 .set_engine_clock = &radeon_atom_set_engine_clock,
1670 .get_memory_clock = NULL,
1671 .set_memory_clock = NULL,
1672 .get_pcie_lanes = NULL,
1673 .set_pcie_lanes = NULL,
1674 .set_clock_gating = NULL,
1675 },
1676 .pflip = {
1677 .pre_page_flip = &evergreen_pre_page_flip,
1678 .page_flip = &evergreen_page_flip,
1679 .post_page_flip = &evergreen_post_page_flip,
1680 },
1681 };
1682
1683 static struct radeon_asic si_asic = {
1684 .init = &si_init,
1685 .fini = &si_fini,
1686 .suspend = &si_suspend,
1687 .resume = &si_resume,
1688 .asic_reset = &si_asic_reset,
1689 .vga_set_state = &r600_vga_set_state,
1690 .ioctl_wait_idle = r600_ioctl_wait_idle,
1691 .gui_idle = &r600_gui_idle,
1692 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1693 .gart = {
1694 .tlb_flush = &si_pcie_gart_tlb_flush,
1695 .set_page = &rs600_gart_set_page,
1696 },
1697 .vm = {
1698 .init = &si_vm_init,
1699 .fini = &si_vm_fini,
1700 .pt_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1701 .set_page = &si_vm_set_page,
1702 },
1703 .ring = {
1704 [RADEON_RING_TYPE_GFX_INDEX] = {
1705 .ib_execute = &si_ring_ib_execute,
1706 .ib_parse = &si_ib_parse,
1707 .emit_fence = &si_fence_ring_emit,
1708 .emit_semaphore = &r600_semaphore_ring_emit,
1709 .cs_parse = NULL,
1710 .ring_test = &r600_ring_test,
1711 .ib_test = &r600_ib_test,
1712 .is_lockup = &si_gpu_is_lockup,
1713 .vm_flush = &si_vm_flush,
1714 },
1715 [CAYMAN_RING_TYPE_CP1_INDEX] = {
1716 .ib_execute = &si_ring_ib_execute,
1717 .ib_parse = &si_ib_parse,
1718 .emit_fence = &si_fence_ring_emit,
1719 .emit_semaphore = &r600_semaphore_ring_emit,
1720 .cs_parse = NULL,
1721 .ring_test = &r600_ring_test,
1722 .ib_test = &r600_ib_test,
1723 .is_lockup = &si_gpu_is_lockup,
1724 .vm_flush = &si_vm_flush,
1725 },
1726 [CAYMAN_RING_TYPE_CP2_INDEX] = {
1727 .ib_execute = &si_ring_ib_execute,
1728 .ib_parse = &si_ib_parse,
1729 .emit_fence = &si_fence_ring_emit,
1730 .emit_semaphore = &r600_semaphore_ring_emit,
1731 .cs_parse = NULL,
1732 .ring_test = &r600_ring_test,
1733 .ib_test = &r600_ib_test,
1734 .is_lockup = &si_gpu_is_lockup,
1735 .vm_flush = &si_vm_flush,
1736 },
1737 [R600_RING_TYPE_DMA_INDEX] = {
1738 .ib_execute = &cayman_dma_ring_ib_execute,
1739 .ib_parse = &evergreen_dma_ib_parse,
1740 .emit_fence = &evergreen_dma_fence_ring_emit,
1741 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1742 .cs_parse = NULL,
1743 .ring_test = &r600_dma_ring_test,
1744 .ib_test = &r600_dma_ib_test,
1745 .is_lockup = &cayman_dma_is_lockup,
1746 .vm_flush = &si_dma_vm_flush,
1747 },
1748 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
1749 .ib_execute = &cayman_dma_ring_ib_execute,
1750 .ib_parse = &evergreen_dma_ib_parse,
1751 .emit_fence = &evergreen_dma_fence_ring_emit,
1752 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1753 .cs_parse = NULL,
1754 .ring_test = &r600_dma_ring_test,
1755 .ib_test = &r600_dma_ib_test,
1756 .is_lockup = &cayman_dma_is_lockup,
1757 .vm_flush = &si_dma_vm_flush,
1758 }
1759 },
1760 .irq = {
1761 .set = &si_irq_set,
1762 .process = &si_irq_process,
1763 },
1764 .display = {
1765 .bandwidth_update = &dce6_bandwidth_update,
1766 .get_vblank_counter = &evergreen_get_vblank_counter,
1767 .wait_for_vblank = &dce4_wait_for_vblank,
1768 .set_backlight_level = &atombios_set_backlight_level,
1769 .get_backlight_level = &atombios_get_backlight_level,
1770 },
1771 .copy = {
1772 .blit = NULL,
1773 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1774 .dma = &si_copy_dma,
1775 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1776 .copy = &si_copy_dma,
1777 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1778 },
1779 .surface = {
1780 .set_reg = r600_set_surface_reg,
1781 .clear_reg = r600_clear_surface_reg,
1782 },
1783 .hpd = {
1784 .init = &evergreen_hpd_init,
1785 .fini = &evergreen_hpd_fini,
1786 .sense = &evergreen_hpd_sense,
1787 .set_polarity = &evergreen_hpd_set_polarity,
1788 },
1789 .pm = {
1790 .misc = &evergreen_pm_misc,
1791 .prepare = &evergreen_pm_prepare,
1792 .finish = &evergreen_pm_finish,
1793 .init_profile = &sumo_pm_init_profile,
1794 .get_dynpm_state = &r600_pm_get_dynpm_state,
1795 .get_engine_clock = &radeon_atom_get_engine_clock,
1796 .set_engine_clock = &radeon_atom_set_engine_clock,
1797 .get_memory_clock = &radeon_atom_get_memory_clock,
1798 .set_memory_clock = &radeon_atom_set_memory_clock,
1799 .get_pcie_lanes = NULL,
1800 .set_pcie_lanes = NULL,
1801 .set_clock_gating = NULL,
1802 },
1803 .pflip = {
1804 .pre_page_flip = &evergreen_pre_page_flip,
1805 .page_flip = &evergreen_page_flip,
1806 .post_page_flip = &evergreen_post_page_flip,
1807 },
1808 };
1809
1810 /**
1811 * radeon_asic_init - register asic specific callbacks
1812 *
1813 * @rdev: radeon device pointer
1814 *
1815 * Registers the appropriate asic specific callbacks for each
1816 * chip family. Also sets other asics specific info like the number
1817 * of crtcs and the register aperture accessors (all asics).
1818 * Returns 0 for success.
1819 */
radeon_asic_init(struct radeon_device * rdev)1820 int radeon_asic_init(struct radeon_device *rdev)
1821 {
1822 radeon_register_accessor_init(rdev);
1823
1824 /* set the number of crtcs */
1825 if (rdev->flags & RADEON_SINGLE_CRTC)
1826 rdev->num_crtc = 1;
1827 else
1828 rdev->num_crtc = 2;
1829
1830 switch (rdev->family) {
1831 case CHIP_R100:
1832 case CHIP_RV100:
1833 case CHIP_RS100:
1834 case CHIP_RV200:
1835 case CHIP_RS200:
1836 rdev->asic = &r100_asic;
1837 break;
1838 case CHIP_R200:
1839 case CHIP_RV250:
1840 case CHIP_RS300:
1841 case CHIP_RV280:
1842 rdev->asic = &r200_asic;
1843 break;
1844 case CHIP_R300:
1845 case CHIP_R350:
1846 case CHIP_RV350:
1847 case CHIP_RV380:
1848 if (rdev->flags & RADEON_IS_PCIE)
1849 rdev->asic = &r300_asic_pcie;
1850 else
1851 rdev->asic = &r300_asic;
1852 break;
1853 case CHIP_R420:
1854 case CHIP_R423:
1855 case CHIP_RV410:
1856 rdev->asic = &r420_asic;
1857 /* handle macs */
1858 if (rdev->bios == NULL) {
1859 rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
1860 rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
1861 rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
1862 rdev->asic->pm.set_memory_clock = NULL;
1863 rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;
1864 }
1865 break;
1866 case CHIP_RS400:
1867 case CHIP_RS480:
1868 rdev->asic = &rs400_asic;
1869 break;
1870 case CHIP_RS600:
1871 rdev->asic = &rs600_asic;
1872 break;
1873 case CHIP_RS690:
1874 case CHIP_RS740:
1875 rdev->asic = &rs690_asic;
1876 break;
1877 case CHIP_RV515:
1878 rdev->asic = &rv515_asic;
1879 break;
1880 case CHIP_R520:
1881 case CHIP_RV530:
1882 case CHIP_RV560:
1883 case CHIP_RV570:
1884 case CHIP_R580:
1885 rdev->asic = &r520_asic;
1886 break;
1887 case CHIP_R600:
1888 case CHIP_RV610:
1889 case CHIP_RV630:
1890 case CHIP_RV620:
1891 case CHIP_RV635:
1892 case CHIP_RV670:
1893 rdev->asic = &r600_asic;
1894 break;
1895 case CHIP_RS780:
1896 case CHIP_RS880:
1897 rdev->asic = &rs780_asic;
1898 break;
1899 case CHIP_RV770:
1900 case CHIP_RV730:
1901 case CHIP_RV710:
1902 case CHIP_RV740:
1903 rdev->asic = &rv770_asic;
1904 break;
1905 case CHIP_CEDAR:
1906 case CHIP_REDWOOD:
1907 case CHIP_JUNIPER:
1908 case CHIP_CYPRESS:
1909 case CHIP_HEMLOCK:
1910 /* set num crtcs */
1911 if (rdev->family == CHIP_CEDAR)
1912 rdev->num_crtc = 4;
1913 else
1914 rdev->num_crtc = 6;
1915 rdev->asic = &evergreen_asic;
1916 break;
1917 case CHIP_PALM:
1918 case CHIP_SUMO:
1919 case CHIP_SUMO2:
1920 rdev->asic = &sumo_asic;
1921 break;
1922 case CHIP_BARTS:
1923 case CHIP_TURKS:
1924 case CHIP_CAICOS:
1925 /* set num crtcs */
1926 if (rdev->family == CHIP_CAICOS)
1927 rdev->num_crtc = 4;
1928 else
1929 rdev->num_crtc = 6;
1930 rdev->asic = &btc_asic;
1931 break;
1932 case CHIP_CAYMAN:
1933 rdev->asic = &cayman_asic;
1934 /* set num crtcs */
1935 rdev->num_crtc = 6;
1936 break;
1937 case CHIP_ARUBA:
1938 rdev->asic = &trinity_asic;
1939 /* set num crtcs */
1940 rdev->num_crtc = 4;
1941 break;
1942 case CHIP_TAHITI:
1943 case CHIP_PITCAIRN:
1944 case CHIP_VERDE:
1945 rdev->asic = &si_asic;
1946 /* set num crtcs */
1947 rdev->num_crtc = 6;
1948 break;
1949 default:
1950 /* FIXME: not supported yet */
1951 return -EINVAL;
1952 }
1953
1954 if (rdev->flags & RADEON_IS_IGP) {
1955 rdev->asic->pm.get_memory_clock = NULL;
1956 rdev->asic->pm.set_memory_clock = NULL;
1957 }
1958
1959 return 0;
1960 }
1961
1962