1 /*
2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
17 * $FreeBSD: stable/9/sys/dev/ath/ath_hal/ar5212/ar5212_beacon.c 225444 2011-09-08 01:23:05Z adrian $
18 */
19 #include "opt_ah.h"
20
21 #include "ah.h"
22 #include "ah_internal.h"
23
24 #include "ar5212/ar5212.h"
25 #include "ar5212/ar5212reg.h"
26 #include "ar5212/ar5212desc.h"
27
28 /*
29 * Return the hardware NextTBTT in TSF
30 */
31 uint64_t
ar5212GetNextTBTT(struct ath_hal * ah)32 ar5212GetNextTBTT(struct ath_hal *ah)
33 {
34 #define TU_TO_TSF(_tu) (((uint64_t)(_tu)) << 10)
35 return TU_TO_TSF(OS_REG_READ(ah, AR_TIMER0));
36 #undef TU_TO_TSF
37 }
38
39 /*
40 * Initialize all of the hardware registers used to
41 * send beacons. Note that for station operation the
42 * driver calls ar5212SetStaBeaconTimers instead.
43 */
44 void
ar5212SetBeaconTimers(struct ath_hal * ah,const HAL_BEACON_TIMERS * bt)45 ar5212SetBeaconTimers(struct ath_hal *ah, const HAL_BEACON_TIMERS *bt)
46 {
47
48 OS_REG_WRITE(ah, AR_TIMER0, bt->bt_nexttbtt);
49 OS_REG_WRITE(ah, AR_TIMER1, bt->bt_nextdba);
50 OS_REG_WRITE(ah, AR_TIMER2, bt->bt_nextswba);
51 OS_REG_WRITE(ah, AR_TIMER3, bt->bt_nextatim);
52 /*
53 * Set the Beacon register after setting all timers.
54 */
55 if (bt->bt_intval & AR_BEACON_RESET_TSF) {
56 /*
57 * When resetting the TSF,
58 * write twice to the corresponding register; each
59 * write to the RESET_TSF bit toggles the internal
60 * signal to cause a reset of the TSF - but if the signal
61 * is left high, it will reset the TSF on the next
62 * chip reset also! writing the bit an even number
63 * of times fixes this issue
64 */
65 OS_REG_WRITE(ah, AR_BEACON, AR_BEACON_RESET_TSF);
66 }
67 OS_REG_WRITE(ah, AR_BEACON, bt->bt_intval);
68 }
69
70 /*
71 * Old api for setting up beacon timer registers when
72 * operating in !station mode. Note the fixed constants
73 * adjusting the DBA and SWBA timers and the fixed ATIM
74 * window.
75 */
76 void
ar5212BeaconInit(struct ath_hal * ah,uint32_t next_beacon,uint32_t beacon_period)77 ar5212BeaconInit(struct ath_hal *ah,
78 uint32_t next_beacon, uint32_t beacon_period)
79 {
80 HAL_BEACON_TIMERS bt;
81
82 bt.bt_nexttbtt = next_beacon;
83 /*
84 * TIMER1: in AP/adhoc mode this controls the DMA beacon
85 * alert timer; otherwise it controls the next wakeup time.
86 * TIMER2: in AP mode, it controls the SBA beacon alert
87 * interrupt; otherwise it sets the start of the next CFP.
88 */
89 switch (AH_PRIVATE(ah)->ah_opmode) {
90 case HAL_M_STA:
91 case HAL_M_MONITOR:
92 bt.bt_nextdba = 0xffff;
93 bt.bt_nextswba = 0x7ffff;
94 break;
95 case HAL_M_HOSTAP:
96 case HAL_M_IBSS:
97 bt.bt_nextdba = (next_beacon -
98 ah->ah_config.ah_dma_beacon_response_time) << 3; /* 1/8 TU */
99 bt.bt_nextswba = (next_beacon -
100 ah->ah_config.ah_sw_beacon_response_time) << 3; /* 1/8 TU */
101 break;
102 }
103 /*
104 * Set the ATIM window
105 * Our hardware does not support an ATIM window of 0
106 * (beacons will not work). If the ATIM windows is 0,
107 * force it to 1.
108 */
109 bt.bt_nextatim = next_beacon + 1;
110 bt.bt_intval = beacon_period &
111 (AR_BEACON_PERIOD | AR_BEACON_RESET_TSF | AR_BEACON_EN);
112 ar5212SetBeaconTimers(ah, &bt);
113 }
114
115 void
ar5212ResetStaBeaconTimers(struct ath_hal * ah)116 ar5212ResetStaBeaconTimers(struct ath_hal *ah)
117 {
118 uint32_t val;
119
120 OS_REG_WRITE(ah, AR_TIMER0, 0); /* no beacons */
121 val = OS_REG_READ(ah, AR_STA_ID1);
122 val |= AR_STA_ID1_PWR_SAV; /* XXX */
123 /* tell the h/w that the associated AP is not PCF capable */
124 OS_REG_WRITE(ah, AR_STA_ID1,
125 val & ~(AR_STA_ID1_USE_DEFANT | AR_STA_ID1_PCF));
126 OS_REG_WRITE(ah, AR_BEACON, AR_BEACON_PERIOD);
127 }
128
129 /*
130 * Set all the beacon related bits on the h/w for stations
131 * i.e. initializes the corresponding h/w timers;
132 * also tells the h/w whether to anticipate PCF beacons
133 */
134 void
ar5212SetStaBeaconTimers(struct ath_hal * ah,const HAL_BEACON_STATE * bs)135 ar5212SetStaBeaconTimers(struct ath_hal *ah, const HAL_BEACON_STATE *bs)
136 {
137 struct ath_hal_5212 *ahp = AH5212(ah);
138 uint32_t nextTbtt, nextdtim,beaconintval, dtimperiod;
139
140 HALASSERT(bs->bs_intval != 0);
141 /* if the AP will do PCF */
142 if (bs->bs_cfpmaxduration != 0) {
143 /* tell the h/w that the associated AP is PCF capable */
144 OS_REG_WRITE(ah, AR_STA_ID1,
145 OS_REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PCF);
146
147 /* set CFP_PERIOD(1.024ms) register */
148 OS_REG_WRITE(ah, AR_CFP_PERIOD, bs->bs_cfpperiod);
149
150 /* set CFP_DUR(1.024ms) register to max cfp duration */
151 OS_REG_WRITE(ah, AR_CFP_DUR, bs->bs_cfpmaxduration);
152
153 /* set TIMER2(128us) to anticipated time of next CFP */
154 OS_REG_WRITE(ah, AR_TIMER2, bs->bs_cfpnext << 3);
155 } else {
156 /* tell the h/w that the associated AP is not PCF capable */
157 OS_REG_WRITE(ah, AR_STA_ID1,
158 OS_REG_READ(ah, AR_STA_ID1) &~ AR_STA_ID1_PCF);
159 }
160
161 /*
162 * Set TIMER0(1.024ms) to the anticipated time of the next beacon.
163 */
164 OS_REG_WRITE(ah, AR_TIMER0, bs->bs_nexttbtt);
165
166 /*
167 * Start the beacon timers by setting the BEACON register
168 * to the beacon interval; also write the tim offset which
169 * we should know by now. The code, in ar5211WriteAssocid,
170 * also sets the tim offset once the AID is known which can
171 * be left as such for now.
172 */
173 OS_REG_WRITE(ah, AR_BEACON,
174 (OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_PERIOD|AR_BEACON_TIM))
175 | SM(bs->bs_intval, AR_BEACON_PERIOD)
176 | SM(bs->bs_timoffset ? bs->bs_timoffset + 4 : 0, AR_BEACON_TIM)
177 );
178
179 /*
180 * Configure the BMISS interrupt. Note that we
181 * assume the caller blocks interrupts while enabling
182 * the threshold.
183 */
184 HALASSERT(bs->bs_bmissthreshold <= MS(0xffffffff, AR_RSSI_THR_BM_THR));
185 ahp->ah_rssiThr = (ahp->ah_rssiThr &~ AR_RSSI_THR_BM_THR)
186 | SM(bs->bs_bmissthreshold, AR_RSSI_THR_BM_THR);
187 OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr);
188
189 /*
190 * Program the sleep registers to correlate with the beacon setup.
191 */
192
193 /*
194 * Oahu beacons timers on the station were used for power
195 * save operation (waking up in anticipation of a beacon)
196 * and any CFP function; Venice does sleep/power-save timers
197 * differently - so this is the right place to set them up;
198 * don't think the beacon timers are used by venice sta hw
199 * for any useful purpose anymore
200 * Setup venice's sleep related timers
201 * Current implementation assumes sw processing of beacons -
202 * assuming an interrupt is generated every beacon which
203 * causes the hardware to become awake until the sw tells
204 * it to go to sleep again; beacon timeout is to allow for
205 * beacon jitter; cab timeout is max time to wait for cab
206 * after seeing the last DTIM or MORE CAB bit
207 */
208 #define CAB_TIMEOUT_VAL 10 /* in TU */
209 #define BEACON_TIMEOUT_VAL 10 /* in TU */
210 #define SLEEP_SLOP 3 /* in TU */
211
212 /*
213 * For max powersave mode we may want to sleep for longer than a
214 * beacon period and not want to receive all beacons; modify the
215 * timers accordingly; make sure to align the next TIM to the
216 * next DTIM if we decide to wake for DTIMs only
217 */
218 beaconintval = bs->bs_intval & HAL_BEACON_PERIOD;
219 HALASSERT(beaconintval != 0);
220 if (bs->bs_sleepduration > beaconintval) {
221 HALASSERT(roundup(bs->bs_sleepduration, beaconintval) ==
222 bs->bs_sleepduration);
223 beaconintval = bs->bs_sleepduration;
224 }
225 dtimperiod = bs->bs_dtimperiod;
226 if (bs->bs_sleepduration > dtimperiod) {
227 HALASSERT(dtimperiod == 0 ||
228 roundup(bs->bs_sleepduration, dtimperiod) ==
229 bs->bs_sleepduration);
230 dtimperiod = bs->bs_sleepduration;
231 }
232 HALASSERT(beaconintval <= dtimperiod);
233 if (beaconintval == dtimperiod)
234 nextTbtt = bs->bs_nextdtim;
235 else
236 nextTbtt = bs->bs_nexttbtt;
237 nextdtim = bs->bs_nextdtim;
238
239 OS_REG_WRITE(ah, AR_SLEEP1,
240 SM((nextdtim - SLEEP_SLOP) << 3, AR_SLEEP1_NEXT_DTIM)
241 | SM(CAB_TIMEOUT_VAL, AR_SLEEP1_CAB_TIMEOUT)
242 | AR_SLEEP1_ASSUME_DTIM
243 | AR_SLEEP1_ENH_SLEEP_ENA
244 );
245 OS_REG_WRITE(ah, AR_SLEEP2,
246 SM((nextTbtt - SLEEP_SLOP) << 3, AR_SLEEP2_NEXT_TIM)
247 | SM(BEACON_TIMEOUT_VAL, AR_SLEEP2_BEACON_TIMEOUT)
248 );
249 OS_REG_WRITE(ah, AR_SLEEP3,
250 SM(beaconintval, AR_SLEEP3_TIM_PERIOD)
251 | SM(dtimperiod, AR_SLEEP3_DTIM_PERIOD)
252 );
253 HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: next DTIM %d\n",
254 __func__, bs->bs_nextdtim);
255 HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: next beacon %d\n",
256 __func__, nextTbtt);
257 HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: beacon period %d\n",
258 __func__, beaconintval);
259 HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: DTIM period %d\n",
260 __func__, dtimperiod);
261 #undef CAB_TIMEOUT_VAL
262 #undef BEACON_TIMEOUT_VAL
263 #undef SLEEP_SLOP
264 }
265