1 /*-
2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD: stable/9/sys/dev/ata/chipsets/ata-ahci.c 243125 2012-11-16 03:04:30Z mav $");
29
30 #include "opt_ata.h"
31 #include <sys/param.h>
32 #include <sys/module.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
35 #include <sys/ata.h>
36 #include <sys/bus.h>
37 #include <sys/endian.h>
38 #include <sys/malloc.h>
39 #include <sys/lock.h>
40 #include <sys/mutex.h>
41 #include <sys/sema.h>
42 #include <sys/taskqueue.h>
43 #include <vm/uma.h>
44 #include <machine/stdarg.h>
45 #include <machine/resource.h>
46 #include <machine/bus.h>
47 #include <sys/rman.h>
48 #include <dev/pci/pcivar.h>
49 #include <dev/pci/pcireg.h>
50 #include <dev/ata/ata-all.h>
51 #include <dev/ata/ata-pci.h>
52 #include <ata_if.h>
53
54 /* local prototypes */
55 static int ata_ahci_ch_attach(device_t dev);
56 static int ata_ahci_ch_detach(device_t dev);
57 static int ata_ahci_ch_suspend(device_t dev);
58 static int ata_ahci_ch_resume(device_t dev);
59 static int ata_ahci_ctlr_reset(device_t dev);
60 static void ata_ahci_reset(device_t dev);
61 static int ata_ahci_suspend(device_t dev);
62 static int ata_ahci_status(device_t dev);
63 static int ata_ahci_begin_transaction(struct ata_request *request);
64 static int ata_ahci_end_transaction(struct ata_request *request);
65 static int ata_ahci_pm_read(device_t dev, int port, int reg, u_int32_t *result);
66 static int ata_ahci_pm_write(device_t dev, int port, int reg, u_int32_t result);
67 static int ata_ahci_hardreset(device_t dev, int port, uint32_t *signature);
68 static u_int32_t ata_ahci_softreset(device_t dev, int port);
69 static void ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
70 static int ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *equest);
71 static void ata_ahci_dmainit(device_t dev);
72 static void ata_ahci_start(device_t dev);
73 static void ata_ahci_stop(device_t dev);
74 static void ata_ahci_clo(device_t dev);
75 static void ata_ahci_start_fr(device_t dev);
76 static void ata_ahci_stop_fr(device_t dev);
77
78 /*
79 * AHCI v1.x compliant SATA chipset support functions
80 */
81 static int
ata_ahci_probe(device_t dev)82 ata_ahci_probe(device_t dev)
83 {
84 struct ata_pci_controller *ctlr = device_get_softc(dev);
85 char buffer[64];
86
87 /* is this a possible AHCI candidate ? */
88 if (pci_get_class(dev) != PCIC_STORAGE ||
89 pci_get_subclass(dev) != PCIS_STORAGE_SATA)
90 return (ENXIO);
91
92 /* is this PCI device flagged as an AHCI compliant chip ? */
93 if (pci_get_progif(dev) != PCIP_STORAGE_SATA_AHCI_1_0)
94 return (ENXIO);
95
96 if (bootverbose)
97 sprintf(buffer, "%s (ID=%08x) AHCI controller",
98 ata_pcivendor2str(dev), pci_get_devid(dev));
99 else
100 sprintf(buffer, "%s AHCI controller", ata_pcivendor2str(dev));
101 device_set_desc_copy(dev, buffer);
102 ctlr->chipinit = ata_ahci_chipinit;
103 return (BUS_PROBE_GENERIC);
104 }
105
106 static int
ata_ahci_ata_probe(device_t dev)107 ata_ahci_ata_probe(device_t dev)
108 {
109 struct ata_pci_controller *ctlr = device_get_softc(dev);
110
111 if ((intptr_t)device_get_ivars(dev) >= 0)
112 return (ENXIO);
113 device_set_desc_copy(dev, "AHCI SATA controller");
114 ctlr->chipinit = ata_ahci_chipinit;
115 return (BUS_PROBE_GENERIC);
116 }
117
118 static int
ata_ahci_ata_attach(device_t dev)119 ata_ahci_ata_attach(device_t dev)
120 {
121 struct ata_pci_controller *ctlr = device_get_softc(dev);
122 device_t child;
123 int unit;
124
125 /* do chipset specific setups only needed once */
126 ctlr->legacy = 0;
127 ctlr->ichannels = -1;
128 ctlr->ch_attach = ata_pci_ch_attach;
129 ctlr->ch_detach = ata_pci_ch_detach;
130 ctlr->dev = dev;
131 if (ctlr->chipinit(dev))
132 return ENXIO;
133 /* attach all channels on this controller */
134 for (unit = 0; unit < ctlr->channels; unit++) {
135 if ((ctlr->ichannels & (1 << unit)) == 0)
136 continue;
137 child = device_add_child(dev, "ata",
138 ((unit == 0 || unit == 1) && ctlr->legacy) ?
139 unit : devclass_find_free_unit(ata_devclass, 2));
140 if (child == NULL)
141 device_printf(dev, "failed to add ata child device\n");
142 else
143 device_set_ivars(child, (void *)(intptr_t)unit);
144 }
145 bus_generic_attach(dev);
146 return 0;
147 }
148
149 int
ata_ahci_chipinit(device_t dev)150 ata_ahci_chipinit(device_t dev)
151 {
152 struct ata_pci_controller *ctlr = device_get_softc(dev);
153 int error, speed;
154 u_int32_t caps, version;
155
156 /* if we have a memory BAR(5) we are likely on an AHCI part */
157 ctlr->r_type2 = SYS_RES_MEMORY;
158 ctlr->r_rid2 = PCIR_BAR(5);
159 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
160 &ctlr->r_rid2, RF_ACTIVE)))
161 return ENXIO;
162
163 /* setup interrupt delivery if not done allready by a vendor driver */
164 if (!ctlr->r_irq) {
165 if (ata_setup_interrupt(dev, ata_generic_intr)) {
166 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2);
167 return ENXIO;
168 }
169 }
170 else
171 device_printf(dev, "AHCI called from vendor specific driver\n");
172
173 /* reset controller */
174 if ((error = ata_ahci_ctlr_reset(dev)) != 0) {
175 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2);
176 return (error);
177 };
178
179 /* get the number of HW channels */
180 ctlr->ichannels = ATA_INL(ctlr->r_res2, ATA_AHCI_PI);
181 ctlr->channels = MAX(flsl(ctlr->ichannels),
182 (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_NPMASK) + 1);
183 if (pci_get_devid(dev) == ATA_M88SE6111)
184 ctlr->channels = 1;
185 else if (pci_get_devid(dev) == ATA_M88SE6121)
186 ctlr->channels = 2;
187 else if (pci_get_devid(dev) == ATA_M88SE6141 ||
188 pci_get_devid(dev) == ATA_M88SE6145)
189 ctlr->channels = 4;
190
191 ctlr->reset = ata_ahci_reset;
192 ctlr->ch_attach = ata_ahci_ch_attach;
193 ctlr->ch_detach = ata_ahci_ch_detach;
194 ctlr->ch_suspend = ata_ahci_ch_suspend;
195 ctlr->ch_resume = ata_ahci_ch_resume;
196 ctlr->setmode = ata_sata_setmode;
197 ctlr->getrev = ata_sata_getrev;
198 ctlr->suspend = ata_ahci_suspend;
199 ctlr->resume = ata_ahci_ctlr_reset;
200
201 /* announce we support the HW */
202 version = ATA_INL(ctlr->r_res2, ATA_AHCI_VS);
203 caps = ATA_INL(ctlr->r_res2, ATA_AHCI_CAP);
204 speed = (caps & ATA_AHCI_CAP_ISS) >> ATA_AHCI_CAP_ISS_SHIFT;
205 device_printf(dev,
206 "AHCI v%x.%02x controller with %d %sGbps ports, PM %s\n",
207 ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f),
208 ((version >> 4) & 0xf0) + (version & 0x0f),
209 (caps & ATA_AHCI_CAP_NPMASK) + 1,
210 ((speed == 1) ? "1.5":((speed == 2) ? "3":
211 ((speed == 3) ? "6":"?"))),
212 (caps & ATA_AHCI_CAP_SPM) ?
213 "supported" : "not supported");
214 if (bootverbose) {
215 device_printf(dev, "Caps:%s%s%s%s%s%s%s%s %sGbps",
216 (caps & ATA_AHCI_CAP_64BIT) ? " 64bit":"",
217 (caps & ATA_AHCI_CAP_SNCQ) ? " NCQ":"",
218 (caps & ATA_AHCI_CAP_SSNTF) ? " SNTF":"",
219 (caps & ATA_AHCI_CAP_SMPS) ? " MPS":"",
220 (caps & ATA_AHCI_CAP_SSS) ? " SS":"",
221 (caps & ATA_AHCI_CAP_SALP) ? " ALP":"",
222 (caps & ATA_AHCI_CAP_SAL) ? " AL":"",
223 (caps & ATA_AHCI_CAP_SCLO) ? " CLO":"",
224 ((speed == 1) ? "1.5":((speed == 2) ? "3":
225 ((speed == 3) ? "6":"?"))));
226 printf("%s%s%s%s%s%s %dcmd%s%s%s %dports\n",
227 (caps & ATA_AHCI_CAP_SAM) ? " AM":"",
228 (caps & ATA_AHCI_CAP_SPM) ? " PM":"",
229 (caps & ATA_AHCI_CAP_FBSS) ? " FBS":"",
230 (caps & ATA_AHCI_CAP_PMD) ? " PMD":"",
231 (caps & ATA_AHCI_CAP_SSC) ? " SSC":"",
232 (caps & ATA_AHCI_CAP_PSC) ? " PSC":"",
233 ((caps & ATA_AHCI_CAP_NCS) >> ATA_AHCI_CAP_NCS_SHIFT) + 1,
234 (caps & ATA_AHCI_CAP_CCCS) ? " CCC":"",
235 (caps & ATA_AHCI_CAP_EMS) ? " EM":"",
236 (caps & ATA_AHCI_CAP_SXS) ? " eSATA":"",
237 (caps & ATA_AHCI_CAP_NPMASK) + 1);
238 }
239 return 0;
240 }
241
242 static int
ata_ahci_ctlr_reset(device_t dev)243 ata_ahci_ctlr_reset(device_t dev)
244 {
245 struct ata_pci_controller *ctlr = device_get_softc(dev);
246 int timeout;
247
248 /* enable AHCI mode */
249 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE);
250
251 /* reset AHCI controller */
252 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE|ATA_AHCI_GHC_HR);
253 for (timeout = 1000; timeout > 0; timeout--) {
254 DELAY(1000);
255 if ((ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) & ATA_AHCI_GHC_HR) == 0)
256 break;
257 }
258 if (timeout == 0) {
259 device_printf(dev, "AHCI controller reset failure\n");
260 return ENXIO;
261 }
262
263 /* reenable AHCI mode */
264 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE);
265
266 /* clear interrupts */
267 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, ATA_INL(ctlr->r_res2, ATA_AHCI_IS));
268
269 /* enable AHCI interrupts */
270 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC,
271 ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_IE);
272
273 return 0;
274 }
275
276 static int
ata_ahci_suspend(device_t dev)277 ata_ahci_suspend(device_t dev)
278 {
279 struct ata_pci_controller *ctlr = device_get_softc(dev);
280
281 /* disable interupts so the state change(s) doesn't trigger */
282 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC,
283 ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) & (~ATA_AHCI_GHC_IE));
284 return 0;
285 }
286
287 static int
ata_ahci_ch_attach(device_t dev)288 ata_ahci_ch_attach(device_t dev)
289 {
290 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
291 struct ata_channel *ch = device_get_softc(dev);
292 int offset = ch->unit << 7;
293
294 ata_ahci_dmainit(dev);
295
296 /* set the SATA resources */
297 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
298 ch->r_io[ATA_SSTATUS].offset = ATA_AHCI_P_SSTS + offset;
299 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
300 ch->r_io[ATA_SERROR].offset = ATA_AHCI_P_SERR + offset;
301 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
302 ch->r_io[ATA_SCONTROL].offset = ATA_AHCI_P_SCTL + offset;
303 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2;
304 ch->r_io[ATA_SACTIVE].offset = ATA_AHCI_P_SACT + offset;
305
306 ch->hw.status = ata_ahci_status;
307 ch->hw.begin_transaction = ata_ahci_begin_transaction;
308 ch->hw.end_transaction = ata_ahci_end_transaction;
309 ch->hw.command = NULL; /* not used here */
310 ch->hw.softreset = ata_ahci_softreset;
311 ch->hw.pm_read = ata_ahci_pm_read;
312 ch->hw.pm_write = ata_ahci_pm_write;
313 ch->flags |= ATA_NO_SLAVE;
314 ch->flags |= ATA_SATA;
315
316 ata_ahci_ch_resume(dev);
317 return 0;
318 }
319
320 static int
ata_ahci_ch_detach(device_t dev)321 ata_ahci_ch_detach(device_t dev)
322 {
323 struct ata_channel *ch = device_get_softc(dev);
324
325 if (ch->dma.work_tag && ch->dma.work_map)
326 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
327 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
328 ata_ahci_ch_suspend(dev);
329 ata_dmafini(dev);
330 return (0);
331 }
332
333 static int
ata_ahci_ch_suspend(device_t dev)334 ata_ahci_ch_suspend(device_t dev)
335 {
336 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
337 struct ata_channel *ch = device_get_softc(dev);
338 int offset = ch->unit << 7;
339
340 /* Disable port interrupts. */
341 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset, 0);
342 /* Reset command register. */
343 ata_ahci_stop(dev);
344 ata_ahci_stop_fr(dev);
345 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 0);
346
347 /* Allow everything including partial and slumber modes. */
348 ATA_IDX_OUTL(ch, ATA_SCONTROL, 0);
349 /* Request slumber mode transition and give some time to get there. */
350 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, ATA_AHCI_P_CMD_SLUMBER);
351 DELAY(100);
352 /* Disable PHY. */
353 ATA_IDX_OUTL(ch, ATA_SCONTROL, ATA_SC_DET_DISABLE);
354
355 return (0);
356 }
357
358 static int
ata_ahci_ch_resume(device_t dev)359 ata_ahci_ch_resume(device_t dev)
360 {
361 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
362 struct ata_channel *ch = device_get_softc(dev);
363 uint64_t work;
364 int offset = ch->unit << 7;
365
366 /* Disable port interrupts */
367 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset, 0);
368
369 /* setup work areas */
370 work = ch->dma.work_bus + ATA_AHCI_CL_OFFSET;
371 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLB + offset, work & 0xffffffff);
372 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLBU + offset, work >> 32);
373
374 work = ch->dma.work_bus + ATA_AHCI_FB_OFFSET;
375 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FB + offset, work & 0xffffffff);
376 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FBU + offset, work >> 32);
377
378 /* activate the channel and power/spin up device */
379 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
380 (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD |
381 ((ch->pm_level > 1) ? ATA_AHCI_P_CMD_ALPE : 0) |
382 ((ch->pm_level > 2) ? ATA_AHCI_P_CMD_ASP : 0 )));
383 ata_ahci_start_fr(dev);
384 ata_ahci_start(dev);
385
386 return (0);
387 }
388
389 static int
ata_ahci_status(device_t dev)390 ata_ahci_status(device_t dev)
391 {
392 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
393 struct ata_channel *ch = device_get_softc(dev);
394 u_int32_t action = ATA_INL(ctlr->r_res2, ATA_AHCI_IS);
395 int offset = ch->unit << 7;
396
397 #define ATA_AHCI_STATBITS \
398 (ATA_AHCI_P_IX_IF|ATA_AHCI_P_IX_HBD|ATA_AHCI_P_IX_HBF|ATA_AHCI_P_IX_TFE)
399
400 if (action & (1 << ch->unit)) {
401 u_int32_t istatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset);
402 u_int32_t cstatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CI + offset);
403
404 /* clear interrupt(s) */
405 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, istatus);
406 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, 1 << ch->unit);
407
408 /* do we have any PHY events ? */
409 if (istatus & (ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC))
410 ata_sata_phy_check_events(dev, -1);
411
412 /* do we have a potentially hanging engine to take care of? */
413 /* XXX SOS what todo on NCQ */
414 if ((istatus & ATA_AHCI_STATBITS) && (cstatus & 1)) {
415
416 u_int32_t cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
417 int timeout = 0;
418
419 /* kill off all activity on this channel */
420 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
421 cmd & ~(ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST));
422
423 /* XXX SOS this is not entirely wrong */
424 do {
425 DELAY(1000);
426 if (timeout++ > 1000) {
427 device_printf(dev, "stopping AHCI engine failed\n");
428 break;
429 }
430 } while (ATA_INL(ctlr->r_res2,
431 ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR);
432
433 /* start operations on this channel */
434 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
435 cmd | (ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST));
436
437 return 1;
438 }
439 else
440 /* XXX SOS what todo on NCQ */
441 return (!(cstatus & 1));
442 }
443 return 0;
444 }
445
446 /* must be called with ATA channel locked and state_mtx held */
447 static int
ata_ahci_begin_transaction(struct ata_request * request)448 ata_ahci_begin_transaction(struct ata_request *request)
449 {
450 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent));
451 struct ata_channel *ch = device_get_softc(request->parent);
452 struct ata_ahci_cmd_tab *ctp;
453 struct ata_ahci_cmd_list *clp;
454 int offset = ch->unit << 7;
455 int port = request->unit & 0x0f;
456 int entries = 0;
457 int fis_size;
458
459 /* get a piece of the workspace for this request */
460 ctp = (struct ata_ahci_cmd_tab *)
461 (ch->dma.work + ATA_AHCI_CT_OFFSET);
462
463 /* setup the FIS for this request */
464 if (!(fis_size = ata_ahci_setup_fis(ctp, request))) {
465 device_printf(request->parent, "setting up SATA FIS failed\n");
466 request->result = EIO;
467 return ATA_OP_FINISHED;
468 }
469
470 /* if request moves data setup and load SG list */
471 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
472 if (ch->dma.load(request, ctp->prd_tab, &entries)) {
473 device_printf(request->parent, "setting up DMA failed\n");
474 request->result = EIO;
475 return ATA_OP_FINISHED;
476 }
477 }
478
479 /* setup the command list entry */
480 clp = (struct ata_ahci_cmd_list *)
481 (ch->dma.work + ATA_AHCI_CL_OFFSET);
482
483 clp->prd_length = entries;
484 clp->cmd_flags = (request->flags & ATA_R_WRITE ? ATA_AHCI_CMD_WRITE : 0) |
485 (request->flags & ATA_R_ATAPI ?
486 (ATA_AHCI_CMD_ATAPI | ATA_AHCI_CMD_PREFETCH) : 0) |
487 (fis_size / sizeof(u_int32_t)) |
488 (port << 12);
489 clp->bytecount = 0;
490 clp->cmd_table_phys = htole64(ch->dma.work_bus + ATA_AHCI_CT_OFFSET);
491
492 /* set command type bit */
493 if (request->flags & ATA_R_ATAPI)
494 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
495 ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) |
496 ATA_AHCI_P_CMD_ATAPI);
497 else
498 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
499 ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) &
500 ~ATA_AHCI_P_CMD_ATAPI);
501
502 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
503 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
504
505 /* issue command to controller */
506 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CI + offset, 1);
507
508 if (!(request->flags & ATA_R_ATAPI)) {
509 /* device reset doesn't interrupt */
510 if (request->u.ata.command == ATA_DEVICE_RESET) {
511 u_int32_t tf_data;
512 int timeout = 1000000;
513
514 do {
515 DELAY(10);
516 tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + (ch->unit<<7));
517 } while ((tf_data & ATA_S_BUSY) && timeout--);
518 if (bootverbose)
519 device_printf(ch->dev, "device_reset timeout=%dus\n",
520 (1000000-timeout)*10);
521 request->status = tf_data;
522 if (request->status & ATA_S_ERROR)
523 request->error = tf_data >> 8;
524 return ATA_OP_FINISHED;
525 }
526 }
527
528 /* start the timeout */
529 callout_reset(&request->callout, request->timeout * hz,
530 (timeout_t*)ata_timeout, request);
531 return ATA_OP_CONTINUES;
532 }
533
534 /* must be called with ATA channel locked and state_mtx held */
535 static int
ata_ahci_end_transaction(struct ata_request * request)536 ata_ahci_end_transaction(struct ata_request *request)
537 {
538 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent));
539 struct ata_channel *ch = device_get_softc(request->parent);
540 struct ata_ahci_cmd_list *clp;
541 u_int32_t tf_data;
542 int offset = ch->unit << 7;
543
544 /* kill the timeout */
545 callout_stop(&request->callout);
546
547 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
548 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
549
550 /* get status */
551 tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + offset);
552 request->status = tf_data;
553
554 /* if error status get details */
555 if (request->status & ATA_S_ERROR)
556 request->error = tf_data >> 8;
557
558 /* Read back registers to the request struct. */
559 if ((request->flags & ATA_R_ATAPI) == 0 &&
560 ((request->status & ATA_S_ERROR) ||
561 (request->flags & (ATA_R_CONTROL | ATA_R_NEEDRESULT)))) {
562 u_int8_t *fis = ch->dma.work + ATA_AHCI_FB_OFFSET + 0x40;
563
564 request->u.ata.count = fis[12] | ((u_int16_t)fis[13] << 8);
565 request->u.ata.lba = fis[4] | ((u_int64_t)fis[5] << 8) |
566 ((u_int64_t)fis[6] << 16);
567 if (request->flags & ATA_R_48BIT)
568 request->u.ata.lba |= ((u_int64_t)fis[8] << 24) |
569 ((u_int64_t)fis[9] << 32) |
570 ((u_int64_t)fis[10] << 40);
571 else
572 request->u.ata.lba |= ((u_int64_t)(fis[7] & 0x0f) << 24);
573 }
574
575 /* record how much data we actually moved */
576 clp = (struct ata_ahci_cmd_list *)
577 (ch->dma.work + ATA_AHCI_CL_OFFSET);
578 request->donecount = le32toh(clp->bytecount);
579
580 /* release SG list etc */
581 ch->dma.unload(request);
582
583 return ATA_OP_FINISHED;
584 }
585
586 static int
ata_ahci_issue_cmd(device_t dev,u_int16_t flags,int timeout)587 ata_ahci_issue_cmd(device_t dev, u_int16_t flags, int timeout)
588 {
589 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
590 struct ata_channel *ch = device_get_softc(dev);
591 struct ata_ahci_cmd_list *clp =
592 (struct ata_ahci_cmd_list *)(ch->dma.work + ATA_AHCI_CL_OFFSET);
593 struct ata_ahci_cmd_tab *ctp =
594 (struct ata_ahci_cmd_tab *)(ch->dma.work + ATA_AHCI_CT_OFFSET);
595 u_int32_t status = 0;
596 int offset = ch->unit << 7;
597 int port = (ctp->cfis[1] & 0x0f);
598 int count;
599
600 clp->prd_length = 0;
601 clp->cmd_flags = (20 / sizeof(u_int32_t)) | flags | (port << 12);
602 clp->bytecount = 0;
603 clp->cmd_table_phys = htole64(ch->dma.work_bus + ATA_AHCI_CT_OFFSET);
604
605 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
606 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
607
608 /* issue command to controller */
609 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CI + offset, 1);
610
611 /* poll for command finished */
612 for (count = 0; count < timeout; count++) {
613 DELAY(1000);
614 if (!((status = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CI + offset)) & 1))
615 break;
616 }
617
618 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
619 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
620
621 /* clear interrupts */
622 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset,
623 ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset));
624
625 if (timeout && (count >= timeout)) {
626 if (bootverbose) {
627 device_printf(dev, "ahci_issue_cmd timeout: %d of %dms, status=%08x\n",
628 count, timeout, status);
629 }
630 return EIO;
631 }
632
633 return 0;
634 }
635
636 static int
ata_ahci_pm_read(device_t dev,int port,int reg,u_int32_t * result)637 ata_ahci_pm_read(device_t dev, int port, int reg, u_int32_t *result)
638 {
639 struct ata_channel *ch = device_get_softc(dev);
640 struct ata_ahci_cmd_tab *ctp =
641 (struct ata_ahci_cmd_tab *)(ch->dma.work + ATA_AHCI_CT_OFFSET);
642 u_int8_t *fis = ch->dma.work + ATA_AHCI_FB_OFFSET + 0x40;
643
644 if (port < 0) {
645 *result = ATA_IDX_INL(ch, reg);
646 return (0);
647 }
648 if (port < ATA_PM) {
649 switch (reg) {
650 case ATA_SSTATUS:
651 reg = 0;
652 break;
653 case ATA_SERROR:
654 reg = 1;
655 break;
656 case ATA_SCONTROL:
657 reg = 2;
658 break;
659 default:
660 return (EINVAL);
661 }
662 }
663 bzero(ctp->cfis, 64);
664 ctp->cfis[0] = 0x27; /* host to device */
665 ctp->cfis[1] = 0x8f; /* command FIS to PM port */
666 ctp->cfis[2] = ATA_READ_PM;
667 ctp->cfis[3] = reg;
668 ctp->cfis[7] = port | ATA_D_LBA;
669 ctp->cfis[15] = ATA_A_4BIT;
670
671 if (ata_ahci_issue_cmd(dev, 0, 10)) {
672 device_printf(dev, "error reading PM port\n");
673 return EIO;
674 }
675
676 *result = fis[12] | (fis[4] << 8) | (fis[5] << 16) | (fis[6] << 24);
677 return 0;
678 }
679
680 static int
ata_ahci_pm_write(device_t dev,int port,int reg,u_int32_t value)681 ata_ahci_pm_write(device_t dev, int port, int reg, u_int32_t value)
682 {
683 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
684 struct ata_channel *ch = device_get_softc(dev);
685 struct ata_ahci_cmd_tab *ctp =
686 (struct ata_ahci_cmd_tab *)(ch->dma.work + ATA_AHCI_CT_OFFSET);
687 int offset = ch->unit << 7;
688
689 if (port < 0) {
690 ATA_IDX_OUTL(ch, reg, value);
691 return (0);
692 }
693 if (port < ATA_PM) {
694 switch (reg) {
695 case ATA_SSTATUS:
696 reg = 0;
697 break;
698 case ATA_SERROR:
699 reg = 1;
700 break;
701 case ATA_SCONTROL:
702 reg = 2;
703 break;
704 default:
705 return (EINVAL);
706 }
707 }
708 bzero(ctp->cfis, 64);
709 ctp->cfis[0] = 0x27; /* host to device */
710 ctp->cfis[1] = 0x8f; /* command FIS to PM port */
711 ctp->cfis[2] = ATA_WRITE_PM;
712 ctp->cfis[3] = reg;
713 ctp->cfis[7] = port | ATA_D_LBA;
714 ctp->cfis[12] = value & 0xff;
715 ctp->cfis[4] = (value >> 8) & 0xff;
716 ctp->cfis[5] = (value >> 16) & 0xff;
717 ctp->cfis[6] = (value >> 24) & 0xff;
718 ctp->cfis[15] = ATA_A_4BIT;
719
720 if (ata_ahci_issue_cmd(dev, 0, 100)) {
721 device_printf(dev, "error writing PM port\n");
722 return ATA_E_ABORT;
723 }
724
725 return (ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + offset) >> 8) & 0xff;
726 }
727
728 static void
ata_ahci_stop(device_t dev)729 ata_ahci_stop(device_t dev)
730 {
731 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
732 struct ata_channel *ch = device_get_softc(dev);
733 u_int32_t cmd;
734 int offset = ch->unit << 7;
735 int timeout;
736
737 /* kill off all activity on this channel */
738 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
739 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
740 cmd & ~ATA_AHCI_P_CMD_ST);
741
742 /* XXX SOS this is not entirely wrong */
743 timeout = 0;
744 do {
745 DELAY(1000);
746 if (timeout++ > 1000) {
747 device_printf(dev, "stopping AHCI engine failed\n");
748 break;
749 }
750 }
751 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR);
752 }
753
754 static void
ata_ahci_clo(device_t dev)755 ata_ahci_clo(device_t dev)
756 {
757 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
758 struct ata_channel *ch = device_get_softc(dev);
759 u_int32_t cmd;
760 int offset = ch->unit << 7;
761 int timeout;
762
763 /* issue Command List Override if supported */
764 if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_SCLO) {
765 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
766 cmd |= ATA_AHCI_P_CMD_CLO;
767 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, cmd);
768 timeout = 0;
769 do {
770 DELAY(1000);
771 if (timeout++ > 1000) {
772 device_printf(dev, "executing CLO failed\n");
773 break;
774 }
775 }
776 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD+offset)&ATA_AHCI_P_CMD_CLO);
777 }
778 }
779
780 static void
ata_ahci_start(device_t dev)781 ata_ahci_start(device_t dev)
782 {
783 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
784 struct ata_channel *ch = device_get_softc(dev);
785 u_int32_t cmd;
786 int offset = ch->unit << 7;
787
788 /* clear SATA error register */
789 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
790
791 /* clear any interrupts pending on this channel */
792 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset,
793 ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset));
794
795 /* start operations on this channel */
796 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
797 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
798 cmd | ATA_AHCI_P_CMD_ST |
799 (ch->devices & ATA_PORTMULTIPLIER ? ATA_AHCI_P_CMD_PMA : 0));
800 }
801
802 static void
ata_ahci_stop_fr(device_t dev)803 ata_ahci_stop_fr(device_t dev)
804 {
805 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
806 struct ata_channel *ch = device_get_softc(dev);
807 u_int32_t cmd;
808 int offset = ch->unit << 7;
809 int timeout;
810
811 /* kill off all activity on this channel */
812 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
813 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, cmd & ~ATA_AHCI_P_CMD_FRE);
814
815 timeout = 0;
816 do {
817 DELAY(1000);
818 if (timeout++ > 1000) {
819 device_printf(dev, "stopping AHCI FR engine failed\n");
820 break;
821 }
822 }
823 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_FR);
824 }
825
826 static void
ata_ahci_start_fr(device_t dev)827 ata_ahci_start_fr(device_t dev)
828 {
829 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
830 struct ata_channel *ch = device_get_softc(dev);
831 u_int32_t cmd;
832 int offset = ch->unit << 7;
833
834 /* start FIS reception on this channel */
835 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
836 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, cmd | ATA_AHCI_P_CMD_FRE);
837 }
838
839 static int
ata_ahci_wait_ready(device_t dev,int t)840 ata_ahci_wait_ready(device_t dev, int t)
841 {
842 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
843 struct ata_channel *ch = device_get_softc(dev);
844 int offset = ch->unit << 7;
845 int timeout = 0;
846 uint32_t val;
847
848 while ((val = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + offset)) &
849 (ATA_S_BUSY | ATA_S_DRQ)) {
850 DELAY(1000);
851 if (timeout++ > t) {
852 device_printf(dev, "port is not ready (timeout %dms) tfd = %08x\n", t, val);
853 return (EBUSY);
854 }
855 }
856 if (bootverbose)
857 device_printf(dev, "ready wait time=%dms\n", timeout);
858 return (0);
859 }
860
861 static int
ata_ahci_hardreset(device_t dev,int port,uint32_t * signature)862 ata_ahci_hardreset(device_t dev, int port, uint32_t *signature)
863 {
864 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
865 struct ata_channel *ch = device_get_softc(dev);
866 int offset = ch->unit << 7;
867
868 *signature = 0xffffffff;
869 ata_ahci_stop(dev);
870 /* Reset port */
871 if (!ata_sata_phy_reset(dev, port, 0))
872 return (ENOENT);
873 /* Wait for clearing busy status. */
874 if (ata_ahci_wait_ready(dev, 15000)) {
875 device_printf(dev, "hardware reset timeout\n");
876 return (EBUSY);
877 }
878 *signature = ATA_INL(ctlr->r_res2, ATA_AHCI_P_SIG + offset);
879 ata_ahci_start(dev);
880 return (0);
881 }
882
883 static u_int32_t
ata_ahci_softreset(device_t dev,int port)884 ata_ahci_softreset(device_t dev, int port)
885 {
886 struct ata_channel *ch = device_get_softc(dev);
887 struct ata_ahci_cmd_tab *ctp =
888 (struct ata_ahci_cmd_tab *)(ch->dma.work + ATA_AHCI_CT_OFFSET);
889 u_int8_t *fis = ch->dma.work + ATA_AHCI_FB_OFFSET + 0x40;
890
891 if (bootverbose)
892 device_printf(dev, "software reset port %d...\n", port);
893
894 /* kick controller into sane state */
895 ata_ahci_stop(dev);
896 ata_ahci_clo(dev);
897 ata_ahci_start(dev);
898
899 /* pull reset active */
900 bzero(ctp->cfis, 64);
901 ctp->cfis[0] = 0x27;
902 ctp->cfis[1] = port & 0x0f;
903 //ctp->cfis[7] = ATA_D_LBA | ATA_D_IBM;
904 ctp->cfis[15] = (ATA_A_4BIT | ATA_A_RESET);
905
906 if (ata_ahci_issue_cmd(dev, ATA_AHCI_CMD_RESET | ATA_AHCI_CMD_CLR_BUSY,100)) {
907 device_printf(dev, "software reset set timeout\n");
908 return (-1);
909 }
910
911 ata_udelay(50);
912
913 /* pull reset inactive -> device softreset */
914 bzero(ctp->cfis, 64);
915 ctp->cfis[0] = 0x27;
916 ctp->cfis[1] = port & 0x0f;
917 //ctp->cfis[7] = ATA_D_LBA | ATA_D_IBM;
918 ctp->cfis[15] = ATA_A_4BIT;
919 ata_ahci_issue_cmd(dev, 0, 3000);
920
921 if (ata_ahci_wait_ready(dev, 0)) {
922 device_printf(dev, "software reset clear timeout\n");
923 return (-1);
924 }
925
926 return (((u_int32_t)fis[6] << 24) |
927 ((u_int32_t)fis[5] << 16) |
928 ((u_int32_t)fis[4] << 8) |
929 (u_int32_t)fis[12]);
930 }
931
932 static void
ata_ahci_reset(device_t dev)933 ata_ahci_reset(device_t dev)
934 {
935 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
936 struct ata_channel *ch = device_get_softc(dev);
937 u_int32_t signature;
938 int offset = ch->unit << 7;
939
940 if (bootverbose)
941 device_printf(dev, "AHCI reset...\n");
942
943 /* Disable port interrupts */
944 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset, 0);
945
946 if (ata_ahci_hardreset(dev, -1, &signature)) {
947 if (bootverbose)
948 device_printf(dev, "AHCI reset done: phy reset found no device\n");
949 ch->devices = 0;
950
951 /* enable wanted port interrupts */
952 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset,
953 (ATA_AHCI_P_IX_CPD | ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC));
954 return;
955 }
956
957 /* enable wanted port interrupts */
958 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset,
959 (ATA_AHCI_P_IX_CPD | ATA_AHCI_P_IX_TFE | ATA_AHCI_P_IX_HBF |
960 ATA_AHCI_P_IX_HBD | ATA_AHCI_P_IX_IF | ATA_AHCI_P_IX_OF |
961 ((ch->pm_level == 0) ? ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC : 0) |
962 ATA_AHCI_P_IX_DP | ATA_AHCI_P_IX_UF | ATA_AHCI_P_IX_SDB |
963 ATA_AHCI_P_IX_DS | ATA_AHCI_P_IX_PS | ATA_AHCI_P_IX_DHR));
964 /*
965 * Only probe for PortMultiplier if HW has support.
966 * Ignore Marvell, which is not working,
967 */
968 if ((ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_SPM) &&
969 pci_get_vendor(ctlr->dev) != 0x11ab) {
970 signature = ata_ahci_softreset(dev, ATA_PM);
971 /* Workaround for some ATI chips, failing to soft-reset
972 * when port multiplicator supported, but absent.
973 * XXX: We can also check PxIS.IPMS==1 here to be sure. */
974 if (signature == 0xffffffff)
975 signature = ata_ahci_softreset(dev, 0);
976 } else {
977 signature = ata_ahci_softreset(dev, 0);
978 }
979 if (bootverbose)
980 device_printf(dev, "SIGNATURE: %08x\n", signature);
981
982 switch (signature >> 16) {
983 case 0x0000:
984 ch->devices = ATA_ATA_MASTER;
985 break;
986 case 0x9669:
987 ch->devices = ATA_PORTMULTIPLIER;
988 ata_pm_identify(dev);
989 break;
990 case 0xeb14:
991 ch->devices = ATA_ATAPI_MASTER;
992 break;
993 default: /* SOS XXX */
994 if (bootverbose)
995 device_printf(dev, "Unknown signature, assuming disk device\n");
996 ch->devices = ATA_ATA_MASTER;
997 }
998 if (bootverbose)
999 device_printf(dev, "AHCI reset done: devices=%08x\n", ch->devices);
1000 }
1001
1002 static void
ata_ahci_dmasetprd(void * xsc,bus_dma_segment_t * segs,int nsegs,int error)1003 ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
1004 {
1005 struct ata_dmasetprd_args *args = xsc;
1006 struct ata_ahci_dma_prd *prd = args->dmatab;
1007 int i;
1008
1009 if (!(args->error = error)) {
1010 for (i = 0; i < nsegs; i++) {
1011 prd[i].dba = htole64(segs[i].ds_addr);
1012 prd[i].dbc = htole32((segs[i].ds_len - 1) & ATA_AHCI_PRD_MASK);
1013 }
1014 }
1015
1016 KASSERT(nsegs <= ATA_AHCI_DMA_ENTRIES, ("too many DMA segment entries\n"));
1017 args->nsegs = nsegs;
1018 }
1019
1020 static void
ata_ahci_dmainit(device_t dev)1021 ata_ahci_dmainit(device_t dev)
1022 {
1023 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
1024 struct ata_channel *ch = device_get_softc(dev);
1025
1026 /* note start and stop are not used here */
1027 ch->dma.setprd = ata_ahci_dmasetprd;
1028 ch->dma.max_iosize = (ATA_AHCI_DMA_ENTRIES - 1) * PAGE_SIZE;
1029 if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_64BIT)
1030 ch->dma.max_address = BUS_SPACE_MAXADDR;
1031 ata_dmainit(dev);
1032 }
1033
1034 static int
ata_ahci_setup_fis(struct ata_ahci_cmd_tab * ctp,struct ata_request * request)1035 ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *request)
1036 {
1037 bzero(ctp->cfis, 64);
1038 if (request->flags & ATA_R_ATAPI) {
1039 bzero(ctp->acmd, 32);
1040 bcopy(request->u.atapi.ccb, ctp->acmd, 16);
1041 }
1042 return ata_request2fis_h2d(request, &ctp->cfis[0]);
1043 }
1044
1045 ATA_DECLARE_DRIVER(ata_ahci);
1046 static device_method_t ata_ahci_ata_methods[] = {
1047 DEVMETHOD(device_probe, ata_ahci_ata_probe),
1048 DEVMETHOD(device_attach, ata_ahci_ata_attach),
1049 DEVMETHOD(device_detach, ata_pci_detach),
1050 DEVMETHOD(device_suspend, ata_pci_suspend),
1051 DEVMETHOD(device_resume, ata_pci_resume),
1052 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1053 DEVMETHOD(bus_read_ivar, ata_pci_read_ivar),
1054 DEVMETHOD(bus_write_ivar, ata_pci_write_ivar),
1055 DEVMETHOD(bus_alloc_resource, ata_pci_alloc_resource),
1056 DEVMETHOD(bus_release_resource, ata_pci_release_resource),
1057 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
1058 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
1059 DEVMETHOD(bus_setup_intr, ata_pci_setup_intr),
1060 DEVMETHOD(bus_teardown_intr, ata_pci_teardown_intr),
1061 DEVMETHOD_END
1062 };
1063 static driver_t ata_ahci_ata_driver = {
1064 "atapci",
1065 ata_ahci_ata_methods,
1066 sizeof(struct ata_pci_controller)
1067 };
1068 DRIVER_MODULE(ata_ahci_ata, atapci, ata_ahci_ata_driver, ata_pci_devclass,
1069 NULL, NULL);
1070