1 //===-- SparcAsmBackend.cpp - Sparc Assembler Backend ---------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9
10 #include "llvm/MC/MCAsmBackend.h"
11 #include "MCTargetDesc/SparcMCTargetDesc.h"
12 #include "MCTargetDesc/SparcFixupKinds.h"
13 #include "llvm/MC/MCELFObjectWriter.h"
14 #include "llvm/MC/MCFixupKindInfo.h"
15 #include "llvm/MC/MCObjectWriter.h"
16 #include "llvm/Support/TargetRegistry.h"
17
18 using namespace llvm;
19
adjustFixupValue(unsigned Kind,uint64_t Value)20 static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
21 switch (Kind) {
22 default:
23 llvm_unreachable("Unknown fixup kind!");
24 case FK_Data_1:
25 case FK_Data_2:
26 case FK_Data_4:
27 case FK_Data_8:
28 return Value;
29
30 case Sparc::fixup_sparc_wplt30:
31 case Sparc::fixup_sparc_call30:
32 return (Value >> 2) & 0x3fffffff;
33
34 case Sparc::fixup_sparc_br22:
35 return (Value >> 2) & 0x3fffff;
36
37 case Sparc::fixup_sparc_br19:
38 return (Value >> 2) & 0x7ffff;
39
40 case Sparc::fixup_sparc_pc22:
41 case Sparc::fixup_sparc_got22:
42 case Sparc::fixup_sparc_tls_gd_hi22:
43 case Sparc::fixup_sparc_tls_ldm_hi22:
44 case Sparc::fixup_sparc_tls_ie_hi22:
45 case Sparc::fixup_sparc_hi22:
46 return (Value >> 10) & 0x3fffff;
47
48 case Sparc::fixup_sparc_pc10:
49 case Sparc::fixup_sparc_got10:
50 case Sparc::fixup_sparc_tls_gd_lo10:
51 case Sparc::fixup_sparc_tls_ldm_lo10:
52 case Sparc::fixup_sparc_tls_ie_lo10:
53 case Sparc::fixup_sparc_lo10:
54 return Value & 0x3ff;
55
56 case Sparc::fixup_sparc_tls_ldo_hix22:
57 case Sparc::fixup_sparc_tls_le_hix22:
58 return (~Value >> 10) & 0x3fffff;
59
60 case Sparc::fixup_sparc_tls_ldo_lox10:
61 case Sparc::fixup_sparc_tls_le_lox10:
62 return (~(~Value & 0x3ff)) & 0x1fff;
63
64 case Sparc::fixup_sparc_h44:
65 return (Value >> 22) & 0x3fffff;
66
67 case Sparc::fixup_sparc_m44:
68 return (Value >> 12) & 0x3ff;
69
70 case Sparc::fixup_sparc_l44:
71 return Value & 0xfff;
72
73 case Sparc::fixup_sparc_hh:
74 return (Value >> 42) & 0x3fffff;
75
76 case Sparc::fixup_sparc_hm:
77 return (Value >> 32) & 0x3ff;
78
79 case Sparc::fixup_sparc_tls_gd_add:
80 case Sparc::fixup_sparc_tls_gd_call:
81 case Sparc::fixup_sparc_tls_ldm_add:
82 case Sparc::fixup_sparc_tls_ldm_call:
83 case Sparc::fixup_sparc_tls_ldo_add:
84 case Sparc::fixup_sparc_tls_ie_ld:
85 case Sparc::fixup_sparc_tls_ie_ldx:
86 case Sparc::fixup_sparc_tls_ie_add:
87 return 0;
88 }
89 }
90
91 namespace {
92 class SparcAsmBackend : public MCAsmBackend {
93 const Target &TheTarget;
94 public:
SparcAsmBackend(const Target & T)95 SparcAsmBackend(const Target &T) : MCAsmBackend(), TheTarget(T) {}
96
getNumFixupKinds() const97 unsigned getNumFixupKinds() const {
98 return Sparc::NumTargetFixupKinds;
99 }
100
getFixupKindInfo(MCFixupKind Kind) const101 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
102 const static MCFixupKindInfo Infos[Sparc::NumTargetFixupKinds] = {
103 // name offset bits flags
104 { "fixup_sparc_call30", 2, 30, MCFixupKindInfo::FKF_IsPCRel },
105 { "fixup_sparc_br22", 10, 22, MCFixupKindInfo::FKF_IsPCRel },
106 { "fixup_sparc_br19", 13, 19, MCFixupKindInfo::FKF_IsPCRel },
107 { "fixup_sparc_hi22", 10, 22, 0 },
108 { "fixup_sparc_lo10", 22, 10, 0 },
109 { "fixup_sparc_h44", 10, 22, 0 },
110 { "fixup_sparc_m44", 22, 10, 0 },
111 { "fixup_sparc_l44", 20, 12, 0 },
112 { "fixup_sparc_hh", 10, 22, 0 },
113 { "fixup_sparc_hm", 22, 10, 0 },
114 { "fixup_sparc_pc22", 10, 22, MCFixupKindInfo::FKF_IsPCRel },
115 { "fixup_sparc_pc10", 22, 10, MCFixupKindInfo::FKF_IsPCRel },
116 { "fixup_sparc_got22", 10, 22, 0 },
117 { "fixup_sparc_got10", 22, 10, 0 },
118 { "fixup_sparc_wplt30", 2, 30, MCFixupKindInfo::FKF_IsPCRel },
119 { "fixup_sparc_tls_gd_hi22", 10, 22, 0 },
120 { "fixup_sparc_tls_gd_lo10", 22, 10, 0 },
121 { "fixup_sparc_tls_gd_add", 0, 0, 0 },
122 { "fixup_sparc_tls_gd_call", 0, 0, 0 },
123 { "fixup_sparc_tls_ldm_hi22", 10, 22, 0 },
124 { "fixup_sparc_tls_ldm_lo10", 22, 10, 0 },
125 { "fixup_sparc_tls_ldm_add", 0, 0, 0 },
126 { "fixup_sparc_tls_ldm_call", 0, 0, 0 },
127 { "fixup_sparc_tls_ldo_hix22", 10, 22, 0 },
128 { "fixup_sparc_tls_ldo_lox10", 22, 10, 0 },
129 { "fixup_sparc_tls_ldo_add", 0, 0, 0 },
130 { "fixup_sparc_tls_ie_hi22", 10, 22, 0 },
131 { "fixup_sparc_tls_ie_lo10", 22, 10, 0 },
132 { "fixup_sparc_tls_ie_ld", 0, 0, 0 },
133 { "fixup_sparc_tls_ie_ldx", 0, 0, 0 },
134 { "fixup_sparc_tls_ie_add", 0, 0, 0 },
135 { "fixup_sparc_tls_le_hix22", 0, 0, 0 },
136 { "fixup_sparc_tls_le_lox10", 0, 0, 0 }
137 };
138
139 if (Kind < FirstTargetFixupKind)
140 return MCAsmBackend::getFixupKindInfo(Kind);
141
142 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
143 "Invalid kind!");
144 return Infos[Kind - FirstTargetFixupKind];
145 }
146
processFixupValue(const MCAssembler & Asm,const MCAsmLayout & Layout,const MCFixup & Fixup,const MCFragment * DF,MCValue & Target,uint64_t & Value,bool & IsResolved)147 void processFixupValue(const MCAssembler &Asm,
148 const MCAsmLayout &Layout,
149 const MCFixup &Fixup,
150 const MCFragment *DF,
151 MCValue & Target,
152 uint64_t &Value,
153 bool &IsResolved) {
154 switch ((Sparc::Fixups)Fixup.getKind()) {
155 default: break;
156 case Sparc::fixup_sparc_wplt30:
157 case Sparc::fixup_sparc_tls_gd_hi22:
158 case Sparc::fixup_sparc_tls_gd_lo10:
159 case Sparc::fixup_sparc_tls_gd_add:
160 case Sparc::fixup_sparc_tls_gd_call:
161 case Sparc::fixup_sparc_tls_ldm_hi22:
162 case Sparc::fixup_sparc_tls_ldm_lo10:
163 case Sparc::fixup_sparc_tls_ldm_add:
164 case Sparc::fixup_sparc_tls_ldm_call:
165 case Sparc::fixup_sparc_tls_ldo_hix22:
166 case Sparc::fixup_sparc_tls_ldo_lox10:
167 case Sparc::fixup_sparc_tls_ldo_add:
168 case Sparc::fixup_sparc_tls_ie_hi22:
169 case Sparc::fixup_sparc_tls_ie_lo10:
170 case Sparc::fixup_sparc_tls_ie_ld:
171 case Sparc::fixup_sparc_tls_ie_ldx:
172 case Sparc::fixup_sparc_tls_ie_add:
173 case Sparc::fixup_sparc_tls_le_hix22:
174 case Sparc::fixup_sparc_tls_le_lox10: IsResolved = false; break;
175 }
176 }
177
mayNeedRelaxation(const MCInst & Inst) const178 bool mayNeedRelaxation(const MCInst &Inst) const {
179 // FIXME.
180 return false;
181 }
182
183 /// fixupNeedsRelaxation - Target specific predicate for whether a given
184 /// fixup requires the associated instruction to be relaxed.
fixupNeedsRelaxation(const MCFixup & Fixup,uint64_t Value,const MCRelaxableFragment * DF,const MCAsmLayout & Layout) const185 bool fixupNeedsRelaxation(const MCFixup &Fixup,
186 uint64_t Value,
187 const MCRelaxableFragment *DF,
188 const MCAsmLayout &Layout) const {
189 // FIXME.
190 assert(0 && "fixupNeedsRelaxation() unimplemented");
191 return false;
192 }
relaxInstruction(const MCInst & Inst,MCInst & Res) const193 void relaxInstruction(const MCInst &Inst, MCInst &Res) const {
194 // FIXME.
195 assert(0 && "relaxInstruction() unimplemented");
196 }
197
writeNopData(uint64_t Count,MCObjectWriter * OW) const198 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const {
199 // FIXME: Zero fill for now.
200 for (uint64_t i = 0; i != Count; ++i)
201 OW->Write8(0);
202 return true;
203 }
204
is64Bit() const205 bool is64Bit() const {
206 StringRef name = TheTarget.getName();
207 return name == "sparcv9";
208 }
209 };
210
211 class ELFSparcAsmBackend : public SparcAsmBackend {
212 Triple::OSType OSType;
213 public:
ELFSparcAsmBackend(const Target & T,Triple::OSType OSType)214 ELFSparcAsmBackend(const Target &T, Triple::OSType OSType) :
215 SparcAsmBackend(T), OSType(OSType) { }
216
applyFixup(const MCFixup & Fixup,char * Data,unsigned DataSize,uint64_t Value) const217 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
218 uint64_t Value) const {
219
220 Value = adjustFixupValue(Fixup.getKind(), Value);
221 if (!Value) return; // Doesn't change encoding.
222
223 unsigned Offset = Fixup.getOffset();
224
225 // For each byte of the fragment that the fixup touches, mask in the bits
226 // from the fixup value. The Value has been "split up" into the
227 // appropriate bitfields above.
228 for (unsigned i = 0; i != 4; ++i)
229 Data[Offset + i] |= uint8_t((Value >> ((4 - i - 1)*8)) & 0xff);
230
231 }
232
createObjectWriter(raw_ostream & OS) const233 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
234 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(OSType);
235 return createSparcELFObjectWriter(OS, is64Bit(), OSABI);
236 }
237
doesSectionRequireSymbols(const MCSection & Section) const238 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
239 return false;
240 }
241 };
242
243 } // end anonymous namespace
244
245
createSparcAsmBackend(const Target & T,const MCRegisterInfo & MRI,StringRef TT,StringRef CPU)246 MCAsmBackend *llvm::createSparcAsmBackend(const Target &T,
247 const MCRegisterInfo &MRI,
248 StringRef TT,
249 StringRef CPU) {
250 return new ELFSparcAsmBackend(T, Triple(TT).getOS());
251 }
252