12006-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com> 2 3 * cr16.h: New file for CR16 target. 4 52007-05-02 Alan Modra <amodra@bigpond.net.au> 6 7 * ppc.h (PPC_OPERAND_PLUS1): Update comment. 8 92007-04-23 Nathan Sidwell <nathan@codesourcery.com> 10 11 * m68k.h (mcfisa_c): New. 12 (mcfusp, mcf_mask): Adjust. 13 142007-04-20 Alan Modra <amodra@bigpond.net.au> 15 16 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm". 17 (num_powerpc_operands): Declare. 18 (PPC_OPERAND_SIGNED et al): Redefine as hex. 19 (PPC_OPERAND_PLUS1): Define. 20 212007-03-21 H.J. Lu <hongjiu.lu@intel.com> 22 23 * i386.h (REX_MODE64): Renamed to ... 24 (REX_W): This. 25 (REX_EXTX): Renamed to ... 26 (REX_R): This. 27 (REX_EXTY): Renamed to ... 28 (REX_X): This. 29 (REX_EXTZ): Renamed to ... 30 (REX_B): This. 31 322007-03-15 H.J. Lu <hongjiu.lu@intel.com> 33 34 * i386.h: Add entries from config/tc-i386.h and move tables 35 to opcodes/i386-opc.h. 36 372007-03-13 H.J. Lu <hongjiu.lu@intel.com> 38 39 * i386.h (FloatDR): Removed. 40 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR. 41 422007-03-01 Alan Modra <amodra@bigpond.net.au> 43 44 * spu-insns.h: Add soma double-float insns. 45 462007-02-20 Thiemo Seufer <ths@mips.com> 47 Chao-Ying Fu <fu@mips.com> 48 49 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction. 50 (INSN_DSPR2): Add flag for DSP R2 instructions. 51 (M_BALIGN): New macro. 52 532007-02-14 Alan Modra <amodra@bigpond.net.au> 54 55 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm 56 and Seg3ShortFrom with Shortform. 57 582007-02-11 H.J. Lu <hongjiu.lu@intel.com> 59 60 PR gas/4027 61 * i386.h (i386_optab): Put the real "test" before the pseudo 62 one. 63 642007-01-08 Kazu Hirata <kazu@codesourcery.com> 65 66 * m68k.h (m68010up): OR fido_a. 67 682006-12-25 Kazu Hirata <kazu@codesourcery.com> 69 70 * m68k.h (fido_a): New. 71 722006-12-24 Kazu Hirata <kazu@codesourcery.com> 73 74 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a, 75 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined 76 values. 77 782006-11-08 H.J. Lu <hongjiu.lu@intel.com> 79 80 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3. 81 822006-10-31 Mei Ligang <ligang@sunnorth.com.cn> 83 84 * score-inst.h (enum score_insn_type): Add Insn_internal. 85 862006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com> 87 Yukishige Shibata <shibata@rd.scei.sony.co.jp> 88 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp> 89 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp> 90 Alan Modra <amodra@bigpond.net.au> 91 92 * spu-insns.h: New file. 93 * spu.h: New file. 94 952006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com> 96 97 * ppc.h (PPC_OPCODE_CELL): Define. 98 992006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> 100 101 * i386.h : Modify opcode to support for the change in POPCNT opcode 102 in amdfam10 architecture. 103 1042006-09-28 H.J. Lu <hongjiu.lu@intel.com> 105 106 * i386.h: Replace CpuMNI with CpuSSSE3. 107 1082006-09-26 Mark Shinwell <shinwell@codesourcery.com> 109 Joseph Myers <joseph@codesourcery.com> 110 Ian Lance Taylor <ian@wasabisystems.com> 111 Ben Elliston <bje@wasabisystems.com> 112 113 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define. 114 1152006-09-17 Mei Ligang <ligang@sunnorth.com.cn> 116 117 * score-datadep.h: New file. 118 * score-inst.h: New file. 119 1202006-07-14 H.J. Lu <hongjiu.lu@intel.com> 121 122 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps, 123 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu, 124 movdq2q and movq2dq. 125 1262006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> 127 Michael Meissner <michael.meissner@amd.com> 128 129 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions). 130 1312006-06-12 H.J. Lu <hongjiu.lu@intel.com> 132 133 * i386.h (i386_optab): Add "nop" with memory reference. 134 1352006-06-12 H.J. Lu <hongjiu.lu@intel.com> 136 137 * i386.h (i386_optab): Update comment for 64bit NOP. 138 1392006-06-06 Ben Elliston <bje@au.ibm.com> 140 Anton Blanchard <anton@samba.org> 141 142 * ppc.h (PPC_OPCODE_POWER6): Define. 143 Adjust whitespace. 144 1452006-06-05 Thiemo Seufer <ths@mips.com> 146 147 * mips.h: Improve description of MT flags. 148 1492006-05-25 Richard Sandiford <richard@codesourcery.com> 150 151 * m68k.h (mcf_mask): Define. 152 1532006-05-05 Thiemo Seufer <ths@mips.com> 154 David Ung <davidu@mips.com> 155 156 * mips.h (enum): Add macro M_CACHE_AB. 157 1582006-05-04 Thiemo Seufer <ths@mips.com> 159 Nigel Stephens <nigel@mips.com> 160 David Ung <davidu@mips.com> 161 162 * mips.h: Add INSN_SMARTMIPS define. 163 1642006-04-30 Thiemo Seufer <ths@mips.com> 165 David Ung <davidu@mips.com> 166 167 * mips.h: Defines udi bits and masks. Add description of 168 characters which may appear in the args field of udi 169 instructions. 170 1712006-04-26 Thiemo Seufer <ths@networkno.de> 172 173 * mips.h: Improve comments describing the bitfield instruction 174 fields. 175 1762006-04-26 Julian Brown <julian@codesourcery.com> 177 178 * arm.h (FPU_VFP_EXT_V3): Define constant. 179 (FPU_NEON_EXT_V1): Likewise. 180 (FPU_VFP_HARD): Update. 181 (FPU_VFP_V3): Define macro. 182 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros. 183 1842006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de> 185 186 * avr.h (AVR_ISA_PWMx): New. 187 1882006-03-28 Nathan Sidwell <nathan@codesourcery.com> 189 190 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010, 191 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851, 192 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e, 193 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x, 194 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove. 195 1962006-03-10 Paul Brook <paul@codesourcery.com> 197 198 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions. 199 2002006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 201 202 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come 203 first. Correct mask of bb "B" opcode. 204 2052006-02-27 H.J. Lu <hongjiu.lu@intel.com> 206 207 * i386.h (i386_optab): Support Intel Merom New Instructions. 208 2092006-02-24 Paul Brook <paul@codesourcery.com> 210 211 * arm.h: Add V7 feature bits. 212 2132006-02-23 H.J. Lu <hongjiu.lu@intel.com> 214 215 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b. 216 2172006-01-31 Paul Brook <paul@codesourcery.com> 218 Richard Earnshaw <rearnsha@arm.com> 219 220 * arm.h: Use ARM_CPU_FEATURE. 221 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New. 222 (arm_feature_set): Change to a structure. 223 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE, 224 ARM_FEATURE): New macros. 225 2262005-12-07 Hans-Peter Nilsson <hp@axis.com> 227 228 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS) 229 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros. 230 (ADD_PC_INCR_OPCODE): Don't define. 231 2322005-12-06 H.J. Lu <hongjiu.lu@intel.com> 233 234 PR gas/1874 235 * i386.h (i386_optab): Add 64bit support for monitor and mwait. 236 2372005-11-14 David Ung <davidu@mips.com> 238 239 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore 240 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for 241 save/restore encoding of the args field. 242 2432005-10-28 Dave Brolley <brolley@redhat.com> 244 245 Contribute the following changes: 246 2005-02-16 Dave Brolley <brolley@redhat.com> 247 248 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename 249 cgen_isa_mask_* to cgen_bitset_*. 250 * cgen.h: Likewise. 251 252 2003-10-21 Richard Sandiford <rsandifo@redhat.com> 253 254 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition. 255 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned". 256 (CGEN_CPU_TABLE): Make isas a ponter. 257 258 2003-09-29 Dave Brolley <brolley@redhat.com> 259 260 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef. 261 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto. 262 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs. 263 264 2002-12-13 Dave Brolley <brolley@redhat.com> 265 266 * cgen.h (symcat.h): #include it. 267 (cgen-bitset.h): #include it. 268 (CGEN_ATTR_VALUE_TYPE): Now a union. 269 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h. 270 (CGEN_ATTR_ENTRY): 'value' now unsigned. 271 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*). 272 * cgen-bitset.h: New file. 273 2742005-09-30 Catherine Moore <clm@cm00re.com> 275 276 * bfin.h: New file. 277 2782005-10-24 Jan Beulich <jbeulich@novell.com> 279 280 * ia64.h (enum ia64_opnd): Move memory operand out of set of 281 indirect operands. 282 2832005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 284 285 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes. 286 Add FLAG_STRICT to pa10 ftest opcode. 287 2882005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 289 290 * hppa.h (pa_opcodes): Remove lha entries. 291 2922005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 293 294 * hppa.h (FLAG_STRICT): Revise comment. 295 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants 296 before corresponding pa11 opcodes. Add strict pa10 register-immediate 297 entries for "fdc". 298 2992005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 300 301 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries. 302 3032005-09-06 Chao-ying Fu <fu@mips.com> 304 305 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H, 306 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New 307 define. 308 Document !, $, *, &, g, +t, +T operand formats for MT instructions. 309 (INSN_ASE_MASK): Update to include INSN_MT. 310 (INSN_MT): New define for MT ASE. 311 3122005-08-25 Chao-ying Fu <fu@mips.com> 313 314 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S, 315 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7, 316 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4, 317 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP, 318 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define. 319 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP 320 instructions. 321 (INSN_DSP): New define for DSP ASE. 322 3232005-08-18 Alan Modra <amodra@bigpond.net.au> 324 325 * a29k.h: Delete. 326 3272005-08-15 Daniel Jacobowitz <dan@codesourcery.com> 328 329 * ppc.h (PPC_OPCODE_E300): Define. 330 3312005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com> 332 333 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109. 334 3352005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 336 337 PR gas/336 338 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb 339 and pitlb. 340 3412005-07-27 Jan Beulich <jbeulich@novell.com> 342 343 * i386.h (i386_optab): Add comment to movd. Use LongMem for all 344 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers. 345 Add movq-s as 64-bit variants of movd-s. 346 3472005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 348 349 * hppa.h: Fix punctuation in comment. 350 351 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for 352 implicit space-register addressing. Set space-register bits on opcodes 353 using implicit space-register addressing. Add various missing pa20 354 long-immediate opcodes. Remove various opcodes using implicit 3-bit 355 space-register addressing. Use "fE" instead of "fe" in various 356 fstw opcodes. 357 3582005-07-18 Jan Beulich <jbeulich@novell.com> 359 360 * i386.h (i386_optab): Operands of aam and aad are unsigned. 361 3622007-07-15 H.J. Lu <hongjiu.lu@intel.com> 363 364 * i386.h (i386_optab): Support Intel VMX Instructions. 365 3662005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 367 368 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores. 369 3702005-07-05 Jan Beulich <jbeulich@novell.com> 371 372 * i386.h (i386_optab): Add new insns. 373 3742005-07-01 Nick Clifton <nickc@redhat.com> 375 376 * sparc.h: Add typedefs to structure declarations. 377 3782005-06-20 H.J. Lu <hongjiu.lu@intel.com> 379 380 PR 1013 381 * i386.h (i386_optab): Update comments for 64bit addressing on 382 mov. Allow 64bit addressing for mov and movq. 383 3842005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 385 386 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx, 387 respectively, in various floating-point load and store patterns. 388 3892005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 390 391 * hppa.h (FLAG_STRICT): Correct comment. 392 (pa_opcodes): Update load and store entries to allow both PA 1.X and 393 PA 2.0 mneumonics when equivalent. Entries with cache control 394 completers now require PA 1.1. Adjust whitespace. 395 3962005-05-19 Anton Blanchard <anton@samba.org> 397 398 * ppc.h (PPC_OPCODE_POWER5): Define. 399 4002005-05-10 Nick Clifton <nickc@redhat.com> 401 402 * Update the address and phone number of the FSF organization in 403 the GPL notices in the following files: 404 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h, 405 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h, 406 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h, 407 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h, 408 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h, 409 tic54x.h, tic80.h, v850.h, vax.h 410 4112005-05-09 Jan Beulich <jbeulich@novell.com> 412 413 * i386.h (i386_optab): Add ht and hnt. 414 4152005-04-18 Mark Kettenis <kettenis@gnu.org> 416 417 * i386.h: Insert hyphens into selected VIA PadLock extensions. 418 Add xcrypt-ctr. Provide aliases without hyphens. 419 4202005-04-13 H.J. Lu <hongjiu.lu@intel.com> 421 422 Moved from ../ChangeLog 423 424 2005-04-12 Paul Brook <paul@codesourcery.com> 425 * m88k.h: Rename psr macros to avoid conflicts. 426 427 2005-03-12 Zack Weinberg <zack@codesourcery.com> 428 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T. 429 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2, 430 and ARM_ARCH_V6ZKT2. 431 432 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com> 433 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4. 434 Remove redundant instruction types. 435 (struct argument): X_op - new field. 436 (struct cst4_entry): Remove. 437 (no_op_insn): Declare. 438 439 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com> 440 * crx.h (enum argtype): Rename types, remove unused types. 441 442 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com> 443 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'. 444 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE. 445 (enum operand_type): Rearrange operands, edit comments. 446 replace us<N> with ui<N> for unsigned immediate. 447 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped 448 displacements (respectively). 449 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index. 450 (instruction type): Add NO_TYPE_INS. 451 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR. 452 (operand_entry): New field - 'flags'. 453 (operand flags): New. 454 455 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com> 456 * crx.h (operand_type): Remove redundant types i3, i4, 457 i5, i8, i12. 458 Add new unsigned immediate types us3, us4, us5, us16. 459 4602005-04-12 Mark Kettenis <kettenis@gnu.org> 461 462 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and 463 adjust them accordingly. 464 4652005-04-01 Jan Beulich <jbeulich@novell.com> 466 467 * i386.h (i386_optab): Add rdtscp. 468 4692005-03-29 H.J. Lu <hongjiu.lu@intel.com> 470 471 * i386.h (i386_optab): Don't allow the `l' suffix for moving 472 between memory and segment register. Allow movq for moving between 473 general-purpose register and segment register. 474 4752005-02-09 Jan Beulich <jbeulich@novell.com> 476 477 PR gas/707 478 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and 479 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and 480 fnstsw. 481 4822006-02-07 Nathan Sidwell <nathan@codesourcery.com> 483 484 * m68k.h (m68008, m68ec030, m68882): Remove. 485 (m68k_mask): New. 486 (cpu_m68k, cpu_cf): New. 487 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407, 488 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants. 489 4902005-01-25 Alexandre Oliva <aoliva@redhat.com> 491 492 2004-11-10 Alexandre Oliva <aoliva@redhat.com> 493 * cgen.h (enum cgen_parse_operand_type): Add 494 CGEN_PARSE_OPERAND_SYMBOLIC. 495 4962005-01-21 Fred Fish <fnf@specifixinc.com> 497 498 * mips.h: Change INSN_ALIAS to INSN2_ALIAS. 499 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC. 500 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC. 501 5022005-01-19 Fred Fish <fnf@specifixinc.com> 503 504 * mips.h (struct mips_opcode): Add new pinfo2 member. 505 (INSN_ALIAS): New define for opcode table entries that are 506 specific instances of another entry, such as 'move' for an 'or' 507 with a zero operand. 508 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2. 509 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4. 510 5112004-12-09 Ian Lance Taylor <ian@wasabisystems.com> 512 513 * mips.h (CPU_RM9000): Define. 514 (OPCODE_IS_MEMBER): Handle CPU_RM9000. 515 5162004-11-25 Jan Beulich <jbeulich@novell.com> 517 518 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves 519 to/from test registers are illegal in 64-bit mode. Add missing 520 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix 521 (previously one had to explicitly encode a rex64 prefix). Re-enable 522 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings 523 support it there. Add cmpxchg16b as per Intel's 64-bit documentation. 524 5252004-11-23 Jan Beulich <jbeulich@novell.com> 526 527 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are 528 available only with SSE2. Change the MMX additions introduced by SSE 529 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A 530 instructions by their now designated identifier (since combining i686 531 and 3DNow! does not really imply 3DNow!A). 532 5332004-11-19 Alan Modra <amodra@bigpond.net.au> 534 535 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes, 536 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c. 537 5382004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com> 539 Vineet Sharma <vineets@noida.hcltech.com> 540 541 * maxq.h: New file: Disassembly information for the maxq port. 542 5432004-11-05 H.J. Lu <hongjiu.lu@intel.com> 544 545 * i386.h (i386_optab): Put back "movzb". 546 5472004-11-04 Hans-Peter Nilsson <hp@axis.com> 548 549 * cris.h (enum cris_insn_version_usage): Tweak formatting and 550 comments. Remove member cris_ver_sim. Add members 551 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10, 552 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p. 553 (struct cris_support_reg, struct cris_cond15): New types. 554 (cris_conds15): Declare. 555 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON) 556 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS) 557 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros. 558 (NOP_Z_BITS): Define in terms of NOP_OPCODE. 559 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and 560 SIZE_FIELD_UNSIGNED. 561 5622004-11-04 Jan Beulich <jbeulich@novell.com> 563 564 * i386.h (sldx_Suf): Remove. 565 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize. 566 (q_FP): Define, implying no REX64. 567 (x_FP, sl_FP): Imply FloatMF. 568 (i386_optab): Split reg and mem forms of moving from segment registers 569 so that the memory forms can ignore the 16-/32-bit operand size 570 distinction. Adjust a few others for Intel mode. Remove *FP uses from 571 all non-floating-point instructions. Unite 32- and 64-bit forms of 572 movsx, movzx, and movd. Adjust floating point operations for the above 573 changes to the *FP macros. Add DefaultSize to floating point control 574 insns operating on larger memory ranges. Remove left over comments 575 hinting at certain insns being Intel-syntax ones where the ones 576 actually meant are already gone. 577 5782004-10-07 Tomer Levi <Tomer.Levi@nsc.com> 579 580 * crx.h: Add COPS_REG_INS - Coprocessor Special register 581 instruction type. 582 5832004-09-30 Paul Brook <paul@codesourcery.com> 584 585 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define. 586 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define. 587 5882004-09-11 Theodore A. Roth <troth@openavr.org> 589 590 * avr.h: Add support for 591 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128. 592 5932004-09-09 Segher Boessenkool <segher@kernel.crashing.org> 594 595 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment. 596 5972004-08-24 Dmitry Diky <diwil@spec.ru> 598 599 * msp430.h (msp430_opc): Add new instructions. 600 (msp430_rcodes): Declare new instructions. 601 (msp430_hcodes): Likewise.. 602 6032004-08-13 Nick Clifton <nickc@redhat.com> 604 605 PR/301 606 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX 607 processors. 608 6092004-08-30 Michal Ludvig <mludvig@suse.cz> 610 611 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns. 612 6132004-07-22 H.J. Lu <hongjiu.lu@intel.com> 614 615 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints. 616 6172004-07-21 Jan Beulich <jbeulich@novell.com> 618 619 * i386.h: Adjust instruction descriptions to better match the 620 specification. 621 6222004-07-16 Richard Earnshaw <rearnsha@arm.com> 623 624 * arm.h: Remove all old content. Replace with architecture defines 625 from gas/config/tc-arm.c. 626 6272004-07-09 Andreas Schwab <schwab@suse.de> 628 629 * m68k.h: Fix comment. 630 6312004-07-07 Tomer Levi <Tomer.Levi@nsc.com> 632 633 * crx.h: New file. 634 6352004-06-24 Alan Modra <amodra@bigpond.net.au> 636 637 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd. 638 6392004-05-24 Peter Barada <peter@the-baradas.com> 640 641 * m68k.h: Add 'size' to m68k_opcode. 642 6432004-05-05 Peter Barada <peter@the-baradas.com> 644 645 * m68k.h: Switch from ColdFire chip name to core variant. 646 6472004-04-22 Peter Barada <peter@the-baradas.com> 648 649 * m68k.h: Add mcfmac/mcfemac definitions. Update operand 650 descriptions for new EMAC cases. 651 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly 652 handle Motorola MAC syntax. 653 Allow disassembly of ColdFire V4e object files. 654 6552004-03-16 Alan Modra <amodra@bigpond.net.au> 656 657 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines. 658 6592004-03-12 Jakub Jelinek <jakub@redhat.com> 660 661 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit. 662 6632004-03-12 Michal Ludvig <mludvig@suse.cz> 664 665 * i386.h (i386_optab): Added xstore as an alias for xstorerng. 666 6672004-03-12 Michal Ludvig <mludvig@suse.cz> 668 669 * i386.h (i386_optab): Added xstore/xcrypt insns. 670 6712004-02-09 Anil Paranjpe <anilp1@KPITCummins.com> 672 673 * h8300.h (32bit ldc/stc): Add relaxing support. 674 6752004-01-12 Anil Paranjpe <anilp1@KPITCummins.com> 676 677 * h8300.h (BITOP): Pass MEMRELAX flag. 678 6792004-01-09 Anil Paranjpe <anilp1@KPITCummins.com> 680 681 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32 682 except for the H8S. 683 684For older changes see ChangeLog-9103 685 686Local Variables: 687mode: change-log 688left-margin: 8 689fill-column: 74 690version-control: never 691End: 692