1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (C) 2002 Benno Rice.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
21 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
22 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
23 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
24 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
25 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 #include <sys/cdefs.h>
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/module.h>
32 #include <sys/bus.h>
33 #include <sys/conf.h>
34 #include <sys/kernel.h>
35 #include <sys/lock.h>
36 #include <sys/mutex.h>
37 #include <sys/rman.h>
38
39 #include <dev/ofw/openfirm.h>
40 #include <dev/ofw/ofw_pci.h>
41 #include <dev/ofw/ofw_bus.h>
42 #include <dev/ofw/ofw_bus_subr.h>
43 #include <dev/ofw/ofwpci.h>
44
45 #include <dev/pci/pcivar.h>
46 #include <dev/pci/pcireg.h>
47
48 #include <machine/bus.h>
49 #include <machine/intr_machdep.h>
50 #include <machine/md_var.h>
51 #include <machine/pio.h>
52 #include <machine/resource.h>
53
54 #include <powerpc/powermac/uninorthvar.h>
55
56 #include <vm/vm.h>
57 #include <vm/pmap.h>
58
59 #include "pcib_if.h"
60
61 #define UNINORTH_DEBUG 0
62
63 /*
64 * Device interface.
65 */
66 static int uninorth_probe(device_t);
67 static int uninorth_attach(device_t);
68
69 /*
70 * pcib interface.
71 */
72 static u_int32_t uninorth_read_config(device_t, u_int, u_int, u_int,
73 u_int, int);
74 static void uninorth_write_config(device_t, u_int, u_int, u_int,
75 u_int, u_int32_t, int);
76
77 /*
78 * Local routines.
79 */
80 static int uninorth_enable_config(struct uninorth_softc *, u_int,
81 u_int, u_int, u_int);
82
83 /*
84 * Driver methods.
85 */
86 static device_method_t uninorth_methods[] = {
87 /* Device interface */
88 DEVMETHOD(device_probe, uninorth_probe),
89 DEVMETHOD(device_attach, uninorth_attach),
90
91 /* pcib interface */
92 DEVMETHOD(pcib_read_config, uninorth_read_config),
93 DEVMETHOD(pcib_write_config, uninorth_write_config),
94
95 DEVMETHOD_END
96 };
97
98 DEFINE_CLASS_1(pcib, uninorth_driver, uninorth_methods,
99 sizeof(struct uninorth_softc), ofw_pcib_driver);
100 EARLY_DRIVER_MODULE(uninorth, ofwbus, uninorth_driver, 0, 0, BUS_PASS_BUS);
101
102 static int
uninorth_probe(device_t dev)103 uninorth_probe(device_t dev)
104 {
105 const char *type, *compatible;
106
107 type = ofw_bus_get_type(dev);
108 compatible = ofw_bus_get_compat(dev);
109
110 if (type == NULL || compatible == NULL)
111 return (ENXIO);
112
113 if (strcmp(type, "pci") != 0)
114 return (ENXIO);
115
116 if (strcmp(compatible, "uni-north") == 0) {
117 device_set_desc(dev, "Apple UniNorth Host-PCI bridge");
118 return (0);
119 } else if (strcmp(compatible, "u3-agp") == 0) {
120 device_set_desc(dev, "Apple U3 Host-AGP bridge");
121 return (0);
122 } else if (strcmp(compatible, "u4-pcie") == 0) {
123 device_set_desc(dev, "IBM CPC945 PCI Express Root");
124 return (0);
125 }
126
127 return (ENXIO);
128 }
129
130 static int
uninorth_attach(device_t dev)131 uninorth_attach(device_t dev)
132 {
133 struct uninorth_softc *sc;
134 const char *compatible;
135 const char *name;
136 phandle_t node;
137 uint32_t reg[3];
138 uint64_t regbase;
139 cell_t acells;
140 int unit;
141
142 node = ofw_bus_get_node(dev);
143 sc = device_get_softc(dev);
144 name = device_get_name(dev);
145 unit = device_get_unit(dev);
146
147 if (OF_getprop(node, "reg", reg, sizeof(reg)) < 8)
148 return (ENXIO);
149
150 sc->sc_ver = 0;
151 compatible = ofw_bus_get_compat(dev);
152 if (strcmp(compatible, "u3-agp") == 0)
153 sc->sc_ver = 3;
154 if (strcmp(compatible, "u4-pcie") == 0)
155 sc->sc_ver = 4;
156
157 acells = 1;
158 OF_getprop(OF_parent(node), "#address-cells", &acells, sizeof(acells));
159
160 regbase = reg[0];
161 if (acells == 2) {
162 regbase <<= 32;
163 regbase |= reg[1];
164 }
165
166 sc->sc_addr = (vm_offset_t)pmap_mapdev(regbase + 0x800000, PAGE_SIZE);
167 sc->sc_data = (vm_offset_t)pmap_mapdev(regbase + 0xc00000, PAGE_SIZE);
168
169 if (resource_int_value(name, unit, "skipslot", &sc->sc_skipslot) != 0)
170 sc->sc_skipslot = -1;
171
172 mtx_init(&sc->sc_cfg_mtx, "uninorth pcicfg", NULL, MTX_SPIN);
173
174 return (ofw_pcib_attach(dev));
175 }
176
177 static u_int32_t
uninorth_read_config(device_t dev,u_int bus,u_int slot,u_int func,u_int reg,int width)178 uninorth_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
179 int width)
180 {
181 struct uninorth_softc *sc;
182 vm_offset_t caoff;
183 u_int32_t val;
184
185 sc = device_get_softc(dev);
186 caoff = sc->sc_data + (reg & 0x07);
187 val = 0xffffffff;
188
189 mtx_lock_spin(&sc->sc_cfg_mtx);
190 if (uninorth_enable_config(sc, bus, slot, func, reg) != 0) {
191 switch (width) {
192 case 1:
193 val = in8rb(caoff);
194 break;
195 case 2:
196 val = in16rb(caoff);
197 break;
198 case 4:
199 val = in32rb(caoff);
200 break;
201 }
202 }
203 mtx_unlock_spin(&sc->sc_cfg_mtx);
204
205 return (val);
206 }
207
208 static void
uninorth_write_config(device_t dev,u_int bus,u_int slot,u_int func,u_int reg,u_int32_t val,int width)209 uninorth_write_config(device_t dev, u_int bus, u_int slot, u_int func,
210 u_int reg, u_int32_t val, int width)
211 {
212 struct uninorth_softc *sc;
213 vm_offset_t caoff;
214
215 sc = device_get_softc(dev);
216 caoff = sc->sc_data + (reg & 0x07);
217
218 mtx_lock_spin(&sc->sc_cfg_mtx);
219 if (uninorth_enable_config(sc, bus, slot, func, reg)) {
220 switch (width) {
221 case 1:
222 out8rb(caoff, val);
223 break;
224 case 2:
225 out16rb(caoff, val);
226 break;
227 case 4:
228 out32rb(caoff, val);
229 break;
230 }
231 }
232 mtx_unlock_spin(&sc->sc_cfg_mtx);
233 }
234
235 static int
uninorth_enable_config(struct uninorth_softc * sc,u_int bus,u_int slot,u_int func,u_int reg)236 uninorth_enable_config(struct uninorth_softc *sc, u_int bus, u_int slot,
237 u_int func, u_int reg)
238 {
239 uint32_t cfgval;
240
241 mtx_assert(&sc->sc_cfg_mtx, MA_OWNED);
242
243 if (sc->sc_skipslot == slot)
244 return (0);
245
246 /*
247 * Issue type 0 configuration space accesses for the root bus.
248 *
249 * NOTE: On U4, issue only type 1 accesses. There is a secret
250 * PCI Express <-> PCI Express bridge not present in the device tree,
251 * and we need to route all of our configuration space through it.
252 */
253 if (sc->pci_sc.sc_bus == bus && sc->sc_ver < 4) {
254 /*
255 * No slots less than 11 on the primary bus on U3 and lower
256 */
257 if (slot < 11)
258 return (0);
259
260 cfgval = (1 << slot) | (func << 8) | (reg & 0xfc);
261 } else {
262 cfgval = (bus << 16) | (slot << 11) | (func << 8) |
263 (reg & 0xfc) | 1;
264 }
265
266 /* Set extended register bits on U4 */
267 if (sc->sc_ver == 4)
268 cfgval |= (reg >> 8) << 28;
269
270 do {
271 out32rb(sc->sc_addr, cfgval);
272 } while (in32rb(sc->sc_addr) != cfgval);
273
274 return (1);
275 }
276