1 /*-
2 * Copyright (c) 2008 Weongyo Jeong <weongyo@FreeBSD.org>
3 *
4 * Permission to use, copy, modify, and distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include "opt_wlan.h"
18
19 #include <sys/param.h>
20 #include <sys/sockio.h>
21 #include <sys/sysctl.h>
22 #include <sys/lock.h>
23 #include <sys/mutex.h>
24 #include <sys/mbuf.h>
25 #include <sys/kernel.h>
26 #include <sys/socket.h>
27 #include <sys/systm.h>
28 #include <sys/malloc.h>
29 #include <sys/module.h>
30 #include <sys/bus.h>
31 #include <sys/endian.h>
32 #include <sys/kdb.h>
33
34 #include <net/if.h>
35 #include <net/if_var.h>
36 #include <net/if_arp.h>
37 #include <net/ethernet.h>
38 #include <net/if_dl.h>
39 #include <net/if_media.h>
40 #include <net/if_types.h>
41
42 #ifdef INET
43 #include <netinet/in.h>
44 #include <netinet/in_systm.h>
45 #include <netinet/in_var.h>
46 #include <netinet/if_ether.h>
47 #include <netinet/ip.h>
48 #endif
49
50 #include <net80211/ieee80211_var.h>
51 #include <net80211/ieee80211_regdomain.h>
52 #include <net80211/ieee80211_radiotap.h>
53
54 #include <dev/usb/usb.h>
55 #include <dev/usb/usbdi.h>
56 #include "usbdevs.h"
57
58 #include <dev/usb/wlan/if_urtwreg.h>
59 #include <dev/usb/wlan/if_urtwvar.h>
60
61 /* copy some rate indices from if_rtwn_ridx.h */
62 #define URTW_RIDX_CCK5 2
63 #define URTW_RIDX_CCK11 3
64 #define URTW_RIDX_OFDM6 4
65 #define URTW_RIDX_OFDM24 8
66
67 static SYSCTL_NODE(_hw_usb, OID_AUTO, urtw, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
68 "USB Realtek 8187L");
69 #ifdef URTW_DEBUG
70 int urtw_debug = 0;
71 SYSCTL_INT(_hw_usb_urtw, OID_AUTO, debug, CTLFLAG_RWTUN, &urtw_debug, 0,
72 "control debugging printfs");
73 enum {
74 URTW_DEBUG_XMIT = 0x00000001, /* basic xmit operation */
75 URTW_DEBUG_RECV = 0x00000002, /* basic recv operation */
76 URTW_DEBUG_RESET = 0x00000004, /* reset processing */
77 URTW_DEBUG_TX_PROC = 0x00000008, /* tx ISR proc */
78 URTW_DEBUG_RX_PROC = 0x00000010, /* rx ISR proc */
79 URTW_DEBUG_STATE = 0x00000020, /* 802.11 state transitions */
80 URTW_DEBUG_STAT = 0x00000040, /* statistic */
81 URTW_DEBUG_INIT = 0x00000080, /* initialization of dev */
82 URTW_DEBUG_TXSTATUS = 0x00000100, /* tx status */
83 URTW_DEBUG_ANY = 0xffffffff
84 };
85 #define DPRINTF(sc, m, fmt, ...) do { \
86 if (sc->sc_debug & (m)) \
87 printf(fmt, __VA_ARGS__); \
88 } while (0)
89 #else
90 #define DPRINTF(sc, m, fmt, ...) do { \
91 (void) sc; \
92 } while (0)
93 #endif
94 static int urtw_preamble_mode = URTW_PREAMBLE_MODE_LONG;
95 SYSCTL_INT(_hw_usb_urtw, OID_AUTO, preamble_mode, CTLFLAG_RWTUN,
96 &urtw_preamble_mode, 0, "set the preable mode (long or short)");
97
98 /* recognized device vendors/products */
99 #define urtw_lookup(v, p) \
100 ((const struct urtw_type *)usb_lookup(urtw_devs, v, p))
101 #define URTW_DEV_B(v,p) \
102 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTW_REV_RTL8187B) }
103 #define URTW_DEV_L(v,p) \
104 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTW_REV_RTL8187L) }
105 #define URTW_REV_RTL8187B 0
106 #define URTW_REV_RTL8187L 1
107 static const STRUCT_USB_HOST_ID urtw_devs[] = {
108 URTW_DEV_B(NETGEAR, WG111V3),
109 URTW_DEV_B(REALTEK, RTL8187B_0),
110 URTW_DEV_B(REALTEK, RTL8187B_1),
111 URTW_DEV_B(REALTEK, RTL8187B_2),
112 URTW_DEV_B(SITECOMEU, WL168V4),
113 URTW_DEV_L(ASUS, P5B_WIFI),
114 URTW_DEV_L(BELKIN, F5D7050E),
115 URTW_DEV_L(LINKSYS4, WUSB54GCV2),
116 URTW_DEV_L(NETGEAR, WG111V2),
117 URTW_DEV_L(REALTEK, RTL8187),
118 URTW_DEV_L(SITECOMEU, WL168V1),
119 URTW_DEV_L(SURECOM, EP9001G2A),
120 { USB_VPI(USB_VENDOR_OVISLINK, 0x8187, URTW_REV_RTL8187L) },
121 { USB_VPI(USB_VENDOR_DICKSMITH, 0x9401, URTW_REV_RTL8187L) },
122 { USB_VPI(USB_VENDOR_HP, 0xca02, URTW_REV_RTL8187L) },
123 { USB_VPI(USB_VENDOR_LOGITEC, 0x010c, URTW_REV_RTL8187L) },
124 { USB_VPI(USB_VENDOR_NETGEAR, 0x6100, URTW_REV_RTL8187L) },
125 { USB_VPI(USB_VENDOR_SPHAIRON, 0x0150, URTW_REV_RTL8187L) },
126 { USB_VPI(USB_VENDOR_QCOM, 0x6232, URTW_REV_RTL8187L) },
127 #undef URTW_DEV_L
128 #undef URTW_DEV_B
129 };
130
131 #define urtw_read8_m(sc, val, data) do { \
132 error = urtw_read8_c(sc, val, data); \
133 if (error != 0) \
134 goto fail; \
135 } while (0)
136 #define urtw_write8_m(sc, val, data) do { \
137 error = urtw_write8_c(sc, val, data); \
138 if (error != 0) \
139 goto fail; \
140 } while (0)
141 #define urtw_read16_m(sc, val, data) do { \
142 error = urtw_read16_c(sc, val, data); \
143 if (error != 0) \
144 goto fail; \
145 } while (0)
146 #define urtw_write16_m(sc, val, data) do { \
147 error = urtw_write16_c(sc, val, data); \
148 if (error != 0) \
149 goto fail; \
150 } while (0)
151 #define urtw_read32_m(sc, val, data) do { \
152 error = urtw_read32_c(sc, val, data); \
153 if (error != 0) \
154 goto fail; \
155 } while (0)
156 #define urtw_write32_m(sc, val, data) do { \
157 error = urtw_write32_c(sc, val, data); \
158 if (error != 0) \
159 goto fail; \
160 } while (0)
161 #define urtw_8187_write_phy_ofdm(sc, val, data) do { \
162 error = urtw_8187_write_phy_ofdm_c(sc, val, data); \
163 if (error != 0) \
164 goto fail; \
165 } while (0)
166 #define urtw_8187_write_phy_cck(sc, val, data) do { \
167 error = urtw_8187_write_phy_cck_c(sc, val, data); \
168 if (error != 0) \
169 goto fail; \
170 } while (0)
171 #define urtw_8225_write(sc, val, data) do { \
172 error = urtw_8225_write_c(sc, val, data); \
173 if (error != 0) \
174 goto fail; \
175 } while (0)
176
177 struct urtw_pair {
178 uint32_t reg;
179 uint32_t val;
180 };
181
182 static uint8_t urtw_8225_agc[] = {
183 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9d, 0x9c, 0x9b,
184 0x9a, 0x99, 0x98, 0x97, 0x96, 0x95, 0x94, 0x93, 0x92, 0x91, 0x90,
185 0x8f, 0x8e, 0x8d, 0x8c, 0x8b, 0x8a, 0x89, 0x88, 0x87, 0x86, 0x85,
186 0x84, 0x83, 0x82, 0x81, 0x80, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b, 0x3a,
187 0x39, 0x38, 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31, 0x30, 0x2f,
188 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29, 0x28, 0x27, 0x26, 0x25, 0x24,
189 0x23, 0x22, 0x21, 0x20, 0x1f, 0x1e, 0x1d, 0x1c, 0x1b, 0x1a, 0x19,
190 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e,
191 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03,
192 0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
193 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
194 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01
195 };
196
197 static uint8_t urtw_8225z2_agc[] = {
198 0x5e, 0x5e, 0x5e, 0x5e, 0x5d, 0x5b, 0x59, 0x57, 0x55, 0x53, 0x51,
199 0x4f, 0x4d, 0x4b, 0x49, 0x47, 0x45, 0x43, 0x41, 0x3f, 0x3d, 0x3b,
200 0x39, 0x37, 0x35, 0x33, 0x31, 0x2f, 0x2d, 0x2b, 0x29, 0x27, 0x25,
201 0x23, 0x21, 0x1f, 0x1d, 0x1b, 0x19, 0x17, 0x15, 0x13, 0x11, 0x0f,
202 0x0d, 0x0b, 0x09, 0x07, 0x05, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01,
203 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x19, 0x19,
204 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x20, 0x21, 0x22, 0x23,
205 0x24, 0x25, 0x26, 0x26, 0x27, 0x27, 0x28, 0x28, 0x29, 0x2a, 0x2a,
206 0x2a, 0x2b, 0x2b, 0x2b, 0x2c, 0x2c, 0x2c, 0x2d, 0x2d, 0x2d, 0x2d,
207 0x2e, 0x2e, 0x2e, 0x2e, 0x2f, 0x2f, 0x2f, 0x30, 0x30, 0x31, 0x31,
208 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31,
209 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31
210 };
211
212 static uint32_t urtw_8225_channel[] = {
213 0x0000, /* dummy channel 0 */
214 0x085c, /* 1 */
215 0x08dc, /* 2 */
216 0x095c, /* 3 */
217 0x09dc, /* 4 */
218 0x0a5c, /* 5 */
219 0x0adc, /* 6 */
220 0x0b5c, /* 7 */
221 0x0bdc, /* 8 */
222 0x0c5c, /* 9 */
223 0x0cdc, /* 10 */
224 0x0d5c, /* 11 */
225 0x0ddc, /* 12 */
226 0x0e5c, /* 13 */
227 0x0f72, /* 14 */
228 };
229
230 static uint8_t urtw_8225_gain[] = {
231 0x23, 0x88, 0x7c, 0xa5, /* -82dbm */
232 0x23, 0x88, 0x7c, 0xb5, /* -82dbm */
233 0x23, 0x88, 0x7c, 0xc5, /* -82dbm */
234 0x33, 0x80, 0x79, 0xc5, /* -78dbm */
235 0x43, 0x78, 0x76, 0xc5, /* -74dbm */
236 0x53, 0x60, 0x73, 0xc5, /* -70dbm */
237 0x63, 0x58, 0x70, 0xc5, /* -66dbm */
238 };
239
240 static struct urtw_pair urtw_8225_rf_part1[] = {
241 { 0x00, 0x0067 }, { 0x01, 0x0fe0 }, { 0x02, 0x044d }, { 0x03, 0x0441 },
242 { 0x04, 0x0486 }, { 0x05, 0x0bc0 }, { 0x06, 0x0ae6 }, { 0x07, 0x082a },
243 { 0x08, 0x001f }, { 0x09, 0x0334 }, { 0x0a, 0x0fd4 }, { 0x0b, 0x0391 },
244 { 0x0c, 0x0050 }, { 0x0d, 0x06db }, { 0x0e, 0x0029 }, { 0x0f, 0x0914 },
245 };
246
247 static struct urtw_pair urtw_8225_rf_part2[] = {
248 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 },
249 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 },
250 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x09 }, { 0x0b, 0x80 },
251 { 0x0c, 0x01 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 }, { 0x10, 0x84 },
252 { 0x11, 0x06 }, { 0x12, 0x20 }, { 0x13, 0x20 }, { 0x14, 0x00 },
253 { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 }, { 0x18, 0xef },
254 { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x76 }, { 0x1c, 0x04 },
255 { 0x1e, 0x95 }, { 0x1f, 0x75 }, { 0x20, 0x1f }, { 0x21, 0x27 },
256 { 0x22, 0x16 }, { 0x24, 0x46 }, { 0x25, 0x20 }, { 0x26, 0x90 },
257 { 0x27, 0x88 }
258 };
259
260 static struct urtw_pair urtw_8225_rf_part3[] = {
261 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 },
262 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x10, 0x9b },
263 { 0x11, 0x88 }, { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 },
264 { 0x1a, 0xa0 }, { 0x1b, 0x08 }, { 0x40, 0x86 }, { 0x41, 0x8d },
265 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x1f }, { 0x45, 0x1e },
266 { 0x46, 0x1a }, { 0x47, 0x15 }, { 0x48, 0x10 }, { 0x49, 0x0a },
267 { 0x4a, 0x05 }, { 0x4b, 0x02 }, { 0x4c, 0x05 }
268 };
269
270 static uint16_t urtw_8225_rxgain[] = {
271 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409,
272 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541,
273 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583,
274 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644,
275 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688,
276 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745,
277 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789,
278 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793,
279 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d,
280 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9,
281 0x07aa, 0x07ab, 0x07ac, 0x07ad, 0x07b0, 0x07b1, 0x07b2, 0x07b3,
282 0x07b4, 0x07b5, 0x07b8, 0x07b9, 0x07ba, 0x07bb, 0x07bb
283 };
284
285 static uint8_t urtw_8225_threshold[] = {
286 0x8d, 0x8d, 0x8d, 0x8d, 0x9d, 0xad, 0xbd,
287 };
288
289 static uint8_t urtw_8225_tx_gain_cck_ofdm[] = {
290 0x02, 0x06, 0x0e, 0x1e, 0x3e, 0x7e
291 };
292
293 static uint8_t urtw_8225_txpwr_cck[] = {
294 0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02,
295 0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02,
296 0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02,
297 0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02,
298 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03,
299 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03
300 };
301
302 static uint8_t urtw_8225_txpwr_cck_ch14[] = {
303 0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00,
304 0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00,
305 0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00,
306 0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00,
307 0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00,
308 0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00
309 };
310
311 static uint8_t urtw_8225_txpwr_ofdm[]={
312 0x80, 0x90, 0xa2, 0xb5, 0xcb, 0xe4
313 };
314
315 static uint8_t urtw_8225v2_gain_bg[]={
316 0x23, 0x15, 0xa5, /* -82-1dbm */
317 0x23, 0x15, 0xb5, /* -82-2dbm */
318 0x23, 0x15, 0xc5, /* -82-3dbm */
319 0x33, 0x15, 0xc5, /* -78dbm */
320 0x43, 0x15, 0xc5, /* -74dbm */
321 0x53, 0x15, 0xc5, /* -70dbm */
322 0x63, 0x15, 0xc5, /* -66dbm */
323 };
324
325 static struct urtw_pair urtw_8225v2_rf_part1[] = {
326 { 0x00, 0x02bf }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 },
327 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a },
328 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb },
329 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 }
330 };
331
332 static struct urtw_pair urtw_8225v2b_rf_part0[] = {
333 { 0x00, 0x00b7 }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 },
334 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a },
335 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb },
336 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 }
337 };
338
339 static struct urtw_pair urtw_8225v2b_rf_part1[] = {
340 {0x0f0, 0x32}, {0x0f1, 0x32}, {0x0f2, 0x00},
341 {0x0f3, 0x00}, {0x0f4, 0x32}, {0x0f5, 0x43},
342 {0x0f6, 0x00}, {0x0f7, 0x00}, {0x0f8, 0x46},
343 {0x0f9, 0xa4}, {0x0fa, 0x00}, {0x0fb, 0x00},
344 {0x0fc, 0x96}, {0x0fd, 0xa4}, {0x0fe, 0x00},
345 {0x0ff, 0x00}, {0x158, 0x4b}, {0x159, 0x00},
346 {0x15a, 0x4b}, {0x15b, 0x00}, {0x160, 0x4b},
347 {0x161, 0x09}, {0x162, 0x4b}, {0x163, 0x09},
348 {0x1ce, 0x0f}, {0x1cf, 0x00}, {0x1e0, 0xff},
349 {0x1e1, 0x0f}, {0x1e2, 0x00}, {0x1f0, 0x4e},
350 {0x1f1, 0x01}, {0x1f2, 0x02}, {0x1f3, 0x03},
351 {0x1f4, 0x04}, {0x1f5, 0x05}, {0x1f6, 0x06},
352 {0x1f7, 0x07}, {0x1f8, 0x08}, {0x24e, 0x00},
353 {0x20c, 0x04}, {0x221, 0x61}, {0x222, 0x68},
354 {0x223, 0x6f}, {0x224, 0x76}, {0x225, 0x7d},
355 {0x226, 0x84}, {0x227, 0x8d}, {0x24d, 0x08},
356 {0x250, 0x05}, {0x251, 0xf5}, {0x252, 0x04},
357 {0x253, 0xa0}, {0x254, 0x1f}, {0x255, 0x23},
358 {0x256, 0x45}, {0x257, 0x67}, {0x258, 0x08},
359 {0x259, 0x08}, {0x25a, 0x08}, {0x25b, 0x08},
360 {0x260, 0x08}, {0x261, 0x08}, {0x262, 0x08},
361 {0x263, 0x08}, {0x264, 0xcf}, {0x272, 0x56},
362 {0x273, 0x9a}, {0x034, 0xf0}, {0x035, 0x0f},
363 {0x05b, 0x40}, {0x084, 0x88}, {0x085, 0x24},
364 {0x088, 0x54}, {0x08b, 0xb8}, {0x08c, 0x07},
365 {0x08d, 0x00}, {0x094, 0x1b}, {0x095, 0x12},
366 {0x096, 0x00}, {0x097, 0x06}, {0x09d, 0x1a},
367 {0x09f, 0x10}, {0x0b4, 0x22}, {0x0be, 0x80},
368 {0x0db, 0x00}, {0x0ee, 0x00}, {0x091, 0x03},
369 {0x24c, 0x00}, {0x39f, 0x00}, {0x08c, 0x01},
370 {0x08d, 0x10}, {0x08e, 0x08}, {0x08f, 0x00}
371 };
372
373 static struct urtw_pair urtw_8225v2_rf_part2[] = {
374 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 },
375 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 },
376 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x08 }, { 0x0b, 0x80 },
377 { 0x0c, 0x01 }, { 0x0d, 0x43 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 },
378 { 0x10, 0x84 }, { 0x11, 0x07 }, { 0x12, 0x20 }, { 0x13, 0x20 },
379 { 0x14, 0x00 }, { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 },
380 { 0x18, 0xef }, { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x15 },
381 { 0x1c, 0x04 }, { 0x1d, 0xc5 }, { 0x1e, 0x95 }, { 0x1f, 0x75 },
382 { 0x20, 0x1f }, { 0x21, 0x17 }, { 0x22, 0x16 }, { 0x23, 0x80 },
383 { 0x24, 0x46 }, { 0x25, 0x00 }, { 0x26, 0x90 }, { 0x27, 0x88 }
384 };
385
386 static struct urtw_pair urtw_8225v2b_rf_part2[] = {
387 { 0x00, 0x10 }, { 0x01, 0x0d }, { 0x02, 0x01 }, { 0x03, 0x00 },
388 { 0x04, 0x14 }, { 0x05, 0xfb }, { 0x06, 0xfb }, { 0x07, 0x60 },
389 { 0x08, 0x00 }, { 0x09, 0x60 }, { 0x0a, 0x00 }, { 0x0b, 0x00 },
390 { 0x0c, 0x00 }, { 0x0d, 0x5c }, { 0x0e, 0x00 }, { 0x0f, 0x00 },
391 { 0x10, 0x40 }, { 0x11, 0x00 }, { 0x12, 0x40 }, { 0x13, 0x00 },
392 { 0x14, 0x00 }, { 0x15, 0x00 }, { 0x16, 0xa8 }, { 0x17, 0x26 },
393 { 0x18, 0x32 }, { 0x19, 0x33 }, { 0x1a, 0x07 }, { 0x1b, 0xa5 },
394 { 0x1c, 0x6f }, { 0x1d, 0x55 }, { 0x1e, 0xc8 }, { 0x1f, 0xb3 },
395 { 0x20, 0x0a }, { 0x21, 0xe1 }, { 0x22, 0x2C }, { 0x23, 0x8a },
396 { 0x24, 0x86 }, { 0x25, 0x83 }, { 0x26, 0x34 }, { 0x27, 0x0f },
397 { 0x28, 0x4f }, { 0x29, 0x24 }, { 0x2a, 0x6f }, { 0x2b, 0xc2 },
398 { 0x2c, 0x6b }, { 0x2d, 0x40 }, { 0x2e, 0x80 }, { 0x2f, 0x00 },
399 { 0x30, 0xc0 }, { 0x31, 0xc1 }, { 0x32, 0x58 }, { 0x33, 0xf1 },
400 { 0x34, 0x00 }, { 0x35, 0xe4 }, { 0x36, 0x90 }, { 0x37, 0x3e },
401 { 0x38, 0x6d }, { 0x39, 0x3c }, { 0x3a, 0xfb }, { 0x3b, 0x07 }
402 };
403
404 static struct urtw_pair urtw_8225v2_rf_part3[] = {
405 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 },
406 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x09, 0x11 },
407 { 0x0a, 0x17 }, { 0x0b, 0x11 }, { 0x10, 0x9b }, { 0x11, 0x88 },
408 { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 }, { 0x1a, 0xa0 },
409 { 0x1b, 0x08 }, { 0x1d, 0x00 }, { 0x40, 0x86 }, { 0x41, 0x9d },
410 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x36 }, { 0x45, 0x35 },
411 { 0x46, 0x2e }, { 0x47, 0x25 }, { 0x48, 0x1c }, { 0x49, 0x12 },
412 { 0x4a, 0x09 }, { 0x4b, 0x04 }, { 0x4c, 0x05 }
413 };
414
415 static uint16_t urtw_8225v2_rxgain[] = {
416 0x0000, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0008, 0x0009,
417 0x000a, 0x000b, 0x0102, 0x0103, 0x0104, 0x0105, 0x0140, 0x0141,
418 0x0142, 0x0143, 0x0144, 0x0145, 0x0180, 0x0181, 0x0182, 0x0183,
419 0x0184, 0x0185, 0x0188, 0x0189, 0x018a, 0x018b, 0x0243, 0x0244,
420 0x0245, 0x0280, 0x0281, 0x0282, 0x0283, 0x0284, 0x0285, 0x0288,
421 0x0289, 0x028a, 0x028b, 0x028c, 0x0342, 0x0343, 0x0344, 0x0345,
422 0x0380, 0x0381, 0x0382, 0x0383, 0x0384, 0x0385, 0x0388, 0x0389,
423 0x038a, 0x038b, 0x038c, 0x038d, 0x0390, 0x0391, 0x0392, 0x0393,
424 0x0394, 0x0395, 0x0398, 0x0399, 0x039a, 0x039b, 0x039c, 0x039d,
425 0x03a0, 0x03a1, 0x03a2, 0x03a3, 0x03a4, 0x03a5, 0x03a8, 0x03a9,
426 0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3,
427 0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb
428 };
429
430 static uint16_t urtw_8225v2b_rxgain[] = {
431 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409,
432 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541,
433 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583,
434 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644,
435 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688,
436 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745,
437 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789,
438 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793,
439 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d,
440 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9,
441 0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3,
442 0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb
443 };
444
445 static uint8_t urtw_8225v2_tx_gain_cck_ofdm[] = {
446 0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
447 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b,
448 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11,
449 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
450 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d,
451 0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23,
452 };
453
454 static uint8_t urtw_8225v2_txpwr_cck[] = {
455 0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04
456 };
457
458 static uint8_t urtw_8225v2_txpwr_cck_ch14[] = {
459 0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00
460 };
461
462 static uint8_t urtw_8225v2b_txpwr_cck[] = {
463 0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04,
464 0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03,
465 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03,
466 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03
467 };
468
469 static uint8_t urtw_8225v2b_txpwr_cck_ch14[] = {
470 0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00,
471 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00,
472 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00,
473 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00
474 };
475
476 static struct urtw_pair urtw_ratetable[] = {
477 { 2, 0 }, { 4, 1 }, { 11, 2 }, { 12, 4 }, { 18, 5 },
478 { 22, 3 }, { 24, 6 }, { 36, 7 }, { 48, 8 }, { 72, 9 },
479 { 96, 10 }, { 108, 11 }
480 };
481
482 #if 0
483 static const uint8_t urtw_8187b_reg_table[][3] = {
484 { 0xf0, 0x32, 0 }, { 0xf1, 0x32, 0 }, { 0xf2, 0x00, 0 },
485 { 0xf3, 0x00, 0 }, { 0xf4, 0x32, 0 }, { 0xf5, 0x43, 0 },
486 { 0xf6, 0x00, 0 }, { 0xf7, 0x00, 0 }, { 0xf8, 0x46, 0 },
487 { 0xf9, 0xa4, 0 }, { 0xfa, 0x00, 0 }, { 0xfb, 0x00, 0 },
488 { 0xfc, 0x96, 0 }, { 0xfd, 0xa4, 0 }, { 0xfe, 0x00, 0 },
489 { 0xff, 0x00, 0 }, { 0x58, 0x4b, 1 }, { 0x59, 0x00, 1 },
490 { 0x5a, 0x4b, 1 }, { 0x5b, 0x00, 1 }, { 0x60, 0x4b, 1 },
491 { 0x61, 0x09, 1 }, { 0x62, 0x4b, 1 }, { 0x63, 0x09, 1 },
492 { 0xce, 0x0f, 1 }, { 0xcf, 0x00, 1 }, { 0xe0, 0xff, 1 },
493 { 0xe1, 0x0f, 1 }, { 0xe2, 0x00, 1 }, { 0xf0, 0x4e, 1 },
494 { 0xf1, 0x01, 1 }, { 0xf2, 0x02, 1 }, { 0xf3, 0x03, 1 },
495 { 0xf4, 0x04, 1 }, { 0xf5, 0x05, 1 }, { 0xf6, 0x06, 1 },
496 { 0xf7, 0x07, 1 }, { 0xf8, 0x08, 1 }, { 0x4e, 0x00, 2 },
497 { 0x0c, 0x04, 2 }, { 0x21, 0x61, 2 }, { 0x22, 0x68, 2 },
498 { 0x23, 0x6f, 2 }, { 0x24, 0x76, 2 }, { 0x25, 0x7d, 2 },
499 { 0x26, 0x84, 2 }, { 0x27, 0x8d, 2 }, { 0x4d, 0x08, 2 },
500 { 0x50, 0x05, 2 }, { 0x51, 0xf5, 2 }, { 0x52, 0x04, 2 },
501 { 0x53, 0xa0, 2 }, { 0x54, 0x1f, 2 }, { 0x55, 0x23, 2 },
502 { 0x56, 0x45, 2 }, { 0x57, 0x67, 2 }, { 0x58, 0x08, 2 },
503 { 0x59, 0x08, 2 }, { 0x5a, 0x08, 2 }, { 0x5b, 0x08, 2 },
504 { 0x60, 0x08, 2 }, { 0x61, 0x08, 2 }, { 0x62, 0x08, 2 },
505 { 0x63, 0x08, 2 }, { 0x64, 0xcf, 2 }, { 0x72, 0x56, 2 },
506 { 0x73, 0x9a, 2 }, { 0x34, 0xf0, 0 }, { 0x35, 0x0f, 0 },
507 { 0x5b, 0x40, 0 }, { 0x84, 0x88, 0 }, { 0x85, 0x24, 0 },
508 { 0x88, 0x54, 0 }, { 0x8b, 0xb8, 0 }, { 0x8c, 0x07, 0 },
509 { 0x8d, 0x00, 0 }, { 0x94, 0x1b, 0 }, { 0x95, 0x12, 0 },
510 { 0x96, 0x00, 0 }, { 0x97, 0x06, 0 }, { 0x9d, 0x1a, 0 },
511 { 0x9f, 0x10, 0 }, { 0xb4, 0x22, 0 }, { 0xbe, 0x80, 0 },
512 { 0xdb, 0x00, 0 }, { 0xee, 0x00, 0 }, { 0x91, 0x03, 0 },
513 { 0x4c, 0x00, 2 }, { 0x9f, 0x00, 3 }, { 0x8c, 0x01, 0 },
514 { 0x8d, 0x10, 0 }, { 0x8e, 0x08, 0 }, { 0x8f, 0x00, 0 }
515 };
516 #endif
517
518 static usb_callback_t urtw_bulk_rx_callback;
519 static usb_callback_t urtw_bulk_tx_callback;
520 static usb_callback_t urtw_bulk_tx_status_callback;
521
522 static const struct usb_config urtw_8187b_usbconfig[URTW_8187B_N_XFERS] = {
523 [URTW_8187B_BULK_RX] = {
524 .type = UE_BULK,
525 .endpoint = 0x83,
526 .direction = UE_DIR_IN,
527 .bufsize = MCLBYTES,
528 .flags = {
529 .ext_buffer = 1,
530 .pipe_bof = 1,
531 .short_xfer_ok = 1
532 },
533 .callback = urtw_bulk_rx_callback
534 },
535 [URTW_8187B_BULK_TX_STATUS] = {
536 .type = UE_BULK,
537 .endpoint = 0x89,
538 .direction = UE_DIR_IN,
539 .bufsize = sizeof(uint64_t),
540 .flags = {
541 .pipe_bof = 1,
542 .short_xfer_ok = 1
543 },
544 .callback = urtw_bulk_tx_status_callback
545 },
546 [URTW_8187B_BULK_TX_BE] = {
547 .type = UE_BULK,
548 .endpoint = URTW_8187B_TXPIPE_BE,
549 .direction = UE_DIR_OUT,
550 .bufsize = URTW_TX_MAXSIZE * URTW_TX_DATA_LIST_COUNT,
551 .flags = {
552 .force_short_xfer = 1,
553 .pipe_bof = 1,
554 },
555 .callback = urtw_bulk_tx_callback,
556 .timeout = URTW_DATA_TIMEOUT
557 },
558 [URTW_8187B_BULK_TX_BK] = {
559 .type = UE_BULK,
560 .endpoint = URTW_8187B_TXPIPE_BK,
561 .direction = UE_DIR_OUT,
562 .bufsize = URTW_TX_MAXSIZE,
563 .flags = {
564 .ext_buffer = 1,
565 .force_short_xfer = 1,
566 .pipe_bof = 1,
567 },
568 .callback = urtw_bulk_tx_callback,
569 .timeout = URTW_DATA_TIMEOUT
570 },
571 [URTW_8187B_BULK_TX_VI] = {
572 .type = UE_BULK,
573 .endpoint = URTW_8187B_TXPIPE_VI,
574 .direction = UE_DIR_OUT,
575 .bufsize = URTW_TX_MAXSIZE,
576 .flags = {
577 .ext_buffer = 1,
578 .force_short_xfer = 1,
579 .pipe_bof = 1,
580 },
581 .callback = urtw_bulk_tx_callback,
582 .timeout = URTW_DATA_TIMEOUT
583 },
584 [URTW_8187B_BULK_TX_VO] = {
585 .type = UE_BULK,
586 .endpoint = URTW_8187B_TXPIPE_VO,
587 .direction = UE_DIR_OUT,
588 .bufsize = URTW_TX_MAXSIZE,
589 .flags = {
590 .ext_buffer = 1,
591 .force_short_xfer = 1,
592 .pipe_bof = 1,
593 },
594 .callback = urtw_bulk_tx_callback,
595 .timeout = URTW_DATA_TIMEOUT
596 },
597 [URTW_8187B_BULK_TX_EP12] = {
598 .type = UE_BULK,
599 .endpoint = 0xc,
600 .direction = UE_DIR_OUT,
601 .bufsize = URTW_TX_MAXSIZE,
602 .flags = {
603 .ext_buffer = 1,
604 .force_short_xfer = 1,
605 .pipe_bof = 1,
606 },
607 .callback = urtw_bulk_tx_callback,
608 .timeout = URTW_DATA_TIMEOUT
609 }
610 };
611
612 static const struct usb_config urtw_8187l_usbconfig[URTW_8187L_N_XFERS] = {
613 [URTW_8187L_BULK_RX] = {
614 .type = UE_BULK,
615 .endpoint = 0x81,
616 .direction = UE_DIR_IN,
617 .bufsize = MCLBYTES,
618 .flags = {
619 .ext_buffer = 1,
620 .pipe_bof = 1,
621 .short_xfer_ok = 1
622 },
623 .callback = urtw_bulk_rx_callback
624 },
625 [URTW_8187L_BULK_TX_LOW] = {
626 .type = UE_BULK,
627 .endpoint = 0x2,
628 .direction = UE_DIR_OUT,
629 .bufsize = URTW_TX_MAXSIZE * URTW_TX_DATA_LIST_COUNT,
630 .flags = {
631 .force_short_xfer = 1,
632 .pipe_bof = 1,
633 },
634 .callback = urtw_bulk_tx_callback,
635 .timeout = URTW_DATA_TIMEOUT
636 },
637 [URTW_8187L_BULK_TX_NORMAL] = {
638 .type = UE_BULK,
639 .endpoint = 0x3,
640 .direction = UE_DIR_OUT,
641 .bufsize = URTW_TX_MAXSIZE,
642 .flags = {
643 .ext_buffer = 1,
644 .force_short_xfer = 1,
645 .pipe_bof = 1,
646 },
647 .callback = urtw_bulk_tx_callback,
648 .timeout = URTW_DATA_TIMEOUT
649 },
650 };
651
652 static struct ieee80211vap *urtw_vap_create(struct ieee80211com *,
653 const char [IFNAMSIZ], int, enum ieee80211_opmode,
654 int, const uint8_t [IEEE80211_ADDR_LEN],
655 const uint8_t [IEEE80211_ADDR_LEN]);
656 static void urtw_vap_delete(struct ieee80211vap *);
657 static void urtw_init(struct urtw_softc *);
658 static void urtw_stop(struct urtw_softc *);
659 static void urtw_parent(struct ieee80211com *);
660 static int urtw_transmit(struct ieee80211com *, struct mbuf *);
661 static void urtw_start(struct urtw_softc *);
662 static int urtw_alloc_rx_data_list(struct urtw_softc *);
663 static int urtw_alloc_tx_data_list(struct urtw_softc *);
664 static int urtw_raw_xmit(struct ieee80211_node *, struct mbuf *,
665 const struct ieee80211_bpf_params *);
666 static void urtw_scan_start(struct ieee80211com *);
667 static void urtw_scan_end(struct ieee80211com *);
668 static void urtw_getradiocaps(struct ieee80211com *, int, int *,
669 struct ieee80211_channel[]);
670 static void urtw_set_channel(struct ieee80211com *);
671 static void urtw_update_promisc(struct ieee80211com *);
672 static void urtw_update_mcast(struct ieee80211com *);
673 static int urtw_tx_start(struct urtw_softc *,
674 struct ieee80211_node *, struct mbuf *,
675 struct urtw_data *, int);
676 static int urtw_newstate(struct ieee80211vap *,
677 enum ieee80211_state, int);
678 static void urtw_led_ch(void *);
679 static void urtw_ledtask(void *, int);
680 static void urtw_watchdog(void *);
681 static void urtw_set_multi(void *);
682 static int urtw_isbmode(uint16_t);
683 static uint16_t urtw_rtl2rate(uint32_t);
684 static usb_error_t urtw_set_rate(struct urtw_softc *);
685 static usb_error_t urtw_update_msr(struct urtw_softc *);
686 static usb_error_t urtw_read8_c(struct urtw_softc *, int, uint8_t *);
687 static usb_error_t urtw_read16_c(struct urtw_softc *, int, uint16_t *);
688 static usb_error_t urtw_read32_c(struct urtw_softc *, int, uint32_t *);
689 static usb_error_t urtw_write8_c(struct urtw_softc *, int, uint8_t);
690 static usb_error_t urtw_write16_c(struct urtw_softc *, int, uint16_t);
691 static usb_error_t urtw_write32_c(struct urtw_softc *, int, uint32_t);
692 static usb_error_t urtw_eprom_cs(struct urtw_softc *, int);
693 static usb_error_t urtw_eprom_ck(struct urtw_softc *);
694 static usb_error_t urtw_eprom_sendbits(struct urtw_softc *, int16_t *,
695 int);
696 static usb_error_t urtw_eprom_read32(struct urtw_softc *, uint32_t,
697 uint32_t *);
698 static usb_error_t urtw_eprom_readbit(struct urtw_softc *, int16_t *);
699 static usb_error_t urtw_eprom_writebit(struct urtw_softc *, int16_t);
700 static usb_error_t urtw_get_macaddr(struct urtw_softc *);
701 static usb_error_t urtw_get_txpwr(struct urtw_softc *);
702 static usb_error_t urtw_get_rfchip(struct urtw_softc *);
703 static usb_error_t urtw_led_init(struct urtw_softc *);
704 static usb_error_t urtw_8185_rf_pins_enable(struct urtw_softc *);
705 static usb_error_t urtw_8185_tx_antenna(struct urtw_softc *, uint8_t);
706 static usb_error_t urtw_8187_write_phy(struct urtw_softc *, uint8_t,
707 uint32_t);
708 static usb_error_t urtw_8187_write_phy_ofdm_c(struct urtw_softc *,
709 uint8_t, uint32_t);
710 static usb_error_t urtw_8187_write_phy_cck_c(struct urtw_softc *, uint8_t,
711 uint32_t);
712 static usb_error_t urtw_8225_setgain(struct urtw_softc *, int16_t);
713 static usb_error_t urtw_8225_usb_init(struct urtw_softc *);
714 static usb_error_t urtw_8225_write_c(struct urtw_softc *, uint8_t,
715 uint16_t);
716 static usb_error_t urtw_8225_write_s16(struct urtw_softc *, uint8_t, int,
717 uint16_t *);
718 static usb_error_t urtw_8225_read(struct urtw_softc *, uint8_t,
719 uint32_t *);
720 static usb_error_t urtw_8225_rf_init(struct urtw_softc *);
721 static usb_error_t urtw_8225_rf_set_chan(struct urtw_softc *, int);
722 static usb_error_t urtw_8225_rf_set_sens(struct urtw_softc *, int);
723 static usb_error_t urtw_8225_set_txpwrlvl(struct urtw_softc *, int);
724 static usb_error_t urtw_8225_rf_stop(struct urtw_softc *);
725 static usb_error_t urtw_8225v2_rf_init(struct urtw_softc *);
726 static usb_error_t urtw_8225v2_rf_set_chan(struct urtw_softc *, int);
727 static usb_error_t urtw_8225v2_set_txpwrlvl(struct urtw_softc *, int);
728 static usb_error_t urtw_8225v2_setgain(struct urtw_softc *, int16_t);
729 static usb_error_t urtw_8225_isv2(struct urtw_softc *, int *);
730 static usb_error_t urtw_8225v2b_rf_init(struct urtw_softc *);
731 static usb_error_t urtw_8225v2b_rf_set_chan(struct urtw_softc *, int);
732 static usb_error_t urtw_read8e(struct urtw_softc *, int, uint8_t *);
733 static usb_error_t urtw_write8e(struct urtw_softc *, int, uint8_t);
734 static usb_error_t urtw_8180_set_anaparam(struct urtw_softc *, uint32_t);
735 static usb_error_t urtw_8185_set_anaparam2(struct urtw_softc *, uint32_t);
736 static usb_error_t urtw_intr_enable(struct urtw_softc *);
737 static usb_error_t urtw_intr_disable(struct urtw_softc *);
738 static usb_error_t urtw_reset(struct urtw_softc *);
739 static usb_error_t urtw_led_on(struct urtw_softc *, int);
740 static usb_error_t urtw_led_ctl(struct urtw_softc *, int);
741 static usb_error_t urtw_led_blink(struct urtw_softc *);
742 static usb_error_t urtw_led_mode0(struct urtw_softc *, int);
743 static usb_error_t urtw_led_mode1(struct urtw_softc *, int);
744 static usb_error_t urtw_led_mode2(struct urtw_softc *, int);
745 static usb_error_t urtw_led_mode3(struct urtw_softc *, int);
746 static usb_error_t urtw_rx_setconf(struct urtw_softc *);
747 static usb_error_t urtw_rx_enable(struct urtw_softc *);
748 static usb_error_t urtw_tx_enable(struct urtw_softc *sc);
749 static void urtw_free_tx_data_list(struct urtw_softc *);
750 static void urtw_free_rx_data_list(struct urtw_softc *);
751 static void urtw_free_data_list(struct urtw_softc *,
752 struct urtw_data data[], int, int);
753 static usb_error_t urtw_set_macaddr(struct urtw_softc *, const uint8_t *);
754 static usb_error_t urtw_adapter_start(struct urtw_softc *);
755 static usb_error_t urtw_adapter_start_b(struct urtw_softc *);
756 static usb_error_t urtw_set_mode(struct urtw_softc *, uint32_t);
757 static usb_error_t urtw_8187b_cmd_reset(struct urtw_softc *);
758 static usb_error_t urtw_do_request(struct urtw_softc *,
759 struct usb_device_request *, void *);
760 static usb_error_t urtw_8225v2b_set_txpwrlvl(struct urtw_softc *, int);
761 static usb_error_t urtw_led_off(struct urtw_softc *, int);
762 static void urtw_abort_xfers(struct urtw_softc *);
763 static struct urtw_data *
764 urtw_getbuf(struct urtw_softc *sc);
765 static int urtw_compute_txtime(uint16_t, uint16_t, uint8_t,
766 uint8_t);
767 static void urtw_updateslot(struct ieee80211com *);
768 static void urtw_updateslottask(void *, int);
769 static void urtw_sysctl_node(struct urtw_softc *);
770
771 static int
urtw_match(device_t dev)772 urtw_match(device_t dev)
773 {
774 struct usb_attach_arg *uaa = device_get_ivars(dev);
775
776 if (uaa->usb_mode != USB_MODE_HOST)
777 return (ENXIO);
778 if (uaa->info.bConfigIndex != URTW_CONFIG_INDEX)
779 return (ENXIO);
780 if (uaa->info.bIfaceIndex != URTW_IFACE_INDEX)
781 return (ENXIO);
782
783 return (usbd_lookup_id_by_uaa(urtw_devs, sizeof(urtw_devs), uaa));
784 }
785
786 static int
urtw_attach(device_t dev)787 urtw_attach(device_t dev)
788 {
789 const struct usb_config *setup_start;
790 int ret = ENXIO;
791 struct urtw_softc *sc = device_get_softc(dev);
792 struct usb_attach_arg *uaa = device_get_ivars(dev);
793 struct ieee80211com *ic = &sc->sc_ic;
794 uint8_t iface_index = URTW_IFACE_INDEX; /* XXX */
795 uint16_t n_setup;
796 uint32_t data;
797 usb_error_t error;
798
799 device_set_usb_desc(dev);
800
801 sc->sc_dev = dev;
802 sc->sc_udev = uaa->device;
803 if (USB_GET_DRIVER_INFO(uaa) == URTW_REV_RTL8187B)
804 sc->sc_flags |= URTW_RTL8187B;
805 #ifdef URTW_DEBUG
806 sc->sc_debug = urtw_debug;
807 #endif
808
809 mtx_init(&sc->sc_mtx, device_get_nameunit(sc->sc_dev), MTX_NETWORK_LOCK,
810 MTX_DEF);
811 usb_callout_init_mtx(&sc->sc_led_ch, &sc->sc_mtx, 0);
812 TASK_INIT(&sc->sc_led_task, 0, urtw_ledtask, sc);
813 TASK_INIT(&sc->sc_updateslot_task, 0, urtw_updateslottask, sc);
814 callout_init(&sc->sc_watchdog_ch, 0);
815 mbufq_init(&sc->sc_snd, ifqmaxlen);
816
817 if (sc->sc_flags & URTW_RTL8187B) {
818 setup_start = urtw_8187b_usbconfig;
819 n_setup = URTW_8187B_N_XFERS;
820 } else {
821 setup_start = urtw_8187l_usbconfig;
822 n_setup = URTW_8187L_N_XFERS;
823 }
824
825 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer,
826 setup_start, n_setup, sc, &sc->sc_mtx);
827 if (error) {
828 device_printf(dev, "could not allocate USB transfers, "
829 "err=%s\n", usbd_errstr(error));
830 ret = ENXIO;
831 goto fail0;
832 }
833
834 if (sc->sc_flags & URTW_RTL8187B) {
835 sc->sc_tx_dma_buf =
836 usbd_xfer_get_frame_buffer(sc->sc_xfer[
837 URTW_8187B_BULK_TX_BE], 0);
838 } else {
839 sc->sc_tx_dma_buf =
840 usbd_xfer_get_frame_buffer(sc->sc_xfer[
841 URTW_8187L_BULK_TX_LOW], 0);
842 }
843
844 URTW_LOCK(sc);
845
846 urtw_read32_m(sc, URTW_RX, &data);
847 sc->sc_epromtype = (data & URTW_RX_9356SEL) ? URTW_EEPROM_93C56 :
848 URTW_EEPROM_93C46;
849
850 error = urtw_get_rfchip(sc);
851 if (error != 0)
852 goto fail;
853 error = urtw_get_macaddr(sc);
854 if (error != 0)
855 goto fail;
856 error = urtw_get_txpwr(sc);
857 if (error != 0)
858 goto fail;
859 error = urtw_led_init(sc);
860 if (error != 0)
861 goto fail;
862
863 URTW_UNLOCK(sc);
864
865 sc->sc_rts_retry = URTW_DEFAULT_RTS_RETRY;
866 sc->sc_tx_retry = URTW_DEFAULT_TX_RETRY;
867 sc->sc_currate = URTW_RIDX_CCK11;
868 sc->sc_preamble_mode = urtw_preamble_mode;
869
870 ic->ic_softc = sc;
871 ic->ic_name = device_get_nameunit(dev);
872 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
873 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */
874
875 /* set device capabilities */
876 ic->ic_caps =
877 IEEE80211_C_STA | /* station mode */
878 IEEE80211_C_MONITOR | /* monitor mode supported */
879 IEEE80211_C_TXPMGT | /* tx power management */
880 IEEE80211_C_SHPREAMBLE | /* short preamble supported */
881 IEEE80211_C_SHSLOT | /* short slot time supported */
882 IEEE80211_C_BGSCAN | /* capable of bg scanning */
883 IEEE80211_C_WPA; /* 802.11i */
884
885 /* XXX TODO: setup regdomain if URTW_EPROM_CHANPLAN_BY_HW bit is set.*/
886
887 urtw_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans,
888 ic->ic_channels);
889
890 ieee80211_ifattach(ic);
891 ic->ic_raw_xmit = urtw_raw_xmit;
892 ic->ic_scan_start = urtw_scan_start;
893 ic->ic_scan_end = urtw_scan_end;
894 ic->ic_getradiocaps = urtw_getradiocaps;
895 ic->ic_set_channel = urtw_set_channel;
896 ic->ic_updateslot = urtw_updateslot;
897 ic->ic_vap_create = urtw_vap_create;
898 ic->ic_vap_delete = urtw_vap_delete;
899 ic->ic_update_promisc = urtw_update_promisc;
900 ic->ic_update_mcast = urtw_update_mcast;
901 ic->ic_parent = urtw_parent;
902 ic->ic_transmit = urtw_transmit;
903
904 ieee80211_radiotap_attach(ic,
905 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap),
906 URTW_TX_RADIOTAP_PRESENT,
907 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap),
908 URTW_RX_RADIOTAP_PRESENT);
909
910 urtw_sysctl_node(sc);
911
912 if (bootverbose)
913 ieee80211_announce(ic);
914 return (0);
915
916 fail:
917 URTW_UNLOCK(sc);
918 usbd_transfer_unsetup(sc->sc_xfer, (sc->sc_flags & URTW_RTL8187B) ?
919 URTW_8187B_N_XFERS : URTW_8187L_N_XFERS);
920 fail0:
921 return (ret);
922 }
923
924 static int
urtw_detach(device_t dev)925 urtw_detach(device_t dev)
926 {
927 struct urtw_softc *sc = device_get_softc(dev);
928 struct ieee80211com *ic = &sc->sc_ic;
929 unsigned x;
930 unsigned n_xfers;
931
932 /* Prevent further ioctls */
933 URTW_LOCK(sc);
934 sc->sc_flags |= URTW_DETACHED;
935 urtw_stop(sc);
936 URTW_UNLOCK(sc);
937
938 ieee80211_draintask(ic, &sc->sc_updateslot_task);
939 ieee80211_draintask(ic, &sc->sc_led_task);
940
941 usb_callout_drain(&sc->sc_led_ch);
942 callout_drain(&sc->sc_watchdog_ch);
943
944 n_xfers = (sc->sc_flags & URTW_RTL8187B) ?
945 URTW_8187B_N_XFERS : URTW_8187L_N_XFERS;
946
947 /* prevent further allocations from RX/TX data lists */
948 URTW_LOCK(sc);
949 STAILQ_INIT(&sc->sc_tx_active);
950 STAILQ_INIT(&sc->sc_tx_inactive);
951 STAILQ_INIT(&sc->sc_tx_pending);
952
953 STAILQ_INIT(&sc->sc_rx_active);
954 STAILQ_INIT(&sc->sc_rx_inactive);
955 URTW_UNLOCK(sc);
956
957 /* drain USB transfers */
958 for (x = 0; x != n_xfers; x++)
959 usbd_transfer_drain(sc->sc_xfer[x]);
960
961 /* free data buffers */
962 URTW_LOCK(sc);
963 urtw_free_tx_data_list(sc);
964 urtw_free_rx_data_list(sc);
965 URTW_UNLOCK(sc);
966
967 /* free USB transfers and some data buffers */
968 usbd_transfer_unsetup(sc->sc_xfer, n_xfers);
969
970 ieee80211_ifdetach(ic);
971 mbufq_drain(&sc->sc_snd);
972 mtx_destroy(&sc->sc_mtx);
973 return (0);
974 }
975
976 static void
urtw_free_tx_data_list(struct urtw_softc * sc)977 urtw_free_tx_data_list(struct urtw_softc *sc)
978 {
979 urtw_free_data_list(sc, sc->sc_tx, URTW_TX_DATA_LIST_COUNT, 0);
980 }
981
982 static void
urtw_free_rx_data_list(struct urtw_softc * sc)983 urtw_free_rx_data_list(struct urtw_softc *sc)
984 {
985 urtw_free_data_list(sc, sc->sc_rx, URTW_RX_DATA_LIST_COUNT, 1);
986 }
987
988 static void
urtw_free_data_list(struct urtw_softc * sc,struct urtw_data data[],int ndata,int fillmbuf)989 urtw_free_data_list(struct urtw_softc *sc, struct urtw_data data[], int ndata,
990 int fillmbuf)
991 {
992 int i;
993
994 for (i = 0; i < ndata; i++) {
995 struct urtw_data *dp = &data[i];
996
997 if (fillmbuf == 1) {
998 if (dp->m != NULL) {
999 m_freem(dp->m);
1000 dp->m = NULL;
1001 dp->buf = NULL;
1002 }
1003 } else {
1004 dp->buf = NULL;
1005 }
1006 if (dp->ni != NULL) {
1007 ieee80211_free_node(dp->ni);
1008 dp->ni = NULL;
1009 }
1010 }
1011 }
1012
1013 static struct ieee80211vap *
urtw_vap_create(struct ieee80211com * ic,const char name[IFNAMSIZ],int unit,enum ieee80211_opmode opmode,int flags,const uint8_t bssid[IEEE80211_ADDR_LEN],const uint8_t mac[IEEE80211_ADDR_LEN])1014 urtw_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
1015 enum ieee80211_opmode opmode, int flags,
1016 const uint8_t bssid[IEEE80211_ADDR_LEN],
1017 const uint8_t mac[IEEE80211_ADDR_LEN])
1018 {
1019 struct urtw_vap *uvp;
1020 struct ieee80211vap *vap;
1021
1022 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */
1023 return (NULL);
1024 uvp = malloc(sizeof(struct urtw_vap), M_80211_VAP, M_WAITOK | M_ZERO);
1025 vap = &uvp->vap;
1026 /* enable s/w bmiss handling for sta mode */
1027
1028 if (ieee80211_vap_setup(ic, vap, name, unit, opmode,
1029 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) {
1030 /* out of memory */
1031 free(uvp, M_80211_VAP);
1032 return (NULL);
1033 }
1034
1035 /* override state transition machine */
1036 uvp->newstate = vap->iv_newstate;
1037 vap->iv_newstate = urtw_newstate;
1038
1039 /* complete setup */
1040 ieee80211_vap_attach(vap, ieee80211_media_change,
1041 ieee80211_media_status, mac);
1042 ic->ic_opmode = opmode;
1043 return (vap);
1044 }
1045
1046 static void
urtw_vap_delete(struct ieee80211vap * vap)1047 urtw_vap_delete(struct ieee80211vap *vap)
1048 {
1049 struct urtw_vap *uvp = URTW_VAP(vap);
1050
1051 ieee80211_vap_detach(vap);
1052 free(uvp, M_80211_VAP);
1053 }
1054
1055 static void
urtw_init(struct urtw_softc * sc)1056 urtw_init(struct urtw_softc *sc)
1057 {
1058 usb_error_t error;
1059 int ret;
1060
1061 URTW_ASSERT_LOCKED(sc);
1062
1063 if (sc->sc_flags & URTW_RUNNING)
1064 urtw_stop(sc);
1065
1066 error = (sc->sc_flags & URTW_RTL8187B) ? urtw_adapter_start_b(sc) :
1067 urtw_adapter_start(sc);
1068 if (error != 0)
1069 goto fail;
1070
1071 /* reset softc variables */
1072 sc->sc_txtimer = 0;
1073
1074 if (!(sc->sc_flags & URTW_INIT_ONCE)) {
1075 ret = urtw_alloc_rx_data_list(sc);
1076 if (ret != 0)
1077 goto fail;
1078 ret = urtw_alloc_tx_data_list(sc);
1079 if (ret != 0)
1080 goto fail;
1081 sc->sc_flags |= URTW_INIT_ONCE;
1082 }
1083
1084 error = urtw_rx_enable(sc);
1085 if (error != 0)
1086 goto fail;
1087 error = urtw_tx_enable(sc);
1088 if (error != 0)
1089 goto fail;
1090
1091 if (sc->sc_flags & URTW_RTL8187B)
1092 usbd_transfer_start(sc->sc_xfer[URTW_8187B_BULK_TX_STATUS]);
1093
1094 sc->sc_flags |= URTW_RUNNING;
1095
1096 callout_reset(&sc->sc_watchdog_ch, hz, urtw_watchdog, sc);
1097 fail:
1098 return;
1099 }
1100
1101 static usb_error_t
urtw_adapter_start_b(struct urtw_softc * sc)1102 urtw_adapter_start_b(struct urtw_softc *sc)
1103 {
1104 uint8_t data8;
1105 usb_error_t error;
1106
1107 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
1108 if (error)
1109 goto fail;
1110
1111 urtw_read8_m(sc, URTW_CONFIG3, &data8);
1112 urtw_write8_m(sc, URTW_CONFIG3,
1113 data8 | URTW_CONFIG3_ANAPARAM_WRITE | URTW_CONFIG3_GNT_SELECT);
1114 urtw_write32_m(sc, URTW_ANAPARAM2, URTW_8187B_8225_ANAPARAM2_ON);
1115 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8187B_8225_ANAPARAM_ON);
1116 urtw_write8_m(sc, URTW_ANAPARAM3, URTW_8187B_8225_ANAPARAM3_ON);
1117
1118 urtw_write8_m(sc, 0x61, 0x10);
1119 urtw_read8_m(sc, 0x62, &data8);
1120 urtw_write8_m(sc, 0x62, data8 & ~(1 << 5));
1121 urtw_write8_m(sc, 0x62, data8 | (1 << 5));
1122
1123 urtw_read8_m(sc, URTW_CONFIG3, &data8);
1124 data8 &= ~URTW_CONFIG3_ANAPARAM_WRITE;
1125 urtw_write8_m(sc, URTW_CONFIG3, data8);
1126
1127 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
1128 if (error)
1129 goto fail;
1130
1131 error = urtw_8187b_cmd_reset(sc);
1132 if (error)
1133 goto fail;
1134
1135 error = sc->sc_rf_init(sc);
1136 if (error != 0)
1137 goto fail;
1138 urtw_write8_m(sc, URTW_CMD, URTW_CMD_RX_ENABLE | URTW_CMD_TX_ENABLE);
1139
1140 /* fix RTL8187B RX stall */
1141 error = urtw_intr_enable(sc);
1142 if (error)
1143 goto fail;
1144
1145 error = urtw_write8e(sc, 0x41, 0xf4);
1146 if (error)
1147 goto fail;
1148 error = urtw_write8e(sc, 0x40, 0x00);
1149 if (error)
1150 goto fail;
1151 error = urtw_write8e(sc, 0x42, 0x00);
1152 if (error)
1153 goto fail;
1154 error = urtw_write8e(sc, 0x42, 0x01);
1155 if (error)
1156 goto fail;
1157 error = urtw_write8e(sc, 0x40, 0x0f);
1158 if (error)
1159 goto fail;
1160 error = urtw_write8e(sc, 0x42, 0x00);
1161 if (error)
1162 goto fail;
1163 error = urtw_write8e(sc, 0x42, 0x01);
1164 if (error)
1165 goto fail;
1166
1167 urtw_read8_m(sc, 0xdb, &data8);
1168 urtw_write8_m(sc, 0xdb, data8 | (1 << 2));
1169 urtw_write16_m(sc, 0x372, 0x59fa);
1170 urtw_write16_m(sc, 0x374, 0x59d2);
1171 urtw_write16_m(sc, 0x376, 0x59d2);
1172 urtw_write16_m(sc, 0x378, 0x19fa);
1173 urtw_write16_m(sc, 0x37a, 0x19fa);
1174 urtw_write16_m(sc, 0x37c, 0x00d0);
1175 urtw_write8_m(sc, 0x61, 0);
1176
1177 urtw_write8_m(sc, 0x180, 0x0f);
1178 urtw_write8_m(sc, 0x183, 0x03);
1179 urtw_write8_m(sc, 0xda, 0x10);
1180 urtw_write8_m(sc, 0x24d, 0x08);
1181 urtw_write32_m(sc, URTW_HSSI_PARA, 0x0600321b);
1182
1183 urtw_write16_m(sc, 0x1ec, 0x800); /* RX MAX SIZE */
1184 fail:
1185 return (error);
1186 }
1187
1188 static usb_error_t
urtw_set_macaddr(struct urtw_softc * sc,const uint8_t * macaddr)1189 urtw_set_macaddr(struct urtw_softc *sc, const uint8_t *macaddr)
1190 {
1191 usb_error_t error;
1192
1193 urtw_write32_m(sc, URTW_MAC0, ((const uint32_t *)macaddr)[0]);
1194 urtw_write16_m(sc, URTW_MAC4, ((const uint32_t *)macaddr)[1] & 0xffff);
1195
1196 fail:
1197 return (error);
1198 }
1199
1200 static usb_error_t
urtw_adapter_start(struct urtw_softc * sc)1201 urtw_adapter_start(struct urtw_softc *sc)
1202 {
1203 struct ieee80211com *ic = &sc->sc_ic;
1204 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
1205 const uint8_t *macaddr;
1206 usb_error_t error;
1207
1208 error = urtw_reset(sc);
1209 if (error)
1210 goto fail;
1211
1212 urtw_write8_m(sc, URTW_ADDR_MAGIC1, 0);
1213 urtw_write8_m(sc, URTW_GPIO, 0);
1214
1215 /* for led */
1216 urtw_write8_m(sc, URTW_ADDR_MAGIC1, 4);
1217 error = urtw_led_ctl(sc, URTW_LED_CTL_POWER_ON);
1218 if (error != 0)
1219 goto fail;
1220
1221 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
1222 if (error)
1223 goto fail;
1224 /* applying MAC address again. */
1225 macaddr = vap ? vap->iv_myaddr : ic->ic_macaddr;
1226 urtw_set_macaddr(sc, macaddr);
1227 if (error)
1228 goto fail;
1229
1230 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
1231 if (error)
1232 goto fail;
1233
1234 error = urtw_update_msr(sc);
1235 if (error)
1236 goto fail;
1237
1238 urtw_write32_m(sc, URTW_INT_TIMEOUT, 0);
1239 urtw_write8_m(sc, URTW_WPA_CONFIG, 0);
1240 urtw_write8_m(sc, URTW_RATE_FALLBACK, URTW_RATE_FALLBACK_ENABLE | 0x1);
1241 error = urtw_set_rate(sc);
1242 if (error != 0)
1243 goto fail;
1244
1245 error = sc->sc_rf_init(sc);
1246 if (error != 0)
1247 goto fail;
1248 if (sc->sc_rf_set_sens != NULL)
1249 sc->sc_rf_set_sens(sc, sc->sc_sens);
1250
1251 /* XXX correct? to call write16 */
1252 urtw_write16_m(sc, URTW_PSR, 1);
1253 urtw_write16_m(sc, URTW_ADDR_MAGIC2, 0x10);
1254 urtw_write8_m(sc, URTW_TALLY_SEL, 0x80);
1255 urtw_write8_m(sc, URTW_ADDR_MAGIC3, 0x60);
1256 /* XXX correct? to call write16 */
1257 urtw_write16_m(sc, URTW_PSR, 0);
1258 urtw_write8_m(sc, URTW_ADDR_MAGIC1, 4);
1259
1260 error = urtw_intr_enable(sc);
1261 if (error != 0)
1262 goto fail;
1263
1264 fail:
1265 return (error);
1266 }
1267
1268 static usb_error_t
urtw_set_mode(struct urtw_softc * sc,uint32_t mode)1269 urtw_set_mode(struct urtw_softc *sc, uint32_t mode)
1270 {
1271 uint8_t data;
1272 usb_error_t error;
1273
1274 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
1275 data = (data & ~URTW_EPROM_CMD_MASK) | (mode << URTW_EPROM_CMD_SHIFT);
1276 data = data & ~(URTW_EPROM_CS | URTW_EPROM_CK);
1277 urtw_write8_m(sc, URTW_EPROM_CMD, data);
1278 fail:
1279 return (error);
1280 }
1281
1282 static void
urtw_pause_ms(struct urtw_softc * sc,int delay)1283 urtw_pause_ms(struct urtw_softc *sc, int delay)
1284 {
1285 usb_pause_mtx(&sc->sc_mtx, USB_MS_TO_TICKS(delay));
1286 }
1287
1288 static usb_error_t
urtw_8187b_cmd_reset(struct urtw_softc * sc)1289 urtw_8187b_cmd_reset(struct urtw_softc *sc)
1290 {
1291 int i;
1292 uint8_t data8;
1293 usb_error_t error;
1294
1295 /* XXX the code can be duplicate with urtw_reset(). */
1296 urtw_read8_m(sc, URTW_CMD, &data8);
1297 data8 = (data8 & 0x2) | URTW_CMD_RST;
1298 urtw_write8_m(sc, URTW_CMD, data8);
1299
1300 for (i = 0; i < 20; i++) {
1301 urtw_pause_ms(sc, 2);
1302 urtw_read8_m(sc, URTW_CMD, &data8);
1303 if (!(data8 & URTW_CMD_RST))
1304 break;
1305 }
1306 if (i >= 20) {
1307 device_printf(sc->sc_dev, "reset timeout\n");
1308 goto fail;
1309 }
1310 fail:
1311 return (error);
1312 }
1313
1314 static usb_error_t
urtw_do_request(struct urtw_softc * sc,struct usb_device_request * req,void * data)1315 urtw_do_request(struct urtw_softc *sc,
1316 struct usb_device_request *req, void *data)
1317 {
1318 usb_error_t err;
1319 int ntries = 10;
1320
1321 URTW_ASSERT_LOCKED(sc);
1322
1323 while (ntries--) {
1324 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx,
1325 req, data, 0, NULL, 250 /* ms */);
1326 if (err == 0)
1327 break;
1328
1329 DPRINTF(sc, URTW_DEBUG_INIT,
1330 "Control request failed, %s (retrying)\n",
1331 usbd_errstr(err));
1332 urtw_pause_ms(sc, 10);
1333 }
1334 return (err);
1335 }
1336
1337 static void
urtw_stop(struct urtw_softc * sc)1338 urtw_stop(struct urtw_softc *sc)
1339 {
1340 uint8_t data8;
1341 usb_error_t error;
1342
1343 URTW_ASSERT_LOCKED(sc);
1344
1345 sc->sc_flags &= ~URTW_RUNNING;
1346
1347 error = urtw_intr_disable(sc);
1348 if (error)
1349 goto fail;
1350 urtw_read8_m(sc, URTW_CMD, &data8);
1351 data8 &= ~(URTW_CMD_RX_ENABLE | URTW_CMD_TX_ENABLE);
1352 urtw_write8_m(sc, URTW_CMD, data8);
1353
1354 error = sc->sc_rf_stop(sc);
1355 if (error != 0)
1356 goto fail;
1357
1358 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
1359 if (error)
1360 goto fail;
1361 urtw_read8_m(sc, URTW_CONFIG4, &data8);
1362 urtw_write8_m(sc, URTW_CONFIG4, data8 | URTW_CONFIG4_VCOOFF);
1363 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
1364 if (error)
1365 goto fail;
1366 fail:
1367 if (error)
1368 device_printf(sc->sc_dev, "failed to stop (%s)\n",
1369 usbd_errstr(error));
1370
1371 usb_callout_stop(&sc->sc_led_ch);
1372 callout_stop(&sc->sc_watchdog_ch);
1373
1374 urtw_abort_xfers(sc);
1375 }
1376
1377 static void
urtw_abort_xfers(struct urtw_softc * sc)1378 urtw_abort_xfers(struct urtw_softc *sc)
1379 {
1380 int i, max;
1381
1382 URTW_ASSERT_LOCKED(sc);
1383
1384 max = (sc->sc_flags & URTW_RTL8187B) ? URTW_8187B_N_XFERS :
1385 URTW_8187L_N_XFERS;
1386
1387 /* abort any pending transfers */
1388 for (i = 0; i < max; i++)
1389 usbd_transfer_stop(sc->sc_xfer[i]);
1390 }
1391
1392 static void
urtw_parent(struct ieee80211com * ic)1393 urtw_parent(struct ieee80211com *ic)
1394 {
1395 struct urtw_softc *sc = ic->ic_softc;
1396 int startall = 0;
1397
1398 URTW_LOCK(sc);
1399 if (sc->sc_flags & URTW_DETACHED) {
1400 URTW_UNLOCK(sc);
1401 return;
1402 }
1403
1404 if (ic->ic_nrunning > 0) {
1405 if (sc->sc_flags & URTW_RUNNING) {
1406 if (ic->ic_promisc > 0 || ic->ic_allmulti > 0)
1407 urtw_set_multi(sc);
1408 } else {
1409 urtw_init(sc);
1410 startall = 1;
1411 }
1412 } else if (sc->sc_flags & URTW_RUNNING)
1413 urtw_stop(sc);
1414 URTW_UNLOCK(sc);
1415 if (startall)
1416 ieee80211_start_all(ic);
1417 }
1418
1419 static int
urtw_transmit(struct ieee80211com * ic,struct mbuf * m)1420 urtw_transmit(struct ieee80211com *ic, struct mbuf *m)
1421 {
1422 struct urtw_softc *sc = ic->ic_softc;
1423 int error;
1424
1425 URTW_LOCK(sc);
1426 if ((sc->sc_flags & URTW_RUNNING) == 0) {
1427 URTW_UNLOCK(sc);
1428 return (ENXIO);
1429 }
1430 error = mbufq_enqueue(&sc->sc_snd, m);
1431 if (error) {
1432 URTW_UNLOCK(sc);
1433 return (error);
1434 }
1435 urtw_start(sc);
1436 URTW_UNLOCK(sc);
1437
1438 return (0);
1439 }
1440
1441 static void
urtw_start(struct urtw_softc * sc)1442 urtw_start(struct urtw_softc *sc)
1443 {
1444 struct urtw_data *bf;
1445 struct ieee80211_node *ni;
1446 struct mbuf *m;
1447
1448 URTW_ASSERT_LOCKED(sc);
1449
1450 if ((sc->sc_flags & URTW_RUNNING) == 0)
1451 return;
1452
1453 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) {
1454 bf = urtw_getbuf(sc);
1455 if (bf == NULL) {
1456 mbufq_prepend(&sc->sc_snd, m);
1457 break;
1458 }
1459
1460 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif;
1461 m->m_pkthdr.rcvif = NULL;
1462
1463 if (urtw_tx_start(sc, ni, m, bf, URTW_PRIORITY_NORMAL) != 0) {
1464 if_inc_counter(ni->ni_vap->iv_ifp,
1465 IFCOUNTER_OERRORS, 1);
1466 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next);
1467 ieee80211_free_node(ni);
1468 break;
1469 }
1470
1471 sc->sc_txtimer = 5;
1472 callout_reset(&sc->sc_watchdog_ch, hz, urtw_watchdog, sc);
1473 }
1474 }
1475
1476 static int
urtw_alloc_data_list(struct urtw_softc * sc,struct urtw_data data[],int ndata,int maxsz,void * dma_buf)1477 urtw_alloc_data_list(struct urtw_softc *sc, struct urtw_data data[],
1478 int ndata, int maxsz, void *dma_buf)
1479 {
1480 int i, error;
1481
1482 for (i = 0; i < ndata; i++) {
1483 struct urtw_data *dp = &data[i];
1484
1485 dp->sc = sc;
1486 if (dma_buf == NULL) {
1487 dp->m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1488 if (dp->m == NULL) {
1489 device_printf(sc->sc_dev,
1490 "could not allocate rx mbuf\n");
1491 error = ENOMEM;
1492 goto fail;
1493 }
1494 dp->buf = mtod(dp->m, uint8_t *);
1495 } else {
1496 dp->m = NULL;
1497 dp->buf = ((uint8_t *)dma_buf) +
1498 (i * maxsz);
1499 }
1500 dp->ni = NULL;
1501 }
1502 return (0);
1503
1504 fail: urtw_free_data_list(sc, data, ndata, 1);
1505 return (error);
1506 }
1507
1508 static int
urtw_alloc_rx_data_list(struct urtw_softc * sc)1509 urtw_alloc_rx_data_list(struct urtw_softc *sc)
1510 {
1511 int error, i;
1512
1513 error = urtw_alloc_data_list(sc,
1514 sc->sc_rx, URTW_RX_DATA_LIST_COUNT,
1515 MCLBYTES, NULL /* mbufs */);
1516 if (error != 0)
1517 return (error);
1518
1519 STAILQ_INIT(&sc->sc_rx_active);
1520 STAILQ_INIT(&sc->sc_rx_inactive);
1521
1522 for (i = 0; i < URTW_RX_DATA_LIST_COUNT; i++)
1523 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next);
1524
1525 return (0);
1526 }
1527
1528 static int
urtw_alloc_tx_data_list(struct urtw_softc * sc)1529 urtw_alloc_tx_data_list(struct urtw_softc *sc)
1530 {
1531 int error, i;
1532
1533 error = urtw_alloc_data_list(sc,
1534 sc->sc_tx, URTW_TX_DATA_LIST_COUNT, URTW_TX_MAXSIZE,
1535 sc->sc_tx_dma_buf /* no mbufs */);
1536 if (error != 0)
1537 return (error);
1538
1539 STAILQ_INIT(&sc->sc_tx_active);
1540 STAILQ_INIT(&sc->sc_tx_inactive);
1541 STAILQ_INIT(&sc->sc_tx_pending);
1542
1543 for (i = 0; i < URTW_TX_DATA_LIST_COUNT; i++)
1544 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i],
1545 next);
1546
1547 return (0);
1548 }
1549
1550 static int
urtw_raw_xmit(struct ieee80211_node * ni,struct mbuf * m,const struct ieee80211_bpf_params * params)1551 urtw_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
1552 const struct ieee80211_bpf_params *params)
1553 {
1554 struct ieee80211com *ic = ni->ni_ic;
1555 struct urtw_softc *sc = ic->ic_softc;
1556 struct urtw_data *bf;
1557
1558 /* prevent management frames from being sent if we're not ready */
1559 if (!(sc->sc_flags & URTW_RUNNING)) {
1560 m_freem(m);
1561 return ENETDOWN;
1562 }
1563 URTW_LOCK(sc);
1564 bf = urtw_getbuf(sc);
1565 if (bf == NULL) {
1566 m_freem(m);
1567 URTW_UNLOCK(sc);
1568 return (ENOBUFS); /* XXX */
1569 }
1570
1571 if (urtw_tx_start(sc, ni, m, bf, URTW_PRIORITY_LOW) != 0) {
1572 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next);
1573 URTW_UNLOCK(sc);
1574 return (EIO);
1575 }
1576 URTW_UNLOCK(sc);
1577
1578 sc->sc_txtimer = 5;
1579 return (0);
1580 }
1581
1582 static void
urtw_scan_start(struct ieee80211com * ic)1583 urtw_scan_start(struct ieee80211com *ic)
1584 {
1585
1586 /* XXX do nothing? */
1587 }
1588
1589 static void
urtw_scan_end(struct ieee80211com * ic)1590 urtw_scan_end(struct ieee80211com *ic)
1591 {
1592
1593 /* XXX do nothing? */
1594 }
1595
1596 static void
urtw_getradiocaps(struct ieee80211com * ic,int maxchans,int * nchans,struct ieee80211_channel chans[])1597 urtw_getradiocaps(struct ieee80211com *ic,
1598 int maxchans, int *nchans, struct ieee80211_channel chans[])
1599 {
1600 uint8_t bands[IEEE80211_MODE_BYTES];
1601
1602 memset(bands, 0, sizeof(bands));
1603 setbit(bands, IEEE80211_MODE_11B);
1604 setbit(bands, IEEE80211_MODE_11G);
1605 ieee80211_add_channels_default_2ghz(chans, maxchans, nchans, bands, 0);
1606 }
1607
1608 static void
urtw_set_channel(struct ieee80211com * ic)1609 urtw_set_channel(struct ieee80211com *ic)
1610 {
1611 struct urtw_softc *sc = ic->ic_softc;
1612 uint32_t data, orig;
1613 usb_error_t error;
1614
1615 /*
1616 * if the user set a channel explicitly using ifconfig(8) this function
1617 * can be called earlier than we're expected that in some cases the
1618 * initialization would be failed if setting a channel is called before
1619 * the init have done.
1620 */
1621 if (!(sc->sc_flags & URTW_RUNNING))
1622 return;
1623
1624 if (sc->sc_curchan != NULL && sc->sc_curchan == ic->ic_curchan)
1625 return;
1626
1627 URTW_LOCK(sc);
1628
1629 /*
1630 * during changing th channel we need to temporarily be disable
1631 * TX.
1632 */
1633 urtw_read32_m(sc, URTW_TX_CONF, &orig);
1634 data = orig & ~URTW_TX_LOOPBACK_MASK;
1635 urtw_write32_m(sc, URTW_TX_CONF, data | URTW_TX_LOOPBACK_MAC);
1636
1637 error = sc->sc_rf_set_chan(sc, ieee80211_chan2ieee(ic, ic->ic_curchan));
1638 if (error != 0)
1639 goto fail;
1640 urtw_pause_ms(sc, 10);
1641 urtw_write32_m(sc, URTW_TX_CONF, orig);
1642
1643 urtw_write16_m(sc, URTW_ATIM_WND, 2);
1644 urtw_write16_m(sc, URTW_ATIM_TR_ITV, 100);
1645 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 100);
1646 urtw_write16_m(sc, URTW_BEACON_INTERVAL_TIME, 100);
1647
1648 fail:
1649 URTW_UNLOCK(sc);
1650
1651 sc->sc_curchan = ic->ic_curchan;
1652
1653 if (error != 0)
1654 device_printf(sc->sc_dev, "could not change the channel\n");
1655 }
1656
1657 static void
urtw_update_promisc(struct ieee80211com * ic)1658 urtw_update_promisc(struct ieee80211com *ic)
1659 {
1660 struct urtw_softc *sc = ic->ic_softc;
1661
1662 URTW_LOCK(sc);
1663 if (sc->sc_flags & URTW_RUNNING)
1664 urtw_rx_setconf(sc);
1665 URTW_UNLOCK(sc);
1666 }
1667
1668 static void
urtw_update_mcast(struct ieee80211com * ic)1669 urtw_update_mcast(struct ieee80211com *ic)
1670 {
1671
1672 /* XXX do nothing? */
1673 }
1674
1675 static int
urtw_tx_start(struct urtw_softc * sc,struct ieee80211_node * ni,struct mbuf * m0,struct urtw_data * data,int prior)1676 urtw_tx_start(struct urtw_softc *sc, struct ieee80211_node *ni, struct mbuf *m0,
1677 struct urtw_data *data, int prior)
1678 {
1679 struct ieee80211_frame *wh = mtod(m0, struct ieee80211_frame *);
1680 struct ieee80211_key *k;
1681 const struct ieee80211_txparam *tp = ni->ni_txparms;
1682 struct ieee80211com *ic = &sc->sc_ic;
1683 struct ieee80211vap *vap = ni->ni_vap;
1684 struct usb_xfer *rtl8187b_pipes[URTW_8187B_TXPIPE_MAX] = {
1685 sc->sc_xfer[URTW_8187B_BULK_TX_BE],
1686 sc->sc_xfer[URTW_8187B_BULK_TX_BK],
1687 sc->sc_xfer[URTW_8187B_BULK_TX_VI],
1688 sc->sc_xfer[URTW_8187B_BULK_TX_VO]
1689 };
1690 struct usb_xfer *xfer;
1691 int dur = 0, rtsdur = 0, rtsenable = 0, ctsenable = 0, rate, type,
1692 pkttime = 0, txdur = 0, isshort = 0, xferlen, ismcast;
1693 uint16_t acktime, rtstime, ctstime;
1694 uint32_t flags;
1695 usb_error_t error;
1696
1697 URTW_ASSERT_LOCKED(sc);
1698
1699 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
1700 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
1701
1702 /*
1703 * Software crypto.
1704 */
1705 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) {
1706 k = ieee80211_crypto_encap(ni, m0);
1707 if (k == NULL) {
1708 device_printf(sc->sc_dev,
1709 "ieee80211_crypto_encap returns NULL.\n");
1710 /* XXX we don't expect the fragmented frames */
1711 m_freem(m0);
1712 return (ENOBUFS);
1713 }
1714
1715 /* in case packet header moved, reset pointer */
1716 wh = mtod(m0, struct ieee80211_frame *);
1717 }
1718
1719 if (ieee80211_radiotap_active_vap(vap)) {
1720 struct urtw_tx_radiotap_header *tap = &sc->sc_txtap;
1721
1722 tap->wt_flags = 0;
1723 ieee80211_radiotap_tx(vap, m0);
1724 }
1725
1726 if (type == IEEE80211_FC0_TYPE_MGT ||
1727 type == IEEE80211_FC0_TYPE_CTL ||
1728 (m0->m_flags & M_EAPOL) != 0) {
1729 rate = tp->mgmtrate;
1730 } else {
1731 /* for data frames */
1732 if (ismcast)
1733 rate = tp->mcastrate;
1734 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE)
1735 rate = tp->ucastrate;
1736 else
1737 rate = urtw_rtl2rate(sc->sc_currate);
1738 }
1739
1740 sc->sc_stats.txrates[sc->sc_currate]++;
1741
1742 if (ismcast)
1743 txdur = pkttime = urtw_compute_txtime(m0->m_pkthdr.len +
1744 IEEE80211_CRC_LEN, rate, 0, 0);
1745 else {
1746 acktime = urtw_compute_txtime(14, 2,0, 0);
1747 if ((m0->m_pkthdr.len + 4) > vap->iv_rtsthreshold) {
1748 rtsenable = 1;
1749 ctsenable = 0;
1750 rtstime = urtw_compute_txtime(URTW_ACKCTS_LEN, 2, 0, 0);
1751 ctstime = urtw_compute_txtime(14, 2, 0, 0);
1752 pkttime = urtw_compute_txtime(m0->m_pkthdr.len +
1753 IEEE80211_CRC_LEN, rate, 0, isshort);
1754 rtsdur = ctstime + pkttime + acktime +
1755 3 * URTW_ASIFS_TIME;
1756 txdur = rtstime + rtsdur;
1757 } else {
1758 rtsenable = ctsenable = rtsdur = 0;
1759 pkttime = urtw_compute_txtime(m0->m_pkthdr.len +
1760 IEEE80211_CRC_LEN, rate, 0, isshort);
1761 txdur = pkttime + URTW_ASIFS_TIME + acktime;
1762 }
1763
1764 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG)
1765 dur = urtw_compute_txtime(m0->m_pkthdr.len +
1766 IEEE80211_CRC_LEN, rate, 0, isshort) +
1767 3 * URTW_ASIFS_TIME +
1768 2 * acktime;
1769 else
1770 dur = URTW_ASIFS_TIME + acktime;
1771 }
1772 USETW(wh->i_dur, dur);
1773
1774 xferlen = m0->m_pkthdr.len;
1775 xferlen += (sc->sc_flags & URTW_RTL8187B) ? (4 * 8) : (4 * 3);
1776 if ((0 == xferlen % 64) || (0 == xferlen % 512))
1777 xferlen += 1;
1778
1779 memset(data->buf, 0, URTW_TX_MAXSIZE);
1780 flags = m0->m_pkthdr.len & 0xfff;
1781 flags |= URTW_TX_FLAG_NO_ENC;
1782 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) &&
1783 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) &&
1784 (sc->sc_preamble_mode == URTW_PREAMBLE_MODE_SHORT) &&
1785 (sc->sc_currate != 0))
1786 flags |= URTW_TX_FLAG_SPLCP;
1787 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG)
1788 flags |= URTW_TX_FLAG_MOREFRAG;
1789
1790 flags |= (sc->sc_currate & 0xf) << URTW_TX_FLAG_TXRATE_SHIFT;
1791
1792 if (sc->sc_flags & URTW_RTL8187B) {
1793 struct urtw_8187b_txhdr *tx;
1794
1795 tx = (struct urtw_8187b_txhdr *)data->buf;
1796 if (ctsenable)
1797 flags |= URTW_TX_FLAG_CTS;
1798 if (rtsenable) {
1799 flags |= URTW_TX_FLAG_RTS;
1800 flags |= URTW_RIDX_CCK5 << URTW_TX_FLAG_RTSRATE_SHIFT;
1801 tx->rtsdur = rtsdur;
1802 }
1803 tx->flag = htole32(flags);
1804 tx->txdur = txdur;
1805 if (type == IEEE80211_FC0_TYPE_MGT &&
1806 (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) ==
1807 IEEE80211_FC0_SUBTYPE_PROBE_RESP)
1808 tx->retry = 1;
1809 else
1810 tx->retry = URTW_TX_MAXRETRY;
1811 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)(tx + 1));
1812 } else {
1813 struct urtw_8187l_txhdr *tx;
1814
1815 tx = (struct urtw_8187l_txhdr *)data->buf;
1816 if (rtsenable) {
1817 flags |= URTW_TX_FLAG_RTS;
1818 tx->rtsdur = rtsdur;
1819 }
1820 flags |= URTW_RIDX_CCK5 << URTW_TX_FLAG_RTSRATE_SHIFT;
1821 tx->flag = htole32(flags);
1822 tx->retry = 3; /* CW minimum */
1823 tx->retry |= 7 << 4; /* CW maximum */
1824 tx->retry |= URTW_TX_MAXRETRY << 8; /* retry limitation */
1825 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)(tx + 1));
1826 }
1827
1828 data->buflen = xferlen;
1829 data->ni = ni;
1830 data->m = m0;
1831
1832 if (sc->sc_flags & URTW_RTL8187B) {
1833 switch (type) {
1834 case IEEE80211_FC0_TYPE_CTL:
1835 case IEEE80211_FC0_TYPE_MGT:
1836 xfer = sc->sc_xfer[URTW_8187B_BULK_TX_EP12];
1837 break;
1838 default:
1839 KASSERT(M_WME_GETAC(m0) < URTW_8187B_TXPIPE_MAX,
1840 ("unsupported WME pipe %d", M_WME_GETAC(m0)));
1841 xfer = rtl8187b_pipes[M_WME_GETAC(m0)];
1842 break;
1843 }
1844 } else
1845 xfer = (prior == URTW_PRIORITY_LOW) ?
1846 sc->sc_xfer[URTW_8187L_BULK_TX_LOW] :
1847 sc->sc_xfer[URTW_8187L_BULK_TX_NORMAL];
1848
1849 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next);
1850 usbd_transfer_start(xfer);
1851
1852 error = urtw_led_ctl(sc, URTW_LED_CTL_TX);
1853 if (error != 0)
1854 device_printf(sc->sc_dev, "could not control LED (%d)\n",
1855 error);
1856 return (0);
1857 }
1858
1859 static int
urtw_newstate(struct ieee80211vap * vap,enum ieee80211_state nstate,int arg)1860 urtw_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
1861 {
1862 struct ieee80211com *ic = vap->iv_ic;
1863 struct urtw_softc *sc = ic->ic_softc;
1864 struct urtw_vap *uvp = URTW_VAP(vap);
1865 struct ieee80211_node *ni;
1866 usb_error_t error = 0;
1867
1868 DPRINTF(sc, URTW_DEBUG_STATE, "%s: %s -> %s\n", __func__,
1869 ieee80211_state_name[vap->iv_state],
1870 ieee80211_state_name[nstate]);
1871
1872 sc->sc_state = nstate;
1873
1874 IEEE80211_UNLOCK(ic);
1875 URTW_LOCK(sc);
1876 usb_callout_stop(&sc->sc_led_ch);
1877 callout_stop(&sc->sc_watchdog_ch);
1878
1879 switch (nstate) {
1880 case IEEE80211_S_INIT:
1881 case IEEE80211_S_SCAN:
1882 case IEEE80211_S_AUTH:
1883 case IEEE80211_S_ASSOC:
1884 break;
1885 case IEEE80211_S_RUN:
1886 ni = ieee80211_ref_node(vap->iv_bss);
1887 /* setting bssid. */
1888 urtw_write32_m(sc, URTW_BSSID, ((uint32_t *)ni->ni_bssid)[0]);
1889 urtw_write16_m(sc, URTW_BSSID + 4,
1890 ((uint16_t *)ni->ni_bssid)[2]);
1891 urtw_update_msr(sc);
1892 /* XXX maybe the below would be incorrect. */
1893 urtw_write16_m(sc, URTW_ATIM_WND, 2);
1894 urtw_write16_m(sc, URTW_ATIM_TR_ITV, 100);
1895 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 0x64);
1896 urtw_write16_m(sc, URTW_BEACON_INTERVAL_TIME, 100);
1897 error = urtw_led_ctl(sc, URTW_LED_CTL_LINK);
1898 if (error != 0)
1899 device_printf(sc->sc_dev,
1900 "could not control LED (%d)\n", error);
1901 ieee80211_free_node(ni);
1902 break;
1903 default:
1904 break;
1905 }
1906 fail:
1907 URTW_UNLOCK(sc);
1908 IEEE80211_LOCK(ic);
1909 return (uvp->newstate(vap, nstate, arg));
1910 }
1911
1912 static void
urtw_watchdog(void * arg)1913 urtw_watchdog(void *arg)
1914 {
1915 struct urtw_softc *sc = arg;
1916 struct ieee80211com *ic = &sc->sc_ic;
1917
1918 if (sc->sc_txtimer > 0) {
1919 if (--sc->sc_txtimer == 0) {
1920 device_printf(sc->sc_dev, "device timeout\n");
1921 counter_u64_add(ic->ic_oerrors, 1);
1922 ieee80211_restart_all(ic);
1923 return;
1924 }
1925 callout_reset(&sc->sc_watchdog_ch, hz, urtw_watchdog, sc);
1926 }
1927 }
1928
1929 static void
urtw_set_multi(void * arg)1930 urtw_set_multi(void *arg)
1931 {
1932 /* XXX don't know how to set a device. Lack of docs. */
1933 }
1934
1935 static usb_error_t
urtw_set_rate(struct urtw_softc * sc)1936 urtw_set_rate(struct urtw_softc *sc)
1937 {
1938 int i, basic_rate, min_rr_rate, max_rr_rate;
1939 uint16_t data;
1940 usb_error_t error;
1941
1942 basic_rate = URTW_RIDX_OFDM24;
1943 min_rr_rate = URTW_RIDX_OFDM6;
1944 max_rr_rate = URTW_RIDX_OFDM24;
1945
1946 urtw_write8_m(sc, URTW_RESP_RATE,
1947 max_rr_rate << URTW_RESP_MAX_RATE_SHIFT |
1948 min_rr_rate << URTW_RESP_MIN_RATE_SHIFT);
1949
1950 urtw_read16_m(sc, URTW_BRSR, &data);
1951 data &= ~URTW_BRSR_MBR_8185;
1952
1953 for (i = 0; i <= basic_rate; i++)
1954 data |= (1 << i);
1955
1956 urtw_write16_m(sc, URTW_BRSR, data);
1957 fail:
1958 return (error);
1959 }
1960
1961 static uint16_t
urtw_rtl2rate(uint32_t rate)1962 urtw_rtl2rate(uint32_t rate)
1963 {
1964 unsigned i;
1965
1966 for (i = 0; i < nitems(urtw_ratetable); i++) {
1967 if (rate == urtw_ratetable[i].val)
1968 return urtw_ratetable[i].reg;
1969 }
1970
1971 return (0);
1972 }
1973
1974 static usb_error_t
urtw_update_msr(struct urtw_softc * sc)1975 urtw_update_msr(struct urtw_softc *sc)
1976 {
1977 struct ieee80211com *ic = &sc->sc_ic;
1978 uint8_t data;
1979 usb_error_t error;
1980
1981 urtw_read8_m(sc, URTW_MSR, &data);
1982 data &= ~URTW_MSR_LINK_MASK;
1983
1984 if (sc->sc_state == IEEE80211_S_RUN) {
1985 switch (ic->ic_opmode) {
1986 case IEEE80211_M_STA:
1987 case IEEE80211_M_MONITOR:
1988 data |= URTW_MSR_LINK_STA;
1989 if (sc->sc_flags & URTW_RTL8187B)
1990 data |= URTW_MSR_LINK_ENEDCA;
1991 break;
1992 case IEEE80211_M_IBSS:
1993 data |= URTW_MSR_LINK_ADHOC;
1994 break;
1995 case IEEE80211_M_HOSTAP:
1996 data |= URTW_MSR_LINK_HOSTAP;
1997 break;
1998 default:
1999 DPRINTF(sc, URTW_DEBUG_STATE,
2000 "unsupported operation mode 0x%x\n",
2001 ic->ic_opmode);
2002 error = USB_ERR_INVAL;
2003 goto fail;
2004 }
2005 } else
2006 data |= URTW_MSR_LINK_NONE;
2007
2008 urtw_write8_m(sc, URTW_MSR, data);
2009 fail:
2010 return (error);
2011 }
2012
2013 static usb_error_t
urtw_read8_c(struct urtw_softc * sc,int val,uint8_t * data)2014 urtw_read8_c(struct urtw_softc *sc, int val, uint8_t *data)
2015 {
2016 struct usb_device_request req;
2017 usb_error_t error;
2018
2019 URTW_ASSERT_LOCKED(sc);
2020
2021 req.bmRequestType = UT_READ_VENDOR_DEVICE;
2022 req.bRequest = URTW_8187_GETREGS_REQ;
2023 USETW(req.wValue, (val & 0xff) | 0xff00);
2024 USETW(req.wIndex, (val >> 8) & 0x3);
2025 USETW(req.wLength, sizeof(uint8_t));
2026
2027 error = urtw_do_request(sc, &req, data);
2028 return (error);
2029 }
2030
2031 static usb_error_t
urtw_read16_c(struct urtw_softc * sc,int val,uint16_t * data)2032 urtw_read16_c(struct urtw_softc *sc, int val, uint16_t *data)
2033 {
2034 struct usb_device_request req;
2035 usb_error_t error;
2036
2037 URTW_ASSERT_LOCKED(sc);
2038
2039 req.bmRequestType = UT_READ_VENDOR_DEVICE;
2040 req.bRequest = URTW_8187_GETREGS_REQ;
2041 USETW(req.wValue, (val & 0xff) | 0xff00);
2042 USETW(req.wIndex, (val >> 8) & 0x3);
2043 USETW(req.wLength, sizeof(uint16_t));
2044
2045 error = urtw_do_request(sc, &req, data);
2046 return (error);
2047 }
2048
2049 static usb_error_t
urtw_read32_c(struct urtw_softc * sc,int val,uint32_t * data)2050 urtw_read32_c(struct urtw_softc *sc, int val, uint32_t *data)
2051 {
2052 struct usb_device_request req;
2053 usb_error_t error;
2054
2055 URTW_ASSERT_LOCKED(sc);
2056
2057 req.bmRequestType = UT_READ_VENDOR_DEVICE;
2058 req.bRequest = URTW_8187_GETREGS_REQ;
2059 USETW(req.wValue, (val & 0xff) | 0xff00);
2060 USETW(req.wIndex, (val >> 8) & 0x3);
2061 USETW(req.wLength, sizeof(uint32_t));
2062
2063 error = urtw_do_request(sc, &req, data);
2064 return (error);
2065 }
2066
2067 static usb_error_t
urtw_write8_c(struct urtw_softc * sc,int val,uint8_t data)2068 urtw_write8_c(struct urtw_softc *sc, int val, uint8_t data)
2069 {
2070 struct usb_device_request req;
2071
2072 URTW_ASSERT_LOCKED(sc);
2073
2074 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
2075 req.bRequest = URTW_8187_SETREGS_REQ;
2076 USETW(req.wValue, (val & 0xff) | 0xff00);
2077 USETW(req.wIndex, (val >> 8) & 0x3);
2078 USETW(req.wLength, sizeof(uint8_t));
2079
2080 return (urtw_do_request(sc, &req, &data));
2081 }
2082
2083 static usb_error_t
urtw_write16_c(struct urtw_softc * sc,int val,uint16_t data)2084 urtw_write16_c(struct urtw_softc *sc, int val, uint16_t data)
2085 {
2086 struct usb_device_request req;
2087
2088 URTW_ASSERT_LOCKED(sc);
2089
2090 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
2091 req.bRequest = URTW_8187_SETREGS_REQ;
2092 USETW(req.wValue, (val & 0xff) | 0xff00);
2093 USETW(req.wIndex, (val >> 8) & 0x3);
2094 USETW(req.wLength, sizeof(uint16_t));
2095
2096 return (urtw_do_request(sc, &req, &data));
2097 }
2098
2099 static usb_error_t
urtw_write32_c(struct urtw_softc * sc,int val,uint32_t data)2100 urtw_write32_c(struct urtw_softc *sc, int val, uint32_t data)
2101 {
2102 struct usb_device_request req;
2103
2104 URTW_ASSERT_LOCKED(sc);
2105
2106 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
2107 req.bRequest = URTW_8187_SETREGS_REQ;
2108 USETW(req.wValue, (val & 0xff) | 0xff00);
2109 USETW(req.wIndex, (val >> 8) & 0x3);
2110 USETW(req.wLength, sizeof(uint32_t));
2111
2112 return (urtw_do_request(sc, &req, &data));
2113 }
2114
2115 static usb_error_t
urtw_get_macaddr(struct urtw_softc * sc)2116 urtw_get_macaddr(struct urtw_softc *sc)
2117 {
2118 struct ieee80211com *ic = &sc->sc_ic;
2119 uint32_t data;
2120 usb_error_t error;
2121
2122 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR, &data);
2123 if (error != 0)
2124 goto fail;
2125 ic->ic_macaddr[0] = data & 0xff;
2126 ic->ic_macaddr[1] = (data & 0xff00) >> 8;
2127 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 1, &data);
2128 if (error != 0)
2129 goto fail;
2130 ic->ic_macaddr[2] = data & 0xff;
2131 ic->ic_macaddr[3] = (data & 0xff00) >> 8;
2132 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 2, &data);
2133 if (error != 0)
2134 goto fail;
2135 ic->ic_macaddr[4] = data & 0xff;
2136 ic->ic_macaddr[5] = (data & 0xff00) >> 8;
2137 fail:
2138 return (error);
2139 }
2140
2141 static usb_error_t
urtw_eprom_read32(struct urtw_softc * sc,uint32_t addr,uint32_t * data)2142 urtw_eprom_read32(struct urtw_softc *sc, uint32_t addr, uint32_t *data)
2143 {
2144 #define URTW_READCMD_LEN 3
2145 int addrlen, i;
2146 int16_t addrstr[8], data16, readcmd[] = { 1, 1, 0 };
2147 usb_error_t error;
2148
2149 /* NB: make sure the buffer is initialized */
2150 *data = 0;
2151
2152 /* enable EPROM programming */
2153 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_PROGRAM_MODE);
2154 DELAY(URTW_EPROM_DELAY);
2155
2156 error = urtw_eprom_cs(sc, URTW_EPROM_ENABLE);
2157 if (error != 0)
2158 goto fail;
2159 error = urtw_eprom_ck(sc);
2160 if (error != 0)
2161 goto fail;
2162 error = urtw_eprom_sendbits(sc, readcmd, URTW_READCMD_LEN);
2163 if (error != 0)
2164 goto fail;
2165 if (sc->sc_epromtype == URTW_EEPROM_93C56) {
2166 addrlen = 8;
2167 addrstr[0] = addr & (1 << 7);
2168 addrstr[1] = addr & (1 << 6);
2169 addrstr[2] = addr & (1 << 5);
2170 addrstr[3] = addr & (1 << 4);
2171 addrstr[4] = addr & (1 << 3);
2172 addrstr[5] = addr & (1 << 2);
2173 addrstr[6] = addr & (1 << 1);
2174 addrstr[7] = addr & (1 << 0);
2175 } else {
2176 addrlen=6;
2177 addrstr[0] = addr & (1 << 5);
2178 addrstr[1] = addr & (1 << 4);
2179 addrstr[2] = addr & (1 << 3);
2180 addrstr[3] = addr & (1 << 2);
2181 addrstr[4] = addr & (1 << 1);
2182 addrstr[5] = addr & (1 << 0);
2183 }
2184 error = urtw_eprom_sendbits(sc, addrstr, addrlen);
2185 if (error != 0)
2186 goto fail;
2187
2188 error = urtw_eprom_writebit(sc, 0);
2189 if (error != 0)
2190 goto fail;
2191
2192 for (i = 0; i < 16; i++) {
2193 error = urtw_eprom_ck(sc);
2194 if (error != 0)
2195 goto fail;
2196 error = urtw_eprom_readbit(sc, &data16);
2197 if (error != 0)
2198 goto fail;
2199
2200 (*data) |= (data16 << (15 - i));
2201 }
2202
2203 error = urtw_eprom_cs(sc, URTW_EPROM_DISABLE);
2204 if (error != 0)
2205 goto fail;
2206 error = urtw_eprom_ck(sc);
2207 if (error != 0)
2208 goto fail;
2209
2210 /* now disable EPROM programming */
2211 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_NORMAL_MODE);
2212 fail:
2213 return (error);
2214 #undef URTW_READCMD_LEN
2215 }
2216
2217 static usb_error_t
urtw_eprom_cs(struct urtw_softc * sc,int able)2218 urtw_eprom_cs(struct urtw_softc *sc, int able)
2219 {
2220 uint8_t data;
2221 usb_error_t error;
2222
2223 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
2224 if (able == URTW_EPROM_ENABLE)
2225 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CS);
2226 else
2227 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CS);
2228 DELAY(URTW_EPROM_DELAY);
2229 fail:
2230 return (error);
2231 }
2232
2233 static usb_error_t
urtw_eprom_ck(struct urtw_softc * sc)2234 urtw_eprom_ck(struct urtw_softc *sc)
2235 {
2236 uint8_t data;
2237 usb_error_t error;
2238
2239 /* masking */
2240 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
2241 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CK);
2242 DELAY(URTW_EPROM_DELAY);
2243 /* unmasking */
2244 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
2245 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CK);
2246 DELAY(URTW_EPROM_DELAY);
2247 fail:
2248 return (error);
2249 }
2250
2251 static usb_error_t
urtw_eprom_readbit(struct urtw_softc * sc,int16_t * data)2252 urtw_eprom_readbit(struct urtw_softc *sc, int16_t *data)
2253 {
2254 uint8_t data8;
2255 usb_error_t error;
2256
2257 urtw_read8_m(sc, URTW_EPROM_CMD, &data8);
2258 *data = (data8 & URTW_EPROM_READBIT) ? 1 : 0;
2259 DELAY(URTW_EPROM_DELAY);
2260
2261 fail:
2262 return (error);
2263 }
2264
2265 static usb_error_t
urtw_eprom_writebit(struct urtw_softc * sc,int16_t bit)2266 urtw_eprom_writebit(struct urtw_softc *sc, int16_t bit)
2267 {
2268 uint8_t data;
2269 usb_error_t error;
2270
2271 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
2272 if (bit != 0)
2273 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_WRITEBIT);
2274 else
2275 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_WRITEBIT);
2276 DELAY(URTW_EPROM_DELAY);
2277 fail:
2278 return (error);
2279 }
2280
2281 static usb_error_t
urtw_eprom_sendbits(struct urtw_softc * sc,int16_t * buf,int buflen)2282 urtw_eprom_sendbits(struct urtw_softc *sc, int16_t *buf, int buflen)
2283 {
2284 int i = 0;
2285 usb_error_t error = 0;
2286
2287 for (i = 0; i < buflen; i++) {
2288 error = urtw_eprom_writebit(sc, buf[i]);
2289 if (error != 0)
2290 goto fail;
2291 error = urtw_eprom_ck(sc);
2292 if (error != 0)
2293 goto fail;
2294 }
2295 fail:
2296 return (error);
2297 }
2298
2299 static usb_error_t
urtw_get_txpwr(struct urtw_softc * sc)2300 urtw_get_txpwr(struct urtw_softc *sc)
2301 {
2302 int i, j;
2303 uint32_t data;
2304 usb_error_t error;
2305
2306 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW_BASE, &data);
2307 if (error != 0)
2308 goto fail;
2309 sc->sc_txpwr_cck_base = data & 0xf;
2310 sc->sc_txpwr_ofdm_base = (data >> 4) & 0xf;
2311
2312 for (i = 1, j = 0; i < 6; i += 2, j++) {
2313 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW0 + j, &data);
2314 if (error != 0)
2315 goto fail;
2316 sc->sc_txpwr_cck[i] = data & 0xf;
2317 sc->sc_txpwr_cck[i + 1] = (data & 0xf00) >> 8;
2318 sc->sc_txpwr_ofdm[i] = (data & 0xf0) >> 4;
2319 sc->sc_txpwr_ofdm[i + 1] = (data & 0xf000) >> 12;
2320 }
2321 for (i = 1, j = 0; i < 4; i += 2, j++) {
2322 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW1 + j, &data);
2323 if (error != 0)
2324 goto fail;
2325 sc->sc_txpwr_cck[i + 6] = data & 0xf;
2326 sc->sc_txpwr_cck[i + 6 + 1] = (data & 0xf00) >> 8;
2327 sc->sc_txpwr_ofdm[i + 6] = (data & 0xf0) >> 4;
2328 sc->sc_txpwr_ofdm[i + 6 + 1] = (data & 0xf000) >> 12;
2329 }
2330 if (sc->sc_flags & URTW_RTL8187B) {
2331 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW2, &data);
2332 if (error != 0)
2333 goto fail;
2334 sc->sc_txpwr_cck[1 + 6 + 4] = data & 0xf;
2335 sc->sc_txpwr_ofdm[1 + 6 + 4] = (data & 0xf0) >> 4;
2336 error = urtw_eprom_read32(sc, 0x0a, &data);
2337 if (error != 0)
2338 goto fail;
2339 sc->sc_txpwr_cck[2 + 6 + 4] = data & 0xf;
2340 sc->sc_txpwr_ofdm[2 + 6 + 4] = (data & 0xf0) >> 4;
2341 error = urtw_eprom_read32(sc, 0x1c, &data);
2342 if (error != 0)
2343 goto fail;
2344 sc->sc_txpwr_cck[3 + 6 + 4] = data & 0xf;
2345 sc->sc_txpwr_cck[3 + 6 + 4 + 1] = (data & 0xf00) >> 8;
2346 sc->sc_txpwr_ofdm[3 + 6 + 4] = (data & 0xf0) >> 4;
2347 sc->sc_txpwr_ofdm[3 + 6 + 4 + 1] = (data & 0xf000) >> 12;
2348 } else {
2349 for (i = 1, j = 0; i < 4; i += 2, j++) {
2350 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW2 + j,
2351 &data);
2352 if (error != 0)
2353 goto fail;
2354 sc->sc_txpwr_cck[i + 6 + 4] = data & 0xf;
2355 sc->sc_txpwr_cck[i + 6 + 4 + 1] = (data & 0xf00) >> 8;
2356 sc->sc_txpwr_ofdm[i + 6 + 4] = (data & 0xf0) >> 4;
2357 sc->sc_txpwr_ofdm[i + 6 + 4 + 1] = (data & 0xf000) >> 12;
2358 }
2359 }
2360 fail:
2361 return (error);
2362 }
2363
2364 static usb_error_t
urtw_get_rfchip(struct urtw_softc * sc)2365 urtw_get_rfchip(struct urtw_softc *sc)
2366 {
2367 int ret;
2368 uint8_t data8;
2369 uint32_t data;
2370 usb_error_t error;
2371
2372 if (sc->sc_flags & URTW_RTL8187B) {
2373 urtw_read8_m(sc, 0xe1, &data8);
2374 switch (data8) {
2375 case 0:
2376 sc->sc_flags |= URTW_RTL8187B_REV_B;
2377 break;
2378 case 1:
2379 sc->sc_flags |= URTW_RTL8187B_REV_D;
2380 break;
2381 case 2:
2382 sc->sc_flags |= URTW_RTL8187B_REV_E;
2383 break;
2384 default:
2385 device_printf(sc->sc_dev, "unknown type: %#x\n", data8);
2386 sc->sc_flags |= URTW_RTL8187B_REV_B;
2387 break;
2388 }
2389 } else {
2390 urtw_read32_m(sc, URTW_TX_CONF, &data);
2391 switch (data & URTW_TX_HWMASK) {
2392 case URTW_TX_R8187vD_B:
2393 sc->sc_flags |= URTW_RTL8187B;
2394 break;
2395 case URTW_TX_R8187vD:
2396 break;
2397 default:
2398 device_printf(sc->sc_dev, "unknown RTL8187L type: %#x\n",
2399 data & URTW_TX_HWMASK);
2400 break;
2401 }
2402 }
2403
2404 error = urtw_eprom_read32(sc, URTW_EPROM_RFCHIPID, &data);
2405 if (error != 0)
2406 goto fail;
2407 switch (data & 0xff) {
2408 case URTW_EPROM_RFCHIPID_RTL8225U:
2409 error = urtw_8225_isv2(sc, &ret);
2410 if (error != 0)
2411 goto fail;
2412 if (ret == 0) {
2413 sc->sc_rf_init = urtw_8225_rf_init;
2414 sc->sc_rf_set_sens = urtw_8225_rf_set_sens;
2415 sc->sc_rf_set_chan = urtw_8225_rf_set_chan;
2416 sc->sc_rf_stop = urtw_8225_rf_stop;
2417 } else {
2418 sc->sc_rf_init = urtw_8225v2_rf_init;
2419 sc->sc_rf_set_chan = urtw_8225v2_rf_set_chan;
2420 sc->sc_rf_stop = urtw_8225_rf_stop;
2421 }
2422 sc->sc_max_sens = URTW_8225_RF_MAX_SENS;
2423 sc->sc_sens = URTW_8225_RF_DEF_SENS;
2424 break;
2425 case URTW_EPROM_RFCHIPID_RTL8225Z2:
2426 sc->sc_rf_init = urtw_8225v2b_rf_init;
2427 sc->sc_rf_set_chan = urtw_8225v2b_rf_set_chan;
2428 sc->sc_max_sens = URTW_8225_RF_MAX_SENS;
2429 sc->sc_sens = URTW_8225_RF_DEF_SENS;
2430 sc->sc_rf_stop = urtw_8225_rf_stop;
2431 break;
2432 default:
2433 DPRINTF(sc, URTW_DEBUG_STATE,
2434 "unsupported RF chip %d\n", data & 0xff);
2435 error = USB_ERR_INVAL;
2436 goto fail;
2437 }
2438
2439 device_printf(sc->sc_dev, "%s rf %s hwrev %s\n",
2440 (sc->sc_flags & URTW_RTL8187B) ? "rtl8187b" : "rtl8187l",
2441 ((data & 0xff) == URTW_EPROM_RFCHIPID_RTL8225U) ? "rtl8225u" :
2442 "rtl8225z2",
2443 (sc->sc_flags & URTW_RTL8187B) ? ((data8 == 0) ? "b" :
2444 (data8 == 1) ? "d" : "e") : "none");
2445
2446 fail:
2447 return (error);
2448 }
2449
2450 static usb_error_t
urtw_led_init(struct urtw_softc * sc)2451 urtw_led_init(struct urtw_softc *sc)
2452 {
2453 uint32_t rev;
2454 usb_error_t error;
2455
2456 urtw_read8_m(sc, URTW_PSR, &sc->sc_psr);
2457 error = urtw_eprom_read32(sc, URTW_EPROM_SWREV, &rev);
2458 if (error != 0)
2459 goto fail;
2460
2461 switch (rev & URTW_EPROM_CID_MASK) {
2462 case URTW_EPROM_CID_ALPHA0:
2463 sc->sc_strategy = URTW_SW_LED_MODE1;
2464 break;
2465 case URTW_EPROM_CID_SERCOMM_PS:
2466 sc->sc_strategy = URTW_SW_LED_MODE3;
2467 break;
2468 case URTW_EPROM_CID_HW_LED:
2469 sc->sc_strategy = URTW_HW_LED;
2470 break;
2471 case URTW_EPROM_CID_RSVD0:
2472 case URTW_EPROM_CID_RSVD1:
2473 default:
2474 sc->sc_strategy = URTW_SW_LED_MODE0;
2475 break;
2476 }
2477
2478 sc->sc_gpio_ledpin = URTW_LED_PIN_GPIO0;
2479
2480 fail:
2481 return (error);
2482 }
2483
2484 static usb_error_t
urtw_8225_rf_init(struct urtw_softc * sc)2485 urtw_8225_rf_init(struct urtw_softc *sc)
2486 {
2487 unsigned i;
2488 uint16_t data;
2489 usb_error_t error;
2490
2491 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON);
2492 if (error)
2493 goto fail;
2494
2495 error = urtw_8225_usb_init(sc);
2496 if (error)
2497 goto fail;
2498
2499 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008);
2500 urtw_read16_m(sc, URTW_BRSR, &data); /* XXX ??? */
2501 urtw_write16_m(sc, URTW_BRSR, 0xffff);
2502 urtw_write32_m(sc, URTW_RF_PARA, 0x100044);
2503
2504 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
2505 if (error)
2506 goto fail;
2507 urtw_write8_m(sc, URTW_CONFIG3, 0x44);
2508 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
2509 if (error)
2510 goto fail;
2511
2512 error = urtw_8185_rf_pins_enable(sc);
2513 if (error)
2514 goto fail;
2515 urtw_pause_ms(sc, 1000);
2516
2517 for (i = 0; i < nitems(urtw_8225_rf_part1); i++) {
2518 urtw_8225_write(sc, urtw_8225_rf_part1[i].reg,
2519 urtw_8225_rf_part1[i].val);
2520 urtw_pause_ms(sc, 1);
2521 }
2522 urtw_pause_ms(sc, 100);
2523 urtw_8225_write(sc,
2524 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1);
2525 urtw_pause_ms(sc, 200);
2526 urtw_8225_write(sc,
2527 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2);
2528 urtw_pause_ms(sc, 200);
2529 urtw_8225_write(sc,
2530 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC3);
2531
2532 for (i = 0; i < 95; i++) {
2533 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1));
2534 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, urtw_8225_rxgain[i]);
2535 }
2536
2537 urtw_8225_write(sc,
2538 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC4);
2539 urtw_8225_write(sc,
2540 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC5);
2541
2542 for (i = 0; i < 128; i++) {
2543 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]);
2544 urtw_pause_ms(sc, 1);
2545 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80);
2546 urtw_pause_ms(sc, 1);
2547 }
2548
2549 for (i = 0; i < nitems(urtw_8225_rf_part2); i++) {
2550 urtw_8187_write_phy_ofdm(sc, urtw_8225_rf_part2[i].reg,
2551 urtw_8225_rf_part2[i].val);
2552 urtw_pause_ms(sc, 1);
2553 }
2554
2555 error = urtw_8225_setgain(sc, 4);
2556 if (error)
2557 goto fail;
2558
2559 for (i = 0; i < nitems(urtw_8225_rf_part3); i++) {
2560 urtw_8187_write_phy_cck(sc, urtw_8225_rf_part3[i].reg,
2561 urtw_8225_rf_part3[i].val);
2562 urtw_pause_ms(sc, 1);
2563 }
2564
2565 urtw_write8_m(sc, URTW_TESTR, 0x0d);
2566
2567 error = urtw_8225_set_txpwrlvl(sc, 1);
2568 if (error)
2569 goto fail;
2570
2571 urtw_8187_write_phy_cck(sc, 0x10, 0x9b);
2572 urtw_pause_ms(sc, 1);
2573 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90);
2574 urtw_pause_ms(sc, 1);
2575
2576 /* TX ant A, 0x0 for B */
2577 error = urtw_8185_tx_antenna(sc, 0x3);
2578 if (error)
2579 goto fail;
2580 urtw_write32_m(sc, URTW_HSSI_PARA, 0x3dc00002);
2581
2582 error = urtw_8225_rf_set_chan(sc, 1);
2583 fail:
2584 return (error);
2585 }
2586
2587 static usb_error_t
urtw_8185_rf_pins_enable(struct urtw_softc * sc)2588 urtw_8185_rf_pins_enable(struct urtw_softc *sc)
2589 {
2590 usb_error_t error = 0;
2591
2592 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1ff7);
2593 fail:
2594 return (error);
2595 }
2596
2597 static usb_error_t
urtw_8185_tx_antenna(struct urtw_softc * sc,uint8_t ant)2598 urtw_8185_tx_antenna(struct urtw_softc *sc, uint8_t ant)
2599 {
2600 usb_error_t error;
2601
2602 urtw_write8_m(sc, URTW_TX_ANTENNA, ant);
2603 urtw_pause_ms(sc, 1);
2604 fail:
2605 return (error);
2606 }
2607
2608 static usb_error_t
urtw_8187_write_phy_ofdm_c(struct urtw_softc * sc,uint8_t addr,uint32_t data)2609 urtw_8187_write_phy_ofdm_c(struct urtw_softc *sc, uint8_t addr, uint32_t data)
2610 {
2611
2612 data = data & 0xff;
2613 return urtw_8187_write_phy(sc, addr, data);
2614 }
2615
2616 static usb_error_t
urtw_8187_write_phy_cck_c(struct urtw_softc * sc,uint8_t addr,uint32_t data)2617 urtw_8187_write_phy_cck_c(struct urtw_softc *sc, uint8_t addr, uint32_t data)
2618 {
2619
2620 data = data & 0xff;
2621 return urtw_8187_write_phy(sc, addr, data | 0x10000);
2622 }
2623
2624 static usb_error_t
urtw_8187_write_phy(struct urtw_softc * sc,uint8_t addr,uint32_t data)2625 urtw_8187_write_phy(struct urtw_softc *sc, uint8_t addr, uint32_t data)
2626 {
2627 uint32_t phyw;
2628 usb_error_t error;
2629
2630 phyw = ((data << 8) | (addr | 0x80));
2631 urtw_write8_m(sc, URTW_PHY_MAGIC4, ((phyw & 0xff000000) >> 24));
2632 urtw_write8_m(sc, URTW_PHY_MAGIC3, ((phyw & 0x00ff0000) >> 16));
2633 urtw_write8_m(sc, URTW_PHY_MAGIC2, ((phyw & 0x0000ff00) >> 8));
2634 urtw_write8_m(sc, URTW_PHY_MAGIC1, ((phyw & 0x000000ff)));
2635 urtw_pause_ms(sc, 1);
2636 fail:
2637 return (error);
2638 }
2639
2640 static usb_error_t
urtw_8225_setgain(struct urtw_softc * sc,int16_t gain)2641 urtw_8225_setgain(struct urtw_softc *sc, int16_t gain)
2642 {
2643 usb_error_t error;
2644
2645 urtw_8187_write_phy_ofdm(sc, 0x0d, urtw_8225_gain[gain * 4]);
2646 urtw_8187_write_phy_ofdm(sc, 0x1b, urtw_8225_gain[gain * 4 + 2]);
2647 urtw_8187_write_phy_ofdm(sc, 0x1d, urtw_8225_gain[gain * 4 + 3]);
2648 urtw_8187_write_phy_ofdm(sc, 0x23, urtw_8225_gain[gain * 4 + 1]);
2649 fail:
2650 return (error);
2651 }
2652
2653 static usb_error_t
urtw_8225_usb_init(struct urtw_softc * sc)2654 urtw_8225_usb_init(struct urtw_softc *sc)
2655 {
2656 uint8_t data;
2657 usb_error_t error;
2658
2659 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 0);
2660 urtw_write8_m(sc, URTW_GPIO, 0);
2661 error = urtw_read8e(sc, 0x53, &data);
2662 if (error)
2663 goto fail;
2664 error = urtw_write8e(sc, 0x53, data | (1 << 7));
2665 if (error)
2666 goto fail;
2667 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 4);
2668 urtw_write8_m(sc, URTW_GPIO, 0x20);
2669 urtw_write8_m(sc, URTW_GP_ENABLE, 0);
2670
2671 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x80);
2672 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x80);
2673 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x80);
2674
2675 urtw_pause_ms(sc, 500);
2676 fail:
2677 return (error);
2678 }
2679
2680 static usb_error_t
urtw_8225_write_c(struct urtw_softc * sc,uint8_t addr,uint16_t data)2681 urtw_8225_write_c(struct urtw_softc *sc, uint8_t addr, uint16_t data)
2682 {
2683 uint16_t d80, d82, d84;
2684 usb_error_t error;
2685
2686 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &d80);
2687 d80 &= URTW_RF_PINS_MAGIC1;
2688 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &d82);
2689 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &d84);
2690 d84 &= URTW_RF_PINS_MAGIC2;
2691 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, d82 | URTW_RF_PINS_MAGIC3);
2692 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84 | URTW_RF_PINS_MAGIC3);
2693 DELAY(10);
2694
2695 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN);
2696 DELAY(2);
2697 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80);
2698 DELAY(10);
2699
2700 error = urtw_8225_write_s16(sc, addr, 0x8225, &data);
2701 if (error != 0)
2702 goto fail;
2703
2704 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN);
2705 DELAY(10);
2706 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN);
2707 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84);
2708 urtw_pause_ms(sc, 2);
2709 fail:
2710 return (error);
2711 }
2712
2713 static usb_error_t
urtw_8225_write_s16(struct urtw_softc * sc,uint8_t addr,int index,uint16_t * data)2714 urtw_8225_write_s16(struct urtw_softc *sc, uint8_t addr, int index,
2715 uint16_t *data)
2716 {
2717 uint8_t buf[2];
2718 uint16_t data16;
2719 struct usb_device_request req;
2720 usb_error_t error = 0;
2721
2722 data16 = *data;
2723
2724 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
2725 req.bRequest = URTW_8187_SETREGS_REQ;
2726 USETW(req.wValue, addr);
2727 USETW(req.wIndex, index);
2728 USETW(req.wLength, sizeof(uint16_t));
2729 buf[0] = (data16 & 0x00ff);
2730 buf[1] = (data16 & 0xff00) >> 8;
2731
2732 error = urtw_do_request(sc, &req, buf);
2733
2734 return (error);
2735 }
2736
2737 static usb_error_t
urtw_8225_rf_set_chan(struct urtw_softc * sc,int chan)2738 urtw_8225_rf_set_chan(struct urtw_softc *sc, int chan)
2739 {
2740 usb_error_t error;
2741
2742 error = urtw_8225_set_txpwrlvl(sc, chan);
2743 if (error)
2744 goto fail;
2745 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]);
2746 urtw_pause_ms(sc, 10);
2747 fail:
2748 return (error);
2749 }
2750
2751 static usb_error_t
urtw_8225_rf_set_sens(struct urtw_softc * sc,int sens)2752 urtw_8225_rf_set_sens(struct urtw_softc *sc, int sens)
2753 {
2754 usb_error_t error;
2755
2756 if (sens < 0 || sens > 6)
2757 return -1;
2758
2759 if (sens > 4)
2760 urtw_8225_write(sc,
2761 URTW_8225_ADDR_C_MAGIC, URTW_8225_ADDR_C_DATA_MAGIC1);
2762 else
2763 urtw_8225_write(sc,
2764 URTW_8225_ADDR_C_MAGIC, URTW_8225_ADDR_C_DATA_MAGIC2);
2765
2766 sens = 6 - sens;
2767 error = urtw_8225_setgain(sc, sens);
2768 if (error)
2769 goto fail;
2770
2771 urtw_8187_write_phy_cck(sc, 0x41, urtw_8225_threshold[sens]);
2772
2773 fail:
2774 return (error);
2775 }
2776
2777 static usb_error_t
urtw_8225_set_txpwrlvl(struct urtw_softc * sc,int chan)2778 urtw_8225_set_txpwrlvl(struct urtw_softc *sc, int chan)
2779 {
2780 int i, idx, set;
2781 uint8_t *cck_pwltable;
2782 uint8_t cck_pwrlvl_max, ofdm_pwrlvl_min, ofdm_pwrlvl_max;
2783 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff;
2784 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff;
2785 usb_error_t error;
2786
2787 cck_pwrlvl_max = 11;
2788 ofdm_pwrlvl_max = 25; /* 12 -> 25 */
2789 ofdm_pwrlvl_min = 10;
2790
2791 /* CCK power setting */
2792 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl;
2793 idx = cck_pwrlvl % 6;
2794 set = cck_pwrlvl / 6;
2795 cck_pwltable = (chan == 14) ? urtw_8225_txpwr_cck_ch14 :
2796 urtw_8225_txpwr_cck;
2797
2798 urtw_write8_m(sc, URTW_TX_GAIN_CCK,
2799 urtw_8225_tx_gain_cck_ofdm[set] >> 1);
2800 for (i = 0; i < 8; i++) {
2801 urtw_8187_write_phy_cck(sc, 0x44 + i,
2802 cck_pwltable[idx * 8 + i]);
2803 }
2804 urtw_pause_ms(sc, 1);
2805
2806 /* OFDM power setting */
2807 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ?
2808 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min;
2809 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl;
2810
2811 idx = ofdm_pwrlvl % 6;
2812 set = ofdm_pwrlvl / 6;
2813
2814 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON);
2815 if (error)
2816 goto fail;
2817 urtw_8187_write_phy_ofdm(sc, 2, 0x42);
2818 urtw_8187_write_phy_ofdm(sc, 6, 0);
2819 urtw_8187_write_phy_ofdm(sc, 8, 0);
2820
2821 urtw_write8_m(sc, URTW_TX_GAIN_OFDM,
2822 urtw_8225_tx_gain_cck_ofdm[set] >> 1);
2823 urtw_8187_write_phy_ofdm(sc, 0x5, urtw_8225_txpwr_ofdm[idx]);
2824 urtw_8187_write_phy_ofdm(sc, 0x7, urtw_8225_txpwr_ofdm[idx]);
2825 urtw_pause_ms(sc, 1);
2826 fail:
2827 return (error);
2828 }
2829
2830 static usb_error_t
urtw_8225_rf_stop(struct urtw_softc * sc)2831 urtw_8225_rf_stop(struct urtw_softc *sc)
2832 {
2833 uint8_t data;
2834 usb_error_t error;
2835
2836 urtw_8225_write(sc, 0x4, 0x1f);
2837
2838 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
2839 if (error)
2840 goto fail;
2841
2842 urtw_read8_m(sc, URTW_CONFIG3, &data);
2843 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE);
2844 if (sc->sc_flags & URTW_RTL8187B) {
2845 urtw_write32_m(sc, URTW_ANAPARAM2,
2846 URTW_8187B_8225_ANAPARAM2_OFF);
2847 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8187B_8225_ANAPARAM_OFF);
2848 urtw_write32_m(sc, URTW_ANAPARAM3,
2849 URTW_8187B_8225_ANAPARAM3_OFF);
2850 } else {
2851 urtw_write32_m(sc, URTW_ANAPARAM2, URTW_8225_ANAPARAM2_OFF);
2852 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8225_ANAPARAM_OFF);
2853 }
2854
2855 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE);
2856 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
2857 if (error)
2858 goto fail;
2859
2860 fail:
2861 return (error);
2862 }
2863
2864 static usb_error_t
urtw_8225v2_rf_init(struct urtw_softc * sc)2865 urtw_8225v2_rf_init(struct urtw_softc *sc)
2866 {
2867 unsigned i;
2868 uint16_t data;
2869 uint32_t data32;
2870 usb_error_t error;
2871
2872 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON);
2873 if (error)
2874 goto fail;
2875
2876 error = urtw_8225_usb_init(sc);
2877 if (error)
2878 goto fail;
2879
2880 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008);
2881 urtw_read16_m(sc, URTW_BRSR, &data); /* XXX ??? */
2882 urtw_write16_m(sc, URTW_BRSR, 0xffff);
2883 urtw_write32_m(sc, URTW_RF_PARA, 0x100044);
2884
2885 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
2886 if (error)
2887 goto fail;
2888 urtw_write8_m(sc, URTW_CONFIG3, 0x44);
2889 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
2890 if (error)
2891 goto fail;
2892
2893 error = urtw_8185_rf_pins_enable(sc);
2894 if (error)
2895 goto fail;
2896
2897 urtw_pause_ms(sc, 500);
2898
2899 for (i = 0; i < nitems(urtw_8225v2_rf_part1); i++) {
2900 urtw_8225_write(sc, urtw_8225v2_rf_part1[i].reg,
2901 urtw_8225v2_rf_part1[i].val);
2902 }
2903 urtw_pause_ms(sc, 50);
2904
2905 urtw_8225_write(sc,
2906 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC1);
2907
2908 for (i = 0; i < 95; i++) {
2909 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1));
2910 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC,
2911 urtw_8225v2_rxgain[i]);
2912 }
2913
2914 urtw_8225_write(sc,
2915 URTW_8225_ADDR_3_MAGIC, URTW_8225_ADDR_3_DATA_MAGIC1);
2916 urtw_8225_write(sc,
2917 URTW_8225_ADDR_5_MAGIC, URTW_8225_ADDR_5_DATA_MAGIC1);
2918 urtw_8225_write(sc,
2919 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC2);
2920 urtw_8225_write(sc,
2921 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1);
2922 urtw_pause_ms(sc, 100);
2923 urtw_8225_write(sc,
2924 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2);
2925 urtw_pause_ms(sc, 100);
2926
2927 error = urtw_8225_read(sc, URTW_8225_ADDR_6_MAGIC, &data32);
2928 if (error != 0)
2929 goto fail;
2930 if (data32 != URTW_8225_ADDR_6_DATA_MAGIC1)
2931 device_printf(sc->sc_dev, "expect 0xe6!! (0x%x)\n", data32);
2932 if (!(data32 & URTW_8225_ADDR_6_DATA_MAGIC2)) {
2933 urtw_8225_write(sc,
2934 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1);
2935 urtw_pause_ms(sc, 100);
2936 urtw_8225_write(sc,
2937 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2);
2938 urtw_pause_ms(sc, 50);
2939 error = urtw_8225_read(sc, URTW_8225_ADDR_6_MAGIC, &data32);
2940 if (error != 0)
2941 goto fail;
2942 if (!(data32 & URTW_8225_ADDR_6_DATA_MAGIC2))
2943 device_printf(sc->sc_dev, "RF calibration failed\n");
2944 }
2945 urtw_pause_ms(sc, 100);
2946
2947 urtw_8225_write(sc,
2948 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC6);
2949 for (i = 0; i < 128; i++) {
2950 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]);
2951 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80);
2952 }
2953
2954 for (i = 0; i < nitems(urtw_8225v2_rf_part2); i++) {
2955 urtw_8187_write_phy_ofdm(sc, urtw_8225v2_rf_part2[i].reg,
2956 urtw_8225v2_rf_part2[i].val);
2957 }
2958
2959 error = urtw_8225v2_setgain(sc, 4);
2960 if (error)
2961 goto fail;
2962
2963 for (i = 0; i < nitems(urtw_8225v2_rf_part3); i++) {
2964 urtw_8187_write_phy_cck(sc, urtw_8225v2_rf_part3[i].reg,
2965 urtw_8225v2_rf_part3[i].val);
2966 }
2967
2968 urtw_write8_m(sc, URTW_TESTR, 0x0d);
2969
2970 error = urtw_8225v2_set_txpwrlvl(sc, 1);
2971 if (error)
2972 goto fail;
2973
2974 urtw_8187_write_phy_cck(sc, 0x10, 0x9b);
2975 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90);
2976
2977 /* TX ant A, 0x0 for B */
2978 error = urtw_8185_tx_antenna(sc, 0x3);
2979 if (error)
2980 goto fail;
2981 urtw_write32_m(sc, URTW_HSSI_PARA, 0x3dc00002);
2982
2983 error = urtw_8225_rf_set_chan(sc, 1);
2984 fail:
2985 return (error);
2986 }
2987
2988 static usb_error_t
urtw_8225v2_rf_set_chan(struct urtw_softc * sc,int chan)2989 urtw_8225v2_rf_set_chan(struct urtw_softc *sc, int chan)
2990 {
2991 usb_error_t error;
2992
2993 error = urtw_8225v2_set_txpwrlvl(sc, chan);
2994 if (error)
2995 goto fail;
2996
2997 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]);
2998 urtw_pause_ms(sc, 10);
2999 fail:
3000 return (error);
3001 }
3002
3003 static usb_error_t
urtw_8225_read(struct urtw_softc * sc,uint8_t addr,uint32_t * data)3004 urtw_8225_read(struct urtw_softc *sc, uint8_t addr, uint32_t *data)
3005 {
3006 int i;
3007 int16_t bit;
3008 uint8_t rlen = 12, wlen = 6;
3009 uint16_t o1, o2, o3, tmp;
3010 uint32_t d2w = ((uint32_t)(addr & 0x1f)) << 27;
3011 uint32_t mask = 0x80000000, value = 0;
3012 usb_error_t error;
3013
3014 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &o1);
3015 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &o2);
3016 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &o3);
3017 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2 | URTW_RF_PINS_MAGIC4);
3018 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3 | URTW_RF_PINS_MAGIC4);
3019 o1 &= ~URTW_RF_PINS_MAGIC4;
3020 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN);
3021 DELAY(5);
3022 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1);
3023 DELAY(5);
3024
3025 for (i = 0; i < (wlen / 2); i++, mask = mask >> 1) {
3026 bit = ((d2w & mask) != 0) ? 1 : 0;
3027
3028 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1);
3029 DELAY(2);
3030 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 |
3031 URTW_BB_HOST_BANG_CLK);
3032 DELAY(2);
3033 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 |
3034 URTW_BB_HOST_BANG_CLK);
3035 DELAY(2);
3036 mask = mask >> 1;
3037 if (i == 2)
3038 break;
3039 bit = ((d2w & mask) != 0) ? 1 : 0;
3040 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 |
3041 URTW_BB_HOST_BANG_CLK);
3042 DELAY(2);
3043 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 |
3044 URTW_BB_HOST_BANG_CLK);
3045 DELAY(2);
3046 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1);
3047 DELAY(1);
3048 }
3049 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW |
3050 URTW_BB_HOST_BANG_CLK);
3051 DELAY(2);
3052 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW);
3053 DELAY(2);
3054 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_RW);
3055 DELAY(2);
3056
3057 mask = 0x800;
3058 for (i = 0; i < rlen; i++, mask = mask >> 1) {
3059 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
3060 o1 | URTW_BB_HOST_BANG_RW);
3061 DELAY(2);
3062 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
3063 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK);
3064 DELAY(2);
3065 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
3066 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK);
3067 DELAY(2);
3068 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
3069 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK);
3070 DELAY(2);
3071
3072 urtw_read16_m(sc, URTW_RF_PINS_INPUT, &tmp);
3073 value |= ((tmp & URTW_BB_HOST_BANG_CLK) ? mask : 0);
3074 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
3075 o1 | URTW_BB_HOST_BANG_RW);
3076 DELAY(2);
3077 }
3078
3079 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN |
3080 URTW_BB_HOST_BANG_RW);
3081 DELAY(2);
3082
3083 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2);
3084 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3);
3085 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, URTW_RF_PINS_OUTPUT_MAGIC1);
3086
3087 if (data != NULL)
3088 *data = value;
3089 fail:
3090 return (error);
3091 }
3092
3093 static usb_error_t
urtw_8225v2_set_txpwrlvl(struct urtw_softc * sc,int chan)3094 urtw_8225v2_set_txpwrlvl(struct urtw_softc *sc, int chan)
3095 {
3096 int i;
3097 uint8_t *cck_pwrtable;
3098 uint8_t cck_pwrlvl_max = 15, ofdm_pwrlvl_max = 25, ofdm_pwrlvl_min = 10;
3099 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff;
3100 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff;
3101 usb_error_t error;
3102
3103 /* CCK power setting */
3104 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl;
3105 cck_pwrlvl += sc->sc_txpwr_cck_base;
3106 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl;
3107 cck_pwrtable = (chan == 14) ? urtw_8225v2_txpwr_cck_ch14 :
3108 urtw_8225v2_txpwr_cck;
3109
3110 for (i = 0; i < 8; i++)
3111 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]);
3112
3113 urtw_write8_m(sc, URTW_TX_GAIN_CCK,
3114 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl]);
3115 urtw_pause_ms(sc, 1);
3116
3117 /* OFDM power setting */
3118 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ?
3119 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min;
3120 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base;
3121 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl;
3122
3123 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON);
3124 if (error)
3125 goto fail;
3126
3127 urtw_8187_write_phy_ofdm(sc, 2, 0x42);
3128 urtw_8187_write_phy_ofdm(sc, 5, 0x0);
3129 urtw_8187_write_phy_ofdm(sc, 6, 0x40);
3130 urtw_8187_write_phy_ofdm(sc, 7, 0x0);
3131 urtw_8187_write_phy_ofdm(sc, 8, 0x40);
3132
3133 urtw_write8_m(sc, URTW_TX_GAIN_OFDM,
3134 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl]);
3135 urtw_pause_ms(sc, 1);
3136 fail:
3137 return (error);
3138 }
3139
3140 static usb_error_t
urtw_8225v2_setgain(struct urtw_softc * sc,int16_t gain)3141 urtw_8225v2_setgain(struct urtw_softc *sc, int16_t gain)
3142 {
3143 uint8_t *gainp;
3144 usb_error_t error;
3145
3146 /* XXX for A? */
3147 gainp = urtw_8225v2_gain_bg;
3148 urtw_8187_write_phy_ofdm(sc, 0x0d, gainp[gain * 3]);
3149 urtw_pause_ms(sc, 1);
3150 urtw_8187_write_phy_ofdm(sc, 0x1b, gainp[gain * 3 + 1]);
3151 urtw_pause_ms(sc, 1);
3152 urtw_8187_write_phy_ofdm(sc, 0x1d, gainp[gain * 3 + 2]);
3153 urtw_pause_ms(sc, 1);
3154 urtw_8187_write_phy_ofdm(sc, 0x21, 0x17);
3155 urtw_pause_ms(sc, 1);
3156 fail:
3157 return (error);
3158 }
3159
3160 static usb_error_t
urtw_8225_isv2(struct urtw_softc * sc,int * ret)3161 urtw_8225_isv2(struct urtw_softc *sc, int *ret)
3162 {
3163 uint32_t data;
3164 usb_error_t error;
3165
3166 *ret = 1;
3167
3168 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, URTW_RF_PINS_MAGIC5);
3169 urtw_write16_m(sc, URTW_RF_PINS_SELECT, URTW_RF_PINS_MAGIC5);
3170 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, URTW_RF_PINS_MAGIC5);
3171 urtw_pause_ms(sc, 500);
3172
3173 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC,
3174 URTW_8225_ADDR_0_DATA_MAGIC1);
3175
3176 error = urtw_8225_read(sc, URTW_8225_ADDR_8_MAGIC, &data);
3177 if (error != 0)
3178 goto fail;
3179 if (data != URTW_8225_ADDR_8_DATA_MAGIC1)
3180 *ret = 0;
3181 else {
3182 error = urtw_8225_read(sc, URTW_8225_ADDR_9_MAGIC, &data);
3183 if (error != 0)
3184 goto fail;
3185 if (data != URTW_8225_ADDR_9_DATA_MAGIC1)
3186 *ret = 0;
3187 }
3188
3189 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC,
3190 URTW_8225_ADDR_0_DATA_MAGIC2);
3191 fail:
3192 return (error);
3193 }
3194
3195 static usb_error_t
urtw_8225v2b_rf_init(struct urtw_softc * sc)3196 urtw_8225v2b_rf_init(struct urtw_softc *sc)
3197 {
3198 struct ieee80211com *ic = &sc->sc_ic;
3199 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
3200 const uint8_t *macaddr;
3201 unsigned i;
3202 uint8_t data8;
3203 usb_error_t error;
3204
3205 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
3206 if (error)
3207 goto fail;
3208
3209 /*
3210 * initialize extra registers on 8187
3211 */
3212 urtw_write16_m(sc, URTW_BRSR_8187B, 0xfff);
3213
3214 /* retry limit */
3215 urtw_read8_m(sc, URTW_CW_CONF, &data8);
3216 data8 |= URTW_CW_CONF_PERPACKET_RETRY;
3217 urtw_write8_m(sc, URTW_CW_CONF, data8);
3218
3219 /* TX AGC */
3220 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data8);
3221 data8 |= URTW_TX_AGC_CTL_PERPACKET_GAIN;
3222 urtw_write8_m(sc, URTW_TX_AGC_CTL, data8);
3223
3224 /* Auto Rate Fallback Control */
3225 #define URTW_ARFR 0x1e0
3226 urtw_write16_m(sc, URTW_ARFR, 0xfff);
3227 urtw_read8_m(sc, URTW_RATE_FALLBACK, &data8);
3228 urtw_write8_m(sc, URTW_RATE_FALLBACK,
3229 data8 | URTW_RATE_FALLBACK_ENABLE);
3230
3231 urtw_read8_m(sc, URTW_MSR, &data8);
3232 urtw_write8_m(sc, URTW_MSR, data8 & 0xf3);
3233 urtw_read8_m(sc, URTW_MSR, &data8);
3234 urtw_write8_m(sc, URTW_MSR, data8 | URTW_MSR_LINK_ENEDCA);
3235 urtw_write8_m(sc, URTW_ACM_CONTROL, sc->sc_acmctl);
3236
3237 urtw_write16_m(sc, URTW_ATIM_WND, 2);
3238 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 100);
3239 #define URTW_FEMR_FOR_8187B 0x1d4
3240 urtw_write16_m(sc, URTW_FEMR_FOR_8187B, 0xffff);
3241
3242 /* led type */
3243 urtw_read8_m(sc, URTW_CONFIG1, &data8);
3244 data8 = (data8 & 0x3f) | 0x80;
3245 urtw_write8_m(sc, URTW_CONFIG1, data8);
3246
3247 /* applying MAC address again. */
3248 macaddr = vap ? vap->iv_myaddr : ic->ic_macaddr;
3249 error = urtw_set_macaddr(sc, macaddr);
3250 if (error)
3251 goto fail;
3252
3253 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
3254 if (error)
3255 goto fail;
3256
3257 urtw_write8_m(sc, URTW_WPA_CONFIG, 0);
3258
3259 /*
3260 * MAC configuration
3261 */
3262 for (i = 0; i < nitems(urtw_8225v2b_rf_part1); i++)
3263 urtw_write8_m(sc, urtw_8225v2b_rf_part1[i].reg,
3264 urtw_8225v2b_rf_part1[i].val);
3265 urtw_write16_m(sc, URTW_TID_AC_MAP, 0xfa50);
3266 urtw_write16_m(sc, URTW_INT_MIG, 0x0000);
3267 urtw_write32_m(sc, 0x1f0, 0);
3268 urtw_write32_m(sc, 0x1f4, 0);
3269 urtw_write8_m(sc, 0x1f8, 0);
3270 urtw_write32_m(sc, URTW_RF_TIMING, 0x4001);
3271
3272 #define URTW_RFSW_CTRL 0x272
3273 urtw_write16_m(sc, URTW_RFSW_CTRL, 0x569a);
3274
3275 /*
3276 * initialize PHY
3277 */
3278 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
3279 if (error)
3280 goto fail;
3281 urtw_read8_m(sc, URTW_CONFIG3, &data8);
3282 urtw_write8_m(sc, URTW_CONFIG3,
3283 data8 | URTW_CONFIG3_ANAPARAM_WRITE);
3284
3285 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
3286 if (error)
3287 goto fail;
3288
3289 /* setup RFE initial timing */
3290 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x0480);
3291 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x2488);
3292 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1fff);
3293 urtw_pause_ms(sc, 1100);
3294
3295 for (i = 0; i < nitems(urtw_8225v2b_rf_part0); i++) {
3296 urtw_8225_write(sc, urtw_8225v2b_rf_part0[i].reg,
3297 urtw_8225v2b_rf_part0[i].val);
3298 urtw_pause_ms(sc, 1);
3299 }
3300 urtw_8225_write(sc, 0x00, 0x01b7);
3301
3302 for (i = 0; i < 95; i++) {
3303 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1));
3304 urtw_pause_ms(sc, 1);
3305 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC,
3306 urtw_8225v2b_rxgain[i]);
3307 urtw_pause_ms(sc, 1);
3308 }
3309
3310 urtw_8225_write(sc, URTW_8225_ADDR_3_MAGIC, 0x080);
3311 urtw_pause_ms(sc, 1);
3312 urtw_8225_write(sc, URTW_8225_ADDR_5_MAGIC, 0x004);
3313 urtw_pause_ms(sc, 1);
3314 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC, 0x0b7);
3315 urtw_pause_ms(sc, 1);
3316 urtw_pause_ms(sc, 3000);
3317 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, 0xc4d);
3318 urtw_pause_ms(sc, 2000);
3319 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, 0x44d);
3320 urtw_pause_ms(sc, 1);
3321 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC, 0x2bf);
3322 urtw_pause_ms(sc, 1);
3323
3324 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 0x03);
3325 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 0x07);
3326 urtw_write8_m(sc, URTW_TX_ANTENNA, 0x03);
3327
3328 urtw_8187_write_phy_ofdm(sc, 0x80, 0x12);
3329 for (i = 0; i < 128; i++) {
3330 uint32_t addr, data;
3331
3332 data = (urtw_8225z2_agc[i] << 8) | 0x0000008f;
3333 addr = ((i + 0x80) << 8) | 0x0000008e;
3334
3335 urtw_8187_write_phy_ofdm(sc, data & 0x7f, (data >> 8) & 0xff);
3336 urtw_8187_write_phy_ofdm(sc, addr & 0x7f, (addr >> 8) & 0xff);
3337 urtw_8187_write_phy_ofdm(sc, 0x0e, 0x00);
3338 }
3339 urtw_8187_write_phy_ofdm(sc, 0x80, 0x10);
3340
3341 for (i = 0; i < nitems(urtw_8225v2b_rf_part2); i++)
3342 urtw_8187_write_phy_ofdm(sc, i, urtw_8225v2b_rf_part2[i].val);
3343
3344 urtw_write32_m(sc, URTW_8187B_AC_VO, (7 << 12) | (3 << 8) | 0x1c);
3345 urtw_write32_m(sc, URTW_8187B_AC_VI, (7 << 12) | (3 << 8) | 0x1c);
3346 urtw_write32_m(sc, URTW_8187B_AC_BE, (7 << 12) | (3 << 8) | 0x1c);
3347 urtw_write32_m(sc, URTW_8187B_AC_BK, (7 << 12) | (3 << 8) | 0x1c);
3348
3349 urtw_8187_write_phy_ofdm(sc, 0x97, 0x46);
3350 urtw_8187_write_phy_ofdm(sc, 0xa4, 0xb6);
3351 urtw_8187_write_phy_ofdm(sc, 0x85, 0xfc);
3352 urtw_8187_write_phy_cck(sc, 0xc1, 0x88);
3353
3354 fail:
3355 return (error);
3356 }
3357
3358 static usb_error_t
urtw_8225v2b_rf_set_chan(struct urtw_softc * sc,int chan)3359 urtw_8225v2b_rf_set_chan(struct urtw_softc *sc, int chan)
3360 {
3361 usb_error_t error;
3362
3363 error = urtw_8225v2b_set_txpwrlvl(sc, chan);
3364 if (error)
3365 goto fail;
3366
3367 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]);
3368 urtw_pause_ms(sc, 10);
3369 fail:
3370 return (error);
3371 }
3372
3373 static usb_error_t
urtw_8225v2b_set_txpwrlvl(struct urtw_softc * sc,int chan)3374 urtw_8225v2b_set_txpwrlvl(struct urtw_softc *sc, int chan)
3375 {
3376 int i;
3377 uint8_t *cck_pwrtable;
3378 uint8_t cck_pwrlvl_max = 15;
3379 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff;
3380 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff;
3381 usb_error_t error;
3382
3383 /* CCK power setting */
3384 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ?
3385 ((sc->sc_flags & URTW_RTL8187B_REV_B) ? cck_pwrlvl_max : 22) :
3386 (cck_pwrlvl + ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 0 : 7));
3387 cck_pwrlvl += sc->sc_txpwr_cck_base;
3388 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl;
3389 cck_pwrtable = (chan == 14) ? urtw_8225v2b_txpwr_cck_ch14 :
3390 urtw_8225v2b_txpwr_cck;
3391
3392 if (sc->sc_flags & URTW_RTL8187B_REV_B)
3393 cck_pwrtable += (cck_pwrlvl <= 6) ? 0 :
3394 ((cck_pwrlvl <= 11) ? 8 : 16);
3395 else
3396 cck_pwrtable += (cck_pwrlvl <= 5) ? 0 :
3397 ((cck_pwrlvl <= 11) ? 8 : ((cck_pwrlvl <= 17) ? 16 : 24));
3398
3399 for (i = 0; i < 8; i++)
3400 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]);
3401
3402 urtw_write8_m(sc, URTW_TX_GAIN_CCK,
3403 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl] << 1);
3404 urtw_pause_ms(sc, 1);
3405
3406 /* OFDM power setting */
3407 ofdm_pwrlvl = (ofdm_pwrlvl > 15) ?
3408 ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 17 : 25) :
3409 (ofdm_pwrlvl + ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 2 : 10));
3410 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base;
3411 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl;
3412
3413 urtw_write8_m(sc, URTW_TX_GAIN_OFDM,
3414 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl] << 1);
3415
3416 if (sc->sc_flags & URTW_RTL8187B_REV_B) {
3417 if (ofdm_pwrlvl <= 11) {
3418 urtw_8187_write_phy_ofdm(sc, 0x87, 0x60);
3419 urtw_8187_write_phy_ofdm(sc, 0x89, 0x60);
3420 } else {
3421 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c);
3422 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c);
3423 }
3424 } else {
3425 if (ofdm_pwrlvl <= 11) {
3426 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c);
3427 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c);
3428 } else if (ofdm_pwrlvl <= 17) {
3429 urtw_8187_write_phy_ofdm(sc, 0x87, 0x54);
3430 urtw_8187_write_phy_ofdm(sc, 0x89, 0x54);
3431 } else {
3432 urtw_8187_write_phy_ofdm(sc, 0x87, 0x50);
3433 urtw_8187_write_phy_ofdm(sc, 0x89, 0x50);
3434 }
3435 }
3436 urtw_pause_ms(sc, 1);
3437 fail:
3438 return (error);
3439 }
3440
3441 static usb_error_t
urtw_read8e(struct urtw_softc * sc,int val,uint8_t * data)3442 urtw_read8e(struct urtw_softc *sc, int val, uint8_t *data)
3443 {
3444 struct usb_device_request req;
3445 usb_error_t error;
3446
3447 req.bmRequestType = UT_READ_VENDOR_DEVICE;
3448 req.bRequest = URTW_8187_GETREGS_REQ;
3449 USETW(req.wValue, val | 0xfe00);
3450 USETW(req.wIndex, 0);
3451 USETW(req.wLength, sizeof(uint8_t));
3452
3453 error = urtw_do_request(sc, &req, data);
3454 return (error);
3455 }
3456
3457 static usb_error_t
urtw_write8e(struct urtw_softc * sc,int val,uint8_t data)3458 urtw_write8e(struct urtw_softc *sc, int val, uint8_t data)
3459 {
3460 struct usb_device_request req;
3461
3462 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
3463 req.bRequest = URTW_8187_SETREGS_REQ;
3464 USETW(req.wValue, val | 0xfe00);
3465 USETW(req.wIndex, 0);
3466 USETW(req.wLength, sizeof(uint8_t));
3467
3468 return (urtw_do_request(sc, &req, &data));
3469 }
3470
3471 static usb_error_t
urtw_8180_set_anaparam(struct urtw_softc * sc,uint32_t val)3472 urtw_8180_set_anaparam(struct urtw_softc *sc, uint32_t val)
3473 {
3474 uint8_t data;
3475 usb_error_t error;
3476
3477 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
3478 if (error)
3479 goto fail;
3480
3481 urtw_read8_m(sc, URTW_CONFIG3, &data);
3482 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE);
3483 urtw_write32_m(sc, URTW_ANAPARAM, val);
3484 urtw_read8_m(sc, URTW_CONFIG3, &data);
3485 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE);
3486
3487 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
3488 if (error)
3489 goto fail;
3490 fail:
3491 return (error);
3492 }
3493
3494 static usb_error_t
urtw_8185_set_anaparam2(struct urtw_softc * sc,uint32_t val)3495 urtw_8185_set_anaparam2(struct urtw_softc *sc, uint32_t val)
3496 {
3497 uint8_t data;
3498 usb_error_t error;
3499
3500 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
3501 if (error)
3502 goto fail;
3503
3504 urtw_read8_m(sc, URTW_CONFIG3, &data);
3505 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE);
3506 urtw_write32_m(sc, URTW_ANAPARAM2, val);
3507 urtw_read8_m(sc, URTW_CONFIG3, &data);
3508 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE);
3509
3510 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
3511 if (error)
3512 goto fail;
3513 fail:
3514 return (error);
3515 }
3516
3517 static usb_error_t
urtw_intr_enable(struct urtw_softc * sc)3518 urtw_intr_enable(struct urtw_softc *sc)
3519 {
3520 usb_error_t error;
3521
3522 urtw_write16_m(sc, URTW_INTR_MASK, 0xffff);
3523 fail:
3524 return (error);
3525 }
3526
3527 static usb_error_t
urtw_intr_disable(struct urtw_softc * sc)3528 urtw_intr_disable(struct urtw_softc *sc)
3529 {
3530 usb_error_t error;
3531
3532 urtw_write16_m(sc, URTW_INTR_MASK, 0);
3533 fail:
3534 return (error);
3535 }
3536
3537 static usb_error_t
urtw_reset(struct urtw_softc * sc)3538 urtw_reset(struct urtw_softc *sc)
3539 {
3540 uint8_t data;
3541 usb_error_t error;
3542
3543 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON);
3544 if (error)
3545 goto fail;
3546 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON);
3547 if (error)
3548 goto fail;
3549
3550 error = urtw_intr_disable(sc);
3551 if (error)
3552 goto fail;
3553 urtw_pause_ms(sc, 100);
3554
3555 error = urtw_write8e(sc, 0x18, 0x10);
3556 if (error != 0)
3557 goto fail;
3558 error = urtw_write8e(sc, 0x18, 0x11);
3559 if (error != 0)
3560 goto fail;
3561 error = urtw_write8e(sc, 0x18, 0x00);
3562 if (error != 0)
3563 goto fail;
3564 urtw_pause_ms(sc, 100);
3565
3566 urtw_read8_m(sc, URTW_CMD, &data);
3567 data = (data & 0x2) | URTW_CMD_RST;
3568 urtw_write8_m(sc, URTW_CMD, data);
3569 urtw_pause_ms(sc, 100);
3570
3571 urtw_read8_m(sc, URTW_CMD, &data);
3572 if (data & URTW_CMD_RST) {
3573 device_printf(sc->sc_dev, "reset timeout\n");
3574 goto fail;
3575 }
3576
3577 error = urtw_set_mode(sc, URTW_EPROM_CMD_LOAD);
3578 if (error)
3579 goto fail;
3580 urtw_pause_ms(sc, 100);
3581
3582 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON);
3583 if (error)
3584 goto fail;
3585 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON);
3586 if (error)
3587 goto fail;
3588 fail:
3589 return (error);
3590 }
3591
3592 static usb_error_t
urtw_led_ctl(struct urtw_softc * sc,int mode)3593 urtw_led_ctl(struct urtw_softc *sc, int mode)
3594 {
3595 usb_error_t error = 0;
3596
3597 switch (sc->sc_strategy) {
3598 case URTW_SW_LED_MODE0:
3599 error = urtw_led_mode0(sc, mode);
3600 break;
3601 case URTW_SW_LED_MODE1:
3602 error = urtw_led_mode1(sc, mode);
3603 break;
3604 case URTW_SW_LED_MODE2:
3605 error = urtw_led_mode2(sc, mode);
3606 break;
3607 case URTW_SW_LED_MODE3:
3608 error = urtw_led_mode3(sc, mode);
3609 break;
3610 default:
3611 DPRINTF(sc, URTW_DEBUG_STATE,
3612 "unsupported LED mode %d\n", sc->sc_strategy);
3613 error = USB_ERR_INVAL;
3614 break;
3615 }
3616
3617 return (error);
3618 }
3619
3620 static usb_error_t
urtw_led_mode0(struct urtw_softc * sc,int mode)3621 urtw_led_mode0(struct urtw_softc *sc, int mode)
3622 {
3623
3624 switch (mode) {
3625 case URTW_LED_CTL_POWER_ON:
3626 sc->sc_gpio_ledstate = URTW_LED_POWER_ON_BLINK;
3627 break;
3628 case URTW_LED_CTL_TX:
3629 if (sc->sc_gpio_ledinprogress == 1)
3630 return (0);
3631
3632 sc->sc_gpio_ledstate = URTW_LED_BLINK_NORMAL;
3633 sc->sc_gpio_blinktime = 2;
3634 break;
3635 case URTW_LED_CTL_LINK:
3636 sc->sc_gpio_ledstate = URTW_LED_ON;
3637 break;
3638 default:
3639 DPRINTF(sc, URTW_DEBUG_STATE,
3640 "unsupported LED mode 0x%x", mode);
3641 return (USB_ERR_INVAL);
3642 }
3643
3644 switch (sc->sc_gpio_ledstate) {
3645 case URTW_LED_ON:
3646 if (sc->sc_gpio_ledinprogress != 0)
3647 break;
3648 urtw_led_on(sc, URTW_LED_GPIO);
3649 break;
3650 case URTW_LED_BLINK_NORMAL:
3651 if (sc->sc_gpio_ledinprogress != 0)
3652 break;
3653 sc->sc_gpio_ledinprogress = 1;
3654 sc->sc_gpio_blinkstate = (sc->sc_gpio_ledon != 0) ?
3655 URTW_LED_OFF : URTW_LED_ON;
3656 usb_callout_reset(&sc->sc_led_ch, hz, urtw_led_ch, sc);
3657 break;
3658 case URTW_LED_POWER_ON_BLINK:
3659 urtw_led_on(sc, URTW_LED_GPIO);
3660 urtw_pause_ms(sc, 100);
3661 urtw_led_off(sc, URTW_LED_GPIO);
3662 break;
3663 default:
3664 DPRINTF(sc, URTW_DEBUG_STATE,
3665 "unknown LED status 0x%x", sc->sc_gpio_ledstate);
3666 return (USB_ERR_INVAL);
3667 }
3668 return (0);
3669 }
3670
3671 static usb_error_t
urtw_led_mode1(struct urtw_softc * sc,int mode)3672 urtw_led_mode1(struct urtw_softc *sc, int mode)
3673 {
3674 return (USB_ERR_INVAL);
3675 }
3676
3677 static usb_error_t
urtw_led_mode2(struct urtw_softc * sc,int mode)3678 urtw_led_mode2(struct urtw_softc *sc, int mode)
3679 {
3680 return (USB_ERR_INVAL);
3681 }
3682
3683 static usb_error_t
urtw_led_mode3(struct urtw_softc * sc,int mode)3684 urtw_led_mode3(struct urtw_softc *sc, int mode)
3685 {
3686 return (USB_ERR_INVAL);
3687 }
3688
3689 static usb_error_t
urtw_led_on(struct urtw_softc * sc,int type)3690 urtw_led_on(struct urtw_softc *sc, int type)
3691 {
3692 usb_error_t error;
3693
3694 if (type == URTW_LED_GPIO) {
3695 switch (sc->sc_gpio_ledpin) {
3696 case URTW_LED_PIN_GPIO0:
3697 urtw_write8_m(sc, URTW_GPIO, 0x01);
3698 urtw_write8_m(sc, URTW_GP_ENABLE, 0x00);
3699 break;
3700 default:
3701 DPRINTF(sc, URTW_DEBUG_STATE,
3702 "unsupported LED PIN type 0x%x",
3703 sc->sc_gpio_ledpin);
3704 error = USB_ERR_INVAL;
3705 goto fail;
3706 }
3707 } else {
3708 DPRINTF(sc, URTW_DEBUG_STATE,
3709 "unsupported LED type 0x%x", type);
3710 error = USB_ERR_INVAL;
3711 goto fail;
3712 }
3713
3714 sc->sc_gpio_ledon = 1;
3715 fail:
3716 return (error);
3717 }
3718
3719 static usb_error_t
urtw_led_off(struct urtw_softc * sc,int type)3720 urtw_led_off(struct urtw_softc *sc, int type)
3721 {
3722 usb_error_t error;
3723
3724 if (type == URTW_LED_GPIO) {
3725 switch (sc->sc_gpio_ledpin) {
3726 case URTW_LED_PIN_GPIO0:
3727 urtw_write8_m(sc, URTW_GPIO, URTW_GPIO_DATA_MAGIC1);
3728 urtw_write8_m(sc,
3729 URTW_GP_ENABLE, URTW_GP_ENABLE_DATA_MAGIC1);
3730 break;
3731 default:
3732 DPRINTF(sc, URTW_DEBUG_STATE,
3733 "unsupported LED PIN type 0x%x",
3734 sc->sc_gpio_ledpin);
3735 error = USB_ERR_INVAL;
3736 goto fail;
3737 }
3738 } else {
3739 DPRINTF(sc, URTW_DEBUG_STATE,
3740 "unsupported LED type 0x%x", type);
3741 error = USB_ERR_INVAL;
3742 goto fail;
3743 }
3744
3745 sc->sc_gpio_ledon = 0;
3746
3747 fail:
3748 return (error);
3749 }
3750
3751 static void
urtw_led_ch(void * arg)3752 urtw_led_ch(void *arg)
3753 {
3754 struct urtw_softc *sc = arg;
3755 struct ieee80211com *ic = &sc->sc_ic;
3756
3757 ieee80211_runtask(ic, &sc->sc_led_task);
3758 }
3759
3760 static void
urtw_ledtask(void * arg,int pending)3761 urtw_ledtask(void *arg, int pending)
3762 {
3763 struct urtw_softc *sc = arg;
3764
3765 if (sc->sc_strategy != URTW_SW_LED_MODE0) {
3766 DPRINTF(sc, URTW_DEBUG_STATE,
3767 "could not process a LED strategy 0x%x",
3768 sc->sc_strategy);
3769 return;
3770 }
3771
3772 URTW_LOCK(sc);
3773 urtw_led_blink(sc);
3774 URTW_UNLOCK(sc);
3775 }
3776
3777 static usb_error_t
urtw_led_blink(struct urtw_softc * sc)3778 urtw_led_blink(struct urtw_softc *sc)
3779 {
3780 uint8_t ing = 0;
3781
3782 if (sc->sc_gpio_blinkstate == URTW_LED_ON)
3783 urtw_led_on(sc, URTW_LED_GPIO);
3784 else
3785 urtw_led_off(sc, URTW_LED_GPIO);
3786 sc->sc_gpio_blinktime--;
3787 if (sc->sc_gpio_blinktime == 0)
3788 ing = 1;
3789 else {
3790 if (sc->sc_gpio_ledstate != URTW_LED_BLINK_NORMAL &&
3791 sc->sc_gpio_ledstate != URTW_LED_BLINK_SLOWLY &&
3792 sc->sc_gpio_ledstate != URTW_LED_BLINK_CM3)
3793 ing = 1;
3794 }
3795 if (ing == 1) {
3796 if (sc->sc_gpio_ledstate == URTW_LED_ON &&
3797 sc->sc_gpio_ledon == 0)
3798 urtw_led_on(sc, URTW_LED_GPIO);
3799 else if (sc->sc_gpio_ledstate == URTW_LED_OFF &&
3800 sc->sc_gpio_ledon == 1)
3801 urtw_led_off(sc, URTW_LED_GPIO);
3802
3803 sc->sc_gpio_blinktime = 0;
3804 sc->sc_gpio_ledinprogress = 0;
3805 return (0);
3806 }
3807
3808 sc->sc_gpio_blinkstate = (sc->sc_gpio_blinkstate != URTW_LED_ON) ?
3809 URTW_LED_ON : URTW_LED_OFF;
3810
3811 switch (sc->sc_gpio_ledstate) {
3812 case URTW_LED_BLINK_NORMAL:
3813 usb_callout_reset(&sc->sc_led_ch, hz, urtw_led_ch, sc);
3814 break;
3815 default:
3816 DPRINTF(sc, URTW_DEBUG_STATE,
3817 "unknown LED status 0x%x",
3818 sc->sc_gpio_ledstate);
3819 return (USB_ERR_INVAL);
3820 }
3821 return (0);
3822 }
3823
3824 static usb_error_t
urtw_rx_enable(struct urtw_softc * sc)3825 urtw_rx_enable(struct urtw_softc *sc)
3826 {
3827 uint8_t data;
3828 usb_error_t error;
3829
3830 usbd_transfer_start((sc->sc_flags & URTW_RTL8187B) ?
3831 sc->sc_xfer[URTW_8187B_BULK_RX] : sc->sc_xfer[URTW_8187L_BULK_RX]);
3832
3833 error = urtw_rx_setconf(sc);
3834 if (error != 0)
3835 goto fail;
3836
3837 if ((sc->sc_flags & URTW_RTL8187B) == 0) {
3838 urtw_read8_m(sc, URTW_CMD, &data);
3839 urtw_write8_m(sc, URTW_CMD, data | URTW_CMD_RX_ENABLE);
3840 }
3841 fail:
3842 return (error);
3843 }
3844
3845 static usb_error_t
urtw_tx_enable(struct urtw_softc * sc)3846 urtw_tx_enable(struct urtw_softc *sc)
3847 {
3848 uint8_t data8;
3849 uint32_t data;
3850 usb_error_t error;
3851
3852 if (sc->sc_flags & URTW_RTL8187B) {
3853 urtw_read32_m(sc, URTW_TX_CONF, &data);
3854 data &= ~URTW_TX_LOOPBACK_MASK;
3855 data &= ~(URTW_TX_DPRETRY_MASK | URTW_TX_RTSRETRY_MASK);
3856 data &= ~(URTW_TX_NOCRC | URTW_TX_MXDMA_MASK);
3857 data &= ~URTW_TX_SWPLCPLEN;
3858 data |= URTW_TX_HW_SEQNUM | URTW_TX_DISREQQSIZE |
3859 (7 << 8) | /* short retry limit */
3860 (7 << 0) | /* long retry limit */
3861 (7 << 21); /* MAX TX DMA */
3862 urtw_write32_m(sc, URTW_TX_CONF, data);
3863
3864 urtw_read8_m(sc, URTW_MSR, &data8);
3865 data8 |= URTW_MSR_LINK_ENEDCA;
3866 urtw_write8_m(sc, URTW_MSR, data8);
3867 return (error);
3868 }
3869
3870 urtw_read8_m(sc, URTW_CW_CONF, &data8);
3871 data8 &= ~(URTW_CW_CONF_PERPACKET_CW | URTW_CW_CONF_PERPACKET_RETRY);
3872 urtw_write8_m(sc, URTW_CW_CONF, data8);
3873
3874 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data8);
3875 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_GAIN;
3876 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_ANTSEL;
3877 data8 &= ~URTW_TX_AGC_CTL_FEEDBACK_ANT;
3878 urtw_write8_m(sc, URTW_TX_AGC_CTL, data8);
3879
3880 urtw_read32_m(sc, URTW_TX_CONF, &data);
3881 data &= ~URTW_TX_LOOPBACK_MASK;
3882 data |= URTW_TX_LOOPBACK_NONE;
3883 data &= ~(URTW_TX_DPRETRY_MASK | URTW_TX_RTSRETRY_MASK);
3884 data |= sc->sc_tx_retry << URTW_TX_DPRETRY_SHIFT;
3885 data |= sc->sc_rts_retry << URTW_TX_RTSRETRY_SHIFT;
3886 data &= ~(URTW_TX_NOCRC | URTW_TX_MXDMA_MASK);
3887 data |= URTW_TX_MXDMA_2048 | URTW_TX_CWMIN | URTW_TX_DISCW;
3888 data &= ~URTW_TX_SWPLCPLEN;
3889 data |= URTW_TX_NOICV;
3890 urtw_write32_m(sc, URTW_TX_CONF, data);
3891
3892 urtw_read8_m(sc, URTW_CMD, &data8);
3893 urtw_write8_m(sc, URTW_CMD, data8 | URTW_CMD_TX_ENABLE);
3894 fail:
3895 return (error);
3896 }
3897
3898 static usb_error_t
urtw_rx_setconf(struct urtw_softc * sc)3899 urtw_rx_setconf(struct urtw_softc *sc)
3900 {
3901 struct ieee80211com *ic = &sc->sc_ic;
3902 uint32_t data;
3903 usb_error_t error;
3904
3905 urtw_read32_m(sc, URTW_RX, &data);
3906 data = data &~ URTW_RX_FILTER_MASK;
3907 if (sc->sc_flags & URTW_RTL8187B) {
3908 data = data | URTW_RX_FILTER_MNG | URTW_RX_FILTER_DATA |
3909 URTW_RX_FILTER_MCAST | URTW_RX_FILTER_BCAST |
3910 URTW_RX_FIFO_THRESHOLD_NONE |
3911 URTW_MAX_RX_DMA_2048 |
3912 URTW_RX_AUTORESETPHY | URTW_RCR_ONLYERLPKT;
3913 } else {
3914 data = data | URTW_RX_FILTER_MNG | URTW_RX_FILTER_DATA;
3915 data = data | URTW_RX_FILTER_BCAST | URTW_RX_FILTER_MCAST;
3916
3917 if (ic->ic_opmode == IEEE80211_M_MONITOR) {
3918 data = data | URTW_RX_FILTER_ICVERR;
3919 data = data | URTW_RX_FILTER_PWR;
3920 }
3921 if (sc->sc_crcmon == 1 && ic->ic_opmode == IEEE80211_M_MONITOR)
3922 data = data | URTW_RX_FILTER_CRCERR;
3923
3924 data = data &~ URTW_RX_FIFO_THRESHOLD_MASK;
3925 data = data | URTW_RX_FIFO_THRESHOLD_NONE |
3926 URTW_RX_AUTORESETPHY;
3927 data = data &~ URTW_MAX_RX_DMA_MASK;
3928 data = data | URTW_MAX_RX_DMA_2048 | URTW_RCR_ONLYERLPKT;
3929 }
3930
3931 /* XXX allmulti should not be checked here... */
3932 if (ic->ic_opmode == IEEE80211_M_MONITOR ||
3933 ic->ic_promisc > 0 || ic->ic_allmulti > 0) {
3934 data = data | URTW_RX_FILTER_CTL;
3935 data = data | URTW_RX_FILTER_ALLMAC;
3936 } else {
3937 data = data | URTW_RX_FILTER_NICMAC;
3938 data = data | URTW_RX_CHECK_BSSID;
3939 }
3940
3941 urtw_write32_m(sc, URTW_RX, data);
3942 fail:
3943 return (error);
3944 }
3945
3946 static struct mbuf *
urtw_rxeof(struct usb_xfer * xfer,struct urtw_data * data,int * rssi_p,int8_t * nf_p)3947 urtw_rxeof(struct usb_xfer *xfer, struct urtw_data *data, int *rssi_p,
3948 int8_t *nf_p)
3949 {
3950 int actlen, flen, rssi;
3951 struct ieee80211_frame *wh;
3952 struct mbuf *m, *mnew;
3953 struct urtw_softc *sc = data->sc;
3954 struct ieee80211com *ic = &sc->sc_ic;
3955 uint8_t noise = 0, rate;
3956 uint64_t mactime;
3957
3958 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
3959
3960 if (sc->sc_flags & URTW_RTL8187B) {
3961 struct urtw_8187b_rxhdr *rx;
3962
3963 if (actlen < sizeof(*rx) + IEEE80211_ACK_LEN)
3964 goto fail;
3965
3966 rx = (struct urtw_8187b_rxhdr *)(data->buf +
3967 (actlen - (sizeof(struct urtw_8187b_rxhdr))));
3968 flen = le32toh(rx->flag) & 0xfff;
3969 if (flen > actlen - sizeof(*rx))
3970 goto fail;
3971
3972 rate = (le32toh(rx->flag) >> URTW_RX_FLAG_RXRATE_SHIFT) & 0xf;
3973 /* XXX correct? */
3974 rssi = rx->rssi & URTW_RX_RSSI_MASK;
3975 noise = rx->noise;
3976
3977 if (ieee80211_radiotap_active(ic))
3978 mactime = rx->mactime;
3979 } else {
3980 struct urtw_8187l_rxhdr *rx;
3981
3982 if (actlen < sizeof(*rx) + IEEE80211_ACK_LEN)
3983 goto fail;
3984
3985 rx = (struct urtw_8187l_rxhdr *)(data->buf +
3986 (actlen - (sizeof(struct urtw_8187l_rxhdr))));
3987 flen = le32toh(rx->flag) & 0xfff;
3988 if (flen > actlen - sizeof(*rx))
3989 goto fail;
3990
3991 rate = (le32toh(rx->flag) >> URTW_RX_FLAG_RXRATE_SHIFT) & 0xf;
3992 /* XXX correct? */
3993 rssi = rx->rssi & URTW_RX_8187L_RSSI_MASK;
3994 noise = rx->noise;
3995
3996 if (ieee80211_radiotap_active(ic))
3997 mactime = rx->mactime;
3998 }
3999
4000 if (flen < IEEE80211_ACK_LEN)
4001 goto fail;
4002
4003 mnew = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
4004 if (mnew == NULL)
4005 goto fail;
4006
4007 m = data->m;
4008 data->m = mnew;
4009 data->buf = mtod(mnew, uint8_t *);
4010
4011 /* finalize mbuf */
4012 m->m_pkthdr.len = m->m_len = flen - IEEE80211_CRC_LEN;
4013
4014 if (ieee80211_radiotap_active(ic)) {
4015 struct urtw_rx_radiotap_header *tap = &sc->sc_rxtap;
4016
4017 tap->wr_tsf = mactime;
4018 tap->wr_flags = 0;
4019 tap->wr_dbm_antsignal = (int8_t)rssi;
4020 }
4021
4022 wh = mtod(m, struct ieee80211_frame *);
4023 if (IEEE80211_IS_DATA(wh))
4024 sc->sc_currate = (rate > 0) ? rate : sc->sc_currate;
4025
4026 *rssi_p = rssi;
4027 *nf_p = noise; /* XXX correct? */
4028
4029 return (m);
4030
4031 fail:
4032 counter_u64_add(ic->ic_ierrors, 1);
4033 return (NULL);
4034 }
4035
4036 static void
urtw_bulk_rx_callback(struct usb_xfer * xfer,usb_error_t error)4037 urtw_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error)
4038 {
4039 struct urtw_softc *sc = usbd_xfer_softc(xfer);
4040 struct ieee80211com *ic = &sc->sc_ic;
4041 struct ieee80211_node *ni;
4042 struct mbuf *m = NULL;
4043 struct urtw_data *data;
4044 int8_t nf = -95;
4045 int rssi = 1;
4046
4047 URTW_ASSERT_LOCKED(sc);
4048
4049 switch (USB_GET_STATE(xfer)) {
4050 case USB_ST_TRANSFERRED:
4051 data = STAILQ_FIRST(&sc->sc_rx_active);
4052 if (data == NULL)
4053 goto setup;
4054 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next);
4055 m = urtw_rxeof(xfer, data, &rssi, &nf);
4056 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next);
4057 /* FALLTHROUGH */
4058 case USB_ST_SETUP:
4059 setup:
4060 data = STAILQ_FIRST(&sc->sc_rx_inactive);
4061 if (data == NULL) {
4062 KASSERT(m == NULL, ("mbuf isn't NULL"));
4063 return;
4064 }
4065 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next);
4066 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next);
4067 usbd_xfer_set_frame_data(xfer, 0, data->buf,
4068 usbd_xfer_max_len(xfer));
4069 usbd_transfer_submit(xfer);
4070
4071 /*
4072 * To avoid LOR we should unlock our private mutex here to call
4073 * ieee80211_input() because here is at the end of a USB
4074 * callback and safe to unlock.
4075 */
4076 URTW_UNLOCK(sc);
4077 if (m != NULL) {
4078 if (m->m_pkthdr.len >=
4079 sizeof(struct ieee80211_frame_min)) {
4080 ni = ieee80211_find_rxnode(ic,
4081 mtod(m, struct ieee80211_frame_min *));
4082 } else
4083 ni = NULL;
4084
4085 if (ni != NULL) {
4086 (void) ieee80211_input(ni, m, rssi, nf);
4087 /* node is no longer needed */
4088 ieee80211_free_node(ni);
4089 } else
4090 (void) ieee80211_input_all(ic, m, rssi, nf);
4091 m = NULL;
4092 }
4093 URTW_LOCK(sc);
4094 break;
4095 default:
4096 /* needs it to the inactive queue due to a error. */
4097 data = STAILQ_FIRST(&sc->sc_rx_active);
4098 if (data != NULL) {
4099 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next);
4100 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next);
4101 }
4102 if (error != USB_ERR_CANCELLED) {
4103 usbd_xfer_set_stall(xfer);
4104 counter_u64_add(ic->ic_ierrors, 1);
4105 goto setup;
4106 }
4107 break;
4108 }
4109 }
4110
4111 #define URTW_STATUS_TYPE_TXCLOSE 1
4112 #define URTW_STATUS_TYPE_BEACON_INTR 0
4113
4114 static void
urtw_txstatus_eof(struct usb_xfer * xfer)4115 urtw_txstatus_eof(struct usb_xfer *xfer)
4116 {
4117 struct urtw_softc *sc = usbd_xfer_softc(xfer);
4118 struct ieee80211com *ic = &sc->sc_ic;
4119 int actlen, type, pktretry;
4120 uint64_t val;
4121
4122 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
4123
4124 if (actlen != sizeof(uint64_t))
4125 return;
4126
4127 val = le64toh(sc->sc_txstatus);
4128 type = (val >> 30) & 0x3;
4129 if (type == URTW_STATUS_TYPE_TXCLOSE) {
4130 pktretry = val & 0xff;
4131 if (pktretry == URTW_TX_MAXRETRY)
4132 counter_u64_add(ic->ic_oerrors, 1);
4133 DPRINTF(sc, URTW_DEBUG_TXSTATUS, "pktretry %d seq %#x\n",
4134 pktretry, (val >> 16) & 0xff);
4135 }
4136 }
4137
4138 static void
urtw_bulk_tx_status_callback(struct usb_xfer * xfer,usb_error_t error)4139 urtw_bulk_tx_status_callback(struct usb_xfer *xfer, usb_error_t error)
4140 {
4141 struct urtw_softc *sc = usbd_xfer_softc(xfer);
4142 struct ieee80211com *ic = &sc->sc_ic;
4143 void *dma_buf = usbd_xfer_get_frame_buffer(xfer, 0);
4144
4145 URTW_ASSERT_LOCKED(sc);
4146
4147 switch (USB_GET_STATE(xfer)) {
4148 case USB_ST_TRANSFERRED:
4149 urtw_txstatus_eof(xfer);
4150 /* FALLTHROUGH */
4151 case USB_ST_SETUP:
4152 setup:
4153 memcpy(dma_buf, &sc->sc_txstatus, sizeof(uint64_t));
4154 usbd_xfer_set_frame_len(xfer, 0, sizeof(uint64_t));
4155 usbd_transfer_submit(xfer);
4156 break;
4157 default:
4158 if (error != USB_ERR_CANCELLED) {
4159 usbd_xfer_set_stall(xfer);
4160 counter_u64_add(ic->ic_ierrors, 1);
4161 goto setup;
4162 }
4163 break;
4164 }
4165 }
4166
4167 static void
urtw_txeof(struct usb_xfer * xfer,struct urtw_data * data)4168 urtw_txeof(struct usb_xfer *xfer, struct urtw_data *data)
4169 {
4170 struct urtw_softc *sc = usbd_xfer_softc(xfer);
4171
4172 URTW_ASSERT_LOCKED(sc);
4173
4174 if (data->m) {
4175 /* XXX status? */
4176 ieee80211_tx_complete(data->ni, data->m, 0);
4177 data->m = NULL;
4178 data->ni = NULL;
4179 }
4180 sc->sc_txtimer = 0;
4181 }
4182
4183 static void
urtw_bulk_tx_callback(struct usb_xfer * xfer,usb_error_t error)4184 urtw_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error)
4185 {
4186 struct urtw_softc *sc = usbd_xfer_softc(xfer);
4187 struct urtw_data *data;
4188
4189 URTW_ASSERT_LOCKED(sc);
4190
4191 switch (USB_GET_STATE(xfer)) {
4192 case USB_ST_TRANSFERRED:
4193 data = STAILQ_FIRST(&sc->sc_tx_active);
4194 if (data == NULL)
4195 goto setup;
4196 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next);
4197 urtw_txeof(xfer, data);
4198 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next);
4199 /* FALLTHROUGH */
4200 case USB_ST_SETUP:
4201 setup:
4202 data = STAILQ_FIRST(&sc->sc_tx_pending);
4203 if (data == NULL) {
4204 DPRINTF(sc, URTW_DEBUG_XMIT,
4205 "%s: empty pending queue\n", __func__);
4206 return;
4207 }
4208 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next);
4209 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next);
4210
4211 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen);
4212 usbd_transfer_submit(xfer);
4213
4214 urtw_start(sc);
4215 break;
4216 default:
4217 data = STAILQ_FIRST(&sc->sc_tx_active);
4218 if (data == NULL)
4219 goto setup;
4220 if (data->ni != NULL) {
4221 if_inc_counter(data->ni->ni_vap->iv_ifp,
4222 IFCOUNTER_OERRORS, 1);
4223 ieee80211_free_node(data->ni);
4224 data->ni = NULL;
4225 }
4226 if (error != USB_ERR_CANCELLED) {
4227 usbd_xfer_set_stall(xfer);
4228 goto setup;
4229 }
4230 break;
4231 }
4232 }
4233
4234 static struct urtw_data *
_urtw_getbuf(struct urtw_softc * sc)4235 _urtw_getbuf(struct urtw_softc *sc)
4236 {
4237 struct urtw_data *bf;
4238
4239 bf = STAILQ_FIRST(&sc->sc_tx_inactive);
4240 if (bf != NULL)
4241 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next);
4242 else
4243 bf = NULL;
4244 if (bf == NULL)
4245 DPRINTF(sc, URTW_DEBUG_XMIT, "%s: %s\n", __func__,
4246 "out of xmit buffers");
4247 return (bf);
4248 }
4249
4250 static struct urtw_data *
urtw_getbuf(struct urtw_softc * sc)4251 urtw_getbuf(struct urtw_softc *sc)
4252 {
4253 struct urtw_data *bf;
4254
4255 URTW_ASSERT_LOCKED(sc);
4256
4257 bf = _urtw_getbuf(sc);
4258 if (bf == NULL)
4259 DPRINTF(sc, URTW_DEBUG_XMIT, "%s: stop queue\n", __func__);
4260 return (bf);
4261 }
4262
4263 static int
urtw_isbmode(uint16_t rate)4264 urtw_isbmode(uint16_t rate)
4265 {
4266
4267 return ((rate <= 22 && rate != 12 && rate != 18) ||
4268 rate == 44) ? (1) : (0);
4269 }
4270
4271 static uint16_t
urtw_rate2dbps(uint16_t rate)4272 urtw_rate2dbps(uint16_t rate)
4273 {
4274
4275 switch(rate) {
4276 case 12:
4277 case 18:
4278 case 24:
4279 case 36:
4280 case 48:
4281 case 72:
4282 case 96:
4283 case 108:
4284 return (rate * 2);
4285 default:
4286 break;
4287 }
4288 return (24);
4289 }
4290
4291 static int
urtw_compute_txtime(uint16_t framelen,uint16_t rate,uint8_t ismgt,uint8_t isshort)4292 urtw_compute_txtime(uint16_t framelen, uint16_t rate,
4293 uint8_t ismgt, uint8_t isshort)
4294 {
4295 uint16_t ceiling, frametime, n_dbps;
4296
4297 if (urtw_isbmode(rate)) {
4298 if (ismgt || !isshort || rate == 2)
4299 frametime = (uint16_t)(144 + 48 +
4300 (framelen * 8 / (rate / 2)));
4301 else
4302 frametime = (uint16_t)(72 + 24 +
4303 (framelen * 8 / (rate / 2)));
4304 if ((framelen * 8 % (rate / 2)) != 0)
4305 frametime++;
4306 } else {
4307 n_dbps = urtw_rate2dbps(rate);
4308 ceiling = (16 + 8 * framelen + 6) / n_dbps
4309 + (((16 + 8 * framelen + 6) % n_dbps) ? 1 : 0);
4310 frametime = (uint16_t)(16 + 4 + 4 * ceiling + 6);
4311 }
4312 return (frametime);
4313 }
4314
4315 /*
4316 * Callback from the 802.11 layer to update the
4317 * slot time based on the current setting.
4318 */
4319 static void
urtw_updateslot(struct ieee80211com * ic)4320 urtw_updateslot(struct ieee80211com *ic)
4321 {
4322 struct urtw_softc *sc = ic->ic_softc;
4323
4324 ieee80211_runtask(ic, &sc->sc_updateslot_task);
4325 }
4326
4327 static void
urtw_updateslottask(void * arg,int pending)4328 urtw_updateslottask(void *arg, int pending)
4329 {
4330 struct urtw_softc *sc = arg;
4331 struct ieee80211com *ic = &sc->sc_ic;
4332 int error;
4333
4334 URTW_LOCK(sc);
4335 if ((sc->sc_flags & URTW_RUNNING) == 0) {
4336 URTW_UNLOCK(sc);
4337 return;
4338 }
4339 if (sc->sc_flags & URTW_RTL8187B) {
4340 urtw_write8_m(sc, URTW_SIFS, 0x22);
4341 if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan))
4342 urtw_write8_m(sc, URTW_SLOT, IEEE80211_DUR_SHSLOT);
4343 else
4344 urtw_write8_m(sc, URTW_SLOT, IEEE80211_DUR_SLOT);
4345 urtw_write8_m(sc, URTW_8187B_EIFS, 0x5b);
4346 urtw_write8_m(sc, URTW_CARRIER_SCOUNT, 0x5b);
4347 } else {
4348 urtw_write8_m(sc, URTW_SIFS, 0x22);
4349 if (sc->sc_state == IEEE80211_S_ASSOC &&
4350 ic->ic_flags & IEEE80211_F_SHSLOT)
4351 urtw_write8_m(sc, URTW_SLOT, IEEE80211_DUR_SHSLOT);
4352 else
4353 urtw_write8_m(sc, URTW_SLOT, IEEE80211_DUR_SLOT);
4354 if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) {
4355 urtw_write8_m(sc, URTW_DIFS, 0x14);
4356 urtw_write8_m(sc, URTW_EIFS, 0x5b - 0x14);
4357 urtw_write8_m(sc, URTW_CW_VAL, 0x73);
4358 } else {
4359 urtw_write8_m(sc, URTW_DIFS, 0x24);
4360 urtw_write8_m(sc, URTW_EIFS, 0x5b - 0x24);
4361 urtw_write8_m(sc, URTW_CW_VAL, 0xa5);
4362 }
4363 }
4364 fail:
4365 URTW_UNLOCK(sc);
4366 }
4367
4368 static void
urtw_sysctl_node(struct urtw_softc * sc)4369 urtw_sysctl_node(struct urtw_softc *sc)
4370 {
4371 #define URTW_SYSCTL_STAT_ADD32(c, h, n, p, d) \
4372 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
4373 struct sysctl_ctx_list *ctx;
4374 struct sysctl_oid_list *child, *parent;
4375 struct sysctl_oid *tree;
4376 struct urtw_stats *stats = &sc->sc_stats;
4377
4378 ctx = device_get_sysctl_ctx(sc->sc_dev);
4379 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->sc_dev));
4380
4381 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats",
4382 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "URTW statistics");
4383 parent = SYSCTL_CHILDREN(tree);
4384
4385 /* Tx statistics. */
4386 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx",
4387 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics");
4388 child = SYSCTL_CHILDREN(tree);
4389 URTW_SYSCTL_STAT_ADD32(ctx, child, "1m", &stats->txrates[0],
4390 "1 Mbit/s");
4391 URTW_SYSCTL_STAT_ADD32(ctx, child, "2m", &stats->txrates[1],
4392 "2 Mbit/s");
4393 URTW_SYSCTL_STAT_ADD32(ctx, child, "5.5m", &stats->txrates[2],
4394 "5.5 Mbit/s");
4395 URTW_SYSCTL_STAT_ADD32(ctx, child, "6m", &stats->txrates[4],
4396 "6 Mbit/s");
4397 URTW_SYSCTL_STAT_ADD32(ctx, child, "9m", &stats->txrates[5],
4398 "9 Mbit/s");
4399 URTW_SYSCTL_STAT_ADD32(ctx, child, "11m", &stats->txrates[3],
4400 "11 Mbit/s");
4401 URTW_SYSCTL_STAT_ADD32(ctx, child, "12m", &stats->txrates[6],
4402 "12 Mbit/s");
4403 URTW_SYSCTL_STAT_ADD32(ctx, child, "18m", &stats->txrates[7],
4404 "18 Mbit/s");
4405 URTW_SYSCTL_STAT_ADD32(ctx, child, "24m", &stats->txrates[8],
4406 "24 Mbit/s");
4407 URTW_SYSCTL_STAT_ADD32(ctx, child, "36m", &stats->txrates[9],
4408 "36 Mbit/s");
4409 URTW_SYSCTL_STAT_ADD32(ctx, child, "48m", &stats->txrates[10],
4410 "48 Mbit/s");
4411 URTW_SYSCTL_STAT_ADD32(ctx, child, "54m", &stats->txrates[11],
4412 "54 Mbit/s");
4413 #undef URTW_SYSCTL_STAT_ADD32
4414 }
4415
4416 static device_method_t urtw_methods[] = {
4417 DEVMETHOD(device_probe, urtw_match),
4418 DEVMETHOD(device_attach, urtw_attach),
4419 DEVMETHOD(device_detach, urtw_detach),
4420 DEVMETHOD_END
4421 };
4422
4423 static driver_t urtw_driver = {
4424 .name = "urtw",
4425 .methods = urtw_methods,
4426 .size = sizeof(struct urtw_softc)
4427 };
4428
4429 DRIVER_MODULE(urtw, uhub, urtw_driver, NULL, NULL);
4430 MODULE_DEPEND(urtw, wlan, 1, 1, 1);
4431 MODULE_DEPEND(urtw, usb, 1, 1, 1);
4432 MODULE_VERSION(urtw, 1);
4433 USB_PNP_HOST_INFO(urtw_devs);
4434