1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org>
5 * Copyright (c) 2017 Marius Strobl <marius@FreeBSD.org>
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/bus.h>
33 #include <sys/callout.h>
34 #include <sys/conf.h>
35 #include <sys/kernel.h>
36 #include <sys/kobj.h>
37 #include <sys/libkern.h>
38 #include <sys/lock.h>
39 #include <sys/malloc.h>
40 #include <sys/module.h>
41 #include <sys/mutex.h>
42 #include <sys/resource.h>
43 #include <sys/rman.h>
44 #include <sys/sysctl.h>
45 #include <sys/taskqueue.h>
46 #include <sys/sbuf.h>
47
48 #include <machine/bus.h>
49 #include <machine/resource.h>
50 #include <machine/stdarg.h>
51
52 #include <dev/mmc/bridge.h>
53 #include <dev/mmc/mmcreg.h>
54 #include <dev/mmc/mmcbrvar.h>
55
56 #include <dev/sdhci/sdhci.h>
57
58 #include <cam/cam.h>
59 #include <cam/cam_ccb.h>
60 #include <cam/cam_debug.h>
61 #include <cam/cam_sim.h>
62 #include <cam/cam_xpt_sim.h>
63
64 #include "mmcbr_if.h"
65 #include "sdhci_if.h"
66
67 #include "opt_mmccam.h"
68
69 SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
70 "sdhci driver");
71
72 static int sdhci_debug = 0;
73 SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RWTUN, &sdhci_debug, 0,
74 "Debug level");
75 u_int sdhci_quirk_clear = 0;
76 SYSCTL_INT(_hw_sdhci, OID_AUTO, quirk_clear, CTLFLAG_RWTUN, &sdhci_quirk_clear,
77 0, "Mask of quirks to clear");
78 u_int sdhci_quirk_set = 0;
79 SYSCTL_INT(_hw_sdhci, OID_AUTO, quirk_set, CTLFLAG_RWTUN, &sdhci_quirk_set, 0,
80 "Mask of quirks to set");
81
82 #define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off))
83 #define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off))
84 #define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off))
85 #define RD_MULTI_4(slot, off, ptr, count) \
86 SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
87
88 #define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val))
89 #define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val))
90 #define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val))
91 #define WR_MULTI_4(slot, off, ptr, count) \
92 SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
93
94 static void sdhci_acmd_irq(struct sdhci_slot *slot, uint16_t acmd_err);
95 static void sdhci_card_poll(void *arg);
96 static void sdhci_card_task(void *arg, int pending);
97 static void sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask);
98 static void sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask);
99 static int sdhci_exec_tuning(struct sdhci_slot *slot, bool reset);
100 static void sdhci_handle_card_present_locked(struct sdhci_slot *slot,
101 bool is_present);
102 static void sdhci_finish_command(struct sdhci_slot *slot);
103 static void sdhci_init(struct sdhci_slot *slot);
104 static void sdhci_read_block_pio(struct sdhci_slot *slot);
105 static void sdhci_req_done(struct sdhci_slot *slot);
106 static void sdhci_req_wakeup(struct mmc_request *req);
107 static void sdhci_retune(void *arg);
108 static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock);
109 static void sdhci_set_power(struct sdhci_slot *slot, u_char power);
110 static void sdhci_set_transfer_mode(struct sdhci_slot *slot,
111 const struct mmc_data *data);
112 static void sdhci_start(struct sdhci_slot *slot);
113 static void sdhci_timeout(void *arg);
114 static void sdhci_start_command(struct sdhci_slot *slot,
115 struct mmc_command *cmd);
116 static void sdhci_start_data(struct sdhci_slot *slot,
117 const struct mmc_data *data);
118 static void sdhci_write_block_pio(struct sdhci_slot *slot);
119 static void sdhci_transfer_pio(struct sdhci_slot *slot);
120
121 #ifdef MMCCAM
122 /* CAM-related */
123 static void sdhci_cam_action(struct cam_sim *sim, union ccb *ccb);
124 static int sdhci_cam_get_possible_host_clock(const struct sdhci_slot *slot,
125 int proposed_clock);
126 static void sdhci_cam_poll(struct cam_sim *sim);
127 static int sdhci_cam_request(struct sdhci_slot *slot, union ccb *ccb);
128 static int sdhci_cam_settran_settings(struct sdhci_slot *slot, union ccb *ccb);
129 static int sdhci_cam_update_ios(struct sdhci_slot *slot);
130 #endif
131
132 /* helper routines */
133 static int sdhci_dma_alloc(struct sdhci_slot *slot);
134 static void sdhci_dma_free(struct sdhci_slot *slot);
135 static void sdhci_dumpcaps(struct sdhci_slot *slot);
136 static void sdhci_dumpcaps_buf(struct sdhci_slot *slot, struct sbuf *s);
137 static void sdhci_dumpregs(struct sdhci_slot *slot);
138 static void sdhci_dumpregs_buf(struct sdhci_slot *slot, struct sbuf *s);
139 static int sdhci_syctl_dumpcaps(SYSCTL_HANDLER_ARGS);
140 static int sdhci_syctl_dumpregs(SYSCTL_HANDLER_ARGS);
141 static void sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs,
142 int error);
143 static int slot_printf(const struct sdhci_slot *slot, const char * fmt, ...)
144 __printflike(2, 3);
145 static int slot_sprintf(const struct sdhci_slot *slot, struct sbuf *s,
146 const char * fmt, ...) __printflike(3, 4);
147 static uint32_t sdhci_tuning_intmask(const struct sdhci_slot *slot);
148
149 #define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx)
150 #define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx)
151 #define SDHCI_LOCK_INIT(_slot) \
152 mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF)
153 #define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx);
154 #define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED);
155 #define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED);
156
157 #define SDHCI_DEFAULT_MAX_FREQ 50
158
159 #define SDHCI_200_MAX_DIVIDER 256
160 #define SDHCI_300_MAX_DIVIDER 2046
161
162 #define SDHCI_CARD_PRESENT_TICKS (hz / 5)
163 #define SDHCI_INSERT_DELAY_TICKS (hz / 2)
164
165 /*
166 * Broadcom BCM577xx Controller Constants
167 */
168 /* Maximum divider supported by the default clock source. */
169 #define BCM577XX_DEFAULT_MAX_DIVIDER 256
170 /* Alternative clock's base frequency. */
171 #define BCM577XX_ALT_CLOCK_BASE 63000000
172
173 #define BCM577XX_HOST_CONTROL 0x198
174 #define BCM577XX_CTRL_CLKSEL_MASK 0xFFFFCFFF
175 #define BCM577XX_CTRL_CLKSEL_SHIFT 12
176 #define BCM577XX_CTRL_CLKSEL_DEFAULT 0x0
177 #define BCM577XX_CTRL_CLKSEL_64MHZ 0x3
178
179 static void
sdhci_getaddr(void * arg,bus_dma_segment_t * segs,int nsegs,int error)180 sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
181 {
182
183 if (error != 0) {
184 printf("getaddr: error %d\n", error);
185 return;
186 }
187 *(bus_addr_t *)arg = segs[0].ds_addr;
188 }
189
190 static int
slot_printf(const struct sdhci_slot * slot,const char * fmt,...)191 slot_printf(const struct sdhci_slot *slot, const char * fmt, ...)
192 {
193 char buf[128];
194 va_list ap;
195 int retval;
196
197 /*
198 * Make sure we print a single line all together rather than in two
199 * halves to avoid console gibberish bingo.
200 */
201 va_start(ap, fmt);
202 retval = vsnprintf(buf, sizeof(buf), fmt, ap);
203 va_end(ap);
204
205 retval += printf("%s-slot%d: %s",
206 device_get_nameunit(slot->bus), slot->num, buf);
207 return (retval);
208 }
209
210 static int
slot_sprintf(const struct sdhci_slot * slot,struct sbuf * s,const char * fmt,...)211 slot_sprintf(const struct sdhci_slot *slot, struct sbuf *s,
212 const char * fmt, ...)
213 {
214 va_list ap;
215 int retval;
216
217 retval = sbuf_printf(s, "%s-slot%d: ", device_get_nameunit(slot->bus), slot->num);
218
219 va_start(ap, fmt);
220 retval += sbuf_vprintf(s, fmt, ap);
221 va_end(ap);
222
223 return (retval);
224 }
225
226 static void
sdhci_dumpregs_buf(struct sdhci_slot * slot,struct sbuf * s)227 sdhci_dumpregs_buf(struct sdhci_slot *slot, struct sbuf *s)
228 {
229 slot_sprintf(slot, s, "============== REGISTER DUMP ==============\n");
230
231 slot_sprintf(slot, s, "Sys addr: 0x%08x | Version: 0x%08x\n",
232 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION));
233 slot_sprintf(slot, s, "Blk size: 0x%08x | Blk cnt: 0x%08x\n",
234 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT));
235 slot_sprintf(slot, s, "Argument: 0x%08x | Trn mode: 0x%08x\n",
236 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE));
237 slot_sprintf(slot, s, "Present: 0x%08x | Host ctl: 0x%08x\n",
238 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL));
239 slot_sprintf(slot, s, "Power: 0x%08x | Blk gap: 0x%08x\n",
240 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL));
241 slot_sprintf(slot, s, "Wake-up: 0x%08x | Clock: 0x%08x\n",
242 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL));
243 slot_sprintf(slot, s, "Timeout: 0x%08x | Int stat: 0x%08x\n",
244 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS));
245 slot_sprintf(slot, s, "Int enab: 0x%08x | Sig enab: 0x%08x\n",
246 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE));
247 slot_sprintf(slot, s, "AC12 err: 0x%08x | Host ctl2:0x%08x\n",
248 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_HOST_CONTROL2));
249 slot_sprintf(slot, s, "Caps: 0x%08x | Caps2: 0x%08x\n",
250 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_CAPABILITIES2));
251 slot_sprintf(slot, s, "Max curr: 0x%08x | ADMA err: 0x%08x\n",
252 RD4(slot, SDHCI_MAX_CURRENT), RD1(slot, SDHCI_ADMA_ERR));
253 slot_sprintf(slot, s, "ADMA addr:0x%08x | Slot int: 0x%08x\n",
254 RD4(slot, SDHCI_ADMA_ADDRESS_LO), RD2(slot, SDHCI_SLOT_INT_STATUS));
255
256 slot_sprintf(slot, s, "===========================================\n");
257 }
258
259 static void
sdhci_dumpregs(struct sdhci_slot * slot)260 sdhci_dumpregs(struct sdhci_slot *slot)
261 {
262 struct sbuf s;
263
264 if (sbuf_new(&s, NULL, 1024, SBUF_NOWAIT | SBUF_AUTOEXTEND) == NULL) {
265 slot_printf(slot, "sdhci_dumpregs: Failed to allocate memory for sbuf\n");
266 return;
267 }
268
269 sbuf_set_drain(&s, &sbuf_printf_drain, NULL);
270 sdhci_dumpregs_buf(slot, &s);
271 sbuf_finish(&s);
272 sbuf_delete(&s);
273 }
274
275 static int
sdhci_syctl_dumpregs(SYSCTL_HANDLER_ARGS)276 sdhci_syctl_dumpregs(SYSCTL_HANDLER_ARGS)
277 {
278 struct sdhci_slot *slot = arg1;
279 struct sbuf s;
280
281 sbuf_new_for_sysctl(&s, NULL, 1024, req);
282 sbuf_putc(&s, '\n');
283 sdhci_dumpregs_buf(slot, &s);
284 sbuf_finish(&s);
285 sbuf_delete(&s);
286
287 return (0);
288 }
289
290 static void
sdhci_dumpcaps_buf(struct sdhci_slot * slot,struct sbuf * s)291 sdhci_dumpcaps_buf(struct sdhci_slot *slot, struct sbuf *s)
292 {
293 int host_caps = slot->host.caps;
294 int caps = slot->caps;
295
296 slot_sprintf(slot, s,
297 "%uMHz%s %s VDD:%s%s%s VCCQ: 3.3V%s%s DRV: B%s%s%s %s %s\n",
298 slot->max_clk / 1000000,
299 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "",
300 (host_caps & MMC_CAP_8_BIT_DATA) ? "8bits" :
301 ((host_caps & MMC_CAP_4_BIT_DATA) ? "4bits" : "1bit"),
302 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "",
303 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "",
304 ((caps & SDHCI_CAN_VDD_180) &&
305 (slot->opt & SDHCI_SLOT_EMBEDDED)) ? " 1.8V" : "",
306 (host_caps & MMC_CAP_SIGNALING_180) ? " 1.8V" : "",
307 (host_caps & MMC_CAP_SIGNALING_120) ? " 1.2V" : "",
308 (host_caps & MMC_CAP_DRIVER_TYPE_A) ? "A" : "",
309 (host_caps & MMC_CAP_DRIVER_TYPE_C) ? "C" : "",
310 (host_caps & MMC_CAP_DRIVER_TYPE_D) ? "D" : "",
311 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO",
312 (slot->opt & SDHCI_SLOT_EMBEDDED) ? "embedded" :
313 (slot->opt & SDHCI_NON_REMOVABLE) ? "non-removable" :
314 "removable");
315 if (host_caps & (MMC_CAP_MMC_DDR52 | MMC_CAP_MMC_HS200 |
316 MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE))
317 slot_sprintf(slot, s, "eMMC:%s%s%s%s\n",
318 (host_caps & MMC_CAP_MMC_DDR52) ? " DDR52" : "",
319 (host_caps & MMC_CAP_MMC_HS200) ? " HS200" : "",
320 (host_caps & MMC_CAP_MMC_HS400) ? " HS400" : "",
321 ((host_caps &
322 (MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) ==
323 (MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) ?
324 " HS400ES" : "");
325 if (host_caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
326 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104))
327 slot_sprintf(slot, s, "UHS-I:%s%s%s%s%s\n",
328 (host_caps & MMC_CAP_UHS_SDR12) ? " SDR12" : "",
329 (host_caps & MMC_CAP_UHS_SDR25) ? " SDR25" : "",
330 (host_caps & MMC_CAP_UHS_SDR50) ? " SDR50" : "",
331 (host_caps & MMC_CAP_UHS_SDR104) ? " SDR104" : "",
332 (host_caps & MMC_CAP_UHS_DDR50) ? " DDR50" : "");
333 if (slot->opt & SDHCI_TUNING_SUPPORTED)
334 slot_sprintf(slot, s,
335 "Re-tuning count %d secs, mode %d\n",
336 slot->retune_count, slot->retune_mode + 1);
337 }
338
339 static void
sdhci_dumpcaps(struct sdhci_slot * slot)340 sdhci_dumpcaps(struct sdhci_slot *slot)
341 {
342 struct sbuf s;
343
344 if (sbuf_new(&s, NULL, 1024, SBUF_NOWAIT | SBUF_AUTOEXTEND) == NULL) {
345 slot_printf(slot, "sdhci_dumpcaps: Failed to allocate memory for sbuf\n");
346 return;
347 }
348
349 sbuf_set_drain(&s, &sbuf_printf_drain, NULL);
350 sdhci_dumpcaps_buf(slot, &s);
351 sbuf_finish(&s);
352 sbuf_delete(&s);
353 }
354
355 static int
sdhci_syctl_dumpcaps(SYSCTL_HANDLER_ARGS)356 sdhci_syctl_dumpcaps(SYSCTL_HANDLER_ARGS)
357 {
358 struct sdhci_slot *slot = arg1;
359 struct sbuf s;
360
361 sbuf_new_for_sysctl(&s, NULL, 1024, req);
362 sbuf_putc(&s, '\n');
363 sdhci_dumpcaps_buf(slot, &s);
364 sbuf_finish(&s);
365 sbuf_delete(&s);
366
367 return (0);
368 }
369
370 static uint32_t
sdhci_tuning_intmask(const struct sdhci_slot * slot)371 sdhci_tuning_intmask(const struct sdhci_slot *slot)
372 {
373 uint32_t intmask;
374
375 intmask = 0;
376 if (slot->opt & SDHCI_TUNING_ENABLED) {
377 intmask |= SDHCI_INT_TUNEERR;
378 if (slot->retune_mode == SDHCI_RETUNE_MODE_2 ||
379 slot->retune_mode == SDHCI_RETUNE_MODE_3)
380 intmask |= SDHCI_INT_RETUNE;
381 }
382 return (intmask);
383 }
384
385 static void
sdhci_init(struct sdhci_slot * slot)386 sdhci_init(struct sdhci_slot *slot)
387 {
388
389 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_ALL);
390
391 /* Enable interrupts. */
392 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
393 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
394 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
395 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
396 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE |
397 SDHCI_INT_ACMD12ERR;
398
399 if (!(slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) &&
400 !(slot->opt & SDHCI_NON_REMOVABLE)) {
401 slot->intmask |= SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT;
402 }
403
404 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
405 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
406 }
407
408 static void
sdhci_set_clock(struct sdhci_slot * slot,uint32_t clock)409 sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock)
410 {
411 uint32_t clk_base;
412 uint32_t clk_sel;
413 uint32_t res;
414 uint16_t clk;
415 uint16_t div;
416 int timeout;
417
418 if (clock == slot->clock)
419 return;
420 clock = SDHCI_SET_CLOCK(slot->bus, slot, clock);
421 slot->clock = clock;
422
423 /* Turn off the clock. */
424 clk = RD2(slot, SDHCI_CLOCK_CONTROL);
425 WR2(slot, SDHCI_CLOCK_CONTROL, clk & ~SDHCI_CLOCK_CARD_EN);
426 /* If no clock requested - leave it so. */
427 if (clock == 0)
428 return;
429
430 /* Determine the clock base frequency */
431 clk_base = slot->max_clk;
432 if (slot->quirks & SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC) {
433 clk_sel = RD2(slot, BCM577XX_HOST_CONTROL) &
434 BCM577XX_CTRL_CLKSEL_MASK;
435
436 /*
437 * Select clock source appropriate for the requested frequency.
438 */
439 if ((clk_base / BCM577XX_DEFAULT_MAX_DIVIDER) > clock) {
440 clk_base = BCM577XX_ALT_CLOCK_BASE;
441 clk_sel |= (BCM577XX_CTRL_CLKSEL_64MHZ <<
442 BCM577XX_CTRL_CLKSEL_SHIFT);
443 } else {
444 clk_sel |= (BCM577XX_CTRL_CLKSEL_DEFAULT <<
445 BCM577XX_CTRL_CLKSEL_SHIFT);
446 }
447
448 WR2(slot, BCM577XX_HOST_CONTROL, clk_sel);
449 }
450
451 /* Recalculate timeout clock frequency based on the new sd clock. */
452 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
453 slot->timeout_clk = slot->clock / 1000;
454
455 if (slot->version < SDHCI_SPEC_300) {
456 /* Looking for highest freq <= clock. */
457 res = clk_base;
458 for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) {
459 if (res <= clock)
460 break;
461 res >>= 1;
462 }
463 /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */
464 div >>= 1;
465 } else {
466 /* Version 3.0 divisors are multiples of two up to 1023 * 2 */
467 if (clock >= clk_base)
468 div = 0;
469 else {
470 for (div = 2; div < SDHCI_300_MAX_DIVIDER; div += 2) {
471 if ((clk_base / div) <= clock)
472 break;
473 }
474 }
475 div >>= 1;
476 }
477
478 if (bootverbose || sdhci_debug)
479 slot_printf(slot, "Divider %d for freq %d (base %d)\n",
480 div, clock, clk_base);
481
482 /* Now we have got divider, set it. */
483 clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT;
484 clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK)
485 << SDHCI_DIVIDER_HI_SHIFT;
486
487 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
488 /* Enable clock. */
489 clk |= SDHCI_CLOCK_INT_EN;
490 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
491 /* Wait up to 10 ms until it stabilize. */
492 timeout = 10;
493 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL))
494 & SDHCI_CLOCK_INT_STABLE)) {
495 if (timeout == 0) {
496 slot_printf(slot,
497 "Internal clock never stabilised.\n");
498 sdhci_dumpregs(slot);
499 return;
500 }
501 timeout--;
502 DELAY(1000);
503 }
504 /* Pass clock signal to the bus. */
505 clk |= SDHCI_CLOCK_CARD_EN;
506 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
507 }
508
509 static void
sdhci_set_power(struct sdhci_slot * slot,u_char power)510 sdhci_set_power(struct sdhci_slot *slot, u_char power)
511 {
512 int i;
513 uint8_t pwr;
514
515 if (slot->power == power)
516 return;
517
518 slot->power = power;
519
520 /* Turn off the power. */
521 pwr = 0;
522 WR1(slot, SDHCI_POWER_CONTROL, pwr);
523 /* If power down requested - leave it so. */
524 if (power == 0)
525 return;
526 /* Set voltage. */
527 switch (1 << power) {
528 case MMC_OCR_LOW_VOLTAGE:
529 pwr |= SDHCI_POWER_180;
530 break;
531 case MMC_OCR_290_300:
532 case MMC_OCR_300_310:
533 pwr |= SDHCI_POWER_300;
534 break;
535 case MMC_OCR_320_330:
536 case MMC_OCR_330_340:
537 pwr |= SDHCI_POWER_330;
538 break;
539 }
540 WR1(slot, SDHCI_POWER_CONTROL, pwr);
541 /*
542 * Turn on VDD1 power. Note that at least some Intel controllers can
543 * fail to enable bus power on the first try after transiting from D3
544 * to D0, so we give them up to 2 ms.
545 */
546 pwr |= SDHCI_POWER_ON;
547 for (i = 0; i < 20; i++) {
548 WR1(slot, SDHCI_POWER_CONTROL, pwr);
549 if (RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON)
550 break;
551 DELAY(100);
552 }
553 if (!(RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON))
554 slot_printf(slot, "Bus power failed to enable\n");
555
556 if (slot->quirks & SDHCI_QUIRK_INTEL_POWER_UP_RESET) {
557 WR1(slot, SDHCI_POWER_CONTROL, pwr | 0x10);
558 DELAY(10);
559 WR1(slot, SDHCI_POWER_CONTROL, pwr);
560 DELAY(300);
561 }
562 }
563
564 static void
sdhci_read_block_pio(struct sdhci_slot * slot)565 sdhci_read_block_pio(struct sdhci_slot *slot)
566 {
567 uint32_t data;
568 char *buffer;
569 size_t left;
570
571 buffer = slot->curcmd->data->data;
572 buffer += slot->offset;
573 /* Transfer one block at a time. */
574 #ifdef MMCCAM
575 if (slot->curcmd->data->flags & MMC_DATA_BLOCK_SIZE)
576 left = min(slot->curcmd->data->block_size,
577 slot->curcmd->data->len - slot->offset);
578 else
579 #endif
580 left = min(512, slot->curcmd->data->len - slot->offset);
581 slot->offset += left;
582
583 /* If we are too fast, broken controllers return zeroes. */
584 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS)
585 DELAY(10);
586 /* Handle unaligned and aligned buffer cases. */
587 if ((intptr_t)buffer & 3) {
588 while (left > 3) {
589 data = RD4(slot, SDHCI_BUFFER);
590 buffer[0] = data;
591 buffer[1] = (data >> 8);
592 buffer[2] = (data >> 16);
593 buffer[3] = (data >> 24);
594 buffer += 4;
595 left -= 4;
596 }
597 } else {
598 RD_MULTI_4(slot, SDHCI_BUFFER,
599 (uint32_t *)buffer, left >> 2);
600 left &= 3;
601 }
602 /* Handle uneven size case. */
603 if (left > 0) {
604 data = RD4(slot, SDHCI_BUFFER);
605 while (left > 0) {
606 *(buffer++) = data;
607 data >>= 8;
608 left--;
609 }
610 }
611 }
612
613 static void
sdhci_write_block_pio(struct sdhci_slot * slot)614 sdhci_write_block_pio(struct sdhci_slot *slot)
615 {
616 uint32_t data = 0;
617 char *buffer;
618 size_t left;
619
620 buffer = slot->curcmd->data->data;
621 buffer += slot->offset;
622 /* Transfer one block at a time. */
623 #ifdef MMCCAM
624 if (slot->curcmd->data->flags & MMC_DATA_BLOCK_SIZE) {
625 left = min(slot->curcmd->data->block_size,
626 slot->curcmd->data->len - slot->offset);
627 } else
628 #endif
629 left = min(512, slot->curcmd->data->len - slot->offset);
630 slot->offset += left;
631
632 /* Handle unaligned and aligned buffer cases. */
633 if ((intptr_t)buffer & 3) {
634 while (left > 3) {
635 data = buffer[0] +
636 (buffer[1] << 8) +
637 (buffer[2] << 16) +
638 (buffer[3] << 24);
639 left -= 4;
640 buffer += 4;
641 WR4(slot, SDHCI_BUFFER, data);
642 }
643 } else {
644 WR_MULTI_4(slot, SDHCI_BUFFER,
645 (uint32_t *)buffer, left >> 2);
646 left &= 3;
647 }
648 /* Handle uneven size case. */
649 if (left > 0) {
650 while (left > 0) {
651 data <<= 8;
652 data += *(buffer++);
653 left--;
654 }
655 WR4(slot, SDHCI_BUFFER, data);
656 }
657 }
658
659 static void
sdhci_transfer_pio(struct sdhci_slot * slot)660 sdhci_transfer_pio(struct sdhci_slot *slot)
661 {
662
663 /* Read as many blocks as possible. */
664 if (slot->curcmd->data->flags & MMC_DATA_READ) {
665 while (RD4(slot, SDHCI_PRESENT_STATE) &
666 SDHCI_DATA_AVAILABLE) {
667 sdhci_read_block_pio(slot);
668 if (slot->offset >= slot->curcmd->data->len)
669 break;
670 }
671 } else {
672 while (RD4(slot, SDHCI_PRESENT_STATE) &
673 SDHCI_SPACE_AVAILABLE) {
674 sdhci_write_block_pio(slot);
675 if (slot->offset >= slot->curcmd->data->len)
676 break;
677 }
678 }
679 }
680
681 static void
sdhci_card_task(void * arg,int pending __unused)682 sdhci_card_task(void *arg, int pending __unused)
683 {
684 struct sdhci_slot *slot = arg;
685 #ifndef MMCCAM
686 device_t d;
687 #endif
688
689 SDHCI_LOCK(slot);
690 if (SDHCI_GET_CARD_PRESENT(slot->bus, slot)) {
691 #ifdef MMCCAM
692 if (slot->card_present == 0) {
693 #else
694 if (slot->dev == NULL) {
695 #endif
696 /* If card is present - attach mmc bus. */
697 if (bootverbose || sdhci_debug)
698 slot_printf(slot, "Card inserted\n");
699 #ifdef MMCCAM
700 slot->card_present = 1;
701 mmccam_start_discovery(slot->sim);
702 SDHCI_UNLOCK(slot);
703 #else
704 SDHCI_UNLOCK(slot);
705 bus_topo_lock();
706 d = slot->dev = device_add_child(slot->bus, "mmc", -1);
707 if (d) {
708 device_set_ivars(d, slot);
709 (void)device_probe_and_attach(d);
710 }
711 bus_topo_unlock();
712 #endif
713 } else
714 SDHCI_UNLOCK(slot);
715 } else {
716 #ifdef MMCCAM
717 if (slot->card_present == 1) {
718 #else
719 if (slot->dev != NULL) {
720 d = slot->dev;
721 #endif
722 /* If no card present - detach mmc bus. */
723 if (bootverbose || sdhci_debug)
724 slot_printf(slot, "Card removed\n");
725 slot->dev = NULL;
726 #ifdef MMCCAM
727 slot->card_present = 0;
728 mmccam_start_discovery(slot->sim);
729 SDHCI_UNLOCK(slot);
730 #else
731 slot->intmask &= ~sdhci_tuning_intmask(slot);
732 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
733 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
734 slot->opt &= ~SDHCI_TUNING_ENABLED;
735 SDHCI_UNLOCK(slot);
736 callout_drain(&slot->retune_callout);
737 bus_topo_lock();
738 device_delete_child(slot->bus, d);
739 bus_topo_unlock();
740 #endif
741 } else
742 SDHCI_UNLOCK(slot);
743 }
744 }
745
746 static void
747 sdhci_handle_card_present_locked(struct sdhci_slot *slot, bool is_present)
748 {
749 bool was_present;
750
751 /*
752 * If there was no card and now there is one, schedule the task to
753 * create the child device after a short delay. The delay is to
754 * debounce the card insert (sometimes the card detect pin stabilizes
755 * before the other pins have made good contact).
756 *
757 * If there was a card present and now it's gone, immediately schedule
758 * the task to delete the child device. No debouncing -- gone is gone,
759 * because once power is removed, a full card re-init is needed, and
760 * that happens by deleting and recreating the child device.
761 */
762 #ifdef MMCCAM
763 was_present = slot->card_present;
764 #else
765 was_present = slot->dev != NULL;
766 #endif
767 if (!was_present && is_present) {
768 taskqueue_enqueue_timeout(taskqueue_bus,
769 &slot->card_delayed_task, -SDHCI_INSERT_DELAY_TICKS);
770 } else if (was_present && !is_present) {
771 taskqueue_enqueue(taskqueue_bus, &slot->card_task);
772 }
773 }
774
775 void
776 sdhci_handle_card_present(struct sdhci_slot *slot, bool is_present)
777 {
778
779 SDHCI_LOCK(slot);
780 sdhci_handle_card_present_locked(slot, is_present);
781 SDHCI_UNLOCK(slot);
782 }
783
784 static void
785 sdhci_card_poll(void *arg)
786 {
787 struct sdhci_slot *slot = arg;
788
789 sdhci_handle_card_present(slot,
790 SDHCI_GET_CARD_PRESENT(slot->bus, slot));
791 callout_reset(&slot->card_poll_callout, SDHCI_CARD_PRESENT_TICKS,
792 sdhci_card_poll, slot);
793 }
794
795 static int
796 sdhci_dma_alloc(struct sdhci_slot *slot)
797 {
798 int err;
799
800 if (!(slot->quirks & SDHCI_QUIRK_BROKEN_SDMA_BOUNDARY)) {
801 if (maxphys <= 1024 * 4)
802 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_4K;
803 else if (maxphys <= 1024 * 8)
804 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_8K;
805 else if (maxphys <= 1024 * 16)
806 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_16K;
807 else if (maxphys <= 1024 * 32)
808 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_32K;
809 else if (maxphys <= 1024 * 64)
810 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_64K;
811 else if (maxphys <= 1024 * 128)
812 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_128K;
813 else if (maxphys <= 1024 * 256)
814 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_256K;
815 else
816 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_512K;
817 }
818 slot->sdma_bbufsz = SDHCI_SDMA_BNDRY_TO_BBUFSZ(slot->sdma_boundary);
819
820 /*
821 * Allocate the DMA tag for an SDMA bounce buffer.
822 * Note that the SDHCI specification doesn't state any alignment
823 * constraint for the SDMA system address. However, controllers
824 * typically ignore the SDMA boundary bits in SDHCI_DMA_ADDRESS when
825 * forming the actual address of data, requiring the SDMA buffer to
826 * be aligned to the SDMA boundary.
827 */
828 err = bus_dma_tag_create(bus_get_dma_tag(slot->bus), slot->sdma_bbufsz,
829 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
830 slot->sdma_bbufsz, 1, slot->sdma_bbufsz, BUS_DMA_ALLOCNOW,
831 NULL, NULL, &slot->dmatag);
832 if (err != 0) {
833 slot_printf(slot, "Can't create DMA tag for SDMA\n");
834 return (err);
835 }
836 /* Allocate DMA memory for the SDMA bounce buffer. */
837 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem,
838 BUS_DMA_NOWAIT, &slot->dmamap);
839 if (err != 0) {
840 slot_printf(slot, "Can't alloc DMA memory for SDMA\n");
841 bus_dma_tag_destroy(slot->dmatag);
842 return (err);
843 }
844 /* Map the memory of the SDMA bounce buffer. */
845 err = bus_dmamap_load(slot->dmatag, slot->dmamap,
846 (void *)slot->dmamem, slot->sdma_bbufsz, sdhci_getaddr,
847 &slot->paddr, 0);
848 if (err != 0 || slot->paddr == 0) {
849 slot_printf(slot, "Can't load DMA memory for SDMA\n");
850 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap);
851 bus_dma_tag_destroy(slot->dmatag);
852 if (err)
853 return (err);
854 else
855 return (EFAULT);
856 }
857
858 return (0);
859 }
860
861 static void
862 sdhci_dma_free(struct sdhci_slot *slot)
863 {
864
865 bus_dmamap_unload(slot->dmatag, slot->dmamap);
866 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap);
867 bus_dma_tag_destroy(slot->dmatag);
868 }
869
870 int
871 sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num)
872 {
873 kobjop_desc_t kobj_desc;
874 kobj_method_t *kobj_method;
875 uint32_t caps, caps2, freq, host_caps;
876 int err;
877 char node_name[8];
878 struct sysctl_oid *node_oid;
879
880 SDHCI_LOCK_INIT(slot);
881
882 slot->num = num;
883 slot->bus = dev;
884
885 slot->version = (RD2(slot, SDHCI_HOST_VERSION)
886 >> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK;
887 if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS) {
888 caps = slot->caps;
889 caps2 = slot->caps2;
890 } else {
891 caps = RD4(slot, SDHCI_CAPABILITIES);
892 if (slot->version >= SDHCI_SPEC_300)
893 caps2 = RD4(slot, SDHCI_CAPABILITIES2);
894 else
895 caps2 = 0;
896 }
897 if (slot->version >= SDHCI_SPEC_300) {
898 if ((caps & SDHCI_SLOTTYPE_MASK) != SDHCI_SLOTTYPE_REMOVABLE &&
899 (caps & SDHCI_SLOTTYPE_MASK) != SDHCI_SLOTTYPE_EMBEDDED) {
900 slot_printf(slot,
901 "Driver doesn't support shared bus slots\n");
902 SDHCI_LOCK_DESTROY(slot);
903 return (ENXIO);
904 } else if ((caps & SDHCI_SLOTTYPE_MASK) ==
905 SDHCI_SLOTTYPE_EMBEDDED) {
906 slot->opt |= SDHCI_SLOT_EMBEDDED | SDHCI_NON_REMOVABLE;
907 }
908 }
909 /* Calculate base clock frequency. */
910 if (slot->version >= SDHCI_SPEC_300)
911 freq = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
912 SDHCI_CLOCK_BASE_SHIFT;
913 else
914 freq = (caps & SDHCI_CLOCK_BASE_MASK) >>
915 SDHCI_CLOCK_BASE_SHIFT;
916 if (freq != 0)
917 slot->max_clk = freq * 1000000;
918 /*
919 * If the frequency wasn't in the capabilities and the hardware driver
920 * hasn't already set max_clk we're probably not going to work right
921 * with an assumption, so complain about it.
922 */
923 if (slot->max_clk == 0) {
924 slot->max_clk = SDHCI_DEFAULT_MAX_FREQ * 1000000;
925 slot_printf(slot, "Hardware doesn't specify base clock "
926 "frequency, using %dMHz as default.\n",
927 SDHCI_DEFAULT_MAX_FREQ);
928 }
929 /* Calculate/set timeout clock frequency. */
930 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) {
931 slot->timeout_clk = slot->max_clk / 1000;
932 } else if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_1MHZ) {
933 slot->timeout_clk = 1000;
934 } else {
935 slot->timeout_clk = (caps & SDHCI_TIMEOUT_CLK_MASK) >>
936 SDHCI_TIMEOUT_CLK_SHIFT;
937 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
938 slot->timeout_clk *= 1000;
939 }
940 /*
941 * If the frequency wasn't in the capabilities and the hardware driver
942 * hasn't already set timeout_clk we'll probably work okay using the
943 * max timeout, but still mention it.
944 */
945 if (slot->timeout_clk == 0) {
946 slot_printf(slot, "Hardware doesn't specify timeout clock "
947 "frequency, setting BROKEN_TIMEOUT quirk.\n");
948 slot->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
949 }
950
951 slot->host.f_min = SDHCI_MIN_FREQ(slot->bus, slot);
952 slot->host.f_max = slot->max_clk;
953 slot->host.host_ocr = 0;
954 if (caps & SDHCI_CAN_VDD_330)
955 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340;
956 if (caps & SDHCI_CAN_VDD_300)
957 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310;
958 /*
959 * 1.8V VDD is not supposed to be used for removable cards. Hardware
960 * prior to v3.0 had no way to indicate embedded slots, but did
961 * sometimes support 1.8v for non-removable devices.
962 */
963 if ((caps & SDHCI_CAN_VDD_180) && (slot->version < SDHCI_SPEC_300 ||
964 (slot->opt & SDHCI_SLOT_EMBEDDED)))
965 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE;
966 if (slot->host.host_ocr == 0) {
967 slot_printf(slot, "Hardware doesn't report any "
968 "support voltages.\n");
969 }
970
971 host_caps = slot->host.caps;
972 host_caps |= MMC_CAP_4_BIT_DATA;
973 if (caps & SDHCI_CAN_DO_8BITBUS)
974 host_caps |= MMC_CAP_8_BIT_DATA;
975 if (caps & SDHCI_CAN_DO_HISPD)
976 host_caps |= MMC_CAP_HSPEED;
977 if (slot->quirks & SDHCI_QUIRK_BOOT_NOACC)
978 host_caps |= MMC_CAP_BOOT_NOACC;
979 if (slot->quirks & SDHCI_QUIRK_WAIT_WHILE_BUSY)
980 host_caps |= MMC_CAP_WAIT_WHILE_BUSY;
981
982 /* Determine supported UHS-I and eMMC modes. */
983 if (caps2 & (SDHCI_CAN_SDR50 | SDHCI_CAN_SDR104 | SDHCI_CAN_DDR50))
984 host_caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
985 if (caps2 & SDHCI_CAN_SDR104) {
986 host_caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
987 if (!(slot->quirks & SDHCI_QUIRK_BROKEN_MMC_HS200))
988 host_caps |= MMC_CAP_MMC_HS200;
989 } else if (caps2 & SDHCI_CAN_SDR50)
990 host_caps |= MMC_CAP_UHS_SDR50;
991 if (caps2 & SDHCI_CAN_DDR50 &&
992 !(slot->quirks & SDHCI_QUIRK_BROKEN_UHS_DDR50))
993 host_caps |= MMC_CAP_UHS_DDR50;
994 if (slot->quirks & SDHCI_QUIRK_MMC_DDR52)
995 host_caps |= MMC_CAP_MMC_DDR52;
996 if (slot->quirks & SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 &&
997 caps2 & SDHCI_CAN_MMC_HS400)
998 host_caps |= MMC_CAP_MMC_HS400;
999 if (slot->quirks & SDHCI_QUIRK_MMC_HS400_IF_CAN_SDR104 &&
1000 caps2 & SDHCI_CAN_SDR104)
1001 host_caps |= MMC_CAP_MMC_HS400;
1002
1003 /*
1004 * Disable UHS-I and eMMC modes if the set_uhs_timing method is the
1005 * default NULL implementation.
1006 */
1007 kobj_desc = &sdhci_set_uhs_timing_desc;
1008 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL,
1009 kobj_desc);
1010 if (kobj_method == &kobj_desc->deflt)
1011 host_caps &= ~(MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
1012 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 |
1013 MMC_CAP_MMC_DDR52 | MMC_CAP_MMC_HS200 | MMC_CAP_MMC_HS400);
1014
1015 #define SDHCI_CAP_MODES_TUNING(caps2) \
1016 (((caps2) & SDHCI_TUNE_SDR50 ? MMC_CAP_UHS_SDR50 : 0) | \
1017 MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 | MMC_CAP_MMC_HS200 | \
1018 MMC_CAP_MMC_HS400)
1019
1020 /*
1021 * Disable UHS-I and eMMC modes that require (re-)tuning if either
1022 * the tune or re-tune method is the default NULL implementation.
1023 */
1024 kobj_desc = &mmcbr_tune_desc;
1025 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL,
1026 kobj_desc);
1027 if (kobj_method == &kobj_desc->deflt)
1028 goto no_tuning;
1029 kobj_desc = &mmcbr_retune_desc;
1030 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL,
1031 kobj_desc);
1032 if (kobj_method == &kobj_desc->deflt) {
1033 no_tuning:
1034 host_caps &= ~(SDHCI_CAP_MODES_TUNING(caps2));
1035 }
1036
1037 /* Allocate tuning structures and determine tuning parameters. */
1038 if (host_caps & SDHCI_CAP_MODES_TUNING(caps2)) {
1039 slot->opt |= SDHCI_TUNING_SUPPORTED;
1040 slot->tune_req = malloc(sizeof(*slot->tune_req), M_DEVBUF,
1041 M_WAITOK);
1042 slot->tune_cmd = malloc(sizeof(*slot->tune_cmd), M_DEVBUF,
1043 M_WAITOK);
1044 slot->tune_data = malloc(sizeof(*slot->tune_data), M_DEVBUF,
1045 M_WAITOK);
1046 if (caps2 & SDHCI_TUNE_SDR50)
1047 slot->opt |= SDHCI_SDR50_NEEDS_TUNING;
1048 slot->retune_mode = (caps2 & SDHCI_RETUNE_MODES_MASK) >>
1049 SDHCI_RETUNE_MODES_SHIFT;
1050 if (slot->retune_mode == SDHCI_RETUNE_MODE_1) {
1051 slot->retune_count = (caps2 & SDHCI_RETUNE_CNT_MASK) >>
1052 SDHCI_RETUNE_CNT_SHIFT;
1053 if (slot->retune_count > 0xb) {
1054 slot_printf(slot, "Unknown re-tuning count "
1055 "%x, using 1 sec\n", slot->retune_count);
1056 slot->retune_count = 1;
1057 } else if (slot->retune_count != 0)
1058 slot->retune_count =
1059 1 << (slot->retune_count - 1);
1060 }
1061 }
1062
1063 #undef SDHCI_CAP_MODES_TUNING
1064
1065 /* Determine supported VCCQ signaling levels. */
1066 host_caps |= MMC_CAP_SIGNALING_330;
1067 if (host_caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
1068 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 |
1069 MMC_CAP_MMC_DDR52_180 | MMC_CAP_MMC_HS200_180 |
1070 MMC_CAP_MMC_HS400_180))
1071 host_caps |= MMC_CAP_SIGNALING_120 | MMC_CAP_SIGNALING_180;
1072
1073 /*
1074 * Disable 1.2 V and 1.8 V signaling if the switch_vccq method is the
1075 * default NULL implementation. Disable 1.2 V support if it's the
1076 * generic SDHCI implementation.
1077 */
1078 kobj_desc = &mmcbr_switch_vccq_desc;
1079 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL,
1080 kobj_desc);
1081 if (kobj_method == &kobj_desc->deflt)
1082 host_caps &= ~(MMC_CAP_SIGNALING_120 | MMC_CAP_SIGNALING_180);
1083 else if (kobj_method->func == (kobjop_t)sdhci_generic_switch_vccq)
1084 host_caps &= ~MMC_CAP_SIGNALING_120;
1085
1086 /* Determine supported driver types (type B is always mandatory). */
1087 if (caps2 & SDHCI_CAN_DRIVE_TYPE_A)
1088 host_caps |= MMC_CAP_DRIVER_TYPE_A;
1089 if (caps2 & SDHCI_CAN_DRIVE_TYPE_C)
1090 host_caps |= MMC_CAP_DRIVER_TYPE_C;
1091 if (caps2 & SDHCI_CAN_DRIVE_TYPE_D)
1092 host_caps |= MMC_CAP_DRIVER_TYPE_D;
1093 slot->host.caps = host_caps;
1094
1095 /* Decide if we have usable DMA. */
1096 if (caps & SDHCI_CAN_DO_DMA)
1097 slot->opt |= SDHCI_HAVE_DMA;
1098
1099 if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA)
1100 slot->opt &= ~SDHCI_HAVE_DMA;
1101 if (slot->quirks & SDHCI_QUIRK_FORCE_DMA)
1102 slot->opt |= SDHCI_HAVE_DMA;
1103 if (slot->quirks & SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE)
1104 slot->opt |= SDHCI_NON_REMOVABLE;
1105
1106 /*
1107 * Use platform-provided transfer backend
1108 * with PIO as a fallback mechanism
1109 */
1110 if (slot->opt & SDHCI_PLATFORM_TRANSFER)
1111 slot->opt &= ~SDHCI_HAVE_DMA;
1112
1113 if (slot->opt & SDHCI_HAVE_DMA) {
1114 err = sdhci_dma_alloc(slot);
1115 if (err != 0) {
1116 if (slot->opt & SDHCI_TUNING_SUPPORTED) {
1117 free(slot->tune_req, M_DEVBUF);
1118 free(slot->tune_cmd, M_DEVBUF);
1119 free(slot->tune_data, M_DEVBUF);
1120 }
1121 SDHCI_LOCK_DESTROY(slot);
1122 return (err);
1123 }
1124 }
1125
1126 if (bootverbose || sdhci_debug) {
1127 sdhci_dumpcaps(slot);
1128 sdhci_dumpregs(slot);
1129 }
1130
1131 slot->timeout = 10;
1132 SYSCTL_ADD_INT(device_get_sysctl_ctx(slot->bus),
1133 SYSCTL_CHILDREN(device_get_sysctl_tree(slot->bus)), OID_AUTO,
1134 "timeout", CTLFLAG_RWTUN, &slot->timeout, 0,
1135 "Maximum timeout for SDHCI transfers (in secs)");
1136 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot);
1137 TIMEOUT_TASK_INIT(taskqueue_bus, &slot->card_delayed_task, 0,
1138 sdhci_card_task, slot);
1139 callout_init(&slot->card_poll_callout, 1);
1140 callout_init_mtx(&slot->timeout_callout, &slot->mtx, 0);
1141 callout_init_mtx(&slot->retune_callout, &slot->mtx, 0);
1142
1143 if ((slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) &&
1144 !(slot->opt & SDHCI_NON_REMOVABLE)) {
1145 callout_reset(&slot->card_poll_callout,
1146 SDHCI_CARD_PRESENT_TICKS, sdhci_card_poll, slot);
1147 }
1148
1149 sdhci_init(slot);
1150
1151 snprintf(node_name, sizeof(node_name), "slot%d", slot->num);
1152
1153 node_oid = SYSCTL_ADD_NODE(device_get_sysctl_ctx(dev),
1154 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
1155 OID_AUTO, node_name, CTLFLAG_RW, 0, "slot specific node");
1156
1157 node_oid = SYSCTL_ADD_NODE(device_get_sysctl_ctx(dev),
1158 SYSCTL_CHILDREN(node_oid), OID_AUTO, "debug", CTLFLAG_RW, 0,
1159 "Debugging node");
1160
1161 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), SYSCTL_CHILDREN(node_oid),
1162 OID_AUTO, "dumpregs", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE,
1163 slot, 0, &sdhci_syctl_dumpregs,
1164 "A", "Dump SDHCI registers");
1165
1166 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), SYSCTL_CHILDREN(node_oid),
1167 OID_AUTO, "dumpcaps", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE,
1168 slot, 0, &sdhci_syctl_dumpcaps,
1169 "A", "Dump SDHCI capabilites");
1170
1171 return (0);
1172 }
1173
1174 #ifndef MMCCAM
1175 void
1176 sdhci_start_slot(struct sdhci_slot *slot)
1177 {
1178
1179 sdhci_card_task(slot, 0);
1180 }
1181 #endif
1182
1183 int
1184 sdhci_cleanup_slot(struct sdhci_slot *slot)
1185 {
1186 device_t d;
1187
1188 callout_drain(&slot->timeout_callout);
1189 callout_drain(&slot->card_poll_callout);
1190 callout_drain(&slot->retune_callout);
1191 taskqueue_drain(taskqueue_bus, &slot->card_task);
1192 taskqueue_drain_timeout(taskqueue_bus, &slot->card_delayed_task);
1193
1194 SDHCI_LOCK(slot);
1195 d = slot->dev;
1196 slot->dev = NULL;
1197 SDHCI_UNLOCK(slot);
1198 if (d != NULL)
1199 device_delete_child(slot->bus, d);
1200
1201 SDHCI_LOCK(slot);
1202 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_ALL);
1203 SDHCI_UNLOCK(slot);
1204 if (slot->opt & SDHCI_HAVE_DMA)
1205 sdhci_dma_free(slot);
1206 if (slot->opt & SDHCI_TUNING_SUPPORTED) {
1207 free(slot->tune_req, M_DEVBUF);
1208 free(slot->tune_cmd, M_DEVBUF);
1209 free(slot->tune_data, M_DEVBUF);
1210 }
1211
1212 SDHCI_LOCK_DESTROY(slot);
1213
1214 return (0);
1215 }
1216
1217 int
1218 sdhci_generic_suspend(struct sdhci_slot *slot)
1219 {
1220
1221 /*
1222 * We expect the MMC layer to issue initial tuning after resume.
1223 * Otherwise, we'd need to indicate re-tuning including circuit reset
1224 * being required at least for re-tuning modes 1 and 2 ourselves.
1225 */
1226 callout_drain(&slot->retune_callout);
1227 SDHCI_LOCK(slot);
1228 slot->opt &= ~SDHCI_TUNING_ENABLED;
1229 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_ALL);
1230 SDHCI_UNLOCK(slot);
1231
1232 return (0);
1233 }
1234
1235 int
1236 sdhci_generic_resume(struct sdhci_slot *slot)
1237 {
1238
1239 SDHCI_LOCK(slot);
1240 sdhci_init(slot);
1241 SDHCI_UNLOCK(slot);
1242
1243 return (0);
1244 }
1245
1246 void
1247 sdhci_generic_reset(device_t brdev __unused, struct sdhci_slot *slot,
1248 uint8_t mask)
1249 {
1250 int timeout;
1251 uint32_t clock;
1252
1253 if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
1254 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot))
1255 return;
1256 }
1257
1258 /* Some controllers need this kick or reset won't work. */
1259 if ((mask & SDHCI_RESET_ALL) == 0 &&
1260 (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) {
1261 /* This is to force an update */
1262 clock = slot->clock;
1263 slot->clock = 0;
1264 sdhci_set_clock(slot, clock);
1265 }
1266
1267 if (mask & SDHCI_RESET_ALL) {
1268 slot->clock = 0;
1269 slot->power = 0;
1270 }
1271
1272 WR1(slot, SDHCI_SOFTWARE_RESET, mask);
1273
1274 if (slot->quirks & SDHCI_QUIRK_WAITFOR_RESET_ASSERTED) {
1275 /*
1276 * Resets on TI OMAPs and AM335x are incompatible with SDHCI
1277 * specification. The reset bit has internal propagation delay,
1278 * so a fast read after write returns 0 even if reset process is
1279 * in progress. The workaround is to poll for 1 before polling
1280 * for 0. In the worst case, if we miss seeing it asserted the
1281 * time we spent waiting is enough to ensure the reset finishes.
1282 */
1283 timeout = 10000;
1284 while ((RD1(slot, SDHCI_SOFTWARE_RESET) & mask) != mask) {
1285 if (timeout <= 0)
1286 break;
1287 timeout--;
1288 DELAY(1);
1289 }
1290 }
1291
1292 /* Wait max 100 ms */
1293 timeout = 10000;
1294 /* Controller clears the bits when it's done */
1295 while (RD1(slot, SDHCI_SOFTWARE_RESET) & mask) {
1296 if (timeout <= 0) {
1297 slot_printf(slot, "Reset 0x%x never completed.\n",
1298 mask);
1299 sdhci_dumpregs(slot);
1300 return;
1301 }
1302 timeout--;
1303 DELAY(10);
1304 }
1305 }
1306
1307 uint32_t
1308 sdhci_generic_min_freq(device_t brdev __unused, struct sdhci_slot *slot)
1309 {
1310
1311 if (slot->version >= SDHCI_SPEC_300)
1312 return (slot->max_clk / SDHCI_300_MAX_DIVIDER);
1313 else
1314 return (slot->max_clk / SDHCI_200_MAX_DIVIDER);
1315 }
1316
1317 bool
1318 sdhci_generic_get_card_present(device_t brdev __unused, struct sdhci_slot *slot)
1319 {
1320
1321 if (slot->opt & SDHCI_NON_REMOVABLE)
1322 return true;
1323
1324 return (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1325 }
1326
1327 void
1328 sdhci_generic_set_uhs_timing(device_t brdev __unused, struct sdhci_slot *slot)
1329 {
1330 const struct mmc_ios *ios;
1331 uint16_t hostctrl2;
1332
1333 if (slot->version < SDHCI_SPEC_300)
1334 return;
1335
1336 SDHCI_ASSERT_LOCKED(slot);
1337 ios = &slot->host.ios;
1338 sdhci_set_clock(slot, 0);
1339 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1340 hostctrl2 &= ~SDHCI_CTRL2_UHS_MASK;
1341 if (ios->clock > SD_SDR50_MAX) {
1342 if (ios->timing == bus_timing_mmc_hs400 ||
1343 ios->timing == bus_timing_mmc_hs400es)
1344 hostctrl2 |= SDHCI_CTRL2_MMC_HS400;
1345 else
1346 hostctrl2 |= SDHCI_CTRL2_UHS_SDR104;
1347 }
1348 else if (ios->clock > SD_SDR25_MAX)
1349 hostctrl2 |= SDHCI_CTRL2_UHS_SDR50;
1350 else if (ios->clock > SD_SDR12_MAX) {
1351 if (ios->timing == bus_timing_uhs_ddr50 ||
1352 ios->timing == bus_timing_mmc_ddr52)
1353 hostctrl2 |= SDHCI_CTRL2_UHS_DDR50;
1354 else
1355 hostctrl2 |= SDHCI_CTRL2_UHS_SDR25;
1356 } else if (ios->clock > SD_MMC_CARD_ID_FREQUENCY)
1357 hostctrl2 |= SDHCI_CTRL2_UHS_SDR12;
1358 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);
1359 sdhci_set_clock(slot, ios->clock);
1360 }
1361
1362 int
1363 sdhci_generic_update_ios(device_t brdev, device_t reqdev)
1364 {
1365 struct sdhci_slot *slot = device_get_ivars(reqdev);
1366 struct mmc_ios *ios = &slot->host.ios;
1367
1368 SDHCI_LOCK(slot);
1369 /* Do full reset on bus power down to clear from any state. */
1370 if (ios->power_mode == power_off) {
1371 WR4(slot, SDHCI_SIGNAL_ENABLE, 0);
1372 sdhci_init(slot);
1373 }
1374 /* Configure the bus. */
1375 sdhci_set_clock(slot, ios->clock);
1376 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd);
1377 if (ios->bus_width == bus_width_8) {
1378 slot->hostctrl |= SDHCI_CTRL_8BITBUS;
1379 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
1380 } else if (ios->bus_width == bus_width_4) {
1381 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
1382 slot->hostctrl |= SDHCI_CTRL_4BITBUS;
1383 } else if (ios->bus_width == bus_width_1) {
1384 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
1385 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
1386 } else {
1387 panic("Invalid bus width: %d", ios->bus_width);
1388 }
1389 if (ios->clock > SD_SDR12_MAX &&
1390 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT))
1391 slot->hostctrl |= SDHCI_CTRL_HISPD;
1392 else
1393 slot->hostctrl &= ~SDHCI_CTRL_HISPD;
1394 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl);
1395 SDHCI_SET_UHS_TIMING(brdev, slot);
1396 /* Some controllers like reset after bus changes. */
1397 if (slot->quirks & SDHCI_QUIRK_RESET_ON_IOS)
1398 SDHCI_RESET(slot->bus, slot,
1399 SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1400
1401 SDHCI_UNLOCK(slot);
1402 return (0);
1403 }
1404
1405 int
1406 sdhci_generic_switch_vccq(device_t brdev __unused, device_t reqdev)
1407 {
1408 struct sdhci_slot *slot = device_get_ivars(reqdev);
1409 enum mmc_vccq vccq;
1410 int err;
1411 uint16_t hostctrl2;
1412
1413 if (slot->version < SDHCI_SPEC_300)
1414 return (0);
1415
1416 err = 0;
1417 vccq = slot->host.ios.vccq;
1418 SDHCI_LOCK(slot);
1419 sdhci_set_clock(slot, 0);
1420 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1421 switch (vccq) {
1422 case vccq_330:
1423 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE))
1424 goto done;
1425 hostctrl2 &= ~SDHCI_CTRL2_S18_ENABLE;
1426 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);
1427 DELAY(5000);
1428 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1429 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE))
1430 goto done;
1431 err = EAGAIN;
1432 break;
1433 case vccq_180:
1434 if (!(slot->host.caps & MMC_CAP_SIGNALING_180)) {
1435 err = EINVAL;
1436 goto done;
1437 }
1438 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE)
1439 goto done;
1440 hostctrl2 |= SDHCI_CTRL2_S18_ENABLE;
1441 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);
1442 DELAY(5000);
1443 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1444 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE)
1445 goto done;
1446 err = EAGAIN;
1447 break;
1448 default:
1449 slot_printf(slot,
1450 "Attempt to set unsupported signaling voltage\n");
1451 err = EINVAL;
1452 break;
1453 }
1454 done:
1455 sdhci_set_clock(slot, slot->host.ios.clock);
1456 SDHCI_UNLOCK(slot);
1457 return (err);
1458 }
1459
1460 int
1461 sdhci_generic_tune(device_t brdev __unused, device_t reqdev, bool hs400)
1462 {
1463 struct sdhci_slot *slot = device_get_ivars(reqdev);
1464 const struct mmc_ios *ios = &slot->host.ios;
1465 struct mmc_command *tune_cmd;
1466 struct mmc_data *tune_data;
1467 uint32_t opcode;
1468 int err;
1469
1470 if (!(slot->opt & SDHCI_TUNING_SUPPORTED))
1471 return (0);
1472
1473 slot->retune_ticks = slot->retune_count * hz;
1474 opcode = MMC_SEND_TUNING_BLOCK;
1475 SDHCI_LOCK(slot);
1476 switch (ios->timing) {
1477 case bus_timing_mmc_hs400:
1478 slot_printf(slot, "HS400 must be tuned in HS200 mode\n");
1479 SDHCI_UNLOCK(slot);
1480 return (EINVAL);
1481 case bus_timing_mmc_hs200:
1482 /*
1483 * In HS400 mode, controllers use the data strobe line to
1484 * latch data from the devices so periodic re-tuning isn't
1485 * expected to be required.
1486 */
1487 if (hs400)
1488 slot->retune_ticks = 0;
1489 opcode = MMC_SEND_TUNING_BLOCK_HS200;
1490 break;
1491 case bus_timing_uhs_ddr50:
1492 case bus_timing_uhs_sdr104:
1493 break;
1494 case bus_timing_uhs_sdr50:
1495 if (slot->opt & SDHCI_SDR50_NEEDS_TUNING)
1496 break;
1497 SDHCI_UNLOCK(slot);
1498 return (0);
1499 default:
1500 slot_printf(slot, "Tuning requested but not required.\n");
1501 SDHCI_UNLOCK(slot);
1502 return (EINVAL);
1503 }
1504
1505 tune_cmd = slot->tune_cmd;
1506 memset(tune_cmd, 0, sizeof(*tune_cmd));
1507 tune_cmd->opcode = opcode;
1508 tune_cmd->flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1509 tune_data = tune_cmd->data = slot->tune_data;
1510 memset(tune_data, 0, sizeof(*tune_data));
1511 tune_data->len = (opcode == MMC_SEND_TUNING_BLOCK_HS200 &&
1512 ios->bus_width == bus_width_8) ? MMC_TUNING_LEN_HS200 :
1513 MMC_TUNING_LEN;
1514 tune_data->flags = MMC_DATA_READ;
1515 tune_data->mrq = tune_cmd->mrq = slot->tune_req;
1516
1517 slot->opt &= ~SDHCI_TUNING_ENABLED;
1518 err = sdhci_exec_tuning(slot, true);
1519 if (err == 0) {
1520 slot->opt |= SDHCI_TUNING_ENABLED;
1521 slot->intmask |= sdhci_tuning_intmask(slot);
1522 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
1523 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
1524 if (slot->retune_ticks) {
1525 callout_reset(&slot->retune_callout, slot->retune_ticks,
1526 sdhci_retune, slot);
1527 }
1528 }
1529 SDHCI_UNLOCK(slot);
1530 return (err);
1531 }
1532
1533 int
1534 sdhci_generic_retune(device_t brdev __unused, device_t reqdev, bool reset)
1535 {
1536 struct sdhci_slot *slot = device_get_ivars(reqdev);
1537 int err;
1538
1539 if (!(slot->opt & SDHCI_TUNING_ENABLED))
1540 return (0);
1541
1542 /* HS400 must be tuned in HS200 mode. */
1543 if (slot->host.ios.timing == bus_timing_mmc_hs400)
1544 return (EINVAL);
1545
1546 SDHCI_LOCK(slot);
1547 err = sdhci_exec_tuning(slot, reset);
1548 /*
1549 * There are two ways sdhci_exec_tuning() can fail:
1550 * EBUSY should not actually happen when requests are only issued
1551 * with the host properly acquired, and
1552 * EIO re-tuning failed (but it did work initially).
1553 *
1554 * In both cases, we should retry at later point if periodic re-tuning
1555 * is enabled. Note that due to slot->retune_req not being cleared in
1556 * these failure cases, the MMC layer should trigger another attempt at
1557 * re-tuning with the next request anyway, though.
1558 */
1559 if (slot->retune_ticks) {
1560 callout_reset(&slot->retune_callout, slot->retune_ticks,
1561 sdhci_retune, slot);
1562 }
1563 SDHCI_UNLOCK(slot);
1564 return (err);
1565 }
1566
1567 static int
1568 sdhci_exec_tuning(struct sdhci_slot *slot, bool reset)
1569 {
1570 struct mmc_request *tune_req;
1571 struct mmc_command *tune_cmd;
1572 int i;
1573 uint32_t intmask;
1574 uint16_t hostctrl2;
1575 u_char opt;
1576
1577 SDHCI_ASSERT_LOCKED(slot);
1578 if (slot->req != NULL)
1579 return (EBUSY);
1580
1581 /* Tuning doesn't work with DMA enabled. */
1582 opt = slot->opt;
1583 slot->opt = opt & ~SDHCI_HAVE_DMA;
1584
1585 /*
1586 * Ensure that as documented, SDHCI_INT_DATA_AVAIL is the only
1587 * kind of interrupt we receive in response to a tuning request.
1588 */
1589 intmask = slot->intmask;
1590 slot->intmask = SDHCI_INT_DATA_AVAIL;
1591 WR4(slot, SDHCI_INT_ENABLE, SDHCI_INT_DATA_AVAIL);
1592 WR4(slot, SDHCI_SIGNAL_ENABLE, SDHCI_INT_DATA_AVAIL);
1593
1594 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1595 if (reset)
1596 hostctrl2 &= ~SDHCI_CTRL2_SAMPLING_CLOCK;
1597 else
1598 hostctrl2 |= SDHCI_CTRL2_SAMPLING_CLOCK;
1599 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2 | SDHCI_CTRL2_EXEC_TUNING);
1600
1601 tune_req = slot->tune_req;
1602 tune_cmd = slot->tune_cmd;
1603 for (i = 0; i < MMC_TUNING_MAX; i++) {
1604 memset(tune_req, 0, sizeof(*tune_req));
1605 tune_req->cmd = tune_cmd;
1606 tune_req->done = sdhci_req_wakeup;
1607 tune_req->done_data = slot;
1608 slot->req = tune_req;
1609 slot->flags = 0;
1610 sdhci_start(slot);
1611 while (!(tune_req->flags & MMC_REQ_DONE))
1612 msleep(tune_req, &slot->mtx, 0, "sdhciet", 0);
1613 if (!(tune_req->flags & MMC_TUNE_DONE))
1614 break;
1615 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1616 if (!(hostctrl2 & SDHCI_CTRL2_EXEC_TUNING))
1617 break;
1618 if (tune_cmd->opcode == MMC_SEND_TUNING_BLOCK)
1619 DELAY(1000);
1620 }
1621
1622 /*
1623 * Restore DMA usage and interrupts.
1624 * Note that the interrupt aggregation code might have cleared
1625 * SDHCI_INT_DMA_END and/or SDHCI_INT_RESPONSE in slot->intmask
1626 * and SDHCI_SIGNAL_ENABLE respectively so ensure SDHCI_INT_ENABLE
1627 * doesn't lose these.
1628 */
1629 slot->opt = opt;
1630 slot->intmask = intmask;
1631 WR4(slot, SDHCI_INT_ENABLE, intmask | SDHCI_INT_DMA_END |
1632 SDHCI_INT_RESPONSE);
1633 WR4(slot, SDHCI_SIGNAL_ENABLE, intmask);
1634
1635 if ((hostctrl2 & (SDHCI_CTRL2_EXEC_TUNING |
1636 SDHCI_CTRL2_SAMPLING_CLOCK)) == SDHCI_CTRL2_SAMPLING_CLOCK) {
1637 slot->retune_req = 0;
1638 return (0);
1639 }
1640
1641 slot_printf(slot, "Tuning failed, using fixed sampling clock\n");
1642 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2 & ~(SDHCI_CTRL2_EXEC_TUNING |
1643 SDHCI_CTRL2_SAMPLING_CLOCK));
1644 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1645 return (EIO);
1646 }
1647
1648 static void
1649 sdhci_retune(void *arg)
1650 {
1651 struct sdhci_slot *slot = arg;
1652
1653 slot->retune_req |= SDHCI_RETUNE_REQ_NEEDED;
1654 }
1655
1656 #ifdef MMCCAM
1657 static void
1658 sdhci_req_done(struct sdhci_slot *slot)
1659 {
1660 union ccb *ccb;
1661
1662 if (__predict_false(sdhci_debug > 1))
1663 slot_printf(slot, "%s\n", __func__);
1664 if (slot->ccb != NULL && slot->curcmd != NULL) {
1665 callout_stop(&slot->timeout_callout);
1666 ccb = slot->ccb;
1667 slot->ccb = NULL;
1668 slot->curcmd = NULL;
1669
1670 /* Tell CAM the request is finished */
1671 struct ccb_mmcio *mmcio;
1672 mmcio = &ccb->mmcio;
1673
1674 ccb->ccb_h.status =
1675 (mmcio->cmd.error == 0 ? CAM_REQ_CMP : CAM_REQ_CMP_ERR);
1676 xpt_done(ccb);
1677 }
1678 }
1679 #else
1680 static void
1681 sdhci_req_done(struct sdhci_slot *slot)
1682 {
1683 struct mmc_request *req;
1684
1685 if (slot->req != NULL && slot->curcmd != NULL) {
1686 callout_stop(&slot->timeout_callout);
1687 req = slot->req;
1688 slot->req = NULL;
1689 slot->curcmd = NULL;
1690 req->done(req);
1691 }
1692 }
1693 #endif
1694
1695 static void
1696 sdhci_req_wakeup(struct mmc_request *req)
1697 {
1698
1699 req->flags |= MMC_REQ_DONE;
1700 wakeup(req);
1701 }
1702
1703 static void
1704 sdhci_timeout(void *arg)
1705 {
1706 struct sdhci_slot *slot = arg;
1707
1708 if (slot->curcmd != NULL) {
1709 slot_printf(slot, "Controller timeout\n");
1710 sdhci_dumpregs(slot);
1711 SDHCI_RESET(slot->bus, slot,
1712 SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1713 slot->curcmd->error = MMC_ERR_TIMEOUT;
1714 sdhci_req_done(slot);
1715 } else {
1716 slot_printf(slot, "Spurious timeout - no active command\n");
1717 }
1718 }
1719
1720 static void
1721 sdhci_set_transfer_mode(struct sdhci_slot *slot, const struct mmc_data *data)
1722 {
1723 uint16_t mode;
1724
1725 if (data == NULL)
1726 return;
1727
1728 mode = SDHCI_TRNS_BLK_CNT_EN;
1729 if (data->len > 512 || data->block_count > 1) {
1730 mode |= SDHCI_TRNS_MULTI;
1731 if (data->block_count == 0 && __predict_true(
1732 #ifdef MMCCAM
1733 slot->ccb->mmcio.stop.opcode == MMC_STOP_TRANSMISSION &&
1734 #else
1735 slot->req->stop != NULL &&
1736 #endif
1737 !(slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP)))
1738 mode |= SDHCI_TRNS_ACMD12;
1739 }
1740 if (data->flags & MMC_DATA_READ)
1741 mode |= SDHCI_TRNS_READ;
1742 if (slot->flags & SDHCI_USE_DMA)
1743 mode |= SDHCI_TRNS_DMA;
1744
1745 WR2(slot, SDHCI_TRANSFER_MODE, mode);
1746 }
1747
1748 static void
1749 sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd)
1750 {
1751 int flags, timeout;
1752 uint32_t mask;
1753
1754 slot->curcmd = cmd;
1755 slot->cmd_done = 0;
1756
1757 cmd->error = MMC_ERR_NONE;
1758
1759 /* This flags combination is not supported by controller. */
1760 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1761 slot_printf(slot, "Unsupported response type!\n");
1762 cmd->error = MMC_ERR_FAILED;
1763 sdhci_req_done(slot);
1764 return;
1765 }
1766
1767 /*
1768 * Do not issue command if there is no card, clock or power.
1769 * Controller will not detect timeout without clock active.
1770 */
1771 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot) ||
1772 slot->power == 0 ||
1773 slot->clock == 0) {
1774 slot_printf(slot,
1775 "Cannot issue a command (power=%d clock=%d)\n",
1776 slot->power, slot->clock);
1777 cmd->error = MMC_ERR_FAILED;
1778 sdhci_req_done(slot);
1779 return;
1780 }
1781 /* Always wait for free CMD bus. */
1782 mask = SDHCI_CMD_INHIBIT;
1783 /* Wait for free DAT if we have data or busy signal. */
1784 if (cmd->data != NULL || (cmd->flags & MMC_RSP_BUSY))
1785 mask |= SDHCI_DAT_INHIBIT;
1786 /*
1787 * We shouldn't wait for DAT for stop commands or CMD19/CMD21. Note
1788 * that these latter are also special in that SDHCI_CMD_DATA should
1789 * be set below but no actual data is ever read from the controller.
1790 */
1791 #ifdef MMCCAM
1792 if (cmd == &slot->ccb->mmcio.stop ||
1793 #else
1794 if (cmd == slot->req->stop ||
1795 #endif
1796 __predict_false(cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1797 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))
1798 mask &= ~SDHCI_DAT_INHIBIT;
1799 /*
1800 * Wait for bus no more then 250 ms. Typically there will be no wait
1801 * here at all, but when writing a crash dump we may be bypassing the
1802 * host platform's interrupt handler, and in some cases that handler
1803 * may be working around hardware quirks such as not respecting r1b
1804 * busy indications. In those cases, this wait-loop serves the purpose
1805 * of waiting for the prior command and data transfers to be done, and
1806 * SD cards are allowed to take up to 250ms for write and erase ops.
1807 * (It's usually more like 20-30ms in the real world.)
1808 */
1809 timeout = 250;
1810 while (mask & RD4(slot, SDHCI_PRESENT_STATE)) {
1811 if (timeout == 0) {
1812 slot_printf(slot, "Controller never released "
1813 "inhibit bit(s).\n");
1814 sdhci_dumpregs(slot);
1815 cmd->error = MMC_ERR_FAILED;
1816 sdhci_req_done(slot);
1817 return;
1818 }
1819 timeout--;
1820 DELAY(1000);
1821 }
1822
1823 /* Prepare command flags. */
1824 if (!(cmd->flags & MMC_RSP_PRESENT))
1825 flags = SDHCI_CMD_RESP_NONE;
1826 else if (cmd->flags & MMC_RSP_136)
1827 flags = SDHCI_CMD_RESP_LONG;
1828 else if (cmd->flags & MMC_RSP_BUSY)
1829 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1830 else
1831 flags = SDHCI_CMD_RESP_SHORT;
1832 if (cmd->flags & MMC_RSP_CRC)
1833 flags |= SDHCI_CMD_CRC;
1834 if (cmd->flags & MMC_RSP_OPCODE)
1835 flags |= SDHCI_CMD_INDEX;
1836 if (cmd->data != NULL)
1837 flags |= SDHCI_CMD_DATA;
1838 if (cmd->opcode == MMC_STOP_TRANSMISSION)
1839 flags |= SDHCI_CMD_TYPE_ABORT;
1840 /* Prepare data. */
1841 sdhci_start_data(slot, cmd->data);
1842 /*
1843 * Interrupt aggregation: To reduce total number of interrupts
1844 * group response interrupt with data interrupt when possible.
1845 * If there going to be data interrupt, mask response one.
1846 */
1847 if (slot->data_done == 0) {
1848 WR4(slot, SDHCI_SIGNAL_ENABLE,
1849 slot->intmask &= ~SDHCI_INT_RESPONSE);
1850 }
1851 /* Set command argument. */
1852 WR4(slot, SDHCI_ARGUMENT, cmd->arg);
1853 /* Set data transfer mode. */
1854 sdhci_set_transfer_mode(slot, cmd->data);
1855 if (__predict_false(sdhci_debug > 1))
1856 slot_printf(slot, "Starting command opcode %#04x flags %#04x\n",
1857 cmd->opcode, flags);
1858
1859 /* Start command. */
1860 WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff));
1861 /* Start timeout callout. */
1862 callout_reset(&slot->timeout_callout, slot->timeout * hz,
1863 sdhci_timeout, slot);
1864 }
1865
1866 static void
1867 sdhci_finish_command(struct sdhci_slot *slot)
1868 {
1869 int i;
1870 uint32_t val;
1871 uint8_t extra;
1872
1873 if (__predict_false(sdhci_debug > 1))
1874 slot_printf(slot, "%s: called, err %d flags %#04x\n",
1875 __func__, slot->curcmd->error, slot->curcmd->flags);
1876 slot->cmd_done = 1;
1877 /*
1878 * Interrupt aggregation: Restore command interrupt.
1879 * Main restore point for the case when command interrupt
1880 * happened first.
1881 */
1882 if (__predict_true(slot->curcmd->opcode != MMC_SEND_TUNING_BLOCK &&
1883 slot->curcmd->opcode != MMC_SEND_TUNING_BLOCK_HS200))
1884 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |=
1885 SDHCI_INT_RESPONSE);
1886 /* In case of error - reset host and return. */
1887 if (slot->curcmd->error) {
1888 if (slot->curcmd->error == MMC_ERR_BADCRC)
1889 slot->retune_req |= SDHCI_RETUNE_REQ_RESET;
1890 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_CMD);
1891 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_DATA);
1892 sdhci_start(slot);
1893 return;
1894 }
1895 /* If command has response - fetch it. */
1896 if (slot->curcmd->flags & MMC_RSP_PRESENT) {
1897 if (slot->curcmd->flags & MMC_RSP_136) {
1898 /* CRC is stripped so we need one byte shift. */
1899 extra = 0;
1900 for (i = 0; i < 4; i++) {
1901 val = RD4(slot, SDHCI_RESPONSE + i * 4);
1902 if (slot->quirks &
1903 SDHCI_QUIRK_DONT_SHIFT_RESPONSE)
1904 slot->curcmd->resp[3 - i] = val;
1905 else {
1906 slot->curcmd->resp[3 - i] =
1907 (val << 8) | extra;
1908 extra = val >> 24;
1909 }
1910 }
1911 } else
1912 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE);
1913 }
1914 if (__predict_false(sdhci_debug > 1))
1915 slot_printf(slot, "Resp: %#04x %#04x %#04x %#04x\n",
1916 slot->curcmd->resp[0], slot->curcmd->resp[1],
1917 slot->curcmd->resp[2], slot->curcmd->resp[3]);
1918
1919 /* If data ready - finish. */
1920 if (slot->data_done)
1921 sdhci_start(slot);
1922 }
1923
1924 static void
1925 sdhci_start_data(struct sdhci_slot *slot, const struct mmc_data *data)
1926 {
1927 uint32_t blkcnt, blksz, current_timeout, sdma_bbufsz, target_timeout;
1928 uint8_t div;
1929
1930 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
1931 slot->data_done = 1;
1932 return;
1933 }
1934
1935 slot->data_done = 0;
1936
1937 /* Calculate and set data timeout.*/
1938 /* XXX: We should have this from mmc layer, now assume 1 sec. */
1939 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) {
1940 div = 0xE;
1941 } else {
1942 target_timeout = 1000000;
1943 div = 0;
1944 current_timeout = (1 << 13) * 1000 / slot->timeout_clk;
1945 while (current_timeout < target_timeout && div < 0xE) {
1946 ++div;
1947 current_timeout <<= 1;
1948 }
1949 /* Compensate for an off-by-one error in the CaFe chip.*/
1950 if (div < 0xE &&
1951 (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)) {
1952 ++div;
1953 }
1954 }
1955 WR1(slot, SDHCI_TIMEOUT_CONTROL, div);
1956
1957 if (data == NULL)
1958 return;
1959
1960 /* Use DMA if possible. */
1961 if ((slot->opt & SDHCI_HAVE_DMA))
1962 slot->flags |= SDHCI_USE_DMA;
1963 /* If data is small, broken DMA may return zeroes instead of data. */
1964 if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) &&
1965 (data->len <= 512))
1966 slot->flags &= ~SDHCI_USE_DMA;
1967 /* Some controllers require even block sizes. */
1968 if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) &&
1969 ((data->len) & 0x3))
1970 slot->flags &= ~SDHCI_USE_DMA;
1971 /* Load DMA buffer. */
1972 if (slot->flags & SDHCI_USE_DMA) {
1973 sdma_bbufsz = slot->sdma_bbufsz;
1974 if (data->flags & MMC_DATA_READ)
1975 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1976 BUS_DMASYNC_PREREAD);
1977 else {
1978 memcpy(slot->dmamem, data->data, ulmin(data->len,
1979 sdma_bbufsz));
1980 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1981 BUS_DMASYNC_PREWRITE);
1982 }
1983 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
1984 /*
1985 * Interrupt aggregation: Mask border interrupt for the last
1986 * bounce buffer and unmask otherwise.
1987 */
1988 if (data->len == sdma_bbufsz)
1989 slot->intmask &= ~SDHCI_INT_DMA_END;
1990 else
1991 slot->intmask |= SDHCI_INT_DMA_END;
1992 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
1993 }
1994 /* Current data offset for both PIO and DMA. */
1995 slot->offset = 0;
1996 #ifdef MMCCAM
1997 if (data->flags & MMC_DATA_BLOCK_SIZE) {
1998 /* Set block size and request border interrupts on the SDMA boundary. */
1999 blksz = SDHCI_MAKE_BLKSZ(slot->sdma_boundary, data->block_size);
2000 blkcnt = data->block_count;
2001 if (__predict_false(sdhci_debug > 0))
2002 slot_printf(slot, "SDIO Custom block params: blksz: "
2003 "%#10x, blk cnt: %#10x\n", blksz, blkcnt);
2004 } else
2005 #endif
2006 {
2007 /* Set block size and request border interrupts on the SDMA boundary. */
2008 blksz = SDHCI_MAKE_BLKSZ(slot->sdma_boundary, ulmin(data->len, 512));
2009 blkcnt = howmany(data->len, 512);
2010 }
2011
2012 WR2(slot, SDHCI_BLOCK_SIZE, blksz);
2013 WR2(slot, SDHCI_BLOCK_COUNT, blkcnt);
2014 if (__predict_false(sdhci_debug > 1))
2015 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n",
2016 blksz, blkcnt);
2017 }
2018
2019 void
2020 sdhci_finish_data(struct sdhci_slot *slot)
2021 {
2022 struct mmc_data *data = slot->curcmd->data;
2023 size_t left;
2024
2025 /* Interrupt aggregation: Restore command interrupt.
2026 * Auxiliary restore point for the case when data interrupt
2027 * happened first. */
2028 if (!slot->cmd_done) {
2029 WR4(slot, SDHCI_SIGNAL_ENABLE,
2030 slot->intmask |= SDHCI_INT_RESPONSE);
2031 }
2032 /* Unload rest of data from DMA buffer. */
2033 if (!slot->data_done && (slot->flags & SDHCI_USE_DMA) &&
2034 slot->curcmd->data != NULL) {
2035 if (data->flags & MMC_DATA_READ) {
2036 left = data->len - slot->offset;
2037 bus_dmamap_sync(slot->dmatag, slot->dmamap,
2038 BUS_DMASYNC_POSTREAD);
2039 memcpy((u_char*)data->data + slot->offset, slot->dmamem,
2040 ulmin(left, slot->sdma_bbufsz));
2041 } else
2042 bus_dmamap_sync(slot->dmatag, slot->dmamap,
2043 BUS_DMASYNC_POSTWRITE);
2044 }
2045 slot->data_done = 1;
2046 /* If there was error - reset the host. */
2047 if (slot->curcmd->error) {
2048 if (slot->curcmd->error == MMC_ERR_BADCRC)
2049 slot->retune_req |= SDHCI_RETUNE_REQ_RESET;
2050 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_CMD);
2051 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_DATA);
2052 sdhci_start(slot);
2053 return;
2054 }
2055 /* If we already have command response - finish. */
2056 if (slot->cmd_done)
2057 sdhci_start(slot);
2058 }
2059
2060 #ifdef MMCCAM
2061 static void
2062 sdhci_start(struct sdhci_slot *slot)
2063 {
2064 union ccb *ccb;
2065 struct ccb_mmcio *mmcio;
2066
2067 ccb = slot->ccb;
2068 if (ccb == NULL)
2069 return;
2070
2071 mmcio = &ccb->mmcio;
2072 if (!(slot->flags & CMD_STARTED)) {
2073 slot->flags |= CMD_STARTED;
2074 sdhci_start_command(slot, &mmcio->cmd);
2075 return;
2076 }
2077
2078 /*
2079 * Old stack doesn't use this!
2080 * Enabling this code causes significant performance degradation
2081 * and IRQ storms on BBB, Wandboard behaves fine.
2082 * Not using this code does no harm...
2083 if (!(slot->flags & STOP_STARTED) && mmcio->stop.opcode != 0) {
2084 slot->flags |= STOP_STARTED;
2085 sdhci_start_command(slot, &mmcio->stop);
2086 return;
2087 }
2088 */
2089 if (__predict_false(sdhci_debug > 1))
2090 slot_printf(slot, "result: %d\n", mmcio->cmd.error);
2091 if (mmcio->cmd.error == 0 &&
2092 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) {
2093 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_CMD);
2094 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_DATA);
2095 }
2096
2097 sdhci_req_done(slot);
2098 }
2099 #else
2100 static void
2101 sdhci_start(struct sdhci_slot *slot)
2102 {
2103 const struct mmc_request *req;
2104
2105 req = slot->req;
2106 if (req == NULL)
2107 return;
2108
2109 if (!(slot->flags & CMD_STARTED)) {
2110 slot->flags |= CMD_STARTED;
2111 sdhci_start_command(slot, req->cmd);
2112 return;
2113 }
2114 if ((slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP) &&
2115 !(slot->flags & STOP_STARTED) && req->stop) {
2116 slot->flags |= STOP_STARTED;
2117 sdhci_start_command(slot, req->stop);
2118 return;
2119 }
2120 if (__predict_false(sdhci_debug > 1))
2121 slot_printf(slot, "result: %d\n", req->cmd->error);
2122 if (!req->cmd->error &&
2123 ((slot->curcmd == req->stop &&
2124 (slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP)) ||
2125 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2126 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_CMD);
2127 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_DATA);
2128 }
2129
2130 sdhci_req_done(slot);
2131 }
2132 #endif
2133
2134 int
2135 sdhci_generic_request(device_t brdev __unused, device_t reqdev,
2136 struct mmc_request *req)
2137 {
2138 struct sdhci_slot *slot = device_get_ivars(reqdev);
2139
2140 SDHCI_LOCK(slot);
2141 if (slot->req != NULL) {
2142 SDHCI_UNLOCK(slot);
2143 return (EBUSY);
2144 }
2145 if (__predict_false(sdhci_debug > 1)) {
2146 slot_printf(slot,
2147 "CMD%u arg %#x flags %#x dlen %u dflags %#x\n",
2148 req->cmd->opcode, req->cmd->arg, req->cmd->flags,
2149 (req->cmd->data)?(u_int)req->cmd->data->len:0,
2150 (req->cmd->data)?req->cmd->data->flags:0);
2151 }
2152 slot->req = req;
2153 slot->flags = 0;
2154 sdhci_start(slot);
2155 SDHCI_UNLOCK(slot);
2156 if (dumping) {
2157 while (slot->req != NULL) {
2158 sdhci_generic_intr(slot);
2159 DELAY(10);
2160 }
2161 }
2162 return (0);
2163 }
2164
2165 int
2166 sdhci_generic_get_ro(device_t brdev __unused, device_t reqdev)
2167 {
2168 struct sdhci_slot *slot = device_get_ivars(reqdev);
2169 uint32_t val;
2170
2171 SDHCI_LOCK(slot);
2172 val = RD4(slot, SDHCI_PRESENT_STATE);
2173 SDHCI_UNLOCK(slot);
2174 return (!(val & SDHCI_WRITE_PROTECT));
2175 }
2176
2177 int
2178 sdhci_generic_acquire_host(device_t brdev __unused, device_t reqdev)
2179 {
2180 struct sdhci_slot *slot = device_get_ivars(reqdev);
2181 int err = 0;
2182
2183 SDHCI_LOCK(slot);
2184 while (slot->bus_busy)
2185 msleep(slot, &slot->mtx, 0, "sdhciah", 0);
2186 slot->bus_busy++;
2187 /* Activate led. */
2188 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED);
2189 SDHCI_UNLOCK(slot);
2190 return (err);
2191 }
2192
2193 int
2194 sdhci_generic_release_host(device_t brdev __unused, device_t reqdev)
2195 {
2196 struct sdhci_slot *slot = device_get_ivars(reqdev);
2197
2198 SDHCI_LOCK(slot);
2199 /* Deactivate led. */
2200 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED);
2201 slot->bus_busy--;
2202 wakeup(slot);
2203 SDHCI_UNLOCK(slot);
2204 return (0);
2205 }
2206
2207 static void
2208 sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask)
2209 {
2210
2211 if (!slot->curcmd) {
2212 slot_printf(slot, "Got command interrupt 0x%08x, but "
2213 "there is no active command.\n", intmask);
2214 sdhci_dumpregs(slot);
2215 return;
2216 }
2217 if (intmask & SDHCI_INT_TIMEOUT)
2218 slot->curcmd->error = MMC_ERR_TIMEOUT;
2219 else if (intmask & SDHCI_INT_CRC)
2220 slot->curcmd->error = MMC_ERR_BADCRC;
2221 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
2222 slot->curcmd->error = MMC_ERR_FIFO;
2223
2224 sdhci_finish_command(slot);
2225 }
2226
2227 static void
2228 sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask)
2229 {
2230 struct mmc_data *data;
2231 size_t left;
2232 uint32_t sdma_bbufsz;
2233
2234 if (!slot->curcmd) {
2235 slot_printf(slot, "Got data interrupt 0x%08x, but "
2236 "there is no active command.\n", intmask);
2237 sdhci_dumpregs(slot);
2238 return;
2239 }
2240 if (slot->curcmd->data == NULL &&
2241 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
2242 slot_printf(slot, "Got data interrupt 0x%08x, but "
2243 "there is no active data operation.\n",
2244 intmask);
2245 sdhci_dumpregs(slot);
2246 return;
2247 }
2248 if (intmask & SDHCI_INT_DATA_TIMEOUT)
2249 slot->curcmd->error = MMC_ERR_TIMEOUT;
2250 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
2251 slot->curcmd->error = MMC_ERR_BADCRC;
2252 if (slot->curcmd->data == NULL &&
2253 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
2254 SDHCI_INT_DMA_END))) {
2255 slot_printf(slot, "Got data interrupt 0x%08x, but "
2256 "there is busy-only command.\n", intmask);
2257 sdhci_dumpregs(slot);
2258 slot->curcmd->error = MMC_ERR_INVALID;
2259 }
2260 if (slot->curcmd->error) {
2261 /* No need to continue after any error. */
2262 goto done;
2263 }
2264
2265 /* Handle tuning completion interrupt. */
2266 if (__predict_false((intmask & SDHCI_INT_DATA_AVAIL) &&
2267 (slot->curcmd->opcode == MMC_SEND_TUNING_BLOCK ||
2268 slot->curcmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) {
2269 slot->req->flags |= MMC_TUNE_DONE;
2270 sdhci_finish_command(slot);
2271 sdhci_finish_data(slot);
2272 return;
2273 }
2274 /* Handle PIO interrupt. */
2275 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) {
2276 if ((slot->opt & SDHCI_PLATFORM_TRANSFER) &&
2277 SDHCI_PLATFORM_WILL_HANDLE(slot->bus, slot)) {
2278 SDHCI_PLATFORM_START_TRANSFER(slot->bus, slot,
2279 &intmask);
2280 slot->flags |= PLATFORM_DATA_STARTED;
2281 } else
2282 sdhci_transfer_pio(slot);
2283 }
2284 /* Handle DMA border. */
2285 if (intmask & SDHCI_INT_DMA_END) {
2286 data = slot->curcmd->data;
2287 sdma_bbufsz = slot->sdma_bbufsz;
2288
2289 /* Unload DMA buffer ... */
2290 left = data->len - slot->offset;
2291 if (data->flags & MMC_DATA_READ) {
2292 bus_dmamap_sync(slot->dmatag, slot->dmamap,
2293 BUS_DMASYNC_POSTREAD);
2294 memcpy((u_char*)data->data + slot->offset, slot->dmamem,
2295 ulmin(left, sdma_bbufsz));
2296 } else {
2297 bus_dmamap_sync(slot->dmatag, slot->dmamap,
2298 BUS_DMASYNC_POSTWRITE);
2299 }
2300 /* ... and reload it again. */
2301 slot->offset += sdma_bbufsz;
2302 left = data->len - slot->offset;
2303 if (data->flags & MMC_DATA_READ) {
2304 bus_dmamap_sync(slot->dmatag, slot->dmamap,
2305 BUS_DMASYNC_PREREAD);
2306 } else {
2307 memcpy(slot->dmamem, (u_char*)data->data + slot->offset,
2308 ulmin(left, sdma_bbufsz));
2309 bus_dmamap_sync(slot->dmatag, slot->dmamap,
2310 BUS_DMASYNC_PREWRITE);
2311 }
2312 /*
2313 * Interrupt aggregation: Mask border interrupt for the last
2314 * bounce buffer.
2315 */
2316 if (left == sdma_bbufsz) {
2317 slot->intmask &= ~SDHCI_INT_DMA_END;
2318 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
2319 }
2320 /* Restart DMA. */
2321 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
2322 }
2323 /* We have got all data. */
2324 if (intmask & SDHCI_INT_DATA_END) {
2325 if (slot->flags & PLATFORM_DATA_STARTED) {
2326 slot->flags &= ~PLATFORM_DATA_STARTED;
2327 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot);
2328 } else
2329 sdhci_finish_data(slot);
2330 }
2331 done:
2332 if (slot->curcmd != NULL && slot->curcmd->error != 0) {
2333 if (slot->flags & PLATFORM_DATA_STARTED) {
2334 slot->flags &= ~PLATFORM_DATA_STARTED;
2335 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot);
2336 } else
2337 sdhci_finish_data(slot);
2338 }
2339 }
2340
2341 static void
2342 sdhci_acmd_irq(struct sdhci_slot *slot, uint16_t acmd_err)
2343 {
2344
2345 if (!slot->curcmd) {
2346 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but "
2347 "there is no active command.\n", acmd_err);
2348 sdhci_dumpregs(slot);
2349 return;
2350 }
2351 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", acmd_err);
2352 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_CMD);
2353 }
2354
2355 void
2356 sdhci_generic_intr(struct sdhci_slot *slot)
2357 {
2358 uint32_t intmask, present;
2359 uint16_t val16;
2360
2361 SDHCI_LOCK(slot);
2362 /* Read slot interrupt status. */
2363 intmask = RD4(slot, SDHCI_INT_STATUS);
2364 if (intmask == 0 || intmask == 0xffffffff) {
2365 SDHCI_UNLOCK(slot);
2366 return;
2367 }
2368 if (__predict_false(sdhci_debug > 2))
2369 slot_printf(slot, "Interrupt %#x\n", intmask);
2370
2371 /* Handle tuning error interrupt. */
2372 if (__predict_false(intmask & SDHCI_INT_TUNEERR)) {
2373 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_TUNEERR);
2374 slot_printf(slot, "Tuning error indicated\n");
2375 slot->retune_req |= SDHCI_RETUNE_REQ_RESET;
2376 if (slot->curcmd) {
2377 slot->curcmd->error = MMC_ERR_BADCRC;
2378 sdhci_finish_command(slot);
2379 }
2380 }
2381 /* Handle re-tuning interrupt. */
2382 if (__predict_false(intmask & SDHCI_INT_RETUNE))
2383 slot->retune_req |= SDHCI_RETUNE_REQ_NEEDED;
2384 /* Handle card presence interrupts. */
2385 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2386 present = (intmask & SDHCI_INT_CARD_INSERT) != 0;
2387 slot->intmask &=
2388 ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2389 slot->intmask |= present ? SDHCI_INT_CARD_REMOVE :
2390 SDHCI_INT_CARD_INSERT;
2391 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
2392 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
2393 WR4(slot, SDHCI_INT_STATUS, intmask &
2394 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE));
2395 sdhci_handle_card_present_locked(slot, present);
2396 }
2397 /* Handle command interrupts. */
2398 if (intmask & SDHCI_INT_CMD_MASK) {
2399 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK);
2400 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK);
2401 }
2402 /* Handle data interrupts. */
2403 if (intmask & SDHCI_INT_DATA_MASK) {
2404 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK);
2405 /* Don't call data_irq in case of errored command. */
2406 if ((intmask & SDHCI_INT_CMD_ERROR_MASK) == 0)
2407 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK);
2408 }
2409 /* Handle AutoCMD12 error interrupt. */
2410 if (intmask & SDHCI_INT_ACMD12ERR) {
2411 /* Clearing SDHCI_INT_ACMD12ERR may clear SDHCI_ACMD12_ERR. */
2412 val16 = RD2(slot, SDHCI_ACMD12_ERR);
2413 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR);
2414 sdhci_acmd_irq(slot, val16);
2415 }
2416 /* Handle bus power interrupt. */
2417 if (intmask & SDHCI_INT_BUS_POWER) {
2418 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER);
2419 slot_printf(slot, "Card is consuming too much power!\n");
2420 }
2421 intmask &= ~(SDHCI_INT_ERROR | SDHCI_INT_TUNEERR | SDHCI_INT_RETUNE |
2422 SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | SDHCI_INT_CMD_MASK |
2423 SDHCI_INT_DATA_MASK | SDHCI_INT_ACMD12ERR | SDHCI_INT_BUS_POWER);
2424 /* The rest is unknown. */
2425 if (intmask) {
2426 WR4(slot, SDHCI_INT_STATUS, intmask);
2427 slot_printf(slot, "Unexpected interrupt 0x%08x.\n",
2428 intmask);
2429 sdhci_dumpregs(slot);
2430 }
2431
2432 SDHCI_UNLOCK(slot);
2433 }
2434
2435 int
2436 sdhci_generic_read_ivar(device_t bus, device_t child, int which,
2437 uintptr_t *result)
2438 {
2439 const struct sdhci_slot *slot = device_get_ivars(child);
2440
2441 switch (which) {
2442 default:
2443 return (EINVAL);
2444 case MMCBR_IVAR_BUS_MODE:
2445 *result = slot->host.ios.bus_mode;
2446 break;
2447 case MMCBR_IVAR_BUS_WIDTH:
2448 *result = slot->host.ios.bus_width;
2449 break;
2450 case MMCBR_IVAR_CHIP_SELECT:
2451 *result = slot->host.ios.chip_select;
2452 break;
2453 case MMCBR_IVAR_CLOCK:
2454 *result = slot->host.ios.clock;
2455 break;
2456 case MMCBR_IVAR_F_MIN:
2457 *result = slot->host.f_min;
2458 break;
2459 case MMCBR_IVAR_F_MAX:
2460 *result = slot->host.f_max;
2461 break;
2462 case MMCBR_IVAR_HOST_OCR:
2463 *result = slot->host.host_ocr;
2464 break;
2465 case MMCBR_IVAR_MODE:
2466 *result = slot->host.mode;
2467 break;
2468 case MMCBR_IVAR_OCR:
2469 *result = slot->host.ocr;
2470 break;
2471 case MMCBR_IVAR_POWER_MODE:
2472 *result = slot->host.ios.power_mode;
2473 break;
2474 case MMCBR_IVAR_VDD:
2475 *result = slot->host.ios.vdd;
2476 break;
2477 case MMCBR_IVAR_RETUNE_REQ:
2478 if (slot->opt & SDHCI_TUNING_ENABLED) {
2479 if (slot->retune_req & SDHCI_RETUNE_REQ_RESET) {
2480 *result = retune_req_reset;
2481 break;
2482 }
2483 if (slot->retune_req & SDHCI_RETUNE_REQ_NEEDED) {
2484 *result = retune_req_normal;
2485 break;
2486 }
2487 }
2488 *result = retune_req_none;
2489 break;
2490 case MMCBR_IVAR_VCCQ:
2491 *result = slot->host.ios.vccq;
2492 break;
2493 case MMCBR_IVAR_CAPS:
2494 *result = slot->host.caps;
2495 break;
2496 case MMCBR_IVAR_TIMING:
2497 *result = slot->host.ios.timing;
2498 break;
2499 case MMCBR_IVAR_MAX_DATA:
2500 /*
2501 * Re-tuning modes 1 and 2 restrict the maximum data length
2502 * per read/write command to 4 MiB.
2503 */
2504 if (slot->opt & SDHCI_TUNING_ENABLED &&
2505 (slot->retune_mode == SDHCI_RETUNE_MODE_1 ||
2506 slot->retune_mode == SDHCI_RETUNE_MODE_2)) {
2507 *result = 4 * 1024 * 1024 / MMC_SECTOR_SIZE;
2508 break;
2509 }
2510 *result = 65535;
2511 break;
2512 case MMCBR_IVAR_MAX_BUSY_TIMEOUT:
2513 /*
2514 * Currently, sdhci_start_data() hardcodes 1 s for all CMDs.
2515 */
2516 *result = 1000000;
2517 break;
2518 }
2519 return (0);
2520 }
2521
2522 int
2523 sdhci_generic_write_ivar(device_t bus, device_t child, int which,
2524 uintptr_t value)
2525 {
2526 struct sdhci_slot *slot = device_get_ivars(child);
2527 uint32_t clock, max_clock;
2528 int i;
2529
2530 if (sdhci_debug > 1)
2531 slot_printf(slot, "%s: var=%d\n", __func__, which);
2532 switch (which) {
2533 default:
2534 return (EINVAL);
2535 case MMCBR_IVAR_BUS_MODE:
2536 slot->host.ios.bus_mode = value;
2537 break;
2538 case MMCBR_IVAR_BUS_WIDTH:
2539 slot->host.ios.bus_width = value;
2540 break;
2541 case MMCBR_IVAR_CHIP_SELECT:
2542 slot->host.ios.chip_select = value;
2543 break;
2544 case MMCBR_IVAR_CLOCK:
2545 if (value > 0) {
2546 max_clock = slot->max_clk;
2547 clock = max_clock;
2548
2549 if (slot->version < SDHCI_SPEC_300) {
2550 for (i = 0; i < SDHCI_200_MAX_DIVIDER;
2551 i <<= 1) {
2552 if (clock <= value)
2553 break;
2554 clock >>= 1;
2555 }
2556 } else {
2557 for (i = 0; i < SDHCI_300_MAX_DIVIDER;
2558 i += 2) {
2559 if (clock <= value)
2560 break;
2561 clock = max_clock / (i + 2);
2562 }
2563 }
2564
2565 slot->host.ios.clock = clock;
2566 } else
2567 slot->host.ios.clock = 0;
2568 break;
2569 case MMCBR_IVAR_MODE:
2570 slot->host.mode = value;
2571 break;
2572 case MMCBR_IVAR_OCR:
2573 slot->host.ocr = value;
2574 break;
2575 case MMCBR_IVAR_POWER_MODE:
2576 slot->host.ios.power_mode = value;
2577 break;
2578 case MMCBR_IVAR_VDD:
2579 slot->host.ios.vdd = value;
2580 break;
2581 case MMCBR_IVAR_VCCQ:
2582 slot->host.ios.vccq = value;
2583 break;
2584 case MMCBR_IVAR_TIMING:
2585 slot->host.ios.timing = value;
2586 break;
2587 case MMCBR_IVAR_CAPS:
2588 case MMCBR_IVAR_HOST_OCR:
2589 case MMCBR_IVAR_F_MIN:
2590 case MMCBR_IVAR_F_MAX:
2591 case MMCBR_IVAR_MAX_DATA:
2592 case MMCBR_IVAR_RETUNE_REQ:
2593 return (EINVAL);
2594 }
2595 return (0);
2596 }
2597
2598 #ifdef MMCCAM
2599 void
2600 sdhci_start_slot(struct sdhci_slot *slot)
2601 {
2602
2603 if ((slot->devq = cam_simq_alloc(1)) == NULL)
2604 goto fail;
2605
2606 mtx_init(&slot->sim_mtx, "sdhcisim", NULL, MTX_DEF);
2607 slot->sim = cam_sim_alloc(sdhci_cam_action, sdhci_cam_poll,
2608 "sdhci_slot", slot, device_get_unit(slot->bus),
2609 &slot->sim_mtx, 1, 1, slot->devq);
2610
2611 if (slot->sim == NULL) {
2612 cam_simq_free(slot->devq);
2613 slot_printf(slot, "cannot allocate CAM SIM\n");
2614 goto fail;
2615 }
2616
2617 mtx_lock(&slot->sim_mtx);
2618 if (xpt_bus_register(slot->sim, slot->bus, 0) != 0) {
2619 slot_printf(slot, "cannot register SCSI pass-through bus\n");
2620 cam_sim_free(slot->sim, FALSE);
2621 cam_simq_free(slot->devq);
2622 mtx_unlock(&slot->sim_mtx);
2623 goto fail;
2624 }
2625 mtx_unlock(&slot->sim_mtx);
2626
2627 /* End CAM-specific init */
2628 slot->card_present = 0;
2629 sdhci_card_task(slot, 0);
2630 return;
2631
2632 fail:
2633 if (slot->sim != NULL) {
2634 mtx_lock(&slot->sim_mtx);
2635 xpt_bus_deregister(cam_sim_path(slot->sim));
2636 cam_sim_free(slot->sim, FALSE);
2637 mtx_unlock(&slot->sim_mtx);
2638 }
2639
2640 if (slot->devq != NULL)
2641 cam_simq_free(slot->devq);
2642 }
2643
2644 void
2645 sdhci_cam_action(struct cam_sim *sim, union ccb *ccb)
2646 {
2647 struct sdhci_slot *slot;
2648
2649 slot = cam_sim_softc(sim);
2650 if (slot == NULL) {
2651 ccb->ccb_h.status = CAM_SEL_TIMEOUT;
2652 xpt_done(ccb);
2653 return;
2654 }
2655
2656 mtx_assert(&slot->sim_mtx, MA_OWNED);
2657
2658 switch (ccb->ccb_h.func_code) {
2659 case XPT_PATH_INQ:
2660 mmc_path_inq(&ccb->cpi, "Deglitch Networks", sim, maxphys);
2661 break;
2662
2663 case XPT_MMC_GET_TRAN_SETTINGS:
2664 case XPT_GET_TRAN_SETTINGS:
2665 {
2666 struct ccb_trans_settings *cts = &ccb->cts;
2667 uint32_t max_data;
2668
2669 if (sdhci_debug > 1)
2670 slot_printf(slot, "Got XPT_GET_TRAN_SETTINGS\n");
2671
2672 cts->protocol = PROTO_MMCSD;
2673 cts->protocol_version = 1;
2674 cts->transport = XPORT_MMCSD;
2675 cts->transport_version = 1;
2676 cts->xport_specific.valid = 0;
2677 cts->proto_specific.mmc.host_ocr = slot->host.host_ocr;
2678 cts->proto_specific.mmc.host_f_min = slot->host.f_min;
2679 cts->proto_specific.mmc.host_f_max = slot->host.f_max;
2680 cts->proto_specific.mmc.host_caps = slot->host.caps;
2681 /*
2682 * Re-tuning modes 1 and 2 restrict the maximum data length
2683 * per read/write command to 4 MiB.
2684 */
2685 if (slot->opt & SDHCI_TUNING_ENABLED &&
2686 (slot->retune_mode == SDHCI_RETUNE_MODE_1 ||
2687 slot->retune_mode == SDHCI_RETUNE_MODE_2)) {
2688 max_data = 4 * 1024 * 1024 / MMC_SECTOR_SIZE;
2689 } else {
2690 max_data = 65535;
2691 }
2692 cts->proto_specific.mmc.host_max_data = max_data;
2693
2694 memcpy(&cts->proto_specific.mmc.ios, &slot->host.ios, sizeof(struct mmc_ios));
2695 ccb->ccb_h.status = CAM_REQ_CMP;
2696 break;
2697 }
2698 case XPT_MMC_SET_TRAN_SETTINGS:
2699 case XPT_SET_TRAN_SETTINGS:
2700 if (sdhci_debug > 1)
2701 slot_printf(slot, "Got XPT_SET_TRAN_SETTINGS\n");
2702 sdhci_cam_settran_settings(slot, ccb);
2703 ccb->ccb_h.status = CAM_REQ_CMP;
2704 break;
2705 case XPT_RESET_BUS:
2706 if (sdhci_debug > 1)
2707 slot_printf(slot, "Got XPT_RESET_BUS, ACK it...\n");
2708 ccb->ccb_h.status = CAM_REQ_CMP;
2709 break;
2710 case XPT_MMC_IO:
2711 /*
2712 * Here is the HW-dependent part of
2713 * sending the command to the underlying h/w
2714 * At some point in the future an interrupt comes.
2715 * Then the request will be marked as completed.
2716 */
2717 if (__predict_false(sdhci_debug > 1))
2718 slot_printf(slot, "Got XPT_MMC_IO\n");
2719 ccb->ccb_h.status = CAM_REQ_INPROG;
2720
2721 sdhci_cam_request(cam_sim_softc(sim), ccb);
2722 return;
2723 default:
2724 ccb->ccb_h.status = CAM_REQ_INVALID;
2725 break;
2726 }
2727 xpt_done(ccb);
2728 return;
2729 }
2730
2731 void
2732 sdhci_cam_poll(struct cam_sim *sim)
2733 {
2734 sdhci_generic_intr(cam_sim_softc(sim));
2735 }
2736
2737 static int
2738 sdhci_cam_get_possible_host_clock(const struct sdhci_slot *slot,
2739 int proposed_clock)
2740 {
2741 int max_clock, clock, i;
2742
2743 if (proposed_clock == 0)
2744 return 0;
2745 max_clock = slot->max_clk;
2746 clock = max_clock;
2747
2748 if (slot->version < SDHCI_SPEC_300) {
2749 for (i = 0; i < SDHCI_200_MAX_DIVIDER; i <<= 1) {
2750 if (clock <= proposed_clock)
2751 break;
2752 clock >>= 1;
2753 }
2754 } else {
2755 for (i = 0; i < SDHCI_300_MAX_DIVIDER; i += 2) {
2756 if (clock <= proposed_clock)
2757 break;
2758 clock = max_clock / (i + 2);
2759 }
2760 }
2761 return clock;
2762 }
2763
2764 static int
2765 sdhci_cam_settran_settings(struct sdhci_slot *slot, union ccb *ccb)
2766 {
2767 struct mmc_ios *ios;
2768 const struct mmc_ios *new_ios;
2769 const struct ccb_trans_settings_mmc *cts;
2770
2771 ios = &slot->host.ios;
2772 cts = &ccb->cts.proto_specific.mmc;
2773 new_ios = &cts->ios;
2774
2775 /* Update only requested fields */
2776 if (cts->ios_valid & MMC_CLK) {
2777 ios->clock = sdhci_cam_get_possible_host_clock(slot, new_ios->clock);
2778 if (sdhci_debug > 1)
2779 slot_printf(slot, "Clock => %d\n", ios->clock);
2780 }
2781 if (cts->ios_valid & MMC_VDD) {
2782 ios->vdd = new_ios->vdd;
2783 if (sdhci_debug > 1)
2784 slot_printf(slot, "VDD => %d\n", ios->vdd);
2785 }
2786 if (cts->ios_valid & MMC_CS) {
2787 ios->chip_select = new_ios->chip_select;
2788 if (sdhci_debug > 1)
2789 slot_printf(slot, "CS => %d\n", ios->chip_select);
2790 }
2791 if (cts->ios_valid & MMC_BW) {
2792 ios->bus_width = new_ios->bus_width;
2793 if (sdhci_debug > 1)
2794 slot_printf(slot, "Bus width => %d\n", ios->bus_width);
2795 }
2796 if (cts->ios_valid & MMC_PM) {
2797 ios->power_mode = new_ios->power_mode;
2798 if (sdhci_debug > 1)
2799 slot_printf(slot, "Power mode => %d\n", ios->power_mode);
2800 }
2801 if (cts->ios_valid & MMC_BT) {
2802 ios->timing = new_ios->timing;
2803 if (sdhci_debug > 1)
2804 slot_printf(slot, "Timing => %d\n", ios->timing);
2805 }
2806 if (cts->ios_valid & MMC_BM) {
2807 ios->bus_mode = new_ios->bus_mode;
2808 if (sdhci_debug > 1)
2809 slot_printf(slot, "Bus mode => %d\n", ios->bus_mode);
2810 }
2811 if (cts->ios_valid & MMC_VCCQ) {
2812 ios->vccq = new_ios->vccq;
2813 if (sdhci_debug > 1)
2814 slot_printf(slot, "VCCQ => %d\n", ios->vccq);
2815 }
2816
2817 /* XXX Provide a way to call a chip-specific IOS update, required for TI */
2818 return (sdhci_cam_update_ios(slot));
2819 }
2820
2821 static int
2822 sdhci_cam_update_ios(struct sdhci_slot *slot)
2823 {
2824 struct mmc_ios *ios = &slot->host.ios;
2825
2826 if (sdhci_debug > 1)
2827 slot_printf(slot, "%s: power_mode=%d, clk=%d, bus_width=%d, timing=%d\n",
2828 __func__, ios->power_mode, ios->clock, ios->bus_width, ios->timing);
2829 SDHCI_LOCK(slot);
2830 /* Do full reset on bus power down to clear from any state. */
2831 if (ios->power_mode == power_off) {
2832 WR4(slot, SDHCI_SIGNAL_ENABLE, 0);
2833 sdhci_init(slot);
2834 }
2835 /* Configure the bus. */
2836 sdhci_set_clock(slot, ios->clock);
2837 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd);
2838 if (ios->bus_width == bus_width_8) {
2839 slot->hostctrl |= SDHCI_CTRL_8BITBUS;
2840 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
2841 } else if (ios->bus_width == bus_width_4) {
2842 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
2843 slot->hostctrl |= SDHCI_CTRL_4BITBUS;
2844 } else if (ios->bus_width == bus_width_1) {
2845 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
2846 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
2847 } else {
2848 panic("Invalid bus width: %d", ios->bus_width);
2849 }
2850 if (ios->timing == bus_timing_hs &&
2851 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT))
2852 slot->hostctrl |= SDHCI_CTRL_HISPD;
2853 else
2854 slot->hostctrl &= ~SDHCI_CTRL_HISPD;
2855 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl);
2856 /* Some controllers like reset after bus changes. */
2857 if(slot->quirks & SDHCI_QUIRK_RESET_ON_IOS)
2858 SDHCI_RESET(slot->bus, slot,
2859 SDHCI_RESET_CMD | SDHCI_RESET_DATA);
2860
2861 SDHCI_UNLOCK(slot);
2862 return (0);
2863 }
2864
2865 static int
2866 sdhci_cam_request(struct sdhci_slot *slot, union ccb *ccb)
2867 {
2868 const struct ccb_mmcio *mmcio;
2869
2870 mmcio = &ccb->mmcio;
2871
2872 SDHCI_LOCK(slot);
2873 /* if (slot->req != NULL) {
2874 SDHCI_UNLOCK(slot);
2875 return (EBUSY);
2876 }
2877 */
2878 if (__predict_false(sdhci_debug > 1)) {
2879 slot_printf(slot, "CMD%u arg %#x flags %#x dlen %u dflags %#x "
2880 "blksz=%zu blkcnt=%zu\n",
2881 mmcio->cmd.opcode, mmcio->cmd.arg, mmcio->cmd.flags,
2882 mmcio->cmd.data != NULL ? (unsigned int) mmcio->cmd.data->len : 0,
2883 mmcio->cmd.data != NULL ? mmcio->cmd.data->flags : 0,
2884 mmcio->cmd.data != NULL ? mmcio->cmd.data->block_size : 0,
2885 mmcio->cmd.data != NULL ? mmcio->cmd.data->block_count : 0);
2886 }
2887 if (mmcio->cmd.data != NULL) {
2888 if (mmcio->cmd.data->len == 0 || mmcio->cmd.data->flags == 0)
2889 panic("data->len = %d, data->flags = %d -- something is b0rked",
2890 (int)mmcio->cmd.data->len, mmcio->cmd.data->flags);
2891 }
2892 slot->ccb = ccb;
2893 slot->flags = 0;
2894 sdhci_start(slot);
2895 SDHCI_UNLOCK(slot);
2896 return (0);
2897 }
2898 #endif /* MMCCAM */
2899
2900 MODULE_VERSION(sdhci, SDHCI_VERSION);
2901