1 /*
2 * Copyright 2017 Emmanuel Vadot <manu@freebsd.org>
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are
6 * met:
7 *
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
18 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
19 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
20 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
21 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
24 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 #include <sys/param.h>
29 #include <sys/kernel.h>
30 #include <sys/bus.h>
31 #include <sys/module.h>
32 #include <sys/queue.h>
33 #include <sys/taskqueue.h>
34
35 #include <machine/bus.h>
36
37 #include <dev/mmc/bridge.h>
38 #include <dev/mmc/mmc_fdt_helpers.h>
39
40 #include <dev/ofw/ofw_bus_subr.h>
41
42 #include <dev/extres/clk/clk.h>
43
44 #include <dev/mmc/host/dwmmc_var.h>
45
46 #include "opt_mmccam.h"
47
48 enum RKTYPE {
49 RK2928 = 1,
50 RK3288,
51 };
52
53 static struct ofw_compat_data compat_data[] = {
54 {"rockchip,rk2928-dw-mshc", RK2928},
55 {"rockchip,rk3288-dw-mshc", RK3288},
56 {NULL, 0},
57 };
58
59 static int dwmmc_rockchip_update_ios(struct dwmmc_softc *sc, struct mmc_ios *ios);
60
61 static int
rockchip_dwmmc_probe(device_t dev)62 rockchip_dwmmc_probe(device_t dev)
63 {
64
65 if (!ofw_bus_status_okay(dev))
66 return (ENXIO);
67
68 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
69 return (ENXIO);
70
71 device_set_desc(dev, "Synopsys DesignWare Mobile "
72 "Storage Host Controller (RockChip)");
73
74 return (BUS_PROBE_VENDOR);
75 }
76
77 static int
rockchip_dwmmc_attach(device_t dev)78 rockchip_dwmmc_attach(device_t dev)
79 {
80 struct dwmmc_softc *sc;
81 int type;
82
83 sc = device_get_softc(dev);
84 sc->hwtype = HWTYPE_ROCKCHIP;
85 type = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
86
87 switch (type) {
88 case RK2928:
89 sc->use_pio = 1;
90 break;
91 }
92
93 sc->update_ios = &dwmmc_rockchip_update_ios;
94
95 return (dwmmc_attach(dev));
96 }
97
98 static int
dwmmc_rockchip_update_ios(struct dwmmc_softc * sc,struct mmc_ios * ios)99 dwmmc_rockchip_update_ios(struct dwmmc_softc *sc, struct mmc_ios *ios)
100 {
101 unsigned int clock;
102 int error;
103
104 if (ios->clock && ios->clock != sc->bus_hz) {
105 sc->bus_hz = clock = ios->clock;
106 /* Set the MMC clock. */
107 if (sc->ciu) {
108 /*
109 * Apparently you need to set the ciu clock to
110 * the double of bus_hz
111 */
112 error = clk_set_freq(sc->ciu, clock * 2,
113 CLK_SET_ROUND_DOWN);
114 if (error != 0) {
115 device_printf(sc->dev,
116 "failed to set frequency to %u Hz: %d\n",
117 clock, error);
118 return (error);
119 }
120 }
121 }
122 return (0);
123 }
124
125 static device_method_t rockchip_dwmmc_methods[] = {
126 /* bus interface */
127 DEVMETHOD(device_probe, rockchip_dwmmc_probe),
128 DEVMETHOD(device_attach, rockchip_dwmmc_attach),
129 DEVMETHOD(device_detach, dwmmc_detach),
130
131 DEVMETHOD_END
132 };
133
134 DEFINE_CLASS_1(rockchip_dwmmc, rockchip_dwmmc_driver, rockchip_dwmmc_methods,
135 sizeof(struct dwmmc_softc), dwmmc_driver);
136
137 DRIVER_MODULE(rockchip_dwmmc, simplebus, rockchip_dwmmc_driver, 0, 0);
138 DRIVER_MODULE(rockchip_dwmmc, ofwbus, rockchip_dwmmc_driver, NULL, NULL);
139 #ifndef MMCCAM
140 MMC_DECLARE_BRIDGE(rockchip_dwmmc);
141 #endif
142