1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2018 Emmanuel Vadot <manu@freebsd.org>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 #include <sys/cdefs.h>
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/bus.h>
32
33 #include <dev/extres/clk/clk.h>
34 #include <dev/extres/syscon/syscon.h>
35
36 #include <arm64/rockchip/clk/rk_clk_composite.h>
37
38 #include "clkdev_if.h"
39 #include "syscon_if.h"
40
41 struct rk_clk_composite_sc {
42 uint32_t muxdiv_offset;
43 uint32_t mux_shift;
44 uint32_t mux_width;
45 uint32_t mux_mask;
46
47 uint32_t div_shift;
48 uint32_t div_width;
49 uint32_t div_mask;
50
51 uint32_t flags;
52
53 struct syscon *grf;
54 };
55
56 #define WRITE4(_clk, off, val) \
57 rk_clk_composite_write_4(_clk, off, val)
58 #define READ4(_clk, off, val) \
59 rk_clk_composite_read_4(_clk, off, val)
60 #define DEVICE_LOCK(_clk) \
61 CLKDEV_DEVICE_LOCK(clknode_get_device(_clk))
62 #define DEVICE_UNLOCK(_clk) \
63 CLKDEV_DEVICE_UNLOCK(clknode_get_device(_clk))
64
65 #define RK_CLK_COMPOSITE_MASK_SHIFT 16
66
67 #if 0
68 #define dprintf(format, arg...) \
69 printf("%s:(%s)" format, __func__, clknode_get_name(clk), arg)
70 #else
71 #define dprintf(format, arg...)
72 #endif
73
74 static void
rk_clk_composite_read_4(struct clknode * clk,bus_addr_t addr,uint32_t * val)75 rk_clk_composite_read_4(struct clknode *clk, bus_addr_t addr, uint32_t *val)
76 {
77 struct rk_clk_composite_sc *sc;
78
79 sc = clknode_get_softc(clk);
80 if (sc->grf)
81 *val = SYSCON_READ_4(sc->grf, addr);
82 else
83 CLKDEV_READ_4(clknode_get_device(clk), addr, val);
84 }
85
86 static void
rk_clk_composite_write_4(struct clknode * clk,bus_addr_t addr,uint32_t val)87 rk_clk_composite_write_4(struct clknode *clk, bus_addr_t addr, uint32_t val)
88 {
89 struct rk_clk_composite_sc *sc;
90
91 sc = clknode_get_softc(clk);
92 if (sc->grf)
93 SYSCON_WRITE_4(sc->grf, addr, val | (0xffff << 16));
94 else
95 CLKDEV_WRITE_4(clknode_get_device(clk), addr, val);
96 }
97
98 static struct syscon *
rk_clk_composite_get_grf(struct clknode * clk)99 rk_clk_composite_get_grf(struct clknode *clk)
100 {
101 device_t dev;
102 phandle_t node;
103 struct syscon *grf;
104
105 grf = NULL;
106 dev = clknode_get_device(clk);
107 node = ofw_bus_get_node(dev);
108 if (OF_hasprop(node, "rockchip,grf") &&
109 syscon_get_by_ofw_property(dev, node,
110 "rockchip,grf", &grf) != 0) {
111 return (NULL);
112 }
113
114 return (grf);
115 }
116
117 static int
rk_clk_composite_init(struct clknode * clk,device_t dev)118 rk_clk_composite_init(struct clknode *clk, device_t dev)
119 {
120 struct rk_clk_composite_sc *sc;
121 uint32_t val, idx;
122
123 sc = clknode_get_softc(clk);
124 if ((sc->flags & RK_CLK_COMPOSITE_GRF) != 0) {
125 sc->grf = rk_clk_composite_get_grf(clk);
126 if (sc->grf == NULL)
127 panic("clock %s has GRF flag set but no syscon is available",
128 clknode_get_name(clk));
129 }
130
131 idx = 0;
132 if ((sc->flags & RK_CLK_COMPOSITE_HAVE_MUX) != 0) {
133 DEVICE_LOCK(clk);
134 READ4(clk, sc->muxdiv_offset, &val);
135 DEVICE_UNLOCK(clk);
136
137 idx = (val & sc->mux_mask) >> sc->mux_shift;
138 }
139
140 clknode_init_parent_idx(clk, idx);
141
142 return (0);
143 }
144
145 static int
rk_clk_composite_set_mux(struct clknode * clk,int index)146 rk_clk_composite_set_mux(struct clknode *clk, int index)
147 {
148 struct rk_clk_composite_sc *sc;
149 uint32_t val = 0;
150
151 sc = clknode_get_softc(clk);
152
153 if ((sc->flags & RK_CLK_COMPOSITE_HAVE_MUX) == 0)
154 return (0);
155
156 dprintf("Set mux to %d\n", index);
157 DEVICE_LOCK(clk);
158 val |= (index << sc->mux_shift);
159 val |= sc->mux_mask << RK_CLK_COMPOSITE_MASK_SHIFT;
160 dprintf("Write: muxdiv_offset=%x, val=%x\n", sc->muxdiv_offset, val);
161 WRITE4(clk, sc->muxdiv_offset, val);
162 DEVICE_UNLOCK(clk);
163
164 return (0);
165 }
166
167 static int
rk_clk_composite_recalc(struct clknode * clk,uint64_t * freq)168 rk_clk_composite_recalc(struct clknode *clk, uint64_t *freq)
169 {
170 struct rk_clk_composite_sc *sc;
171 uint32_t reg, div;
172
173 sc = clknode_get_softc(clk);
174
175 DEVICE_LOCK(clk);
176
177 READ4(clk, sc->muxdiv_offset, ®);
178 dprintf("Read: muxdiv_offset=%x, val=%x\n", sc->muxdiv_offset, reg);
179
180 DEVICE_UNLOCK(clk);
181
182 div = ((reg & sc->div_mask) >> sc->div_shift);
183 if (sc->flags & RK_CLK_COMPOSITE_DIV_EXP)
184 div = 1 << div;
185 else
186 div += 1;
187 dprintf("parent_freq=%ju, div=%u\n", *freq, div);
188 *freq = *freq / div;
189 dprintf("Final freq=%ju\n", *freq);
190 return (0);
191 }
192
193 static uint32_t
rk_clk_composite_find_best(struct rk_clk_composite_sc * sc,uint64_t fparent,uint64_t freq,uint32_t * reg)194 rk_clk_composite_find_best(struct rk_clk_composite_sc *sc, uint64_t fparent,
195 uint64_t freq, uint32_t *reg)
196 {
197 uint64_t best, cur;
198 uint32_t best_div, best_div_reg;
199 uint32_t div, div_reg;
200
201 best = 0;
202 best_div = 0;
203 best_div_reg = 0;
204
205 for (div_reg = 0; div_reg <= ((sc->div_mask >> sc->div_shift) + 1);
206 div_reg++) {
207 if (sc->flags == RK_CLK_COMPOSITE_DIV_EXP)
208 div = 1 << div_reg;
209 else
210 div = div_reg + 1;
211 cur = fparent / div;
212 if ((freq - cur) < (freq - best)) {
213 best = cur;
214 best_div = div;
215 best_div_reg = div_reg;
216 break;
217 }
218 }
219 *reg = best_div_reg;
220 return (best_div);
221 }
222
223 static int
rk_clk_composite_set_freq(struct clknode * clk,uint64_t fparent,uint64_t * fout,int flags,int * stop)224 rk_clk_composite_set_freq(struct clknode *clk, uint64_t fparent, uint64_t *fout,
225 int flags, int *stop)
226 {
227 struct rk_clk_composite_sc *sc;
228 struct clknode *p_clk;
229 const char **p_names;
230 uint64_t best, cur;
231 uint32_t div, div_reg, best_div, best_div_reg, val;
232 int p_idx, best_parent;
233
234 sc = clknode_get_softc(clk);
235 dprintf("Finding best parent/div for target freq of %ju\n", *fout);
236 p_names = clknode_get_parent_names(clk);
237 for (best_div = 0, best = 0, p_idx = 0;
238 p_idx != clknode_get_parents_num(clk); p_idx++) {
239 p_clk = clknode_find_by_name(p_names[p_idx]);
240 clknode_get_freq(p_clk, &fparent);
241 dprintf("Testing with parent %s (%d) at freq %ju\n",
242 clknode_get_name(p_clk), p_idx, fparent);
243 div = rk_clk_composite_find_best(sc, fparent, *fout, &div_reg);
244 cur = fparent / div;
245 if ((*fout - cur) < (*fout - best)) {
246 best = cur;
247 best_div = div;
248 best_div_reg = div_reg;
249 best_parent = p_idx;
250 dprintf("Best parent so far %s (%d) with best freq at "
251 "%ju\n", clknode_get_name(p_clk), p_idx, best);
252 }
253 }
254
255 *stop = 1;
256 if (best_div == 0)
257 return (ERANGE);
258
259 if ((best < *fout) && ((flags & CLK_SET_ROUND_DOWN) == 0))
260 return (ERANGE);
261
262 if ((best > *fout) && ((flags & CLK_SET_ROUND_UP) == 0)) {
263 return (ERANGE);
264 }
265
266 if ((flags & CLK_SET_DRYRUN) != 0) {
267 *fout = best;
268 return (0);
269 }
270
271 p_idx = clknode_get_parent_idx(clk);
272 if (p_idx != best_parent) {
273 dprintf("Switching parent index from %d to %d\n", p_idx,
274 best_parent);
275 clknode_set_parent_by_idx(clk, best_parent);
276 }
277
278 dprintf("Setting divider to %d (reg: %d)\n", best_div, best_div_reg);
279 dprintf(" div_mask: 0x%X, div_shift: %d\n", sc->div_mask,
280 sc->div_shift);
281
282 DEVICE_LOCK(clk);
283 val = best_div_reg << sc->div_shift;
284 val |= sc->div_mask << RK_CLK_COMPOSITE_MASK_SHIFT;
285 dprintf("Write: muxdiv_offset=%x, val=%x\n", sc->muxdiv_offset, val);
286 WRITE4(clk, sc->muxdiv_offset, val);
287 DEVICE_UNLOCK(clk);
288
289 *fout = best;
290 return (0);
291 }
292
293 static clknode_method_t rk_clk_composite_clknode_methods[] = {
294 /* Device interface */
295 CLKNODEMETHOD(clknode_init, rk_clk_composite_init),
296 CLKNODEMETHOD(clknode_set_mux, rk_clk_composite_set_mux),
297 CLKNODEMETHOD(clknode_recalc_freq, rk_clk_composite_recalc),
298 CLKNODEMETHOD(clknode_set_freq, rk_clk_composite_set_freq),
299 CLKNODEMETHOD_END
300 };
301
302 DEFINE_CLASS_1(rk_clk_composite_clknode, rk_clk_composite_clknode_class,
303 rk_clk_composite_clknode_methods, sizeof(struct rk_clk_composite_sc),
304 clknode_class);
305
306 int
rk_clk_composite_register(struct clkdom * clkdom,struct rk_clk_composite_def * clkdef)307 rk_clk_composite_register(struct clkdom *clkdom,
308 struct rk_clk_composite_def *clkdef)
309 {
310 struct clknode *clk;
311 struct rk_clk_composite_sc *sc;
312
313 clk = clknode_create(clkdom, &rk_clk_composite_clknode_class,
314 &clkdef->clkdef);
315 if (clk == NULL)
316 return (1);
317
318 sc = clknode_get_softc(clk);
319
320 sc->muxdiv_offset = clkdef->muxdiv_offset;
321
322 sc->mux_shift = clkdef->mux_shift;
323 sc->mux_width = clkdef->mux_width;
324 sc->mux_mask = ((1 << clkdef->mux_width) - 1) << sc->mux_shift;
325
326 sc->div_shift = clkdef->div_shift;
327 sc->div_width = clkdef->div_width;
328 sc->div_mask = ((1 << clkdef->div_width) - 1) << sc->div_shift;
329
330 sc->flags = clkdef->flags;
331
332 clknode_register(clkdom, clk);
333
334 return (0);
335 }
336