1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
3 *
4 * Copyright (c) 2003 Peter Wemm.
5 * Copyright (c) 1991 Regents of the University of California.
6 * All rights reserved.
7 *
8 * This code is derived from software contributed to Berkeley by
9 * the Systems Programming Group of the University of Utah Computer
10 * Science Department and William Jolitz of UUNET Technologies Inc.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. Neither the name of the University nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * SUCH DAMAGE.
35 *
36 * Derived from hp300 version by Mike Hibler, this version by William
37 * Jolitz uses a recursive map [a pde points to the page directory] to
38 * map the page tables using the pagetables themselves. This is done to
39 * reduce the impact on kernel virtual memory for lots of sparse address
40 * space, and to reduce the cost of memory to each process.
41 *
42 * from: hp300: @(#)pmap.h 7.2 (Berkeley) 12/16/90
43 * from: @(#)pmap.h 7.4 (Berkeley) 5/12/91
44 */
45
46 #ifdef __i386__
47 #include <i386/pmap.h>
48 #else /* !__i386__ */
49
50 #ifndef _MACHINE_PMAP_H_
51 #define _MACHINE_PMAP_H_
52
53 #include <machine/pte.h>
54
55 /*
56 * Define the PG_xx macros in terms of the bits on x86 PTEs.
57 */
58 #define PG_V X86_PG_V
59 #define PG_RW X86_PG_RW
60 #define PG_U X86_PG_U
61 #define PG_NC_PWT X86_PG_NC_PWT
62 #define PG_NC_PCD X86_PG_NC_PCD
63 #define PG_A X86_PG_A
64 #define PG_M X86_PG_M
65 #define PG_PS X86_PG_PS
66 #define PG_PTE_PAT X86_PG_PTE_PAT
67 #define PG_G X86_PG_G
68 #define PG_AVAIL1 X86_PG_AVAIL1
69 #define PG_AVAIL2 X86_PG_AVAIL2
70 #define PG_AVAIL3 X86_PG_AVAIL3
71 #define PG_PDE_PAT X86_PG_PDE_PAT
72 #define PG_NX X86_PG_NX
73 #define PG_PDE_CACHE X86_PG_PDE_CACHE
74 #define PG_PTE_CACHE X86_PG_PTE_CACHE
75
76 /* Our various interpretations of the above */
77 #define PG_W X86_PG_AVAIL3 /* "Wired" pseudoflag */
78 #define PG_MANAGED X86_PG_AVAIL2
79 #define EPT_PG_EMUL_V X86_PG_AVAIL(52)
80 #define EPT_PG_EMUL_RW X86_PG_AVAIL(53)
81 #define PG_PROMOTED X86_PG_AVAIL(54) /* PDE only */
82
83 /*
84 * Promotion to a 2MB (PDE) page mapping requires that the corresponding 4KB
85 * (PTE) page mappings have identical settings for the following fields:
86 */
87 #define PG_PTE_PROMOTE (PG_NX | PG_MANAGED | PG_W | PG_G | PG_PTE_CACHE | \
88 PG_M | PG_U | PG_RW | PG_V | PG_PKU_MASK)
89
90 /*
91 * undef the PG_xx macros that define bits in the regular x86 PTEs that
92 * have a different position in nested PTEs. This is done when compiling
93 * code that needs to be aware of the differences between regular x86 and
94 * nested PTEs.
95 *
96 * The appropriate bitmask will be calculated at runtime based on the pmap
97 * type.
98 */
99 #ifdef AMD64_NPT_AWARE
100 #undef PG_AVAIL1 /* X86_PG_AVAIL1 aliases with EPT_PG_M */
101 #undef PG_G
102 #undef PG_A
103 #undef PG_M
104 #undef PG_PDE_PAT
105 #undef PG_PDE_CACHE
106 #undef PG_PTE_PAT
107 #undef PG_PTE_CACHE
108 #undef PG_RW
109 #undef PG_V
110 #endif
111
112 /*
113 * Pte related macros. This is complicated by having to deal with
114 * the sign extension of the 48th bit.
115 */
116 #define KV4ADDR(l4, l3, l2, l1) ( \
117 ((unsigned long)-1 << 47) | \
118 ((unsigned long)(l4) << PML4SHIFT) | \
119 ((unsigned long)(l3) << PDPSHIFT) | \
120 ((unsigned long)(l2) << PDRSHIFT) | \
121 ((unsigned long)(l1) << PAGE_SHIFT))
122 #define KV5ADDR(l5, l4, l3, l2, l1) ( \
123 ((unsigned long)-1 << 56) | \
124 ((unsigned long)(l5) << PML5SHIFT) | \
125 ((unsigned long)(l4) << PML4SHIFT) | \
126 ((unsigned long)(l3) << PDPSHIFT) | \
127 ((unsigned long)(l2) << PDRSHIFT) | \
128 ((unsigned long)(l1) << PAGE_SHIFT))
129
130 #define UVADDR(l5, l4, l3, l2, l1) ( \
131 ((unsigned long)(l5) << PML5SHIFT) | \
132 ((unsigned long)(l4) << PML4SHIFT) | \
133 ((unsigned long)(l3) << PDPSHIFT) | \
134 ((unsigned long)(l2) << PDRSHIFT) | \
135 ((unsigned long)(l1) << PAGE_SHIFT))
136
137 /*
138 * Number of kernel PML4 slots. Can be anywhere from 1 to 64 or so,
139 * but setting it larger than NDMPML4E makes no sense.
140 *
141 * Each slot provides .5 TB of kernel virtual space.
142 */
143 #define NKPML4E 4
144
145 /*
146 * Number of PML4 slots for the KASAN shadow map. It requires 1 byte of memory
147 * for every 8 bytes of the kernel address space.
148 */
149 #define NKASANPML4E ((NKPML4E + 7) / 8)
150
151 /*
152 * Number of PML4 slots for the KMSAN shadow and origin maps. These are
153 * one-to-one with the kernel map.
154 */
155 #define NKMSANSHADPML4E NKPML4E
156 #define NKMSANORIGPML4E NKPML4E
157
158 /*
159 * We use the same numbering of the page table pages for 5-level and
160 * 4-level paging structures.
161 */
162 #define NUPML5E (NPML5EPG / 2) /* number of userland PML5
163 pages */
164 #define NUPML4E (NUPML5E * NPML4EPG) /* number of userland PML4
165 pages */
166 #define NUPDPE (NUPML4E * NPDPEPG) /* number of userland PDP
167 pages */
168 #define NUPDE (NUPDPE * NPDEPG) /* number of userland PD
169 entries */
170 #define NUP4ML4E (NPML4EPG / 2)
171
172 /*
173 * NDMPML4E is the maximum number of PML4 entries that will be
174 * used to implement the direct map. It must be a power of two,
175 * and should generally exceed NKPML4E. The maximum possible
176 * value is 64; using 128 will make the direct map intrude into
177 * the recursive page table map.
178 */
179 #define NDMPML4E 8
180
181 /*
182 * These values control the layout of virtual memory. The starting address
183 * of the direct map, which is controlled by DMPML4I, must be a multiple of
184 * its size. (See the PHYS_TO_DMAP() and DMAP_TO_PHYS() macros.)
185 *
186 * Note: KPML4I is the index of the (single) level 4 page that maps
187 * the KVA that holds KERNBASE, while KPML4BASE is the index of the
188 * first level 4 page that maps VM_MIN_KERNEL_ADDRESS. If NKPML4E
189 * is 1, these are the same, otherwise KPML4BASE < KPML4I and extra
190 * level 4 PDEs are needed to map from VM_MIN_KERNEL_ADDRESS up to
191 * KERNBASE.
192 *
193 * (KPML4I combines with KPDPI to choose where KERNBASE starts.
194 * Or, in other words, KPML4I provides bits 39..47 of KERNBASE,
195 * and KPDPI provides bits 30..38.)
196 */
197 #define PML4PML4I (NPML4EPG / 2) /* Index of recursive pml4 mapping */
198 #define PML5PML5I (NPML5EPG / 2) /* Index of recursive pml5 mapping */
199
200 #define KPML4BASE (NPML4EPG-NKPML4E) /* KVM at highest addresses */
201 #define DMPML4I rounddown(KPML4BASE-NDMPML4E, NDMPML4E) /* Below KVM */
202
203 #define KPML4I (NPML4EPG-1)
204 #define KPDPI (NPDPEPG-2) /* kernbase at -2GB */
205
206 #define KASANPML4I (DMPML4I - NKASANPML4E) /* Below the direct map */
207
208 #define KMSANSHADPML4I (KPML4BASE - NKMSANSHADPML4E)
209 #define KMSANORIGPML4I (DMPML4I - NKMSANORIGPML4E)
210
211 /* Large map: index of the first and max last pml4 entry */
212 #define LMSPML4I (PML4PML4I + 1)
213 #define LMEPML4I (KASANPML4I - 1)
214
215 /*
216 * XXX doesn't really belong here I guess...
217 */
218 #define ISA_HOLE_START 0xa0000
219 #define ISA_HOLE_LENGTH (0x100000-ISA_HOLE_START)
220
221 #define PMAP_PCID_NONE 0xffffffff
222 #define PMAP_PCID_KERN 0
223 #define PMAP_PCID_OVERMAX 0x1000
224 #define PMAP_PCID_OVERMAX_KERN 0x800
225 #define PMAP_PCID_USER_PT 0x800
226
227 #define PMAP_NO_CR3 0xffffffffffffffff
228 #define PMAP_UCR3_NOMASK 0xffffffffffffffff
229
230 #ifndef LOCORE
231
232 #include <sys/kassert.h>
233 #include <sys/queue.h>
234 #include <sys/_cpuset.h>
235 #include <sys/_lock.h>
236 #include <sys/_mutex.h>
237 #include <sys/_pctrie.h>
238 #include <machine/_pmap.h>
239 #include <sys/_pv_entry.h>
240 #include <sys/_rangeset.h>
241 #include <sys/_smr.h>
242
243 #include <vm/_vm_radix.h>
244
245 typedef u_int64_t pd_entry_t;
246 typedef u_int64_t pt_entry_t;
247 typedef u_int64_t pdp_entry_t;
248 typedef u_int64_t pml4_entry_t;
249 typedef u_int64_t pml5_entry_t;
250
251 /*
252 * Address of current address space page table maps and directories.
253 */
254 #ifdef _KERNEL
255 #define addr_P4Tmap (KV4ADDR(PML4PML4I, 0, 0, 0))
256 #define addr_P4Dmap (KV4ADDR(PML4PML4I, PML4PML4I, 0, 0))
257 #define addr_P4DPmap (KV4ADDR(PML4PML4I, PML4PML4I, PML4PML4I, 0))
258 #define addr_P4ML4map (KV4ADDR(PML4PML4I, PML4PML4I, PML4PML4I, PML4PML4I))
259 #define addr_P4ML4pml4e (addr_PML4map + (PML4PML4I * sizeof(pml4_entry_t)))
260 #define P4Tmap ((pt_entry_t *)(addr_P4Tmap))
261 #define P4Dmap ((pd_entry_t *)(addr_P4Dmap))
262
263 #define addr_P5Tmap (KV5ADDR(PML5PML5I, 0, 0, 0, 0))
264 #define addr_P5Dmap (KV5ADDR(PML5PML5I, PML5PML5I, 0, 0, 0))
265 #define addr_P5DPmap (KV5ADDR(PML5PML5I, PML5PML5I, PML5PML5I, 0, 0))
266 #define addr_P5ML4map (KV5ADDR(PML5PML5I, PML5PML5I, PML5PML5I, PML5PML5I, 0))
267 #define addr_P5ML5map \
268 (KVADDR(PML5PML5I, PML5PML5I, PML5PML5I, PML5PML5I, PML5PML5I))
269 #define addr_P5ML5pml5e (addr_P5ML5map + (PML5PML5I * sizeof(pml5_entry_t)))
270 #define P5Tmap ((pt_entry_t *)(addr_P5Tmap))
271 #define P5Dmap ((pd_entry_t *)(addr_P5Dmap))
272
273 extern int nkpt; /* Initial number of kernel page tables */
274 extern u_int64_t KPML4phys; /* physical address of kernel level 4 */
275 extern u_int64_t KPML5phys; /* physical address of kernel level 5 */
276
277 /*
278 * virtual address to page table entry and
279 * to physical address.
280 * Note: these work recursively, thus vtopte of a pte will give
281 * the corresponding pde that in turn maps it.
282 */
283 pt_entry_t *vtopte(vm_offset_t);
284 #define vtophys(va) pmap_kextract(((vm_offset_t) (va)))
285
286 #define pte_load_store(ptep, pte) atomic_swap_long(ptep, pte)
287 #define pte_load_clear(ptep) atomic_swap_long(ptep, 0)
288 #define pte_store(ptep, pte) do { \
289 *(u_long *)(ptep) = (u_long)(pte); \
290 } while (0)
291 #define pte_clear(ptep) pte_store(ptep, 0)
292
293 #define pde_store(pdep, pde) pte_store(pdep, pde)
294
295 extern pt_entry_t pg_nx;
296
297 #endif /* _KERNEL */
298
299 /*
300 * Pmap stuff
301 */
302
303 /*
304 * Locks
305 * (p) PV list lock
306 */
307 struct md_page {
308 TAILQ_HEAD(, pv_entry) pv_list; /* (p) */
309 int pv_gen; /* (p) */
310 int pat_mode;
311 };
312
313 enum pmap_type {
314 PT_X86, /* regular x86 page tables */
315 PT_EPT, /* Intel's nested page tables */
316 PT_RVI, /* AMD's nested page tables */
317 };
318
319 /*
320 * The kernel virtual address (KVA) of the level 4 page table page is always
321 * within the direct map (DMAP) region.
322 */
323 struct pmap {
324 struct mtx pm_mtx;
325 pml4_entry_t *pm_pmltop; /* KVA of top level page table */
326 pml4_entry_t *pm_pmltopu; /* KVA of user top page table */
327 uint64_t pm_cr3;
328 uint64_t pm_ucr3;
329 TAILQ_HEAD(,pv_chunk) pm_pvchunk; /* list of mappings in pmap */
330 cpuset_t pm_active; /* active on cpus */
331 enum pmap_type pm_type; /* regular or nested tables */
332 struct pmap_statistics pm_stats; /* pmap statistics */
333 struct vm_radix pm_root; /* spare page table pages */
334 long pm_eptgen; /* EPT pmap generation id */
335 smr_t pm_eptsmr;
336 int pm_flags;
337 struct pmap_pcid *pm_pcidp;
338 struct rangeset pm_pkru;
339 };
340
341 /* flags */
342 #define PMAP_NESTED_IPIMASK 0xff
343 #define PMAP_PDE_SUPERPAGE (1 << 8) /* supports 2MB superpages */
344 #define PMAP_EMULATE_AD_BITS (1 << 9) /* needs A/D bits emulation */
345 #define PMAP_SUPPORTS_EXEC_ONLY (1 << 10) /* execute only mappings ok */
346
347 typedef struct pmap *pmap_t;
348
349 #ifdef _KERNEL
350 extern struct pmap kernel_pmap_store;
351 #define kernel_pmap (&kernel_pmap_store)
352
353 #define PMAP_LOCK(pmap) mtx_lock(&(pmap)->pm_mtx)
354 #define PMAP_LOCK_ASSERT(pmap, type) \
355 mtx_assert(&(pmap)->pm_mtx, (type))
356 #define PMAP_LOCK_DESTROY(pmap) mtx_destroy(&(pmap)->pm_mtx)
357 #define PMAP_LOCK_INIT(pmap) mtx_init(&(pmap)->pm_mtx, "pmap", \
358 NULL, MTX_DEF | MTX_DUPOK)
359 #define PMAP_LOCKED(pmap) mtx_owned(&(pmap)->pm_mtx)
360 #define PMAP_MTX(pmap) (&(pmap)->pm_mtx)
361 #define PMAP_TRYLOCK(pmap) mtx_trylock(&(pmap)->pm_mtx)
362 #define PMAP_UNLOCK(pmap) mtx_unlock(&(pmap)->pm_mtx)
363
364 int pmap_pinit_type(pmap_t pmap, enum pmap_type pm_type, int flags);
365 int pmap_emulate_accessed_dirty(pmap_t pmap, vm_offset_t va, int ftype);
366
367 extern caddr_t CADDR1;
368 extern pt_entry_t *CMAP1;
369 extern vm_offset_t virtual_avail;
370 extern vm_offset_t virtual_end;
371 extern vm_paddr_t dmaplimit;
372 extern int pmap_pcid_enabled;
373 extern int invpcid_works;
374 extern int invlpgb_works;
375 extern int invlpgb_maxcnt;
376 extern int pmap_pcid_invlpg_workaround;
377 extern int pmap_pcid_invlpg_workaround_uena;
378
379 #define pmap_page_get_memattr(m) ((vm_memattr_t)(m)->md.pat_mode)
380 #define pmap_page_is_write_mapped(m) (((m)->a.flags & PGA_WRITEABLE) != 0)
381 #define pmap_unmapbios(va, sz) pmap_unmapdev((va), (sz))
382
383 #define pmap_vm_page_alloc_check(m) \
384 KASSERT(m->phys_addr < kernphys || \
385 m->phys_addr >= kernphys + (vm_offset_t)&_end - KERNSTART, \
386 ("allocating kernel page %p pa %#lx kernphys %#lx end %p", \
387 m, m->phys_addr, kernphys, &_end));
388
389 struct thread;
390
391 void pmap_activate_boot(pmap_t pmap);
392 void pmap_activate_sw(struct thread *);
393 void pmap_allow_2m_x_ept_recalculate(void);
394 void pmap_bootstrap(vm_paddr_t *);
395 int pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde);
396 int pmap_change_attr(vm_offset_t, vm_size_t, int);
397 int pmap_change_prot(vm_offset_t, vm_size_t, vm_prot_t);
398 void pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, boolean_t invalidate);
399 void pmap_flush_cache_range(vm_offset_t, vm_offset_t);
400 void pmap_flush_cache_phys_range(vm_paddr_t, vm_paddr_t, vm_memattr_t);
401 void pmap_init_pat(void);
402 void pmap_kenter(vm_offset_t va, vm_paddr_t pa);
403 void *pmap_kenter_temporary(vm_paddr_t pa, int i);
404 vm_paddr_t pmap_kextract(vm_offset_t);
405 void pmap_kremove(vm_offset_t);
406 int pmap_large_map(vm_paddr_t, vm_size_t, void **, vm_memattr_t);
407 void pmap_large_map_wb(void *sva, vm_size_t len);
408 void pmap_large_unmap(void *sva, vm_size_t len);
409 void *pmap_mapbios(vm_paddr_t, vm_size_t);
410 void *pmap_mapdev(vm_paddr_t, vm_size_t);
411 void *pmap_mapdev_attr(vm_paddr_t, vm_size_t, int);
412 void *pmap_mapdev_pciecfg(vm_paddr_t pa, vm_size_t size);
413 bool pmap_not_in_di(void);
414 boolean_t pmap_page_is_mapped(vm_page_t m);
415 void pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma);
416 void pmap_page_set_memattr_noflush(vm_page_t m, vm_memattr_t ma);
417 void pmap_pinit_pml4(vm_page_t);
418 void pmap_pinit_pml5(vm_page_t);
419 bool pmap_ps_enabled(pmap_t pmap);
420 void pmap_unmapdev(void *, vm_size_t);
421 void pmap_invalidate_page(pmap_t, vm_offset_t);
422 void pmap_invalidate_range(pmap_t, vm_offset_t, vm_offset_t);
423 void pmap_invalidate_all(pmap_t);
424 void pmap_invalidate_cache(void);
425 void pmap_invalidate_cache_pages(vm_page_t *pages, int count);
426 void pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva);
427 void pmap_force_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva);
428 void pmap_get_mapping(pmap_t pmap, vm_offset_t va, uint64_t *ptr, int *num);
429 bool pmap_map_io_transient(vm_page_t *, vm_offset_t *, int, bool);
430 void pmap_unmap_io_transient(vm_page_t *, vm_offset_t *, int, bool);
431 void pmap_map_delete(pmap_t, vm_offset_t, vm_offset_t);
432 void pmap_pti_add_kva(vm_offset_t sva, vm_offset_t eva, bool exec);
433 void pmap_pti_remove_kva(vm_offset_t sva, vm_offset_t eva);
434 void pmap_pti_pcid_invalidate(uint64_t ucr3, uint64_t kcr3);
435 void pmap_pti_pcid_invlpg(uint64_t ucr3, uint64_t kcr3, vm_offset_t va);
436 void pmap_pti_pcid_invlrng(uint64_t ucr3, uint64_t kcr3, vm_offset_t sva,
437 vm_offset_t eva);
438 int pmap_pkru_clear(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
439 int pmap_pkru_set(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
440 u_int keyidx, int flags);
441 void pmap_thread_init_invl_gen(struct thread *td);
442 int pmap_vmspace_copy(pmap_t dst_pmap, pmap_t src_pmap);
443 void pmap_page_array_startup(long count);
444 vm_page_t pmap_page_alloc_below_4g(bool zeroed);
445
446 #if defined(KASAN) || defined(KMSAN)
447 void pmap_san_enter(vm_offset_t);
448 #endif
449
450 /*
451 * Returns a pointer to a set of CPUs on which the pmap is currently active.
452 * Note that the set can be modified without any mutual exclusion, so a copy
453 * must be made if a stable value is required.
454 */
455 static __inline volatile cpuset_t *
pmap_invalidate_cpu_mask(pmap_t pmap)456 pmap_invalidate_cpu_mask(pmap_t pmap)
457 {
458 return (&pmap->pm_active);
459 }
460
461 #if defined(_SYS_PCPU_H_) && defined(_MACHINE_CPUFUNC_H_)
462 /*
463 * It seems that AlderLake+ small cores have some microarchitectural
464 * bug, which results in the INVLPG instruction failing to flush all
465 * global TLB entries when PCID is enabled. Work around it for now,
466 * by doing global invalidation on small cores instead of INVLPG.
467 */
468 static __inline void
pmap_invlpg(pmap_t pmap,vm_offset_t va)469 pmap_invlpg(pmap_t pmap, vm_offset_t va)
470 {
471 if (pmap == kernel_pmap && PCPU_GET(pcid_invlpg_workaround)) {
472 struct invpcid_descr d = { 0 };
473
474 invpcid(&d, INVPCID_CTXGLOB);
475 } else {
476 invlpg(va);
477 }
478 }
479 #endif /* sys/pcpu.h && machine/cpufunc.h */
480
481 #if defined(_SYS_PCPU_H_)
482 /* Return pcid for the pmap pmap on current cpu */
483 static __inline uint32_t
pmap_get_pcid(pmap_t pmap)484 pmap_get_pcid(pmap_t pmap)
485 {
486 struct pmap_pcid *pcidp;
487
488 MPASS(pmap_pcid_enabled);
489 pcidp = zpcpu_get(pmap->pm_pcidp);
490 return (pcidp->pm_pcid);
491 }
492 #endif /* sys/pcpu.h */
493
494 /*
495 * Invalidation request. PCPU pc_smp_tlb_op uses u_int instead of the
496 * enum to avoid both namespace and ABI issues (with enums).
497 */
498 enum invl_op_codes {
499 INVL_OP_TLB = 1,
500 INVL_OP_TLB_INVPCID = 2,
501 INVL_OP_TLB_INVPCID_PTI = 3,
502 INVL_OP_TLB_PCID = 4,
503 INVL_OP_PGRNG = 5,
504 INVL_OP_PGRNG_INVPCID = 6,
505 INVL_OP_PGRNG_PCID = 7,
506 INVL_OP_PG = 8,
507 INVL_OP_PG_INVPCID = 9,
508 INVL_OP_PG_PCID = 10,
509 INVL_OP_CACHE = 11,
510 };
511
512 typedef void (*smp_invl_local_cb_t)(struct pmap *, vm_offset_t addr1,
513 vm_offset_t addr2);
514 typedef void (*smp_targeted_tlb_shootdown_t)(pmap_t, vm_offset_t, vm_offset_t,
515 smp_invl_local_cb_t, enum invl_op_codes);
516
517 void smp_targeted_tlb_shootdown_native(pmap_t, vm_offset_t, vm_offset_t,
518 smp_invl_local_cb_t, enum invl_op_codes);
519 extern smp_targeted_tlb_shootdown_t smp_targeted_tlb_shootdown;
520
521 #endif /* _KERNEL */
522
523 /* Return various clipped indexes for a given VA */
524 static __inline vm_pindex_t
pmap_pte_index(vm_offset_t va)525 pmap_pte_index(vm_offset_t va)
526 {
527
528 return ((va >> PAGE_SHIFT) & ((1ul << NPTEPGSHIFT) - 1));
529 }
530
531 static __inline vm_pindex_t
pmap_pde_index(vm_offset_t va)532 pmap_pde_index(vm_offset_t va)
533 {
534
535 return ((va >> PDRSHIFT) & ((1ul << NPDEPGSHIFT) - 1));
536 }
537
538 static __inline vm_pindex_t
pmap_pdpe_index(vm_offset_t va)539 pmap_pdpe_index(vm_offset_t va)
540 {
541
542 return ((va >> PDPSHIFT) & ((1ul << NPDPEPGSHIFT) - 1));
543 }
544
545 static __inline vm_pindex_t
pmap_pml4e_index(vm_offset_t va)546 pmap_pml4e_index(vm_offset_t va)
547 {
548
549 return ((va >> PML4SHIFT) & ((1ul << NPML4EPGSHIFT) - 1));
550 }
551
552 static __inline vm_pindex_t
pmap_pml5e_index(vm_offset_t va)553 pmap_pml5e_index(vm_offset_t va)
554 {
555
556 return ((va >> PML5SHIFT) & ((1ul << NPML5EPGSHIFT) - 1));
557 }
558
559 #endif /* !LOCORE */
560
561 #endif /* !_MACHINE_PMAP_H_ */
562
563 #endif /* __i386__ */
564