1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2012 NetApp, Inc.
5 * Copyright (c) 2013 Neel Natu <neel@freebsd.org>
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 #include <sys/cdefs.h>
31 #include <sys/types.h>
32 #include <dev/ic/ns16550.h>
33 #ifndef WITHOUT_CAPSICUM
34 #include <sys/capsicum.h>
35 #include <capsicum_helpers.h>
36 #endif
37
38 #include <machine/vmm_snapshot.h>
39
40 #include <stdio.h>
41 #include <stdlib.h>
42 #include <assert.h>
43 #include <err.h>
44 #include <errno.h>
45 #include <fcntl.h>
46 #include <termios.h>
47 #include <unistd.h>
48 #include <stdbool.h>
49 #include <string.h>
50 #include <pthread.h>
51 #include <sysexits.h>
52
53 #include "mevent.h"
54 #include "uart_emul.h"
55 #include "debug.h"
56
57 #define COM1_BASE 0x3F8
58 #define COM1_IRQ 4
59 #define COM2_BASE 0x2F8
60 #define COM2_IRQ 3
61 #define COM3_BASE 0x3E8
62 #define COM3_IRQ 4
63 #define COM4_BASE 0x2E8
64 #define COM4_IRQ 3
65
66 #define DEFAULT_RCLK 1843200
67 #define DEFAULT_BAUD 9600
68
69 #define FCR_RX_MASK 0xC0
70
71 #define MCR_OUT1 0x04
72 #define MCR_OUT2 0x08
73
74 #define MSR_DELTA_MASK 0x0f
75
76 #ifndef REG_SCR
77 #define REG_SCR com_scr
78 #endif
79
80 #define FIFOSZ 16
81
82 static bool uart_stdio; /* stdio in use for i/o */
83 static struct termios tio_stdio_orig;
84
85 static struct {
86 int baseaddr;
87 int irq;
88 bool inuse;
89 } uart_lres[] = {
90 { COM1_BASE, COM1_IRQ, false},
91 { COM2_BASE, COM2_IRQ, false},
92 { COM3_BASE, COM3_IRQ, false},
93 { COM4_BASE, COM4_IRQ, false},
94 };
95
96 #define UART_NLDEVS (sizeof(uart_lres) / sizeof(uart_lres[0]))
97
98 struct fifo {
99 uint8_t buf[FIFOSZ];
100 int rindex; /* index to read from */
101 int windex; /* index to write to */
102 int num; /* number of characters in the fifo */
103 int size; /* size of the fifo */
104 };
105
106 struct ttyfd {
107 bool opened;
108 int rfd; /* fd for reading */
109 int wfd; /* fd for writing, may be == rfd */
110 };
111
112 struct uart_softc {
113 pthread_mutex_t mtx; /* protects all softc elements */
114 uint8_t data; /* Data register (R/W) */
115 uint8_t ier; /* Interrupt enable register (R/W) */
116 uint8_t lcr; /* Line control register (R/W) */
117 uint8_t mcr; /* Modem control register (R/W) */
118 uint8_t lsr; /* Line status register (R/W) */
119 uint8_t msr; /* Modem status register (R/W) */
120 uint8_t fcr; /* FIFO control register (W) */
121 uint8_t scr; /* Scratch register (R/W) */
122
123 uint8_t dll; /* Baudrate divisor latch LSB */
124 uint8_t dlh; /* Baudrate divisor latch MSB */
125
126 struct fifo rxfifo;
127 struct mevent *mev;
128
129 struct ttyfd tty;
130 bool thre_int_pending; /* THRE interrupt pending */
131
132 void *arg;
133 uart_intr_func_t intr_assert;
134 uart_intr_func_t intr_deassert;
135 };
136
137 static void uart_drain(int fd, enum ev_type ev, void *arg);
138
139 static void
ttyclose(void)140 ttyclose(void)
141 {
142
143 tcsetattr(STDIN_FILENO, TCSANOW, &tio_stdio_orig);
144 }
145
146 static void
ttyopen(struct ttyfd * tf)147 ttyopen(struct ttyfd *tf)
148 {
149 struct termios orig, new;
150
151 tcgetattr(tf->rfd, &orig);
152 new = orig;
153 cfmakeraw(&new);
154 new.c_cflag |= CLOCAL;
155 tcsetattr(tf->rfd, TCSANOW, &new);
156 if (uart_stdio) {
157 tio_stdio_orig = orig;
158 atexit(ttyclose);
159 }
160 raw_stdio = 1;
161 }
162
163 static int
ttyread(struct ttyfd * tf)164 ttyread(struct ttyfd *tf)
165 {
166 unsigned char rb;
167
168 if (read(tf->rfd, &rb, 1) == 1)
169 return (rb);
170 else
171 return (-1);
172 }
173
174 static void
ttywrite(struct ttyfd * tf,unsigned char wb)175 ttywrite(struct ttyfd *tf, unsigned char wb)
176 {
177
178 (void)write(tf->wfd, &wb, 1);
179 }
180
181 static void
rxfifo_reset(struct uart_softc * sc,int size)182 rxfifo_reset(struct uart_softc *sc, int size)
183 {
184 char flushbuf[32];
185 struct fifo *fifo;
186 ssize_t nread;
187 int error;
188
189 fifo = &sc->rxfifo;
190 bzero(fifo, sizeof(struct fifo));
191 fifo->size = size;
192
193 if (sc->tty.opened) {
194 /*
195 * Flush any unread input from the tty buffer.
196 */
197 while (1) {
198 nread = read(sc->tty.rfd, flushbuf, sizeof(flushbuf));
199 if (nread != sizeof(flushbuf))
200 break;
201 }
202
203 /*
204 * Enable mevent to trigger when new characters are available
205 * on the tty fd.
206 */
207 error = mevent_enable(sc->mev);
208 assert(error == 0);
209 }
210 }
211
212 static int
rxfifo_available(struct uart_softc * sc)213 rxfifo_available(struct uart_softc *sc)
214 {
215 struct fifo *fifo;
216
217 fifo = &sc->rxfifo;
218 return (fifo->num < fifo->size);
219 }
220
221 static int
rxfifo_putchar(struct uart_softc * sc,uint8_t ch)222 rxfifo_putchar(struct uart_softc *sc, uint8_t ch)
223 {
224 struct fifo *fifo;
225 int error;
226
227 fifo = &sc->rxfifo;
228
229 if (fifo->num < fifo->size) {
230 fifo->buf[fifo->windex] = ch;
231 fifo->windex = (fifo->windex + 1) % fifo->size;
232 fifo->num++;
233 if (!rxfifo_available(sc)) {
234 if (sc->tty.opened) {
235 /*
236 * Disable mevent callback if the FIFO is full.
237 */
238 error = mevent_disable(sc->mev);
239 assert(error == 0);
240 }
241 }
242 return (0);
243 } else
244 return (-1);
245 }
246
247 static int
rxfifo_getchar(struct uart_softc * sc)248 rxfifo_getchar(struct uart_softc *sc)
249 {
250 struct fifo *fifo;
251 int c, error, wasfull;
252
253 wasfull = 0;
254 fifo = &sc->rxfifo;
255 if (fifo->num > 0) {
256 if (!rxfifo_available(sc))
257 wasfull = 1;
258 c = fifo->buf[fifo->rindex];
259 fifo->rindex = (fifo->rindex + 1) % fifo->size;
260 fifo->num--;
261 if (wasfull) {
262 if (sc->tty.opened) {
263 error = mevent_enable(sc->mev);
264 assert(error == 0);
265 }
266 }
267 return (c);
268 } else
269 return (-1);
270 }
271
272 static int
rxfifo_numchars(struct uart_softc * sc)273 rxfifo_numchars(struct uart_softc *sc)
274 {
275 struct fifo *fifo = &sc->rxfifo;
276
277 return (fifo->num);
278 }
279
280 static void
uart_opentty(struct uart_softc * sc)281 uart_opentty(struct uart_softc *sc)
282 {
283
284 ttyopen(&sc->tty);
285 sc->mev = mevent_add(sc->tty.rfd, EVF_READ, uart_drain, sc);
286 assert(sc->mev != NULL);
287 }
288
289 static uint8_t
modem_status(uint8_t mcr)290 modem_status(uint8_t mcr)
291 {
292 uint8_t msr;
293
294 if (mcr & MCR_LOOPBACK) {
295 /*
296 * In the loopback mode certain bits from the MCR are
297 * reflected back into MSR.
298 */
299 msr = 0;
300 if (mcr & MCR_RTS)
301 msr |= MSR_CTS;
302 if (mcr & MCR_DTR)
303 msr |= MSR_DSR;
304 if (mcr & MCR_OUT1)
305 msr |= MSR_RI;
306 if (mcr & MCR_OUT2)
307 msr |= MSR_DCD;
308 } else {
309 /*
310 * Always assert DCD and DSR so tty open doesn't block
311 * even if CLOCAL is turned off.
312 */
313 msr = MSR_DCD | MSR_DSR;
314 }
315 assert((msr & MSR_DELTA_MASK) == 0);
316
317 return (msr);
318 }
319
320 /*
321 * The IIR returns a prioritized interrupt reason:
322 * - receive data available
323 * - transmit holding register empty
324 * - modem status change
325 *
326 * Return an interrupt reason if one is available.
327 */
328 static int
uart_intr_reason(struct uart_softc * sc)329 uart_intr_reason(struct uart_softc *sc)
330 {
331
332 if ((sc->lsr & LSR_OE) != 0 && (sc->ier & IER_ERLS) != 0)
333 return (IIR_RLS);
334 else if (rxfifo_numchars(sc) > 0 && (sc->ier & IER_ERXRDY) != 0)
335 return (IIR_RXTOUT);
336 else if (sc->thre_int_pending && (sc->ier & IER_ETXRDY) != 0)
337 return (IIR_TXRDY);
338 else if ((sc->msr & MSR_DELTA_MASK) != 0 && (sc->ier & IER_EMSC) != 0)
339 return (IIR_MLSC);
340 else
341 return (IIR_NOPEND);
342 }
343
344 static void
uart_reset(struct uart_softc * sc)345 uart_reset(struct uart_softc *sc)
346 {
347 uint16_t divisor;
348
349 divisor = DEFAULT_RCLK / DEFAULT_BAUD / 16;
350 sc->dll = divisor;
351 sc->dlh = divisor >> 16;
352 sc->msr = modem_status(sc->mcr);
353
354 rxfifo_reset(sc, 1); /* no fifo until enabled by software */
355 }
356
357 /*
358 * Toggle the COM port's intr pin depending on whether or not we have an
359 * interrupt condition to report to the processor.
360 */
361 static void
uart_toggle_intr(struct uart_softc * sc)362 uart_toggle_intr(struct uart_softc *sc)
363 {
364 uint8_t intr_reason;
365
366 intr_reason = uart_intr_reason(sc);
367
368 if (intr_reason == IIR_NOPEND)
369 (*sc->intr_deassert)(sc->arg);
370 else
371 (*sc->intr_assert)(sc->arg);
372 }
373
374 static void
uart_drain(int fd,enum ev_type ev,void * arg)375 uart_drain(int fd, enum ev_type ev, void *arg)
376 {
377 struct uart_softc *sc;
378 int ch;
379
380 sc = arg;
381
382 assert(fd == sc->tty.rfd);
383 assert(ev == EVF_READ);
384
385 /*
386 * This routine is called in the context of the mevent thread
387 * to take out the softc lock to protect against concurrent
388 * access from a vCPU i/o exit
389 */
390 pthread_mutex_lock(&sc->mtx);
391
392 if ((sc->mcr & MCR_LOOPBACK) != 0) {
393 (void) ttyread(&sc->tty);
394 } else {
395 while (rxfifo_available(sc) &&
396 ((ch = ttyread(&sc->tty)) != -1)) {
397 rxfifo_putchar(sc, ch);
398 }
399 uart_toggle_intr(sc);
400 }
401
402 pthread_mutex_unlock(&sc->mtx);
403 }
404
405 void
uart_write(struct uart_softc * sc,int offset,uint8_t value)406 uart_write(struct uart_softc *sc, int offset, uint8_t value)
407 {
408 int fifosz;
409 uint8_t msr;
410
411 pthread_mutex_lock(&sc->mtx);
412
413 /*
414 * Take care of the special case DLAB accesses first
415 */
416 if ((sc->lcr & LCR_DLAB) != 0) {
417 if (offset == REG_DLL) {
418 sc->dll = value;
419 goto done;
420 }
421
422 if (offset == REG_DLH) {
423 sc->dlh = value;
424 goto done;
425 }
426 }
427
428 switch (offset) {
429 case REG_DATA:
430 if (sc->mcr & MCR_LOOPBACK) {
431 if (rxfifo_putchar(sc, value) != 0)
432 sc->lsr |= LSR_OE;
433 } else if (sc->tty.opened) {
434 ttywrite(&sc->tty, value);
435 } /* else drop on floor */
436 sc->thre_int_pending = true;
437 break;
438 case REG_IER:
439 /* Set pending when IER_ETXRDY is raised (edge-triggered). */
440 if ((sc->ier & IER_ETXRDY) == 0 && (value & IER_ETXRDY) != 0)
441 sc->thre_int_pending = true;
442 /*
443 * Apply mask so that bits 4-7 are 0
444 * Also enables bits 0-3 only if they're 1
445 */
446 sc->ier = value & 0x0F;
447 break;
448 case REG_FCR:
449 /*
450 * When moving from FIFO and 16450 mode and vice versa,
451 * the FIFO contents are reset.
452 */
453 if ((sc->fcr & FCR_ENABLE) ^ (value & FCR_ENABLE)) {
454 fifosz = (value & FCR_ENABLE) ? FIFOSZ : 1;
455 rxfifo_reset(sc, fifosz);
456 }
457
458 /*
459 * The FCR_ENABLE bit must be '1' for the programming
460 * of other FCR bits to be effective.
461 */
462 if ((value & FCR_ENABLE) == 0) {
463 sc->fcr = 0;
464 } else {
465 if ((value & FCR_RCV_RST) != 0)
466 rxfifo_reset(sc, FIFOSZ);
467
468 sc->fcr = value &
469 (FCR_ENABLE | FCR_DMA | FCR_RX_MASK);
470 }
471 break;
472 case REG_LCR:
473 sc->lcr = value;
474 break;
475 case REG_MCR:
476 /* Apply mask so that bits 5-7 are 0 */
477 sc->mcr = value & 0x1F;
478 msr = modem_status(sc->mcr);
479
480 /*
481 * Detect if there has been any change between the
482 * previous and the new value of MSR. If there is
483 * then assert the appropriate MSR delta bit.
484 */
485 if ((msr & MSR_CTS) ^ (sc->msr & MSR_CTS))
486 sc->msr |= MSR_DCTS;
487 if ((msr & MSR_DSR) ^ (sc->msr & MSR_DSR))
488 sc->msr |= MSR_DDSR;
489 if ((msr & MSR_DCD) ^ (sc->msr & MSR_DCD))
490 sc->msr |= MSR_DDCD;
491 if ((sc->msr & MSR_RI) != 0 && (msr & MSR_RI) == 0)
492 sc->msr |= MSR_TERI;
493
494 /*
495 * Update the value of MSR while retaining the delta
496 * bits.
497 */
498 sc->msr &= MSR_DELTA_MASK;
499 sc->msr |= msr;
500 break;
501 case REG_LSR:
502 /*
503 * Line status register is not meant to be written to
504 * during normal operation.
505 */
506 break;
507 case REG_MSR:
508 /*
509 * As far as I can tell MSR is a read-only register.
510 */
511 break;
512 case REG_SCR:
513 sc->scr = value;
514 break;
515 default:
516 break;
517 }
518
519 done:
520 uart_toggle_intr(sc);
521 pthread_mutex_unlock(&sc->mtx);
522 }
523
524 uint8_t
uart_read(struct uart_softc * sc,int offset)525 uart_read(struct uart_softc *sc, int offset)
526 {
527 uint8_t iir, intr_reason, reg;
528
529 pthread_mutex_lock(&sc->mtx);
530
531 /*
532 * Take care of the special case DLAB accesses first
533 */
534 if ((sc->lcr & LCR_DLAB) != 0) {
535 if (offset == REG_DLL) {
536 reg = sc->dll;
537 goto done;
538 }
539
540 if (offset == REG_DLH) {
541 reg = sc->dlh;
542 goto done;
543 }
544 }
545
546 switch (offset) {
547 case REG_DATA:
548 reg = rxfifo_getchar(sc);
549 break;
550 case REG_IER:
551 reg = sc->ier;
552 break;
553 case REG_IIR:
554 iir = (sc->fcr & FCR_ENABLE) ? IIR_FIFO_MASK : 0;
555
556 intr_reason = uart_intr_reason(sc);
557
558 /*
559 * Deal with side effects of reading the IIR register
560 */
561 if (intr_reason == IIR_TXRDY)
562 sc->thre_int_pending = false;
563
564 iir |= intr_reason;
565
566 reg = iir;
567 break;
568 case REG_LCR:
569 reg = sc->lcr;
570 break;
571 case REG_MCR:
572 reg = sc->mcr;
573 break;
574 case REG_LSR:
575 /* Transmitter is always ready for more data */
576 sc->lsr |= LSR_TEMT | LSR_THRE;
577
578 /* Check for new receive data */
579 if (rxfifo_numchars(sc) > 0)
580 sc->lsr |= LSR_RXRDY;
581 else
582 sc->lsr &= ~LSR_RXRDY;
583
584 reg = sc->lsr;
585
586 /* The LSR_OE bit is cleared on LSR read */
587 sc->lsr &= ~LSR_OE;
588 break;
589 case REG_MSR:
590 /*
591 * MSR delta bits are cleared on read
592 */
593 reg = sc->msr;
594 sc->msr &= ~MSR_DELTA_MASK;
595 break;
596 case REG_SCR:
597 reg = sc->scr;
598 break;
599 default:
600 reg = 0xFF;
601 break;
602 }
603
604 done:
605 uart_toggle_intr(sc);
606 pthread_mutex_unlock(&sc->mtx);
607
608 return (reg);
609 }
610
611 int
uart_legacy_alloc(int which,int * baseaddr,int * irq)612 uart_legacy_alloc(int which, int *baseaddr, int *irq)
613 {
614
615 if (which < 0 || which >= (int)UART_NLDEVS || uart_lres[which].inuse)
616 return (-1);
617
618 uart_lres[which].inuse = true;
619 *baseaddr = uart_lres[which].baseaddr;
620 *irq = uart_lres[which].irq;
621
622 return (0);
623 }
624
625 struct uart_softc *
uart_init(uart_intr_func_t intr_assert,uart_intr_func_t intr_deassert,void * arg)626 uart_init(uart_intr_func_t intr_assert, uart_intr_func_t intr_deassert,
627 void *arg)
628 {
629 struct uart_softc *sc;
630
631 sc = calloc(1, sizeof(struct uart_softc));
632
633 sc->arg = arg;
634 sc->intr_assert = intr_assert;
635 sc->intr_deassert = intr_deassert;
636
637 pthread_mutex_init(&sc->mtx, NULL);
638
639 uart_reset(sc);
640
641 return (sc);
642 }
643
644 static int
uart_stdio_backend(struct uart_softc * sc)645 uart_stdio_backend(struct uart_softc *sc)
646 {
647 #ifndef WITHOUT_CAPSICUM
648 cap_rights_t rights;
649 cap_ioctl_t cmds[] = { TIOCGETA, TIOCSETA, TIOCGWINSZ };
650 #endif
651
652 if (uart_stdio)
653 return (-1);
654
655 sc->tty.rfd = STDIN_FILENO;
656 sc->tty.wfd = STDOUT_FILENO;
657 sc->tty.opened = true;
658
659 if (fcntl(sc->tty.rfd, F_SETFL, O_NONBLOCK) != 0)
660 return (-1);
661 if (fcntl(sc->tty.wfd, F_SETFL, O_NONBLOCK) != 0)
662 return (-1);
663
664 #ifndef WITHOUT_CAPSICUM
665 cap_rights_init(&rights, CAP_EVENT, CAP_IOCTL, CAP_READ);
666 if (caph_rights_limit(sc->tty.rfd, &rights) == -1)
667 errx(EX_OSERR, "Unable to apply rights for sandbox");
668 if (caph_ioctls_limit(sc->tty.rfd, cmds, nitems(cmds)) == -1)
669 errx(EX_OSERR, "Unable to apply rights for sandbox");
670 #endif
671
672 uart_stdio = true;
673
674 return (0);
675 }
676
677 static int
uart_tty_backend(struct uart_softc * sc,const char * path)678 uart_tty_backend(struct uart_softc *sc, const char *path)
679 {
680 #ifndef WITHOUT_CAPSICUM
681 cap_rights_t rights;
682 cap_ioctl_t cmds[] = { TIOCGETA, TIOCSETA, TIOCGWINSZ };
683 #endif
684 int fd;
685
686 fd = open(path, O_RDWR | O_NONBLOCK);
687 if (fd < 0)
688 return (-1);
689
690 if (!isatty(fd)) {
691 close(fd);
692 return (-1);
693 }
694
695 sc->tty.rfd = sc->tty.wfd = fd;
696 sc->tty.opened = true;
697
698 #ifndef WITHOUT_CAPSICUM
699 cap_rights_init(&rights, CAP_EVENT, CAP_IOCTL, CAP_READ, CAP_WRITE);
700 if (caph_rights_limit(fd, &rights) == -1)
701 errx(EX_OSERR, "Unable to apply rights for sandbox");
702 if (caph_ioctls_limit(fd, cmds, nitems(cmds)) == -1)
703 errx(EX_OSERR, "Unable to apply rights for sandbox");
704 #endif
705
706 return (0);
707 }
708
709 int
uart_set_backend(struct uart_softc * sc,const char * device)710 uart_set_backend(struct uart_softc *sc, const char *device)
711 {
712 int retval;
713
714 if (device == NULL)
715 return (0);
716
717 if (strcmp("stdio", device) == 0)
718 retval = uart_stdio_backend(sc);
719 else
720 retval = uart_tty_backend(sc, device);
721 if (retval == 0)
722 uart_opentty(sc);
723
724 return (retval);
725 }
726
727 #ifdef BHYVE_SNAPSHOT
728 int
uart_snapshot(struct uart_softc * sc,struct vm_snapshot_meta * meta)729 uart_snapshot(struct uart_softc *sc, struct vm_snapshot_meta *meta)
730 {
731 int ret;
732
733 SNAPSHOT_VAR_OR_LEAVE(sc->data, meta, ret, done);
734 SNAPSHOT_VAR_OR_LEAVE(sc->ier, meta, ret, done);
735 SNAPSHOT_VAR_OR_LEAVE(sc->lcr, meta, ret, done);
736 SNAPSHOT_VAR_OR_LEAVE(sc->mcr, meta, ret, done);
737 SNAPSHOT_VAR_OR_LEAVE(sc->lsr, meta, ret, done);
738 SNAPSHOT_VAR_OR_LEAVE(sc->msr, meta, ret, done);
739 SNAPSHOT_VAR_OR_LEAVE(sc->fcr, meta, ret, done);
740 SNAPSHOT_VAR_OR_LEAVE(sc->scr, meta, ret, done);
741
742 SNAPSHOT_VAR_OR_LEAVE(sc->dll, meta, ret, done);
743 SNAPSHOT_VAR_OR_LEAVE(sc->dlh, meta, ret, done);
744
745 SNAPSHOT_VAR_OR_LEAVE(sc->rxfifo.rindex, meta, ret, done);
746 SNAPSHOT_VAR_OR_LEAVE(sc->rxfifo.windex, meta, ret, done);
747 SNAPSHOT_VAR_OR_LEAVE(sc->rxfifo.num, meta, ret, done);
748 SNAPSHOT_VAR_OR_LEAVE(sc->rxfifo.size, meta, ret, done);
749 SNAPSHOT_BUF_OR_LEAVE(sc->rxfifo.buf, sizeof(sc->rxfifo.buf),
750 meta, ret, done);
751
752 sc->thre_int_pending = 1;
753
754 done:
755 return (ret);
756 }
757 #endif
758