1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2011 NetApp, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 #include <sys/param.h>
31 #ifndef WITHOUT_CAPSICUM
32 #include <sys/capsicum.h>
33 #endif
34 #include <sys/types.h>
35 #include <sys/mman.h>
36 #include <sys/pciio.h>
37 #include <sys/ioctl.h>
38 #include <sys/stat.h>
39
40 #include <dev/io/iodev.h>
41 #include <dev/pci/pcireg.h>
42
43 #include <vm/vm.h>
44
45 #include <machine/iodev.h>
46 #include <machine/vm.h>
47
48 #ifndef WITHOUT_CAPSICUM
49 #include <capsicum_helpers.h>
50 #endif
51 #include <ctype.h>
52 #include <stdio.h>
53 #include <stdlib.h>
54 #include <string.h>
55 #include <err.h>
56 #include <errno.h>
57 #include <fcntl.h>
58 #include <sysexits.h>
59 #include <unistd.h>
60
61 #include <machine/vmm.h>
62
63 #include "debug.h"
64 #include "mem.h"
65 #include "pci_passthru.h"
66
67 #ifndef _PATH_DEVPCI
68 #define _PATH_DEVPCI "/dev/pci"
69 #endif
70
71 #define LEGACY_SUPPORT 1
72
73 #define MSIX_TABLE_COUNT(ctrl) (((ctrl) & PCIM_MSIXCTRL_TABLE_SIZE) + 1)
74 #define MSIX_CAPLEN 12
75
76 #define PASSTHRU_MMIO_MAX 2
77
78 static int pcifd = -1;
79
80 SET_DECLARE(passthru_dev_set, struct passthru_dev);
81
82 struct passthru_softc {
83 struct pci_devinst *psc_pi;
84 /* ROM is handled like a BAR */
85 struct pcibar psc_bar[PCI_BARMAX_WITH_ROM + 1];
86 struct {
87 int capoff;
88 int msgctrl;
89 int emulated;
90 } psc_msi;
91 struct {
92 int capoff;
93 } psc_msix;
94 struct pcisel psc_sel;
95
96 struct passthru_mmio_mapping psc_mmio_map[PASSTHRU_MMIO_MAX];
97 cfgread_handler psc_pcir_rhandler[PCI_REGMAX + 1];
98 cfgwrite_handler psc_pcir_whandler[PCI_REGMAX + 1];
99 };
100
101 static int
msi_caplen(int msgctrl)102 msi_caplen(int msgctrl)
103 {
104 int len;
105
106 len = 10; /* minimum length of msi capability */
107
108 if (msgctrl & PCIM_MSICTRL_64BIT)
109 len += 4;
110
111 #if 0
112 /*
113 * Ignore the 'mask' and 'pending' bits in the MSI capability.
114 * We'll let the guest manipulate them directly.
115 */
116 if (msgctrl & PCIM_MSICTRL_VECTOR)
117 len += 10;
118 #endif
119
120 return (len);
121 }
122
123 static int
pcifd_init(void)124 pcifd_init(void)
125 {
126 pcifd = open(_PATH_DEVPCI, O_RDWR, 0);
127 if (pcifd < 0) {
128 warn("failed to open %s", _PATH_DEVPCI);
129 return (1);
130 }
131
132 #ifndef WITHOUT_CAPSICUM
133 cap_rights_t pcifd_rights;
134 cap_rights_init(&pcifd_rights, CAP_IOCTL, CAP_READ, CAP_WRITE);
135 if (caph_rights_limit(pcifd, &pcifd_rights) == -1)
136 errx(EX_OSERR, "Unable to apply rights for sandbox");
137
138 const cap_ioctl_t pcifd_ioctls[] = { PCIOCREAD, PCIOCWRITE, PCIOCGETBAR,
139 PCIOCBARIO, PCIOCBARMMAP, PCIOCGETCONF };
140 if (caph_ioctls_limit(pcifd, pcifd_ioctls, nitems(pcifd_ioctls)) == -1)
141 errx(EX_OSERR, "Unable to apply rights for sandbox");
142 #endif
143
144 return (0);
145 }
146
147 uint32_t
read_config(const struct pcisel * sel,long reg,int width)148 read_config(const struct pcisel *sel, long reg, int width)
149 {
150 struct pci_io pi;
151
152 if (pcifd < 0 && pcifd_init()) {
153 return (0);
154 }
155
156 bzero(&pi, sizeof(pi));
157 pi.pi_sel = *sel;
158 pi.pi_reg = reg;
159 pi.pi_width = width;
160
161 if (ioctl(pcifd, PCIOCREAD, &pi) < 0)
162 return (0); /* XXX */
163 else
164 return (pi.pi_data);
165 }
166
167 void
write_config(const struct pcisel * sel,long reg,int width,uint32_t data)168 write_config(const struct pcisel *sel, long reg, int width, uint32_t data)
169 {
170 struct pci_io pi;
171
172 if (pcifd < 0 && pcifd_init()) {
173 return;
174 }
175
176 bzero(&pi, sizeof(pi));
177 pi.pi_sel = *sel;
178 pi.pi_reg = reg;
179 pi.pi_width = width;
180 pi.pi_data = data;
181
182 (void)ioctl(pcifd, PCIOCWRITE, &pi); /* XXX */
183 }
184
185 #ifdef LEGACY_SUPPORT
186 static int
passthru_add_msicap(struct pci_devinst * pi,int msgnum,int nextptr)187 passthru_add_msicap(struct pci_devinst *pi, int msgnum, int nextptr)
188 {
189 int capoff;
190 struct msicap msicap;
191 u_char *capdata;
192
193 pci_populate_msicap(&msicap, msgnum, nextptr);
194
195 /*
196 * XXX
197 * Copy the msi capability structure in the last 16 bytes of the
198 * config space. This is wrong because it could shadow something
199 * useful to the device.
200 */
201 capoff = 256 - roundup(sizeof(msicap), 4);
202 capdata = (u_char *)&msicap;
203 for (size_t i = 0; i < sizeof(msicap); i++)
204 pci_set_cfgdata8(pi, capoff + i, capdata[i]);
205
206 return (capoff);
207 }
208 #endif /* LEGACY_SUPPORT */
209
210 static int
cfginitmsi(struct passthru_softc * sc)211 cfginitmsi(struct passthru_softc *sc)
212 {
213 int i, ptr, capptr, cap, sts, caplen, table_size;
214 uint32_t u32;
215 struct pcisel sel;
216 struct pci_devinst *pi;
217 struct msixcap msixcap;
218 char *msixcap_ptr;
219
220 pi = sc->psc_pi;
221 sel = sc->psc_sel;
222
223 /*
224 * Parse the capabilities and cache the location of the MSI
225 * and MSI-X capabilities.
226 */
227 sts = read_config(&sel, PCIR_STATUS, 2);
228 if (sts & PCIM_STATUS_CAPPRESENT) {
229 ptr = read_config(&sel, PCIR_CAP_PTR, 1);
230 while (ptr != 0 && ptr != 0xff) {
231 cap = read_config(&sel, ptr + PCICAP_ID, 1);
232 if (cap == PCIY_MSI) {
233 /*
234 * Copy the MSI capability into the config
235 * space of the emulated pci device
236 */
237 sc->psc_msi.capoff = ptr;
238 sc->psc_msi.msgctrl = read_config(&sel,
239 ptr + 2, 2);
240 sc->psc_msi.emulated = 0;
241 caplen = msi_caplen(sc->psc_msi.msgctrl);
242 capptr = ptr;
243 while (caplen > 0) {
244 u32 = read_config(&sel, capptr, 4);
245 pci_set_cfgdata32(pi, capptr, u32);
246 caplen -= 4;
247 capptr += 4;
248 }
249 } else if (cap == PCIY_MSIX) {
250 /*
251 * Copy the MSI-X capability
252 */
253 sc->psc_msix.capoff = ptr;
254 caplen = 12;
255 msixcap_ptr = (char *)&msixcap;
256 capptr = ptr;
257 while (caplen > 0) {
258 u32 = read_config(&sel, capptr, 4);
259 memcpy(msixcap_ptr, &u32, 4);
260 pci_set_cfgdata32(pi, capptr, u32);
261 caplen -= 4;
262 capptr += 4;
263 msixcap_ptr += 4;
264 }
265 }
266 ptr = read_config(&sel, ptr + PCICAP_NEXTPTR, 1);
267 }
268 }
269
270 if (sc->psc_msix.capoff != 0) {
271 pi->pi_msix.pba_bar =
272 msixcap.pba_info & PCIM_MSIX_BIR_MASK;
273 pi->pi_msix.pba_offset =
274 msixcap.pba_info & ~PCIM_MSIX_BIR_MASK;
275 pi->pi_msix.table_bar =
276 msixcap.table_info & PCIM_MSIX_BIR_MASK;
277 pi->pi_msix.table_offset =
278 msixcap.table_info & ~PCIM_MSIX_BIR_MASK;
279 pi->pi_msix.table_count = MSIX_TABLE_COUNT(msixcap.msgctrl);
280 pi->pi_msix.pba_size = PBA_SIZE(pi->pi_msix.table_count);
281
282 /* Allocate the emulated MSI-X table array */
283 table_size = pi->pi_msix.table_count * MSIX_TABLE_ENTRY_SIZE;
284 pi->pi_msix.table = calloc(1, table_size);
285
286 /* Mask all table entries */
287 for (i = 0; i < pi->pi_msix.table_count; i++) {
288 pi->pi_msix.table[i].vector_control |=
289 PCIM_MSIX_VCTRL_MASK;
290 }
291 }
292
293 #ifdef LEGACY_SUPPORT
294 /*
295 * If the passthrough device does not support MSI then craft a
296 * MSI capability for it. We link the new MSI capability at the
297 * head of the list of capabilities.
298 */
299 if ((sts & PCIM_STATUS_CAPPRESENT) != 0 && sc->psc_msi.capoff == 0) {
300 int origptr, msiptr;
301 origptr = read_config(&sel, PCIR_CAP_PTR, 1);
302 msiptr = passthru_add_msicap(pi, 1, origptr);
303 sc->psc_msi.capoff = msiptr;
304 sc->psc_msi.msgctrl = pci_get_cfgdata16(pi, msiptr + 2);
305 sc->psc_msi.emulated = 1;
306 pci_set_cfgdata8(pi, PCIR_CAP_PTR, msiptr);
307 }
308 #endif
309
310 /* Make sure one of the capabilities is present */
311 if (sc->psc_msi.capoff == 0 && sc->psc_msix.capoff == 0)
312 return (-1);
313 else
314 return (0);
315 }
316
317 static uint64_t
msix_table_read(struct passthru_softc * sc,uint64_t offset,int size)318 msix_table_read(struct passthru_softc *sc, uint64_t offset, int size)
319 {
320 struct pci_devinst *pi;
321 struct msix_table_entry *entry;
322 uint8_t *src8;
323 uint16_t *src16;
324 uint32_t *src32;
325 uint64_t *src64;
326 uint64_t data;
327 size_t entry_offset;
328 uint32_t table_offset;
329 int index, table_count;
330
331 pi = sc->psc_pi;
332
333 table_offset = pi->pi_msix.table_offset;
334 table_count = pi->pi_msix.table_count;
335 if (offset < table_offset ||
336 offset >= table_offset + table_count * MSIX_TABLE_ENTRY_SIZE) {
337 switch (size) {
338 case 1:
339 src8 = (uint8_t *)(pi->pi_msix.mapped_addr + offset);
340 data = *src8;
341 break;
342 case 2:
343 src16 = (uint16_t *)(pi->pi_msix.mapped_addr + offset);
344 data = *src16;
345 break;
346 case 4:
347 src32 = (uint32_t *)(pi->pi_msix.mapped_addr + offset);
348 data = *src32;
349 break;
350 case 8:
351 src64 = (uint64_t *)(pi->pi_msix.mapped_addr + offset);
352 data = *src64;
353 break;
354 default:
355 return (-1);
356 }
357 return (data);
358 }
359
360 offset -= table_offset;
361 index = offset / MSIX_TABLE_ENTRY_SIZE;
362 assert(index < table_count);
363
364 entry = &pi->pi_msix.table[index];
365 entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
366
367 switch (size) {
368 case 1:
369 src8 = (uint8_t *)((uint8_t *)entry + entry_offset);
370 data = *src8;
371 break;
372 case 2:
373 src16 = (uint16_t *)((uint8_t *)entry + entry_offset);
374 data = *src16;
375 break;
376 case 4:
377 src32 = (uint32_t *)((uint8_t *)entry + entry_offset);
378 data = *src32;
379 break;
380 case 8:
381 src64 = (uint64_t *)((uint8_t *)entry + entry_offset);
382 data = *src64;
383 break;
384 default:
385 return (-1);
386 }
387
388 return (data);
389 }
390
391 static void
msix_table_write(struct passthru_softc * sc,uint64_t offset,int size,uint64_t data)392 msix_table_write(struct passthru_softc *sc, uint64_t offset, int size,
393 uint64_t data)
394 {
395 struct pci_devinst *pi;
396 struct msix_table_entry *entry;
397 uint8_t *dest8;
398 uint16_t *dest16;
399 uint32_t *dest32;
400 uint64_t *dest64;
401 size_t entry_offset;
402 uint32_t table_offset, vector_control;
403 int index, table_count;
404
405 pi = sc->psc_pi;
406
407 table_offset = pi->pi_msix.table_offset;
408 table_count = pi->pi_msix.table_count;
409 if (offset < table_offset ||
410 offset >= table_offset + table_count * MSIX_TABLE_ENTRY_SIZE) {
411 switch (size) {
412 case 1:
413 dest8 = (uint8_t *)(pi->pi_msix.mapped_addr + offset);
414 *dest8 = data;
415 break;
416 case 2:
417 dest16 = (uint16_t *)(pi->pi_msix.mapped_addr + offset);
418 *dest16 = data;
419 break;
420 case 4:
421 dest32 = (uint32_t *)(pi->pi_msix.mapped_addr + offset);
422 *dest32 = data;
423 break;
424 case 8:
425 dest64 = (uint64_t *)(pi->pi_msix.mapped_addr + offset);
426 *dest64 = data;
427 break;
428 }
429 return;
430 }
431
432 offset -= table_offset;
433 index = offset / MSIX_TABLE_ENTRY_SIZE;
434 assert(index < table_count);
435
436 entry = &pi->pi_msix.table[index];
437 entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
438
439 /* Only 4 byte naturally-aligned writes are supported */
440 assert(size == 4);
441 assert(entry_offset % 4 == 0);
442
443 vector_control = entry->vector_control;
444 dest32 = (uint32_t *)((uint8_t *)entry + entry_offset);
445 *dest32 = data;
446 /* If MSI-X hasn't been enabled, do nothing */
447 if (pi->pi_msix.enabled) {
448 /* If the entry is masked, don't set it up */
449 if ((entry->vector_control & PCIM_MSIX_VCTRL_MASK) == 0 ||
450 (vector_control & PCIM_MSIX_VCTRL_MASK) == 0) {
451 (void)vm_setup_pptdev_msix(sc->psc_pi->pi_vmctx, 0,
452 sc->psc_sel.pc_bus, sc->psc_sel.pc_dev,
453 sc->psc_sel.pc_func, index, entry->addr,
454 entry->msg_data, entry->vector_control);
455 }
456 }
457 }
458
459 static int
init_msix_table(struct passthru_softc * sc)460 init_msix_table(struct passthru_softc *sc)
461 {
462 struct pci_devinst *pi = sc->psc_pi;
463 struct pci_bar_mmap pbm;
464 int b, s, f;
465 uint32_t table_size, table_offset;
466
467 assert(pci_msix_table_bar(pi) >= 0 && pci_msix_pba_bar(pi) >= 0);
468
469 b = sc->psc_sel.pc_bus;
470 s = sc->psc_sel.pc_dev;
471 f = sc->psc_sel.pc_func;
472
473 /*
474 * Map the region of the BAR containing the MSI-X table. This is
475 * necessary for two reasons:
476 * 1. The PBA may reside in the first or last page containing the MSI-X
477 * table.
478 * 2. While PCI devices are not supposed to use the page(s) containing
479 * the MSI-X table for other purposes, some do in practice.
480 */
481 memset(&pbm, 0, sizeof(pbm));
482 pbm.pbm_sel = sc->psc_sel;
483 pbm.pbm_flags = PCIIO_BAR_MMAP_RW;
484 pbm.pbm_reg = PCIR_BAR(pi->pi_msix.table_bar);
485 pbm.pbm_memattr = VM_MEMATTR_DEVICE;
486
487 if (ioctl(pcifd, PCIOCBARMMAP, &pbm) != 0) {
488 warn("Failed to map MSI-X table BAR on %d/%d/%d", b, s, f);
489 return (-1);
490 }
491 assert(pbm.pbm_bar_off == 0);
492 pi->pi_msix.mapped_addr = (uint8_t *)(uintptr_t)pbm.pbm_map_base;
493 pi->pi_msix.mapped_size = pbm.pbm_map_length;
494
495 table_offset = rounddown2(pi->pi_msix.table_offset, 4096);
496
497 table_size = pi->pi_msix.table_offset - table_offset;
498 table_size += pi->pi_msix.table_count * MSIX_TABLE_ENTRY_SIZE;
499 table_size = roundup2(table_size, 4096);
500
501 /*
502 * Unmap any pages not containing the table, we do not need to emulate
503 * accesses to them. Avoid releasing address space to help ensure that
504 * a buggy out-of-bounds access causes a crash.
505 */
506 if (table_offset != 0)
507 if (mprotect(pi->pi_msix.mapped_addr, table_offset,
508 PROT_NONE) != 0)
509 warn("Failed to unmap MSI-X table BAR region");
510 if (table_offset + table_size != pi->pi_msix.mapped_size)
511 if (mprotect(
512 pi->pi_msix.mapped_addr + table_offset + table_size,
513 pi->pi_msix.mapped_size - (table_offset + table_size),
514 PROT_NONE) != 0)
515 warn("Failed to unmap MSI-X table BAR region");
516
517 return (0);
518 }
519
520 static int
cfginitbar(struct passthru_softc * sc)521 cfginitbar(struct passthru_softc *sc)
522 {
523 int i, error;
524 struct pci_devinst *pi;
525 struct pci_bar_io bar;
526 enum pcibar_type bartype;
527 uint64_t base, size;
528
529 pi = sc->psc_pi;
530
531 /*
532 * Initialize BAR registers
533 */
534 for (i = 0; i <= PCI_BARMAX; i++) {
535 bzero(&bar, sizeof(bar));
536 bar.pbi_sel = sc->psc_sel;
537 bar.pbi_reg = PCIR_BAR(i);
538
539 if (ioctl(pcifd, PCIOCGETBAR, &bar) < 0)
540 continue;
541
542 if (PCI_BAR_IO(bar.pbi_base)) {
543 bartype = PCIBAR_IO;
544 base = bar.pbi_base & PCIM_BAR_IO_BASE;
545 } else {
546 switch (bar.pbi_base & PCIM_BAR_MEM_TYPE) {
547 case PCIM_BAR_MEM_64:
548 bartype = PCIBAR_MEM64;
549 break;
550 default:
551 bartype = PCIBAR_MEM32;
552 break;
553 }
554 base = bar.pbi_base & PCIM_BAR_MEM_BASE;
555 }
556 size = bar.pbi_length;
557
558 if (bartype != PCIBAR_IO) {
559 if (((base | size) & PAGE_MASK) != 0) {
560 warnx("passthru device %d/%d/%d BAR %d: "
561 "base %#lx or size %#lx not page aligned\n",
562 sc->psc_sel.pc_bus, sc->psc_sel.pc_dev,
563 sc->psc_sel.pc_func, i, base, size);
564 return (-1);
565 }
566 }
567
568 /* Cache information about the "real" BAR */
569 sc->psc_bar[i].type = bartype;
570 sc->psc_bar[i].size = size;
571 sc->psc_bar[i].addr = base;
572 sc->psc_bar[i].lobits = 0;
573
574 /* Allocate the BAR in the guest I/O or MMIO space */
575 error = pci_emul_alloc_bar(pi, i, bartype, size);
576 if (error)
577 return (-1);
578
579 /* Use same lobits as physical bar */
580 uint8_t lobits = read_config(&sc->psc_sel, PCIR_BAR(i), 0x01);
581 if (bartype == PCIBAR_MEM32 || bartype == PCIBAR_MEM64) {
582 lobits &= ~PCIM_BAR_MEM_BASE;
583 } else {
584 lobits &= ~PCIM_BAR_IO_BASE;
585 }
586 sc->psc_bar[i].lobits = lobits;
587 pi->pi_bar[i].lobits = lobits;
588
589 /*
590 * 64-bit BAR takes up two slots so skip the next one.
591 */
592 if (bartype == PCIBAR_MEM64) {
593 i++;
594 assert(i <= PCI_BARMAX);
595 sc->psc_bar[i].type = PCIBAR_MEMHI64;
596 }
597 }
598 return (0);
599 }
600
601 static int
cfginit(struct pci_devinst * pi,int bus,int slot,int func)602 cfginit(struct pci_devinst *pi, int bus, int slot, int func)
603 {
604 int error;
605 struct passthru_softc *sc;
606 uint8_t intline, intpin;
607
608 error = 1;
609 sc = pi->pi_arg;
610
611 bzero(&sc->psc_sel, sizeof(struct pcisel));
612 sc->psc_sel.pc_bus = bus;
613 sc->psc_sel.pc_dev = slot;
614 sc->psc_sel.pc_func = func;
615
616 /*
617 * Copy physical PCI header to virtual config space. INTLINE and INTPIN
618 * shouldn't be aligned with their physical value and they are already set by
619 * pci_emul_init().
620 */
621 intline = pci_get_cfgdata8(pi, PCIR_INTLINE);
622 intpin = pci_get_cfgdata8(pi, PCIR_INTPIN);
623 for (int i = 0; i <= PCIR_MAXLAT; i += 4) {
624 pci_set_cfgdata32(pi, i, read_config(&sc->psc_sel, i, 4));
625 }
626 pci_set_cfgdata8(pi, PCIR_INTLINE, intline);
627 pci_set_cfgdata8(pi, PCIR_INTPIN, intpin);
628
629 if (cfginitmsi(sc) != 0) {
630 warnx("failed to initialize MSI for PCI %d/%d/%d",
631 bus, slot, func);
632 goto done;
633 }
634
635 if (cfginitbar(sc) != 0) {
636 warnx("failed to initialize BARs for PCI %d/%d/%d",
637 bus, slot, func);
638 goto done;
639 }
640
641 write_config(&sc->psc_sel, PCIR_COMMAND, 2,
642 pci_get_cfgdata16(pi, PCIR_COMMAND));
643
644 /*
645 * We need to do this after PCIR_COMMAND got possibly updated, e.g.,
646 * a BAR was enabled, as otherwise the PCIOCBARMMAP might fail on us.
647 */
648 if (pci_msix_table_bar(pi) >= 0) {
649 error = init_msix_table(sc);
650 if (error != 0) {
651 warnx(
652 "failed to initialize MSI-X table for PCI %d/%d/%d: %d",
653 bus, slot, func, error);
654 goto done;
655 }
656 }
657
658 error = 0; /* success */
659 done:
660 return (error);
661 }
662
663 struct passthru_mmio_mapping *
passthru_get_mmio(struct passthru_softc * sc,int num)664 passthru_get_mmio(struct passthru_softc *sc, int num)
665 {
666 assert(sc != NULL);
667 assert(num < PASSTHRU_MMIO_MAX);
668
669 return (&sc->psc_mmio_map[num]);
670 }
671
672 struct pcisel *
passthru_get_sel(struct passthru_softc * sc)673 passthru_get_sel(struct passthru_softc *sc)
674 {
675 assert(sc != NULL);
676
677 return (&sc->psc_sel);
678 }
679
680 int
set_pcir_handler(struct passthru_softc * sc,int reg,int len,cfgread_handler rhandler,cfgwrite_handler whandler)681 set_pcir_handler(struct passthru_softc *sc, int reg, int len,
682 cfgread_handler rhandler, cfgwrite_handler whandler)
683 {
684 if (reg > PCI_REGMAX || reg + len > PCI_REGMAX + 1)
685 return (-1);
686
687 for (int i = reg; i < reg + len; ++i) {
688 assert(sc->psc_pcir_rhandler[i] == NULL || rhandler == NULL);
689 assert(sc->psc_pcir_whandler[i] == NULL || whandler == NULL);
690 sc->psc_pcir_rhandler[i] = rhandler;
691 sc->psc_pcir_whandler[i] = whandler;
692 }
693
694 return (0);
695 }
696
697 static int
passthru_legacy_config(nvlist_t * nvl,const char * opts)698 passthru_legacy_config(nvlist_t *nvl, const char *opts)
699 {
700 const char *cp;
701 char *tofree;
702 char value[16];
703 int bus, slot, func;
704
705 if (opts == NULL)
706 return (0);
707
708 cp = strchr(opts, ',');
709
710 if (strncmp(opts, "ppt", strlen("ppt")) == 0) {
711 tofree = strndup(opts, cp - opts);
712 set_config_value_node(nvl, "pptdev", tofree);
713 free(tofree);
714 } else if (sscanf(opts, "pci0:%d:%d:%d", &bus, &slot, &func) == 3 ||
715 sscanf(opts, "pci%d:%d:%d", &bus, &slot, &func) == 3 ||
716 sscanf(opts, "%d/%d/%d", &bus, &slot, &func) == 3) {
717 snprintf(value, sizeof(value), "%d", bus);
718 set_config_value_node(nvl, "bus", value);
719 snprintf(value, sizeof(value), "%d", slot);
720 set_config_value_node(nvl, "slot", value);
721 snprintf(value, sizeof(value), "%d", func);
722 set_config_value_node(nvl, "func", value);
723 } else {
724 EPRINTLN("passthru: invalid options \"%s\"", opts);
725 return (-1);
726 }
727
728 if (cp == NULL) {
729 return (0);
730 }
731
732 return (pci_parse_legacy_config(nvl, cp + 1));
733 }
734
735 static int
passthru_init_rom(struct passthru_softc * const sc,const char * const romfile)736 passthru_init_rom(struct passthru_softc *const sc, const char *const romfile)
737 {
738 if (romfile == NULL) {
739 return (0);
740 }
741
742 const int fd = open(romfile, O_RDONLY);
743 if (fd < 0) {
744 warnx("%s: can't open romfile \"%s\"", __func__, romfile);
745 return (-1);
746 }
747
748 struct stat sbuf;
749 if (fstat(fd, &sbuf) < 0) {
750 warnx("%s: can't fstat romfile \"%s\"", __func__, romfile);
751 close(fd);
752 return (-1);
753 }
754 const uint64_t rom_size = sbuf.st_size;
755
756 void *const rom_data = mmap(NULL, rom_size, PROT_READ, MAP_SHARED, fd,
757 0);
758 if (rom_data == MAP_FAILED) {
759 warnx("%s: unable to mmap romfile \"%s\" (%d)", __func__,
760 romfile, errno);
761 close(fd);
762 return (-1);
763 }
764
765 void *rom_addr;
766 int error = pci_emul_alloc_rom(sc->psc_pi, rom_size, &rom_addr);
767 if (error) {
768 warnx("%s: failed to alloc rom segment", __func__);
769 munmap(rom_data, rom_size);
770 close(fd);
771 return (error);
772 }
773 memcpy(rom_addr, rom_data, rom_size);
774
775 sc->psc_bar[PCI_ROM_IDX].type = PCIBAR_ROM;
776 sc->psc_bar[PCI_ROM_IDX].addr = (uint64_t)rom_addr;
777 sc->psc_bar[PCI_ROM_IDX].size = rom_size;
778
779 munmap(rom_data, rom_size);
780 close(fd);
781
782 return (0);
783 }
784
785 static bool
passthru_lookup_pptdev(const char * name,int * bus,int * slot,int * func)786 passthru_lookup_pptdev(const char *name, int *bus, int *slot, int *func)
787 {
788 struct pci_conf_io pc;
789 struct pci_conf conf[1];
790 struct pci_match_conf patterns[1];
791 char *cp;
792
793 bzero(&pc, sizeof(struct pci_conf_io));
794 pc.match_buf_len = sizeof(conf);
795 pc.matches = conf;
796
797 bzero(&patterns, sizeof(patterns));
798
799 /*
800 * The pattern structure requires the unit to be split out from
801 * the driver name. Walk backwards from the end of the name to
802 * find the start of the unit.
803 */
804 cp = strchr(name, '\0');
805 assert(cp != NULL);
806 while (cp != name && isdigit(cp[-1]))
807 cp--;
808 if (cp == name || !isdigit(*cp)) {
809 EPRINTLN("Invalid passthru device name %s", name);
810 return (false);
811 }
812 if ((size_t)(cp - name) + 1 > sizeof(patterns[0].pd_name)) {
813 EPRINTLN("Passthru device name %s is too long", name);
814 return (false);
815 }
816 memcpy(patterns[0].pd_name, name, cp - name);
817 patterns[0].pd_unit = strtol(cp, &cp, 10);
818 if (*cp != '\0') {
819 EPRINTLN("Invalid passthru device name %s", name);
820 return (false);
821 }
822 patterns[0].flags = PCI_GETCONF_MATCH_NAME | PCI_GETCONF_MATCH_UNIT;
823 pc.num_patterns = 1;
824 pc.pat_buf_len = sizeof(patterns);
825 pc.patterns = patterns;
826
827 if (ioctl(pcifd, PCIOCGETCONF, &pc) == -1) {
828 EPRINTLN("ioctl(PCIOCGETCONF): %s", strerror(errno));
829 return (false);
830 }
831 if (pc.status != PCI_GETCONF_LAST_DEVICE &&
832 pc.status != PCI_GETCONF_MORE_DEVS) {
833 EPRINTLN("error returned from PCIOCGETCONF ioctl");
834 return (false);
835 }
836 if (pc.num_matches == 0) {
837 EPRINTLN("Passthru device %s not found", name);
838 return (false);
839 }
840
841 if (conf[0].pc_sel.pc_domain != 0) {
842 EPRINTLN("Passthru device %s on unsupported domain", name);
843 return (false);
844 }
845 *bus = conf[0].pc_sel.pc_bus;
846 *slot = conf[0].pc_sel.pc_dev;
847 *func = conf[0].pc_sel.pc_func;
848 return (true);
849 }
850
851 static int
passthru_init(struct pci_devinst * pi,nvlist_t * nvl)852 passthru_init(struct pci_devinst *pi, nvlist_t *nvl)
853 {
854 int bus, slot, func, error, memflags;
855 struct passthru_softc *sc;
856 struct passthru_dev **devpp;
857 struct passthru_dev *devp, *dev = NULL;
858 const char *value;
859
860 sc = NULL;
861 error = 1;
862
863 memflags = vm_get_memflags(pi->pi_vmctx);
864 if (!(memflags & VM_MEM_F_WIRED)) {
865 warnx("passthru requires guest memory to be wired");
866 return (error);
867 }
868
869 if (pcifd < 0 && pcifd_init()) {
870 return (error);
871 }
872
873 #define GET_INT_CONFIG(var, name) do { \
874 value = get_config_value_node(nvl, name); \
875 if (value == NULL) { \
876 EPRINTLN("passthru: missing required %s setting", name); \
877 return (error); \
878 } \
879 var = atoi(value); \
880 } while (0)
881
882 value = get_config_value_node(nvl, "pptdev");
883 if (value != NULL) {
884 if (!passthru_lookup_pptdev(value, &bus, &slot, &func))
885 return (error);
886 } else {
887 GET_INT_CONFIG(bus, "bus");
888 GET_INT_CONFIG(slot, "slot");
889 GET_INT_CONFIG(func, "func");
890 }
891
892 if (vm_assign_pptdev(pi->pi_vmctx, bus, slot, func) != 0) {
893 warnx("PCI device at %d/%d/%d is not using the ppt(4) driver",
894 bus, slot, func);
895 goto done;
896 }
897
898 sc = calloc(1, sizeof(struct passthru_softc));
899
900 pi->pi_arg = sc;
901 sc->psc_pi = pi;
902
903 /* initialize config space */
904 if ((error = cfginit(pi, bus, slot, func)) != 0)
905 goto done;
906
907 /* initialize ROM */
908 if ((error = passthru_init_rom(sc,
909 get_config_value_node(nvl, "rom"))) != 0)
910 goto done;
911
912 /* Emulate most PCI header register. */
913 if ((error = set_pcir_handler(sc, 0, PCIR_MAXLAT + 1,
914 passthru_cfgread_emulate, passthru_cfgwrite_emulate)) != 0)
915 goto done;
916
917 /* Allow access to the physical command and status register. */
918 if ((error = set_pcir_handler(sc, PCIR_COMMAND, 0x04, NULL, NULL)) != 0)
919 goto done;
920
921 SET_FOREACH(devpp, passthru_dev_set) {
922 devp = *devpp;
923 assert(devp->probe != NULL);
924 if (devp->probe(pi) == 0) {
925 dev = devp;
926 break;
927 }
928 }
929
930 if (dev != NULL) {
931 error = dev->init(pi, nvl);
932 if (error != 0)
933 goto done;
934 }
935
936 error = 0; /* success */
937 done:
938 if (error) {
939 if (dev != NULL)
940 dev->deinit(pi);
941 free(sc);
942 vm_unassign_pptdev(pi->pi_vmctx, bus, slot, func);
943 }
944 return (error);
945 }
946
947 static int
msicap_access(struct passthru_softc * sc,int coff)948 msicap_access(struct passthru_softc *sc, int coff)
949 {
950 int caplen;
951
952 if (sc->psc_msi.capoff == 0)
953 return (0);
954
955 caplen = msi_caplen(sc->psc_msi.msgctrl);
956
957 if (coff >= sc->psc_msi.capoff && coff < sc->psc_msi.capoff + caplen)
958 return (1);
959 else
960 return (0);
961 }
962
963 static int
msixcap_access(struct passthru_softc * sc,int coff)964 msixcap_access(struct passthru_softc *sc, int coff)
965 {
966 if (sc->psc_msix.capoff == 0)
967 return (0);
968
969 return (coff >= sc->psc_msix.capoff &&
970 coff < sc->psc_msix.capoff + MSIX_CAPLEN);
971 }
972
973 static int
passthru_cfgread_default(struct passthru_softc * sc,struct pci_devinst * pi __unused,int coff,int bytes,uint32_t * rv)974 passthru_cfgread_default(struct passthru_softc *sc,
975 struct pci_devinst *pi __unused, int coff, int bytes, uint32_t *rv)
976 {
977 /*
978 * MSI capability is emulated.
979 */
980 if (msicap_access(sc, coff) || msixcap_access(sc, coff))
981 return (-1);
982
983 /*
984 * Emulate the command register. If a single read reads both the
985 * command and status registers, read the status register from the
986 * device's config space.
987 */
988 if (coff == PCIR_COMMAND) {
989 if (bytes <= 2)
990 return (-1);
991 *rv = read_config(&sc->psc_sel, PCIR_STATUS, 2) << 16 |
992 pci_get_cfgdata16(pi, PCIR_COMMAND);
993 return (0);
994 }
995
996 /* Everything else just read from the device's config space */
997 *rv = read_config(&sc->psc_sel, coff, bytes);
998
999 return (0);
1000 }
1001
1002 int
passthru_cfgread_emulate(struct passthru_softc * sc __unused,struct pci_devinst * pi __unused,int coff __unused,int bytes __unused,uint32_t * rv __unused)1003 passthru_cfgread_emulate(struct passthru_softc *sc __unused,
1004 struct pci_devinst *pi __unused, int coff __unused, int bytes __unused,
1005 uint32_t *rv __unused)
1006 {
1007 return (-1);
1008 }
1009
1010 static int
passthru_cfgread(struct pci_devinst * pi,int coff,int bytes,uint32_t * rv)1011 passthru_cfgread(struct pci_devinst *pi, int coff, int bytes, uint32_t *rv)
1012 {
1013 struct passthru_softc *sc;
1014
1015 sc = pi->pi_arg;
1016
1017 if (sc->psc_pcir_rhandler[coff] != NULL)
1018 return (sc->psc_pcir_rhandler[coff](sc, pi, coff, bytes, rv));
1019
1020 return (passthru_cfgread_default(sc, pi, coff, bytes, rv));
1021 }
1022
1023 static int
passthru_cfgwrite_default(struct passthru_softc * sc,struct pci_devinst * pi,int coff,int bytes,uint32_t val)1024 passthru_cfgwrite_default(struct passthru_softc *sc, struct pci_devinst *pi,
1025 int coff, int bytes, uint32_t val)
1026 {
1027 int error, msix_table_entries, i;
1028 uint16_t cmd_old;
1029
1030 /*
1031 * MSI capability is emulated
1032 */
1033 if (msicap_access(sc, coff)) {
1034 pci_emul_capwrite(pi, coff, bytes, val, sc->psc_msi.capoff,
1035 PCIY_MSI);
1036 error = vm_setup_pptdev_msi(pi->pi_vmctx, 0, sc->psc_sel.pc_bus,
1037 sc->psc_sel.pc_dev, sc->psc_sel.pc_func,
1038 pi->pi_msi.addr, pi->pi_msi.msg_data,
1039 pi->pi_msi.maxmsgnum);
1040 if (error != 0)
1041 err(1, "vm_setup_pptdev_msi");
1042 return (0);
1043 }
1044
1045 if (msixcap_access(sc, coff)) {
1046 pci_emul_capwrite(pi, coff, bytes, val, sc->psc_msix.capoff,
1047 PCIY_MSIX);
1048 if (pi->pi_msix.enabled) {
1049 msix_table_entries = pi->pi_msix.table_count;
1050 for (i = 0; i < msix_table_entries; i++) {
1051 error = vm_setup_pptdev_msix(pi->pi_vmctx, 0,
1052 sc->psc_sel.pc_bus, sc->psc_sel.pc_dev,
1053 sc->psc_sel.pc_func, i,
1054 pi->pi_msix.table[i].addr,
1055 pi->pi_msix.table[i].msg_data,
1056 pi->pi_msix.table[i].vector_control);
1057
1058 if (error)
1059 err(1, "vm_setup_pptdev_msix");
1060 }
1061 } else {
1062 error = vm_disable_pptdev_msix(pi->pi_vmctx,
1063 sc->psc_sel.pc_bus, sc->psc_sel.pc_dev,
1064 sc->psc_sel.pc_func);
1065 if (error)
1066 err(1, "vm_disable_pptdev_msix");
1067 }
1068 return (0);
1069 }
1070
1071 #ifdef LEGACY_SUPPORT
1072 /*
1073 * If this device does not support MSI natively then we cannot let
1074 * the guest disable legacy interrupts from the device. It is the
1075 * legacy interrupt that is triggering the virtual MSI to the guest.
1076 */
1077 if (sc->psc_msi.emulated && pci_msi_enabled(pi)) {
1078 if (coff == PCIR_COMMAND && bytes == 2)
1079 val &= ~PCIM_CMD_INTxDIS;
1080 }
1081 #endif
1082
1083 write_config(&sc->psc_sel, coff, bytes, val);
1084 if (coff == PCIR_COMMAND) {
1085 cmd_old = pci_get_cfgdata16(pi, PCIR_COMMAND);
1086 if (bytes == 1)
1087 pci_set_cfgdata8(pi, PCIR_COMMAND, val);
1088 else if (bytes == 2)
1089 pci_set_cfgdata16(pi, PCIR_COMMAND, val);
1090 pci_emul_cmd_changed(pi, cmd_old);
1091 }
1092
1093 return (0);
1094 }
1095
1096 int
passthru_cfgwrite_emulate(struct passthru_softc * sc __unused,struct pci_devinst * pi __unused,int coff __unused,int bytes __unused,uint32_t val __unused)1097 passthru_cfgwrite_emulate(struct passthru_softc *sc __unused,
1098 struct pci_devinst *pi __unused, int coff __unused, int bytes __unused,
1099 uint32_t val __unused)
1100 {
1101 return (-1);
1102 }
1103
1104 static int
passthru_cfgwrite(struct pci_devinst * pi,int coff,int bytes,uint32_t val)1105 passthru_cfgwrite(struct pci_devinst *pi, int coff, int bytes, uint32_t val)
1106 {
1107 struct passthru_softc *sc;
1108
1109 sc = pi->pi_arg;
1110
1111 if (sc->psc_pcir_whandler[coff] != NULL)
1112 return (sc->psc_pcir_whandler[coff](sc, pi, coff, bytes, val));
1113
1114 return (passthru_cfgwrite_default(sc, pi, coff, bytes, val));
1115 }
1116
1117 static void
passthru_write(struct pci_devinst * pi,int baridx,uint64_t offset,int size,uint64_t value)1118 passthru_write(struct pci_devinst *pi, int baridx, uint64_t offset, int size,
1119 uint64_t value)
1120 {
1121 struct passthru_softc *sc;
1122 struct pci_bar_ioreq pio;
1123
1124 sc = pi->pi_arg;
1125
1126 if (baridx == pci_msix_table_bar(pi)) {
1127 msix_table_write(sc, offset, size, value);
1128 } else {
1129 assert(pi->pi_bar[baridx].type == PCIBAR_IO);
1130 assert(size == 1 || size == 2 || size == 4);
1131 assert(offset <= UINT32_MAX && offset + size <= UINT32_MAX);
1132
1133 bzero(&pio, sizeof(pio));
1134 pio.pbi_sel = sc->psc_sel;
1135 pio.pbi_op = PCIBARIO_WRITE;
1136 pio.pbi_bar = baridx;
1137 pio.pbi_offset = (uint32_t)offset;
1138 pio.pbi_width = size;
1139 pio.pbi_value = (uint32_t)value;
1140
1141 (void)ioctl(pcifd, PCIOCBARIO, &pio);
1142 }
1143 }
1144
1145 static uint64_t
passthru_read(struct pci_devinst * pi,int baridx,uint64_t offset,int size)1146 passthru_read(struct pci_devinst *pi, int baridx, uint64_t offset, int size)
1147 {
1148 struct passthru_softc *sc;
1149 struct pci_bar_ioreq pio;
1150 uint64_t val;
1151
1152 sc = pi->pi_arg;
1153
1154 if (baridx == pci_msix_table_bar(pi)) {
1155 val = msix_table_read(sc, offset, size);
1156 } else {
1157 assert(pi->pi_bar[baridx].type == PCIBAR_IO);
1158 assert(size == 1 || size == 2 || size == 4);
1159 assert(offset <= UINT32_MAX && offset + size <= UINT32_MAX);
1160
1161 bzero(&pio, sizeof(pio));
1162 pio.pbi_sel = sc->psc_sel;
1163 pio.pbi_op = PCIBARIO_READ;
1164 pio.pbi_bar = baridx;
1165 pio.pbi_offset = (uint32_t)offset;
1166 pio.pbi_width = size;
1167
1168 (void)ioctl(pcifd, PCIOCBARIO, &pio);
1169
1170 val = pio.pbi_value;
1171 }
1172
1173 return (val);
1174 }
1175
1176 static void
passthru_msix_addr(struct pci_devinst * pi,int baridx,int enabled,uint64_t address)1177 passthru_msix_addr(struct pci_devinst *pi, int baridx, int enabled,
1178 uint64_t address)
1179 {
1180 struct passthru_softc *sc;
1181 size_t remaining;
1182 uint32_t table_size, table_offset;
1183
1184 sc = pi->pi_arg;
1185 table_offset = rounddown2(pi->pi_msix.table_offset, 4096);
1186 if (table_offset > 0) {
1187 if (!enabled) {
1188 if (vm_unmap_pptdev_mmio(pi->pi_vmctx,
1189 sc->psc_sel.pc_bus,
1190 sc->psc_sel.pc_dev,
1191 sc->psc_sel.pc_func, address,
1192 table_offset) != 0)
1193 warnx("pci_passthru: unmap_pptdev_mmio failed");
1194 } else {
1195 if (vm_map_pptdev_mmio(pi->pi_vmctx, sc->psc_sel.pc_bus,
1196 sc->psc_sel.pc_dev,
1197 sc->psc_sel.pc_func, address,
1198 table_offset,
1199 sc->psc_bar[baridx].addr) != 0)
1200 warnx("pci_passthru: map_pptdev_mmio failed");
1201 }
1202 }
1203 table_size = pi->pi_msix.table_offset - table_offset;
1204 table_size += pi->pi_msix.table_count * MSIX_TABLE_ENTRY_SIZE;
1205 table_size = roundup2(table_size, 4096);
1206 remaining = pi->pi_bar[baridx].size - table_offset - table_size;
1207 if (remaining > 0) {
1208 address += table_offset + table_size;
1209 if (!enabled) {
1210 if (vm_unmap_pptdev_mmio(pi->pi_vmctx,
1211 sc->psc_sel.pc_bus,
1212 sc->psc_sel.pc_dev,
1213 sc->psc_sel.pc_func, address,
1214 remaining) != 0)
1215 warnx("pci_passthru: unmap_pptdev_mmio failed");
1216 } else {
1217 if (vm_map_pptdev_mmio(pi->pi_vmctx, sc->psc_sel.pc_bus,
1218 sc->psc_sel.pc_dev,
1219 sc->psc_sel.pc_func, address,
1220 remaining,
1221 sc->psc_bar[baridx].addr +
1222 table_offset + table_size) != 0)
1223 warnx("pci_passthru: map_pptdev_mmio failed");
1224 }
1225 }
1226 }
1227
1228 static void
passthru_mmio_addr(struct pci_devinst * pi,int baridx,int enabled,uint64_t address)1229 passthru_mmio_addr(struct pci_devinst *pi, int baridx, int enabled,
1230 uint64_t address)
1231 {
1232 struct passthru_softc *sc;
1233
1234 sc = pi->pi_arg;
1235 if (!enabled) {
1236 if (vm_unmap_pptdev_mmio(pi->pi_vmctx, sc->psc_sel.pc_bus,
1237 sc->psc_sel.pc_dev,
1238 sc->psc_sel.pc_func, address,
1239 sc->psc_bar[baridx].size) != 0)
1240 warnx("pci_passthru: unmap_pptdev_mmio failed");
1241 } else {
1242 if (vm_map_pptdev_mmio(pi->pi_vmctx, sc->psc_sel.pc_bus,
1243 sc->psc_sel.pc_dev,
1244 sc->psc_sel.pc_func, address,
1245 sc->psc_bar[baridx].size,
1246 sc->psc_bar[baridx].addr) != 0)
1247 warnx("pci_passthru: map_pptdev_mmio failed");
1248 }
1249 }
1250
1251 static void
passthru_addr_rom(struct pci_devinst * const pi,const int idx,const int enabled)1252 passthru_addr_rom(struct pci_devinst *const pi, const int idx,
1253 const int enabled)
1254 {
1255 const uint64_t addr = pi->pi_bar[idx].addr;
1256 const uint64_t size = pi->pi_bar[idx].size;
1257
1258 if (!enabled) {
1259 if (vm_munmap_memseg(pi->pi_vmctx, addr, size) != 0) {
1260 errx(4, "%s: munmap_memseg @ [%016lx - %016lx] failed",
1261 __func__, addr, addr + size);
1262 }
1263
1264 } else {
1265 if (vm_mmap_memseg(pi->pi_vmctx, addr, VM_PCIROM,
1266 pi->pi_romoffset, size, PROT_READ | PROT_EXEC) != 0) {
1267 errx(4, "%s: mmap_memseg @ [%016lx - %016lx] failed",
1268 __func__, addr, addr + size);
1269 }
1270 }
1271 }
1272
1273 static void
passthru_addr(struct pci_devinst * pi,int baridx,int enabled,uint64_t address)1274 passthru_addr(struct pci_devinst *pi, int baridx, int enabled, uint64_t address)
1275 {
1276 switch (pi->pi_bar[baridx].type) {
1277 case PCIBAR_IO:
1278 /* IO BARs are emulated */
1279 break;
1280 case PCIBAR_ROM:
1281 passthru_addr_rom(pi, baridx, enabled);
1282 break;
1283 case PCIBAR_MEM32:
1284 case PCIBAR_MEM64:
1285 if (baridx == pci_msix_table_bar(pi))
1286 passthru_msix_addr(pi, baridx, enabled, address);
1287 else
1288 passthru_mmio_addr(pi, baridx, enabled, address);
1289 break;
1290 default:
1291 errx(4, "%s: invalid BAR type %d", __func__,
1292 pi->pi_bar[baridx].type);
1293 }
1294 }
1295
1296 static const struct pci_devemu passthru = {
1297 .pe_emu = "passthru",
1298 .pe_init = passthru_init,
1299 .pe_legacy_config = passthru_legacy_config,
1300 .pe_cfgwrite = passthru_cfgwrite,
1301 .pe_cfgread = passthru_cfgread,
1302 .pe_barwrite = passthru_write,
1303 .pe_barread = passthru_read,
1304 .pe_baraddr = passthru_addr,
1305 };
1306 PCI_EMUL_SET(passthru);
1307