1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
3 *
4 * Copyright (c) 2006 Michael Lorenz
5 * Copyright 2008 by Nathan Whitehorn
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The name of the author may not be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
24 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
26 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
27 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 */
32
33 #include <sys/cdefs.h>
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/module.h>
37 #include <sys/bus.h>
38 #include <sys/conf.h>
39 #include <sys/eventhandler.h>
40 #include <sys/kernel.h>
41 #include <sys/lock.h>
42 #include <sys/mutex.h>
43 #include <sys/clock.h>
44 #include <sys/reboot.h>
45
46 #include <dev/ofw/ofw_bus.h>
47 #include <dev/ofw/openfirm.h>
48
49 #include <machine/bus.h>
50 #include <machine/intr_machdep.h>
51 #include <machine/md_var.h>
52 #include <machine/pio.h>
53 #include <machine/resource.h>
54
55 #include <vm/vm.h>
56 #include <vm/pmap.h>
57
58 #include <sys/rman.h>
59
60 #include <dev/adb/adb.h>
61
62 #include "clock_if.h"
63 #include "cudavar.h"
64 #include "viareg.h"
65
66 /*
67 * MacIO interface
68 */
69 static int cuda_probe(device_t);
70 static int cuda_attach(device_t);
71 static int cuda_detach(device_t);
72
73 static u_int cuda_adb_send(device_t dev, u_char command_byte, int len,
74 u_char *data, u_char poll);
75 static u_int cuda_adb_autopoll(device_t dev, uint16_t mask);
76 static u_int cuda_poll(device_t dev);
77 static void cuda_send_inbound(struct cuda_softc *sc);
78 static void cuda_send_outbound(struct cuda_softc *sc);
79 static void cuda_shutdown(void *xsc, int howto);
80
81 /*
82 * Clock interface
83 */
84 static int cuda_gettime(device_t dev, struct timespec *ts);
85 static int cuda_settime(device_t dev, struct timespec *ts);
86
87 static device_method_t cuda_methods[] = {
88 /* Device interface */
89 DEVMETHOD(device_probe, cuda_probe),
90 DEVMETHOD(device_attach, cuda_attach),
91 DEVMETHOD(device_detach, cuda_detach),
92 DEVMETHOD(device_shutdown, bus_generic_shutdown),
93 DEVMETHOD(device_suspend, bus_generic_suspend),
94 DEVMETHOD(device_resume, bus_generic_resume),
95
96 /* ADB bus interface */
97 DEVMETHOD(adb_hb_send_raw_packet, cuda_adb_send),
98 DEVMETHOD(adb_hb_controller_poll, cuda_poll),
99 DEVMETHOD(adb_hb_set_autopoll_mask, cuda_adb_autopoll),
100
101 /* Clock interface */
102 DEVMETHOD(clock_gettime, cuda_gettime),
103 DEVMETHOD(clock_settime, cuda_settime),
104
105 DEVMETHOD_END
106 };
107
108 static driver_t cuda_driver = {
109 "cuda",
110 cuda_methods,
111 sizeof(struct cuda_softc),
112 };
113
114 static devclass_t cuda_devclass;
115
116 DRIVER_MODULE(cuda, macio, cuda_driver, cuda_devclass, 0, 0);
117 DRIVER_MODULE(adb, cuda, adb_driver, adb_devclass, 0, 0);
118
119 static void cuda_intr(void *arg);
120 static uint8_t cuda_read_reg(struct cuda_softc *sc, u_int offset);
121 static void cuda_write_reg(struct cuda_softc *sc, u_int offset, uint8_t value);
122 static void cuda_idle(struct cuda_softc *);
123 static void cuda_tip(struct cuda_softc *);
124 static void cuda_clear_tip(struct cuda_softc *);
125 static void cuda_in(struct cuda_softc *);
126 static void cuda_out(struct cuda_softc *);
127 static void cuda_toggle_ack(struct cuda_softc *);
128 static void cuda_ack_off(struct cuda_softc *);
129 static int cuda_intr_state(struct cuda_softc *);
130
131 static int
cuda_probe(device_t dev)132 cuda_probe(device_t dev)
133 {
134 const char *type = ofw_bus_get_type(dev);
135
136 if (strcmp(type, "via-cuda") != 0)
137 return (ENXIO);
138
139 device_set_desc(dev, CUDA_DEVSTR);
140 return (0);
141 }
142
143 static int
cuda_attach(device_t dev)144 cuda_attach(device_t dev)
145 {
146 struct cuda_softc *sc;
147
148 volatile int i;
149 uint8_t reg;
150 phandle_t node,child;
151
152 sc = device_get_softc(dev);
153 sc->sc_dev = dev;
154
155 sc->sc_memrid = 0;
156 sc->sc_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
157 &sc->sc_memrid, RF_ACTIVE);
158
159 if (sc->sc_memr == NULL) {
160 device_printf(dev, "Could not alloc mem resource!\n");
161 return (ENXIO);
162 }
163
164 sc->sc_irqrid = 0;
165 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_irqrid,
166 RF_ACTIVE);
167 if (sc->sc_irq == NULL) {
168 device_printf(dev, "could not allocate interrupt\n");
169 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_memrid,
170 sc->sc_memr);
171 return (ENXIO);
172 }
173
174 if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_MISC | INTR_MPSAFE
175 | INTR_ENTROPY, NULL, cuda_intr, dev, &sc->sc_ih) != 0) {
176 device_printf(dev, "could not setup interrupt\n");
177 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_memrid,
178 sc->sc_memr);
179 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irqrid,
180 sc->sc_irq);
181 return (ENXIO);
182 }
183
184 mtx_init(&sc->sc_mutex,"cuda",NULL,MTX_DEF | MTX_RECURSE);
185
186 sc->sc_sent = 0;
187 sc->sc_received = 0;
188 sc->sc_waiting = 0;
189 sc->sc_polling = 0;
190 sc->sc_state = CUDA_NOTREADY;
191 sc->sc_autopoll = 0;
192 sc->sc_rtc = -1;
193
194 STAILQ_INIT(&sc->sc_inq);
195 STAILQ_INIT(&sc->sc_outq);
196 STAILQ_INIT(&sc->sc_freeq);
197
198 for (i = 0; i < CUDA_MAXPACKETS; i++)
199 STAILQ_INSERT_TAIL(&sc->sc_freeq, &sc->sc_pkts[i], pkt_q);
200
201 /* Init CUDA */
202
203 reg = cuda_read_reg(sc, vDirB);
204 reg |= 0x30; /* register B bits 4 and 5: outputs */
205 cuda_write_reg(sc, vDirB, reg);
206
207 reg = cuda_read_reg(sc, vDirB);
208 reg &= 0xf7; /* register B bit 3: input */
209 cuda_write_reg(sc, vDirB, reg);
210
211 reg = cuda_read_reg(sc, vACR);
212 reg &= ~vSR_OUT; /* make sure SR is set to IN */
213 cuda_write_reg(sc, vACR, reg);
214
215 cuda_write_reg(sc, vACR, (cuda_read_reg(sc, vACR) | 0x0c) & ~0x10);
216
217 sc->sc_state = CUDA_IDLE; /* used by all types of hardware */
218
219 cuda_write_reg(sc, vIER, 0x84); /* make sure VIA interrupts are on */
220
221 cuda_idle(sc); /* reset ADB */
222
223 /* Reset CUDA */
224
225 i = cuda_read_reg(sc, vSR); /* clear interrupt */
226 cuda_write_reg(sc, vIER, 0x04); /* no interrupts while clearing */
227 cuda_idle(sc); /* reset state to idle */
228 DELAY(150);
229 cuda_tip(sc); /* signal start of frame */
230 DELAY(150);
231 cuda_toggle_ack(sc);
232 DELAY(150);
233 cuda_clear_tip(sc);
234 DELAY(150);
235 cuda_idle(sc); /* back to idle state */
236 i = cuda_read_reg(sc, vSR); /* clear interrupt */
237 cuda_write_reg(sc, vIER, 0x84); /* ints ok now */
238
239 /* Initialize child buses (ADB) */
240 node = ofw_bus_get_node(dev);
241
242 for (child = OF_child(node); child != 0; child = OF_peer(child)) {
243 char name[32];
244
245 memset(name, 0, sizeof(name));
246 OF_getprop(child, "name", name, sizeof(name));
247
248 if (bootverbose)
249 device_printf(dev, "CUDA child <%s>\n",name);
250
251 if (strncmp(name, "adb", 4) == 0) {
252 sc->adb_bus = device_add_child(dev,"adb",-1);
253 }
254 }
255
256 clock_register(dev, 1000);
257 EVENTHANDLER_REGISTER(shutdown_final, cuda_shutdown, sc,
258 SHUTDOWN_PRI_LAST);
259
260 return (bus_generic_attach(dev));
261 }
262
cuda_detach(device_t dev)263 static int cuda_detach(device_t dev) {
264 struct cuda_softc *sc;
265
266 sc = device_get_softc(dev);
267
268 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih);
269 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irqrid, sc->sc_irq);
270 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_memrid, sc->sc_memr);
271 mtx_destroy(&sc->sc_mutex);
272
273 return (bus_generic_detach(dev));
274 }
275
276 static uint8_t
cuda_read_reg(struct cuda_softc * sc,u_int offset)277 cuda_read_reg(struct cuda_softc *sc, u_int offset) {
278 return (bus_read_1(sc->sc_memr, offset));
279 }
280
281 static void
cuda_write_reg(struct cuda_softc * sc,u_int offset,uint8_t value)282 cuda_write_reg(struct cuda_softc *sc, u_int offset, uint8_t value) {
283 bus_write_1(sc->sc_memr, offset, value);
284 }
285
286 static void
cuda_idle(struct cuda_softc * sc)287 cuda_idle(struct cuda_softc *sc)
288 {
289 uint8_t reg;
290
291 reg = cuda_read_reg(sc, vBufB);
292 reg |= (vPB4 | vPB5);
293 cuda_write_reg(sc, vBufB, reg);
294 }
295
296 static void
cuda_tip(struct cuda_softc * sc)297 cuda_tip(struct cuda_softc *sc)
298 {
299 uint8_t reg;
300
301 reg = cuda_read_reg(sc, vBufB);
302 reg &= ~vPB5;
303 cuda_write_reg(sc, vBufB, reg);
304 }
305
306 static void
cuda_clear_tip(struct cuda_softc * sc)307 cuda_clear_tip(struct cuda_softc *sc)
308 {
309 uint8_t reg;
310
311 reg = cuda_read_reg(sc, vBufB);
312 reg |= vPB5;
313 cuda_write_reg(sc, vBufB, reg);
314 }
315
316 static void
cuda_in(struct cuda_softc * sc)317 cuda_in(struct cuda_softc *sc)
318 {
319 uint8_t reg;
320
321 reg = cuda_read_reg(sc, vACR);
322 reg &= ~vSR_OUT;
323 cuda_write_reg(sc, vACR, reg);
324 }
325
326 static void
cuda_out(struct cuda_softc * sc)327 cuda_out(struct cuda_softc *sc)
328 {
329 uint8_t reg;
330
331 reg = cuda_read_reg(sc, vACR);
332 reg |= vSR_OUT;
333 cuda_write_reg(sc, vACR, reg);
334 }
335
336 static void
cuda_toggle_ack(struct cuda_softc * sc)337 cuda_toggle_ack(struct cuda_softc *sc)
338 {
339 uint8_t reg;
340
341 reg = cuda_read_reg(sc, vBufB);
342 reg ^= vPB4;
343 cuda_write_reg(sc, vBufB, reg);
344 }
345
346 static void
cuda_ack_off(struct cuda_softc * sc)347 cuda_ack_off(struct cuda_softc *sc)
348 {
349 uint8_t reg;
350
351 reg = cuda_read_reg(sc, vBufB);
352 reg |= vPB4;
353 cuda_write_reg(sc, vBufB, reg);
354 }
355
356 static int
cuda_intr_state(struct cuda_softc * sc)357 cuda_intr_state(struct cuda_softc *sc)
358 {
359 return ((cuda_read_reg(sc, vBufB) & vPB3) == 0);
360 }
361
362 static int
cuda_send(void * cookie,int poll,int length,uint8_t * msg)363 cuda_send(void *cookie, int poll, int length, uint8_t *msg)
364 {
365 struct cuda_softc *sc = cookie;
366 device_t dev = sc->sc_dev;
367 struct cuda_packet *pkt;
368
369 if (sc->sc_state == CUDA_NOTREADY)
370 return (-1);
371
372 mtx_lock(&sc->sc_mutex);
373
374 pkt = STAILQ_FIRST(&sc->sc_freeq);
375 if (pkt == NULL) {
376 mtx_unlock(&sc->sc_mutex);
377 return (-1);
378 }
379
380 pkt->len = length - 1;
381 pkt->type = msg[0];
382 memcpy(pkt->data, &msg[1], pkt->len);
383
384 STAILQ_REMOVE_HEAD(&sc->sc_freeq, pkt_q);
385 STAILQ_INSERT_TAIL(&sc->sc_outq, pkt, pkt_q);
386
387 /*
388 * If we already are sending a packet, we should bail now that this
389 * one has been added to the queue.
390 */
391
392 if (sc->sc_waiting) {
393 mtx_unlock(&sc->sc_mutex);
394 return (0);
395 }
396
397 cuda_send_outbound(sc);
398 mtx_unlock(&sc->sc_mutex);
399
400 if (sc->sc_polling || poll || cold)
401 cuda_poll(dev);
402
403 return (0);
404 }
405
406 static void
cuda_send_outbound(struct cuda_softc * sc)407 cuda_send_outbound(struct cuda_softc *sc)
408 {
409 struct cuda_packet *pkt;
410
411 mtx_assert(&sc->sc_mutex, MA_OWNED);
412
413 pkt = STAILQ_FIRST(&sc->sc_outq);
414 if (pkt == NULL)
415 return;
416
417 sc->sc_out_length = pkt->len + 1;
418 memcpy(sc->sc_out, &pkt->type, pkt->len + 1);
419 sc->sc_sent = 0;
420
421 STAILQ_REMOVE_HEAD(&sc->sc_outq, pkt_q);
422 STAILQ_INSERT_TAIL(&sc->sc_freeq, pkt, pkt_q);
423
424 sc->sc_waiting = 1;
425
426 cuda_poll(sc->sc_dev);
427
428 DELAY(150);
429
430 if (sc->sc_state == CUDA_IDLE && !cuda_intr_state(sc)) {
431 sc->sc_state = CUDA_OUT;
432 cuda_out(sc);
433 cuda_write_reg(sc, vSR, sc->sc_out[0]);
434 cuda_ack_off(sc);
435 cuda_tip(sc);
436 }
437 }
438
439 static void
cuda_send_inbound(struct cuda_softc * sc)440 cuda_send_inbound(struct cuda_softc *sc)
441 {
442 device_t dev;
443 struct cuda_packet *pkt;
444
445 dev = sc->sc_dev;
446
447 mtx_lock(&sc->sc_mutex);
448
449 while ((pkt = STAILQ_FIRST(&sc->sc_inq)) != NULL) {
450 STAILQ_REMOVE_HEAD(&sc->sc_inq, pkt_q);
451
452 mtx_unlock(&sc->sc_mutex);
453
454 /* check if we have a handler for this message */
455 switch (pkt->type) {
456 case CUDA_ADB:
457 if (pkt->len > 2) {
458 adb_receive_raw_packet(sc->adb_bus,
459 pkt->data[0],pkt->data[1],
460 pkt->len - 2,&pkt->data[2]);
461 } else {
462 adb_receive_raw_packet(sc->adb_bus,
463 pkt->data[0],pkt->data[1],0,NULL);
464 }
465 break;
466 case CUDA_PSEUDO:
467 mtx_lock(&sc->sc_mutex);
468 switch (pkt->data[1]) {
469 case CMD_AUTOPOLL:
470 sc->sc_autopoll = 1;
471 break;
472 case CMD_READ_RTC:
473 memcpy(&sc->sc_rtc, &pkt->data[2],
474 sizeof(sc->sc_rtc));
475 wakeup(&sc->sc_rtc);
476 break;
477 case CMD_WRITE_RTC:
478 break;
479 }
480 mtx_unlock(&sc->sc_mutex);
481 break;
482 case CUDA_ERROR:
483 /*
484 * CUDA will throw errors if we miss a race between
485 * sending and receiving packets. This is already
486 * handled when we abort packet output to handle
487 * this packet in cuda_intr(). Thus, we ignore
488 * these messages.
489 */
490 break;
491 default:
492 device_printf(dev,"unknown CUDA command %d\n",
493 pkt->type);
494 break;
495 }
496
497 mtx_lock(&sc->sc_mutex);
498
499 STAILQ_INSERT_TAIL(&sc->sc_freeq, pkt, pkt_q);
500 }
501
502 mtx_unlock(&sc->sc_mutex);
503 }
504
505 static u_int
cuda_poll(device_t dev)506 cuda_poll(device_t dev)
507 {
508 struct cuda_softc *sc = device_get_softc(dev);
509
510 if (sc->sc_state == CUDA_IDLE && !cuda_intr_state(sc) &&
511 !sc->sc_waiting)
512 return (0);
513
514 cuda_intr(dev);
515 return (0);
516 }
517
518 static void
cuda_intr(void * arg)519 cuda_intr(void *arg)
520 {
521 device_t dev;
522 struct cuda_softc *sc;
523
524 int i, ending, restart_send, process_inbound;
525 uint8_t reg;
526
527 dev = (device_t)arg;
528 sc = device_get_softc(dev);
529
530 mtx_lock(&sc->sc_mutex);
531
532 restart_send = 0;
533 process_inbound = 0;
534 reg = cuda_read_reg(sc, vIFR);
535 if ((reg & vSR_INT) != vSR_INT) {
536 mtx_unlock(&sc->sc_mutex);
537 return;
538 }
539
540 cuda_write_reg(sc, vIFR, 0x7f); /* Clear interrupt */
541
542 switch_start:
543 switch (sc->sc_state) {
544 case CUDA_IDLE:
545 /*
546 * This is an unexpected packet, so grab the first (dummy)
547 * byte, set up the proper vars, and tell the chip we are
548 * starting to receive the packet by setting the TIP bit.
549 */
550 sc->sc_in[1] = cuda_read_reg(sc, vSR);
551
552 if (cuda_intr_state(sc) == 0) {
553 /* must have been a fake start */
554
555 if (sc->sc_waiting) {
556 /* start over */
557 DELAY(150);
558 sc->sc_state = CUDA_OUT;
559 sc->sc_sent = 0;
560 cuda_out(sc);
561 cuda_write_reg(sc, vSR, sc->sc_out[1]);
562 cuda_ack_off(sc);
563 cuda_tip(sc);
564 }
565 break;
566 }
567
568 cuda_in(sc);
569 cuda_tip(sc);
570
571 sc->sc_received = 1;
572 sc->sc_state = CUDA_IN;
573 break;
574
575 case CUDA_IN:
576 sc->sc_in[sc->sc_received] = cuda_read_reg(sc, vSR);
577 ending = 0;
578
579 if (sc->sc_received > 255) {
580 /* bitch only once */
581 if (sc->sc_received == 256) {
582 device_printf(dev,"input overflow\n");
583 ending = 1;
584 }
585 } else
586 sc->sc_received++;
587
588 /* intr off means this is the last byte (end of frame) */
589 if (cuda_intr_state(sc) == 0) {
590 ending = 1;
591 } else {
592 cuda_toggle_ack(sc);
593 }
594
595 if (ending == 1) { /* end of message? */
596 struct cuda_packet *pkt;
597
598 /* reset vars and signal the end of this frame */
599 cuda_idle(sc);
600
601 /* Queue up the packet */
602 pkt = STAILQ_FIRST(&sc->sc_freeq);
603 if (pkt != NULL) {
604 /* If we have a free packet, process it */
605
606 pkt->len = sc->sc_received - 2;
607 pkt->type = sc->sc_in[1];
608 memcpy(pkt->data, &sc->sc_in[2], pkt->len);
609
610 STAILQ_REMOVE_HEAD(&sc->sc_freeq, pkt_q);
611 STAILQ_INSERT_TAIL(&sc->sc_inq, pkt, pkt_q);
612
613 process_inbound = 1;
614 }
615
616 sc->sc_state = CUDA_IDLE;
617 sc->sc_received = 0;
618
619 /*
620 * If there is something waiting to be sent out,
621 * set everything up and send the first byte.
622 */
623 if (sc->sc_waiting == 1) {
624 DELAY(1500); /* required */
625 sc->sc_sent = 0;
626 sc->sc_state = CUDA_OUT;
627
628 /*
629 * If the interrupt is on, we were too slow
630 * and the chip has already started to send
631 * something to us, so back out of the write
632 * and start a read cycle.
633 */
634 if (cuda_intr_state(sc)) {
635 cuda_in(sc);
636 cuda_idle(sc);
637 sc->sc_sent = 0;
638 sc->sc_state = CUDA_IDLE;
639 sc->sc_received = 0;
640 DELAY(150);
641 goto switch_start;
642 }
643
644 /*
645 * If we got here, it's ok to start sending
646 * so load the first byte and tell the chip
647 * we want to send.
648 */
649 cuda_out(sc);
650 cuda_write_reg(sc, vSR,
651 sc->sc_out[sc->sc_sent]);
652 cuda_ack_off(sc);
653 cuda_tip(sc);
654 }
655 }
656 break;
657
658 case CUDA_OUT:
659 i = cuda_read_reg(sc, vSR); /* reset SR-intr in IFR */
660
661 sc->sc_sent++;
662 if (cuda_intr_state(sc)) { /* ADB intr low during write */
663 cuda_in(sc); /* make sure SR is set to IN */
664 cuda_idle(sc);
665 sc->sc_sent = 0; /* must start all over */
666 sc->sc_state = CUDA_IDLE; /* new state */
667 sc->sc_received = 0;
668 sc->sc_waiting = 1; /* must retry when done with
669 * read */
670 DELAY(150);
671 goto switch_start; /* process next state right
672 * now */
673 break;
674 }
675 if (sc->sc_out_length == sc->sc_sent) { /* check for done */
676 sc->sc_waiting = 0; /* done writing */
677 sc->sc_state = CUDA_IDLE; /* signal bus is idle */
678 cuda_in(sc);
679 cuda_idle(sc);
680 } else {
681 /* send next byte */
682 cuda_write_reg(sc, vSR, sc->sc_out[sc->sc_sent]);
683 cuda_toggle_ack(sc); /* signal byte ready to
684 * shift */
685 }
686 break;
687
688 case CUDA_NOTREADY:
689 break;
690
691 default:
692 break;
693 }
694
695 mtx_unlock(&sc->sc_mutex);
696
697 if (process_inbound)
698 cuda_send_inbound(sc);
699
700 mtx_lock(&sc->sc_mutex);
701 /* If we have another packet waiting, set it up */
702 if (!sc->sc_waiting && sc->sc_state == CUDA_IDLE)
703 cuda_send_outbound(sc);
704
705 mtx_unlock(&sc->sc_mutex);
706
707 }
708
709 static u_int
cuda_adb_send(device_t dev,u_char command_byte,int len,u_char * data,u_char poll)710 cuda_adb_send(device_t dev, u_char command_byte, int len, u_char *data,
711 u_char poll)
712 {
713 struct cuda_softc *sc = device_get_softc(dev);
714 uint8_t packet[16];
715 int i;
716
717 /* construct an ADB command packet and send it */
718 packet[0] = CUDA_ADB;
719 packet[1] = command_byte;
720 for (i = 0; i < len; i++)
721 packet[i + 2] = data[i];
722
723 cuda_send(sc, poll, len + 2, packet);
724
725 return (0);
726 }
727
728 static u_int
cuda_adb_autopoll(device_t dev,uint16_t mask)729 cuda_adb_autopoll(device_t dev, uint16_t mask) {
730 struct cuda_softc *sc = device_get_softc(dev);
731
732 uint8_t cmd[] = {CUDA_PSEUDO, CMD_AUTOPOLL, mask != 0};
733
734 mtx_lock(&sc->sc_mutex);
735
736 if (cmd[2] == sc->sc_autopoll) {
737 mtx_unlock(&sc->sc_mutex);
738 return (0);
739 }
740
741 sc->sc_autopoll = -1;
742 cuda_send(sc, 1, 3, cmd);
743
744 mtx_unlock(&sc->sc_mutex);
745
746 return (0);
747 }
748
749 static void
cuda_shutdown(void * xsc,int howto)750 cuda_shutdown(void *xsc, int howto)
751 {
752 struct cuda_softc *sc = xsc;
753 uint8_t cmd[] = {CUDA_PSEUDO, 0};
754
755 cmd[1] = (howto & RB_HALT) ? CMD_POWEROFF : CMD_RESET;
756 cuda_poll(sc->sc_dev);
757 cuda_send(sc, 1, 2, cmd);
758
759 while (1)
760 cuda_poll(sc->sc_dev);
761 }
762
763 #define DIFF19041970 2082844800
764
765 static int
cuda_gettime(device_t dev,struct timespec * ts)766 cuda_gettime(device_t dev, struct timespec *ts)
767 {
768 struct cuda_softc *sc = device_get_softc(dev);
769 uint8_t cmd[] = {CUDA_PSEUDO, CMD_READ_RTC};
770
771 mtx_lock(&sc->sc_mutex);
772 sc->sc_rtc = -1;
773 cuda_send(sc, 1, 2, cmd);
774 if (sc->sc_rtc == -1)
775 mtx_sleep(&sc->sc_rtc, &sc->sc_mutex, 0, "rtc", 100);
776
777 ts->tv_sec = sc->sc_rtc - DIFF19041970;
778 ts->tv_nsec = 0;
779 mtx_unlock(&sc->sc_mutex);
780
781 return (0);
782 }
783
784 static int
cuda_settime(device_t dev,struct timespec * ts)785 cuda_settime(device_t dev, struct timespec *ts)
786 {
787 struct cuda_softc *sc = device_get_softc(dev);
788 uint8_t cmd[] = {CUDA_PSEUDO, CMD_WRITE_RTC, 0, 0, 0, 0};
789 uint32_t sec;
790
791 sec = ts->tv_sec + DIFF19041970;
792 memcpy(&cmd[2], &sec, sizeof(sec));
793
794 mtx_lock(&sc->sc_mutex);
795 cuda_send(sc, 0, 6, cmd);
796 mtx_unlock(&sc->sc_mutex);
797
798 return (0);
799 }
800