1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com>
5 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com>
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
22 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
23 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
26 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Some hw specific parts of this pmap were derived or influenced
29 * by NetBSD's ibm4xx pmap module. More generic code is shared with
30 * a few other pmap modules from the FreeBSD tree.
31 */
32
33 /*
34 * VM layout notes:
35 *
36 * Kernel and user threads run within one common virtual address space
37 * defined by AS=0.
38 *
39 * 32-bit pmap:
40 * Virtual address space layout:
41 * -----------------------------
42 * 0x0000_0000 - 0x7fff_ffff : user process
43 * 0x8000_0000 - 0xbfff_ffff : pmap_mapdev()-ed area (PCI/PCIE etc.)
44 * 0xc000_0000 - 0xc0ff_ffff : kernel reserved
45 * 0xc000_0000 - data_end : kernel code+data, env, metadata etc.
46 * 0xc100_0000 - 0xffff_ffff : KVA
47 * 0xc100_0000 - 0xc100_3fff : reserved for page zero/copy
48 * 0xc100_4000 - 0xc200_3fff : reserved for ptbl bufs
49 * 0xc200_4000 - 0xc200_8fff : guard page + kstack0
50 * 0xc200_9000 - 0xfeef_ffff : actual free KVA space
51 *
52 * 64-bit pmap:
53 * Virtual address space layout:
54 * -----------------------------
55 * 0x0000_0000_0000_0000 - 0xbfff_ffff_ffff_ffff : user process
56 * 0x0000_0000_0000_0000 - 0x8fff_ffff_ffff_ffff : text, data, heap, maps, libraries
57 * 0x9000_0000_0000_0000 - 0xafff_ffff_ffff_ffff : mmio region
58 * 0xb000_0000_0000_0000 - 0xbfff_ffff_ffff_ffff : stack
59 * 0xc000_0000_0000_0000 - 0xcfff_ffff_ffff_ffff : kernel reserved
60 * 0xc000_0000_0000_0000 - endkernel-1 : kernel code & data
61 * endkernel - msgbufp-1 : flat device tree
62 * msgbufp - kernel_pdir-1 : message buffer
63 * kernel_pdir - kernel_pp2d-1 : kernel page directory
64 * kernel_pp2d - . : kernel pointers to page directory
65 * pmap_zero_copy_min - crashdumpmap-1 : reserved for page zero/copy
66 * crashdumpmap - ptbl_buf_pool_vabase-1 : reserved for ptbl bufs
67 * ptbl_buf_pool_vabase - virtual_avail-1 : user page directories and page tables
68 * virtual_avail - 0xcfff_ffff_ffff_ffff : actual free KVA space
69 * 0xd000_0000_0000_0000 - 0xdfff_ffff_ffff_ffff : coprocessor region
70 * 0xe000_0000_0000_0000 - 0xefff_ffff_ffff_ffff : mmio region
71 * 0xf000_0000_0000_0000 - 0xffff_ffff_ffff_ffff : direct map
72 * 0xf000_0000_0000_0000 - +Maxmem : physmem map
73 * - 0xffff_ffff_ffff_ffff : device direct map
74 */
75
76 #include <sys/cdefs.h>
77 #include "opt_ddb.h"
78 #include "opt_kstack_pages.h"
79
80 #include <sys/param.h>
81 #include <sys/conf.h>
82 #include <sys/malloc.h>
83 #include <sys/ktr.h>
84 #include <sys/proc.h>
85 #include <sys/user.h>
86 #include <sys/queue.h>
87 #include <sys/systm.h>
88 #include <sys/kernel.h>
89 #include <sys/kerneldump.h>
90 #include <sys/linker.h>
91 #include <sys/msgbuf.h>
92 #include <sys/lock.h>
93 #include <sys/mutex.h>
94 #include <sys/rwlock.h>
95 #include <sys/sched.h>
96 #include <sys/smp.h>
97 #include <sys/vmmeter.h>
98
99 #include <vm/vm.h>
100 #include <vm/vm_param.h>
101 #include <vm/vm_page.h>
102 #include <vm/vm_kern.h>
103 #include <vm/vm_pageout.h>
104 #include <vm/vm_extern.h>
105 #include <vm/vm_object.h>
106 #include <vm/vm_map.h>
107 #include <vm/vm_pager.h>
108 #include <vm/vm_phys.h>
109 #include <vm/vm_pagequeue.h>
110 #include <vm/vm_dumpset.h>
111 #include <vm/uma.h>
112
113 #include <machine/_inttypes.h>
114 #include <machine/cpu.h>
115 #include <machine/pcb.h>
116 #include <machine/platform.h>
117
118 #include <machine/tlb.h>
119 #include <machine/spr.h>
120 #include <machine/md_var.h>
121 #include <machine/mmuvar.h>
122 #include <machine/pmap.h>
123 #include <machine/pte.h>
124
125 #include <ddb/ddb.h>
126
127 #define SPARSE_MAPDEV
128
129 /* Use power-of-two mappings in mmu_booke_mapdev(), to save entries. */
130 #define POW2_MAPPINGS
131
132 #ifdef DEBUG
133 #define debugf(fmt, args...) printf(fmt, ##args)
134 #else
135 #define debugf(fmt, args...)
136 #endif
137
138 #ifdef __powerpc64__
139 #define PRI0ptrX "016lx"
140 #else
141 #define PRI0ptrX "08x"
142 #endif
143
144 #define TODO panic("%s: not implemented", __func__);
145
146 extern unsigned char _etext[];
147 extern unsigned char _end[];
148
149 extern uint32_t *bootinfo;
150
151 vm_paddr_t kernload;
152 vm_offset_t kernstart;
153 vm_size_t kernsize;
154
155 /* Message buffer and tables. */
156 static vm_offset_t data_start;
157 static vm_size_t data_end;
158
159 /* Phys/avail memory regions. */
160 static struct mem_region *availmem_regions;
161 static int availmem_regions_sz;
162 static struct mem_region *physmem_regions;
163 static int physmem_regions_sz;
164
165 #ifndef __powerpc64__
166 /* Reserved KVA space and mutex for mmu_booke_zero_page. */
167 static vm_offset_t zero_page_va;
168 static struct mtx zero_page_mutex;
169
170 /* Reserved KVA space and mutex for mmu_booke_copy_page. */
171 static vm_offset_t copy_page_src_va;
172 static vm_offset_t copy_page_dst_va;
173 static struct mtx copy_page_mutex;
174 #endif
175
176 static struct mtx tlbivax_mutex;
177
178 /**************************************************************************/
179 /* PMAP */
180 /**************************************************************************/
181
182 static int mmu_booke_enter_locked(pmap_t, vm_offset_t, vm_page_t,
183 vm_prot_t, u_int flags, int8_t psind);
184
185 unsigned int kptbl_min; /* Index of the first kernel ptbl. */
186 static uma_zone_t ptbl_root_zone;
187
188 /*
189 * If user pmap is processed with mmu_booke_remove and the resident count
190 * drops to 0, there are no more pages to remove, so we need not continue.
191 */
192 #define PMAP_REMOVE_DONE(pmap) \
193 ((pmap) != kernel_pmap && (pmap)->pm_stats.resident_count == 0)
194
195 #if defined(COMPAT_FREEBSD32) || !defined(__powerpc64__)
196 extern int elf32_nxstack;
197 #endif
198
199 /**************************************************************************/
200 /* TLB and TID handling */
201 /**************************************************************************/
202
203 /* Translation ID busy table */
204 static volatile pmap_t tidbusy[MAXCPU][TID_MAX + 1];
205
206 /*
207 * TLB0 capabilities (entry, way numbers etc.). These can vary between e500
208 * core revisions and should be read from h/w registers during early config.
209 */
210 uint32_t tlb0_entries;
211 uint32_t tlb0_ways;
212 uint32_t tlb0_entries_per_way;
213 uint32_t tlb1_entries;
214
215 #define TLB0_ENTRIES (tlb0_entries)
216 #define TLB0_WAYS (tlb0_ways)
217 #define TLB0_ENTRIES_PER_WAY (tlb0_entries_per_way)
218
219 #define TLB1_ENTRIES (tlb1_entries)
220
221 static tlbtid_t tid_alloc(struct pmap *);
222
223 #ifdef DDB
224 #ifdef __powerpc64__
225 static void tlb_print_entry(int, uint32_t, uint64_t, uint32_t, uint32_t);
226 #else
227 static void tlb_print_entry(int, uint32_t, uint32_t, uint32_t, uint32_t);
228 #endif
229 #endif
230
231 static void tlb1_read_entry(tlb_entry_t *, unsigned int);
232 static void tlb1_write_entry(tlb_entry_t *, unsigned int);
233 static int tlb1_iomapped(int, vm_paddr_t, vm_size_t, vm_offset_t *);
234 static vm_size_t tlb1_mapin_region(vm_offset_t, vm_paddr_t, vm_size_t, int);
235
236 static __inline uint32_t tlb_calc_wimg(vm_paddr_t pa, vm_memattr_t ma);
237
238 static vm_size_t tsize2size(unsigned int);
239 static unsigned int size2tsize(vm_size_t);
240 static unsigned long ilog2(unsigned long);
241
242 static void set_mas4_defaults(void);
243
244 static inline void tlb0_flush_entry(vm_offset_t);
245 static inline unsigned int tlb0_tableidx(vm_offset_t, unsigned int);
246
247 /**************************************************************************/
248 /* Page table management */
249 /**************************************************************************/
250
251 static struct rwlock_padalign pvh_global_lock;
252
253 /* Data for the pv entry allocation mechanism */
254 static uma_zone_t pvzone;
255 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
256
257 #define PV_ENTRY_ZONE_MIN 2048 /* min pv entries in uma zone */
258
259 #ifndef PMAP_SHPGPERPROC
260 #define PMAP_SHPGPERPROC 200
261 #endif
262
263 static vm_paddr_t pte_vatopa(pmap_t, vm_offset_t);
264 static int pte_enter(pmap_t, vm_page_t, vm_offset_t, uint32_t, boolean_t);
265 static int pte_remove(pmap_t, vm_offset_t, uint8_t);
266 static pte_t *pte_find(pmap_t, vm_offset_t);
267 static void kernel_pte_alloc(vm_offset_t, vm_offset_t);
268
269 static pv_entry_t pv_alloc(void);
270 static void pv_free(pv_entry_t);
271 static void pv_insert(pmap_t, vm_offset_t, vm_page_t);
272 static void pv_remove(pmap_t, vm_offset_t, vm_page_t);
273
274 static void booke_pmap_init_qpages(void);
275
276 static inline void tlb_miss_lock(void);
277 static inline void tlb_miss_unlock(void);
278
279 #ifdef SMP
280 extern tlb_entry_t __boot_tlb1[];
281 void pmap_bootstrap_ap(volatile uint32_t *);
282 #endif
283
284 /*
285 * Kernel MMU interface
286 */
287 static void mmu_booke_clear_modify(vm_page_t);
288 static void mmu_booke_copy(pmap_t, pmap_t, vm_offset_t,
289 vm_size_t, vm_offset_t);
290 static void mmu_booke_copy_page(vm_page_t, vm_page_t);
291 static void mmu_booke_copy_pages(vm_page_t *,
292 vm_offset_t, vm_page_t *, vm_offset_t, int);
293 static int mmu_booke_enter(pmap_t, vm_offset_t, vm_page_t,
294 vm_prot_t, u_int flags, int8_t psind);
295 static void mmu_booke_enter_object(pmap_t, vm_offset_t, vm_offset_t,
296 vm_page_t, vm_prot_t);
297 static void mmu_booke_enter_quick(pmap_t, vm_offset_t, vm_page_t,
298 vm_prot_t);
299 static vm_paddr_t mmu_booke_extract(pmap_t, vm_offset_t);
300 static vm_page_t mmu_booke_extract_and_hold(pmap_t, vm_offset_t,
301 vm_prot_t);
302 static void mmu_booke_init(void);
303 static boolean_t mmu_booke_is_modified(vm_page_t);
304 static boolean_t mmu_booke_is_prefaultable(pmap_t, vm_offset_t);
305 static boolean_t mmu_booke_is_referenced(vm_page_t);
306 static int mmu_booke_ts_referenced(vm_page_t);
307 static vm_offset_t mmu_booke_map(vm_offset_t *, vm_paddr_t, vm_paddr_t,
308 int);
309 static int mmu_booke_mincore(pmap_t, vm_offset_t,
310 vm_paddr_t *);
311 static void mmu_booke_object_init_pt(pmap_t, vm_offset_t,
312 vm_object_t, vm_pindex_t, vm_size_t);
313 static boolean_t mmu_booke_page_exists_quick(pmap_t, vm_page_t);
314 static void mmu_booke_page_init(vm_page_t);
315 static int mmu_booke_page_wired_mappings(vm_page_t);
316 static int mmu_booke_pinit(pmap_t);
317 static void mmu_booke_pinit0(pmap_t);
318 static void mmu_booke_protect(pmap_t, vm_offset_t, vm_offset_t,
319 vm_prot_t);
320 static void mmu_booke_qenter(vm_offset_t, vm_page_t *, int);
321 static void mmu_booke_qremove(vm_offset_t, int);
322 static void mmu_booke_release(pmap_t);
323 static void mmu_booke_remove(pmap_t, vm_offset_t, vm_offset_t);
324 static void mmu_booke_remove_all(vm_page_t);
325 static void mmu_booke_remove_write(vm_page_t);
326 static void mmu_booke_unwire(pmap_t, vm_offset_t, vm_offset_t);
327 static void mmu_booke_zero_page(vm_page_t);
328 static void mmu_booke_zero_page_area(vm_page_t, int, int);
329 static void mmu_booke_activate(struct thread *);
330 static void mmu_booke_deactivate(struct thread *);
331 static void mmu_booke_bootstrap(vm_offset_t, vm_offset_t);
332 static void *mmu_booke_mapdev(vm_paddr_t, vm_size_t);
333 static void *mmu_booke_mapdev_attr(vm_paddr_t, vm_size_t, vm_memattr_t);
334 static void mmu_booke_unmapdev(vm_offset_t, vm_size_t);
335 static vm_paddr_t mmu_booke_kextract(vm_offset_t);
336 static void mmu_booke_kenter(vm_offset_t, vm_paddr_t);
337 static void mmu_booke_kenter_attr(vm_offset_t, vm_paddr_t, vm_memattr_t);
338 static void mmu_booke_kremove(vm_offset_t);
339 static int mmu_booke_dev_direct_mapped(vm_paddr_t, vm_size_t);
340 static void mmu_booke_sync_icache(pmap_t, vm_offset_t,
341 vm_size_t);
342 static void mmu_booke_dumpsys_map(vm_paddr_t pa, size_t,
343 void **);
344 static void mmu_booke_dumpsys_unmap(vm_paddr_t pa, size_t,
345 void *);
346 static void mmu_booke_scan_init(void);
347 static vm_offset_t mmu_booke_quick_enter_page(vm_page_t m);
348 static void mmu_booke_quick_remove_page(vm_offset_t addr);
349 static int mmu_booke_change_attr(vm_offset_t addr,
350 vm_size_t sz, vm_memattr_t mode);
351 static int mmu_booke_decode_kernel_ptr(vm_offset_t addr,
352 int *is_user, vm_offset_t *decoded_addr);
353 static void mmu_booke_page_array_startup(long);
354 static boolean_t mmu_booke_page_is_mapped(vm_page_t m);
355 static bool mmu_booke_ps_enabled(pmap_t pmap);
356
357 static struct pmap_funcs mmu_booke_methods = {
358 /* pmap dispatcher interface */
359 .clear_modify = mmu_booke_clear_modify,
360 .copy = mmu_booke_copy,
361 .copy_page = mmu_booke_copy_page,
362 .copy_pages = mmu_booke_copy_pages,
363 .enter = mmu_booke_enter,
364 .enter_object = mmu_booke_enter_object,
365 .enter_quick = mmu_booke_enter_quick,
366 .extract = mmu_booke_extract,
367 .extract_and_hold = mmu_booke_extract_and_hold,
368 .init = mmu_booke_init,
369 .is_modified = mmu_booke_is_modified,
370 .is_prefaultable = mmu_booke_is_prefaultable,
371 .is_referenced = mmu_booke_is_referenced,
372 .ts_referenced = mmu_booke_ts_referenced,
373 .map = mmu_booke_map,
374 .mincore = mmu_booke_mincore,
375 .object_init_pt = mmu_booke_object_init_pt,
376 .page_exists_quick = mmu_booke_page_exists_quick,
377 .page_init = mmu_booke_page_init,
378 .page_wired_mappings = mmu_booke_page_wired_mappings,
379 .pinit = mmu_booke_pinit,
380 .pinit0 = mmu_booke_pinit0,
381 .protect = mmu_booke_protect,
382 .qenter = mmu_booke_qenter,
383 .qremove = mmu_booke_qremove,
384 .release = mmu_booke_release,
385 .remove = mmu_booke_remove,
386 .remove_all = mmu_booke_remove_all,
387 .remove_write = mmu_booke_remove_write,
388 .sync_icache = mmu_booke_sync_icache,
389 .unwire = mmu_booke_unwire,
390 .zero_page = mmu_booke_zero_page,
391 .zero_page_area = mmu_booke_zero_page_area,
392 .activate = mmu_booke_activate,
393 .deactivate = mmu_booke_deactivate,
394 .quick_enter_page = mmu_booke_quick_enter_page,
395 .quick_remove_page = mmu_booke_quick_remove_page,
396 .page_array_startup = mmu_booke_page_array_startup,
397 .page_is_mapped = mmu_booke_page_is_mapped,
398 .ps_enabled = mmu_booke_ps_enabled,
399
400 /* Internal interfaces */
401 .bootstrap = mmu_booke_bootstrap,
402 .dev_direct_mapped = mmu_booke_dev_direct_mapped,
403 .mapdev = mmu_booke_mapdev,
404 .mapdev_attr = mmu_booke_mapdev_attr,
405 .kenter = mmu_booke_kenter,
406 .kenter_attr = mmu_booke_kenter_attr,
407 .kextract = mmu_booke_kextract,
408 .kremove = mmu_booke_kremove,
409 .unmapdev = mmu_booke_unmapdev,
410 .change_attr = mmu_booke_change_attr,
411 .decode_kernel_ptr = mmu_booke_decode_kernel_ptr,
412
413 /* dumpsys() support */
414 .dumpsys_map_chunk = mmu_booke_dumpsys_map,
415 .dumpsys_unmap_chunk = mmu_booke_dumpsys_unmap,
416 .dumpsys_pa_init = mmu_booke_scan_init,
417 };
418
419 MMU_DEF(booke_mmu, MMU_TYPE_BOOKE, mmu_booke_methods);
420
421 #ifdef __powerpc64__
422 #include "pmap_64.c"
423 #else
424 #include "pmap_32.c"
425 #endif
426
427 static vm_offset_t tlb1_map_base = VM_MAPDEV_BASE;
428
429 static __inline uint32_t
tlb_calc_wimg(vm_paddr_t pa,vm_memattr_t ma)430 tlb_calc_wimg(vm_paddr_t pa, vm_memattr_t ma)
431 {
432 uint32_t attrib;
433 int i;
434
435 if (ma != VM_MEMATTR_DEFAULT) {
436 switch (ma) {
437 case VM_MEMATTR_UNCACHEABLE:
438 return (MAS2_I | MAS2_G);
439 case VM_MEMATTR_WRITE_COMBINING:
440 case VM_MEMATTR_WRITE_BACK:
441 case VM_MEMATTR_PREFETCHABLE:
442 return (MAS2_I);
443 case VM_MEMATTR_WRITE_THROUGH:
444 return (MAS2_W | MAS2_M);
445 case VM_MEMATTR_CACHEABLE:
446 return (MAS2_M);
447 }
448 }
449
450 /*
451 * Assume the page is cache inhibited and access is guarded unless
452 * it's in our available memory array.
453 */
454 attrib = _TLB_ENTRY_IO;
455 for (i = 0; i < physmem_regions_sz; i++) {
456 if ((pa >= physmem_regions[i].mr_start) &&
457 (pa < (physmem_regions[i].mr_start +
458 physmem_regions[i].mr_size))) {
459 attrib = _TLB_ENTRY_MEM;
460 break;
461 }
462 }
463
464 return (attrib);
465 }
466
467 static inline void
tlb_miss_lock(void)468 tlb_miss_lock(void)
469 {
470 #ifdef SMP
471 struct pcpu *pc;
472
473 if (!smp_started)
474 return;
475
476 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
477 if (pc != pcpup) {
478 CTR3(KTR_PMAP, "%s: tlb miss LOCK of CPU=%d, "
479 "tlb_lock=%p", __func__, pc->pc_cpuid, pc->pc_booke.tlb_lock);
480
481 KASSERT((pc->pc_cpuid != PCPU_GET(cpuid)),
482 ("tlb_miss_lock: tried to lock self"));
483
484 tlb_lock(pc->pc_booke.tlb_lock);
485
486 CTR1(KTR_PMAP, "%s: locked", __func__);
487 }
488 }
489 #endif
490 }
491
492 static inline void
tlb_miss_unlock(void)493 tlb_miss_unlock(void)
494 {
495 #ifdef SMP
496 struct pcpu *pc;
497
498 if (!smp_started)
499 return;
500
501 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
502 if (pc != pcpup) {
503 CTR2(KTR_PMAP, "%s: tlb miss UNLOCK of CPU=%d",
504 __func__, pc->pc_cpuid);
505
506 tlb_unlock(pc->pc_booke.tlb_lock);
507
508 CTR1(KTR_PMAP, "%s: unlocked", __func__);
509 }
510 }
511 #endif
512 }
513
514 /* Return number of entries in TLB0. */
515 static __inline void
tlb0_get_tlbconf(void)516 tlb0_get_tlbconf(void)
517 {
518 uint32_t tlb0_cfg;
519
520 tlb0_cfg = mfspr(SPR_TLB0CFG);
521 tlb0_entries = tlb0_cfg & TLBCFG_NENTRY_MASK;
522 tlb0_ways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT;
523 tlb0_entries_per_way = tlb0_entries / tlb0_ways;
524 }
525
526 /* Return number of entries in TLB1. */
527 static __inline void
tlb1_get_tlbconf(void)528 tlb1_get_tlbconf(void)
529 {
530 uint32_t tlb1_cfg;
531
532 tlb1_cfg = mfspr(SPR_TLB1CFG);
533 tlb1_entries = tlb1_cfg & TLBCFG_NENTRY_MASK;
534 }
535
536 /**************************************************************************/
537 /* Page table related */
538 /**************************************************************************/
539
540 /* Allocate pv_entry structure. */
541 pv_entry_t
pv_alloc(void)542 pv_alloc(void)
543 {
544 pv_entry_t pv;
545
546 pv_entry_count++;
547 if (pv_entry_count > pv_entry_high_water)
548 pagedaemon_wakeup(0); /* XXX powerpc NUMA */
549 pv = uma_zalloc(pvzone, M_NOWAIT);
550
551 return (pv);
552 }
553
554 /* Free pv_entry structure. */
555 static __inline void
pv_free(pv_entry_t pve)556 pv_free(pv_entry_t pve)
557 {
558
559 pv_entry_count--;
560 uma_zfree(pvzone, pve);
561 }
562
563 /* Allocate and initialize pv_entry structure. */
564 static void
pv_insert(pmap_t pmap,vm_offset_t va,vm_page_t m)565 pv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m)
566 {
567 pv_entry_t pve;
568
569 //int su = (pmap == kernel_pmap);
570 //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su,
571 // (u_int32_t)pmap, va, (u_int32_t)m);
572
573 pve = pv_alloc();
574 if (pve == NULL)
575 panic("pv_insert: no pv entries!");
576
577 pve->pv_pmap = pmap;
578 pve->pv_va = va;
579
580 /* add to pv_list */
581 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
582 rw_assert(&pvh_global_lock, RA_WLOCKED);
583
584 TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link);
585
586 //debugf("pv_insert: e\n");
587 }
588
589 /* Destroy pv entry. */
590 static void
pv_remove(pmap_t pmap,vm_offset_t va,vm_page_t m)591 pv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m)
592 {
593 pv_entry_t pve;
594
595 //int su = (pmap == kernel_pmap);
596 //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va);
597
598 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
599 rw_assert(&pvh_global_lock, RA_WLOCKED);
600
601 /* find pv entry */
602 TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) {
603 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) {
604 /* remove from pv_list */
605 TAILQ_REMOVE(&m->md.pv_list, pve, pv_link);
606 if (TAILQ_EMPTY(&m->md.pv_list))
607 vm_page_aflag_clear(m, PGA_WRITEABLE);
608
609 /* free pv entry struct */
610 pv_free(pve);
611 break;
612 }
613 }
614
615 //debugf("pv_remove: e\n");
616 }
617
618 /**************************************************************************/
619 /* PMAP related */
620 /**************************************************************************/
621
622 /*
623 * This is called during booke_init, before the system is really initialized.
624 */
625 static void
mmu_booke_bootstrap(vm_offset_t start,vm_offset_t kernelend)626 mmu_booke_bootstrap(vm_offset_t start, vm_offset_t kernelend)
627 {
628 vm_paddr_t phys_kernelend;
629 struct mem_region *mp, *mp1;
630 int cnt, i, j;
631 vm_paddr_t s, e, sz;
632 vm_paddr_t physsz, hwphyssz;
633 u_int phys_avail_count;
634 vm_size_t kstack0_sz;
635 vm_paddr_t kstack0_phys;
636 vm_offset_t kstack0;
637 void *dpcpu;
638
639 debugf("mmu_booke_bootstrap: entered\n");
640
641 /* Set interesting system properties */
642 #ifdef __powerpc64__
643 hw_direct_map = 1;
644 #else
645 hw_direct_map = 0;
646 #endif
647 #if defined(COMPAT_FREEBSD32) || !defined(__powerpc64__)
648 elf32_nxstack = 1;
649 #endif
650
651 /* Initialize invalidation mutex */
652 mtx_init(&tlbivax_mutex, "tlbivax", NULL, MTX_SPIN);
653
654 /* Read TLB0 size and associativity. */
655 tlb0_get_tlbconf();
656
657 /*
658 * Align kernel start and end address (kernel image).
659 * Note that kernel end does not necessarily relate to kernsize.
660 * kernsize is the size of the kernel that is actually mapped.
661 */
662 data_start = round_page(kernelend);
663 data_end = data_start;
664
665 /* Allocate the dynamic per-cpu area. */
666 dpcpu = (void *)data_end;
667 data_end += DPCPU_SIZE;
668
669 /* Allocate space for the message buffer. */
670 msgbufp = (struct msgbuf *)data_end;
671 data_end += msgbufsize;
672 debugf(" msgbufp at 0x%"PRI0ptrX" end = 0x%"PRI0ptrX"\n",
673 (uintptr_t)msgbufp, data_end);
674
675 data_end = round_page(data_end);
676 data_end = round_page(mmu_booke_alloc_kernel_pgtables(data_end));
677
678 /* Retrieve phys/avail mem regions */
679 mem_regions(&physmem_regions, &physmem_regions_sz,
680 &availmem_regions, &availmem_regions_sz);
681
682 if (PHYS_AVAIL_ENTRIES < availmem_regions_sz)
683 panic("mmu_booke_bootstrap: phys_avail too small");
684
685 data_end = round_page(data_end);
686 vm_page_array = (vm_page_t)data_end;
687 /*
688 * Get a rough idea (upper bound) on the size of the page array. The
689 * vm_page_array will not handle any more pages than we have in the
690 * avail_regions array, and most likely much less.
691 */
692 sz = 0;
693 for (mp = availmem_regions; mp->mr_size; mp++) {
694 sz += mp->mr_size;
695 }
696 sz = (round_page(sz) / (PAGE_SIZE + sizeof(struct vm_page)));
697 data_end += round_page(sz * sizeof(struct vm_page));
698
699 /* Pre-round up to 1MB. This wastes some space, but saves TLB entries */
700 data_end = roundup2(data_end, 1 << 20);
701
702 debugf(" data_end: 0x%"PRI0ptrX"\n", data_end);
703 debugf(" kernstart: %#zx\n", kernstart);
704 debugf(" kernsize: %#zx\n", kernsize);
705
706 if (data_end - kernstart > kernsize) {
707 kernsize += tlb1_mapin_region(kernstart + kernsize,
708 kernload + kernsize, (data_end - kernstart) - kernsize,
709 _TLB_ENTRY_MEM);
710 }
711 data_end = kernstart + kernsize;
712 debugf(" updated data_end: 0x%"PRI0ptrX"\n", data_end);
713
714 /*
715 * Clear the structures - note we can only do it safely after the
716 * possible additional TLB1 translations are in place (above) so that
717 * all range up to the currently calculated 'data_end' is covered.
718 */
719 bzero((void *)data_start, data_end - data_start);
720 dpcpu_init(dpcpu, 0);
721
722 /*******************************************************/
723 /* Set the start and end of kva. */
724 /*******************************************************/
725 virtual_avail = round_page(data_end);
726 virtual_end = VM_MAX_KERNEL_ADDRESS;
727
728 #ifndef __powerpc64__
729 /* Allocate KVA space for page zero/copy operations. */
730 zero_page_va = virtual_avail;
731 virtual_avail += PAGE_SIZE;
732 copy_page_src_va = virtual_avail;
733 virtual_avail += PAGE_SIZE;
734 copy_page_dst_va = virtual_avail;
735 virtual_avail += PAGE_SIZE;
736 debugf("zero_page_va = 0x%"PRI0ptrX"\n", zero_page_va);
737 debugf("copy_page_src_va = 0x%"PRI0ptrX"\n", copy_page_src_va);
738 debugf("copy_page_dst_va = 0x%"PRI0ptrX"\n", copy_page_dst_va);
739
740 /* Initialize page zero/copy mutexes. */
741 mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF);
742 mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF);
743
744 /* Allocate KVA space for ptbl bufs. */
745 ptbl_buf_pool_vabase = virtual_avail;
746 virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE;
747 debugf("ptbl_buf_pool_vabase = 0x%"PRI0ptrX" end = 0x%"PRI0ptrX"\n",
748 ptbl_buf_pool_vabase, virtual_avail);
749 #endif
750
751 /* Calculate corresponding physical addresses for the kernel region. */
752 phys_kernelend = kernload + kernsize;
753 debugf("kernel image and allocated data:\n");
754 debugf(" kernload = 0x%09jx\n", (uintmax_t)kernload);
755 debugf(" kernstart = 0x%"PRI0ptrX"\n", kernstart);
756 debugf(" kernsize = 0x%"PRI0ptrX"\n", kernsize);
757
758 /*
759 * Remove kernel physical address range from avail regions list. Page
760 * align all regions. Non-page aligned memory isn't very interesting
761 * to us. Also, sort the entries for ascending addresses.
762 */
763
764 sz = 0;
765 cnt = availmem_regions_sz;
766 debugf("processing avail regions:\n");
767 for (mp = availmem_regions; mp->mr_size; mp++) {
768 s = mp->mr_start;
769 e = mp->mr_start + mp->mr_size;
770 debugf(" %09jx-%09jx -> ", (uintmax_t)s, (uintmax_t)e);
771 /* Check whether this region holds all of the kernel. */
772 if (s < kernload && e > phys_kernelend) {
773 availmem_regions[cnt].mr_start = phys_kernelend;
774 availmem_regions[cnt++].mr_size = e - phys_kernelend;
775 e = kernload;
776 }
777 /* Look whether this regions starts within the kernel. */
778 if (s >= kernload && s < phys_kernelend) {
779 if (e <= phys_kernelend)
780 goto empty;
781 s = phys_kernelend;
782 }
783 /* Now look whether this region ends within the kernel. */
784 if (e > kernload && e <= phys_kernelend) {
785 if (s >= kernload)
786 goto empty;
787 e = kernload;
788 }
789 /* Now page align the start and size of the region. */
790 s = round_page(s);
791 e = trunc_page(e);
792 if (e < s)
793 e = s;
794 sz = e - s;
795 debugf("%09jx-%09jx = %jx\n",
796 (uintmax_t)s, (uintmax_t)e, (uintmax_t)sz);
797
798 /* Check whether some memory is left here. */
799 if (sz == 0) {
800 empty:
801 memmove(mp, mp + 1,
802 (cnt - (mp - availmem_regions)) * sizeof(*mp));
803 cnt--;
804 mp--;
805 continue;
806 }
807
808 /* Do an insertion sort. */
809 for (mp1 = availmem_regions; mp1 < mp; mp1++)
810 if (s < mp1->mr_start)
811 break;
812 if (mp1 < mp) {
813 memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1);
814 mp1->mr_start = s;
815 mp1->mr_size = sz;
816 } else {
817 mp->mr_start = s;
818 mp->mr_size = sz;
819 }
820 }
821 availmem_regions_sz = cnt;
822
823 /*******************************************************/
824 /* Steal physical memory for kernel stack from the end */
825 /* of the first avail region */
826 /*******************************************************/
827 kstack0_sz = kstack_pages * PAGE_SIZE;
828 kstack0_phys = availmem_regions[0].mr_start +
829 availmem_regions[0].mr_size;
830 kstack0_phys -= kstack0_sz;
831 availmem_regions[0].mr_size -= kstack0_sz;
832
833 /*******************************************************/
834 /* Fill in phys_avail table, based on availmem_regions */
835 /*******************************************************/
836 phys_avail_count = 0;
837 physsz = 0;
838 hwphyssz = 0;
839 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
840
841 debugf("fill in phys_avail:\n");
842 for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) {
843 debugf(" region: 0x%jx - 0x%jx (0x%jx)\n",
844 (uintmax_t)availmem_regions[i].mr_start,
845 (uintmax_t)availmem_regions[i].mr_start +
846 availmem_regions[i].mr_size,
847 (uintmax_t)availmem_regions[i].mr_size);
848
849 if (hwphyssz != 0 &&
850 (physsz + availmem_regions[i].mr_size) >= hwphyssz) {
851 debugf(" hw.physmem adjust\n");
852 if (physsz < hwphyssz) {
853 phys_avail[j] = availmem_regions[i].mr_start;
854 phys_avail[j + 1] =
855 availmem_regions[i].mr_start +
856 hwphyssz - physsz;
857 physsz = hwphyssz;
858 phys_avail_count++;
859 dump_avail[j] = phys_avail[j];
860 dump_avail[j + 1] = phys_avail[j + 1];
861 }
862 break;
863 }
864
865 phys_avail[j] = availmem_regions[i].mr_start;
866 phys_avail[j + 1] = availmem_regions[i].mr_start +
867 availmem_regions[i].mr_size;
868 phys_avail_count++;
869 physsz += availmem_regions[i].mr_size;
870 dump_avail[j] = phys_avail[j];
871 dump_avail[j + 1] = phys_avail[j + 1];
872 }
873 physmem = btoc(physsz);
874
875 /* Calculate the last available physical address. */
876 for (i = 0; phys_avail[i + 2] != 0; i += 2)
877 ;
878 Maxmem = powerpc_btop(phys_avail[i + 1]);
879
880 debugf("Maxmem = 0x%08lx\n", Maxmem);
881 debugf("phys_avail_count = %d\n", phys_avail_count);
882 debugf("physsz = 0x%09jx physmem = %jd (0x%09jx)\n",
883 (uintmax_t)physsz, (uintmax_t)physmem, (uintmax_t)physmem);
884
885 #ifdef __powerpc64__
886 /*
887 * Map the physical memory contiguously in TLB1.
888 * Round so it fits into a single mapping.
889 */
890 tlb1_mapin_region(DMAP_BASE_ADDRESS, 0,
891 phys_avail[i + 1], _TLB_ENTRY_MEM);
892 #endif
893
894 /*******************************************************/
895 /* Initialize (statically allocated) kernel pmap. */
896 /*******************************************************/
897 PMAP_LOCK_INIT(kernel_pmap);
898
899 debugf("kernel_pmap = 0x%"PRI0ptrX"\n", (uintptr_t)kernel_pmap);
900 kernel_pte_alloc(virtual_avail, kernstart);
901 for (i = 0; i < MAXCPU; i++) {
902 kernel_pmap->pm_tid[i] = TID_KERNEL;
903
904 /* Initialize each CPU's tidbusy entry 0 with kernel_pmap */
905 tidbusy[i][TID_KERNEL] = kernel_pmap;
906 }
907
908 /* Mark kernel_pmap active on all CPUs */
909 CPU_FILL(&kernel_pmap->pm_active);
910
911 /*
912 * Initialize the global pv list lock.
913 */
914 rw_init(&pvh_global_lock, "pmap pv global");
915
916 /*******************************************************/
917 /* Final setup */
918 /*******************************************************/
919
920 /* Enter kstack0 into kernel map, provide guard page */
921 kstack0 = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE;
922 thread0.td_kstack = kstack0;
923 thread0.td_kstack_pages = kstack_pages;
924
925 debugf("kstack_sz = 0x%08jx\n", (uintmax_t)kstack0_sz);
926 debugf("kstack0_phys at 0x%09jx - 0x%09jx\n",
927 (uintmax_t)kstack0_phys, (uintmax_t)kstack0_phys + kstack0_sz);
928 debugf("kstack0 at 0x%"PRI0ptrX" - 0x%"PRI0ptrX"\n",
929 kstack0, kstack0 + kstack0_sz);
930
931 virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz;
932 for (i = 0; i < kstack_pages; i++) {
933 mmu_booke_kenter(kstack0, kstack0_phys);
934 kstack0 += PAGE_SIZE;
935 kstack0_phys += PAGE_SIZE;
936 }
937
938 pmap_bootstrapped = 1;
939
940 debugf("virtual_avail = %"PRI0ptrX"\n", virtual_avail);
941 debugf("virtual_end = %"PRI0ptrX"\n", virtual_end);
942
943 debugf("mmu_booke_bootstrap: exit\n");
944 }
945
946 #ifdef SMP
947 void
tlb1_ap_prep(void)948 tlb1_ap_prep(void)
949 {
950 tlb_entry_t *e, tmp;
951 unsigned int i;
952
953 /* Prepare TLB1 image for AP processors */
954 e = __boot_tlb1;
955 for (i = 0; i < TLB1_ENTRIES; i++) {
956 tlb1_read_entry(&tmp, i);
957
958 if ((tmp.mas1 & MAS1_VALID) && (tmp.mas2 & _TLB_ENTRY_SHARED))
959 memcpy(e++, &tmp, sizeof(tmp));
960 }
961 }
962
963 void
pmap_bootstrap_ap(volatile uint32_t * trcp __unused)964 pmap_bootstrap_ap(volatile uint32_t *trcp __unused)
965 {
966 int i;
967
968 /*
969 * Finish TLB1 configuration: the BSP already set up its TLB1 and we
970 * have the snapshot of its contents in the s/w __boot_tlb1[] table
971 * created by tlb1_ap_prep(), so use these values directly to
972 * (re)program AP's TLB1 hardware.
973 *
974 * Start at index 1 because index 0 has the kernel map.
975 */
976 for (i = 1; i < TLB1_ENTRIES; i++) {
977 if (__boot_tlb1[i].mas1 & MAS1_VALID)
978 tlb1_write_entry(&__boot_tlb1[i], i);
979 }
980
981 set_mas4_defaults();
982 }
983 #endif
984
985 static void
booke_pmap_init_qpages(void)986 booke_pmap_init_qpages(void)
987 {
988 struct pcpu *pc;
989 int i;
990
991 CPU_FOREACH(i) {
992 pc = pcpu_find(i);
993 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE);
994 if (pc->pc_qmap_addr == 0)
995 panic("pmap_init_qpages: unable to allocate KVA");
996 }
997 }
998
999 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, booke_pmap_init_qpages, NULL);
1000
1001 /*
1002 * Get the physical page address for the given pmap/virtual address.
1003 */
1004 static vm_paddr_t
mmu_booke_extract(pmap_t pmap,vm_offset_t va)1005 mmu_booke_extract(pmap_t pmap, vm_offset_t va)
1006 {
1007 vm_paddr_t pa;
1008
1009 PMAP_LOCK(pmap);
1010 pa = pte_vatopa(pmap, va);
1011 PMAP_UNLOCK(pmap);
1012
1013 return (pa);
1014 }
1015
1016 /*
1017 * Extract the physical page address associated with the given
1018 * kernel virtual address.
1019 */
1020 static vm_paddr_t
mmu_booke_kextract(vm_offset_t va)1021 mmu_booke_kextract(vm_offset_t va)
1022 {
1023 tlb_entry_t e;
1024 vm_paddr_t p = 0;
1025 int i;
1026
1027 #ifdef __powerpc64__
1028 if (va >= DMAP_BASE_ADDRESS && va <= DMAP_MAX_ADDRESS)
1029 return (DMAP_TO_PHYS(va));
1030 #endif
1031
1032 if (va >= VM_MIN_KERNEL_ADDRESS && va <= VM_MAX_KERNEL_ADDRESS)
1033 p = pte_vatopa(kernel_pmap, va);
1034
1035 if (p == 0) {
1036 /* Check TLB1 mappings */
1037 for (i = 0; i < TLB1_ENTRIES; i++) {
1038 tlb1_read_entry(&e, i);
1039 if (!(e.mas1 & MAS1_VALID))
1040 continue;
1041 if (va >= e.virt && va < e.virt + e.size)
1042 return (e.phys + (va - e.virt));
1043 }
1044 }
1045
1046 return (p);
1047 }
1048
1049 /*
1050 * Initialize the pmap module.
1051 *
1052 * Called by vm_mem_init(), to initialize any structures that the pmap system
1053 * needs to map virtual memory.
1054 */
1055 static void
mmu_booke_init()1056 mmu_booke_init()
1057 {
1058 int shpgperproc = PMAP_SHPGPERPROC;
1059
1060 /*
1061 * Initialize the address space (zone) for the pv entries. Set a
1062 * high water mark so that the system can recover from excessive
1063 * numbers of pv entries.
1064 */
1065 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL,
1066 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1067
1068 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
1069 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
1070
1071 TUNABLE_INT_FETCH("vm.pmap.pv_entry_max", &pv_entry_max);
1072 pv_entry_high_water = 9 * (pv_entry_max / 10);
1073
1074 uma_zone_reserve_kva(pvzone, pv_entry_max);
1075
1076 /* Pre-fill pvzone with initial number of pv entries. */
1077 uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN);
1078
1079 /* Create a UMA zone for page table roots. */
1080 ptbl_root_zone = uma_zcreate("pmap root", PMAP_ROOT_SIZE,
1081 NULL, NULL, NULL, NULL, UMA_ALIGN_CACHE, UMA_ZONE_VM);
1082
1083 /* Initialize ptbl allocation. */
1084 ptbl_init();
1085 }
1086
1087 /*
1088 * Map a list of wired pages into kernel virtual address space. This is
1089 * intended for temporary mappings which do not need page modification or
1090 * references recorded. Existing mappings in the region are overwritten.
1091 */
1092 static void
mmu_booke_qenter(vm_offset_t sva,vm_page_t * m,int count)1093 mmu_booke_qenter(vm_offset_t sva, vm_page_t *m, int count)
1094 {
1095 vm_offset_t va;
1096
1097 va = sva;
1098 while (count-- > 0) {
1099 mmu_booke_kenter(va, VM_PAGE_TO_PHYS(*m));
1100 va += PAGE_SIZE;
1101 m++;
1102 }
1103 }
1104
1105 /*
1106 * Remove page mappings from kernel virtual address space. Intended for
1107 * temporary mappings entered by mmu_booke_qenter.
1108 */
1109 static void
mmu_booke_qremove(vm_offset_t sva,int count)1110 mmu_booke_qremove(vm_offset_t sva, int count)
1111 {
1112 vm_offset_t va;
1113
1114 va = sva;
1115 while (count-- > 0) {
1116 mmu_booke_kremove(va);
1117 va += PAGE_SIZE;
1118 }
1119 }
1120
1121 /*
1122 * Map a wired page into kernel virtual address space.
1123 */
1124 static void
mmu_booke_kenter(vm_offset_t va,vm_paddr_t pa)1125 mmu_booke_kenter(vm_offset_t va, vm_paddr_t pa)
1126 {
1127
1128 mmu_booke_kenter_attr(va, pa, VM_MEMATTR_DEFAULT);
1129 }
1130
1131 static void
mmu_booke_kenter_attr(vm_offset_t va,vm_paddr_t pa,vm_memattr_t ma)1132 mmu_booke_kenter_attr(vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma)
1133 {
1134 uint32_t flags;
1135 pte_t *pte;
1136
1137 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) &&
1138 (va <= VM_MAX_KERNEL_ADDRESS)), ("mmu_booke_kenter: invalid va"));
1139
1140 flags = PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID;
1141 flags |= tlb_calc_wimg(pa, ma) << PTE_MAS2_SHIFT;
1142 flags |= PTE_PS_4KB;
1143
1144 pte = pte_find(kernel_pmap, va);
1145 KASSERT((pte != NULL), ("mmu_booke_kenter: invalid va. NULL PTE"));
1146
1147 mtx_lock_spin(&tlbivax_mutex);
1148 tlb_miss_lock();
1149
1150 if (PTE_ISVALID(pte)) {
1151 CTR1(KTR_PMAP, "%s: replacing entry!", __func__);
1152
1153 /* Flush entry from TLB0 */
1154 tlb0_flush_entry(va);
1155 }
1156
1157 *pte = PTE_RPN_FROM_PA(pa) | flags;
1158
1159 //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x "
1160 // "pa=0x%08x rpn=0x%08x flags=0x%08x\n",
1161 // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags);
1162
1163 /* Flush the real memory from the instruction cache. */
1164 if ((flags & (PTE_I | PTE_G)) == 0)
1165 __syncicache((void *)va, PAGE_SIZE);
1166
1167 tlb_miss_unlock();
1168 mtx_unlock_spin(&tlbivax_mutex);
1169 }
1170
1171 /*
1172 * Remove a page from kernel page table.
1173 */
1174 static void
mmu_booke_kremove(vm_offset_t va)1175 mmu_booke_kremove(vm_offset_t va)
1176 {
1177 pte_t *pte;
1178
1179 CTR2(KTR_PMAP,"%s: s (va = 0x%"PRI0ptrX")\n", __func__, va);
1180
1181 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) &&
1182 (va <= VM_MAX_KERNEL_ADDRESS)),
1183 ("mmu_booke_kremove: invalid va"));
1184
1185 pte = pte_find(kernel_pmap, va);
1186
1187 if (!PTE_ISVALID(pte)) {
1188 CTR1(KTR_PMAP, "%s: invalid pte", __func__);
1189
1190 return;
1191 }
1192
1193 mtx_lock_spin(&tlbivax_mutex);
1194 tlb_miss_lock();
1195
1196 /* Invalidate entry in TLB0, update PTE. */
1197 tlb0_flush_entry(va);
1198 *pte = 0;
1199
1200 tlb_miss_unlock();
1201 mtx_unlock_spin(&tlbivax_mutex);
1202 }
1203
1204 /*
1205 * Figure out where a given kernel pointer (usually in a fault) points
1206 * to from the VM's perspective, potentially remapping into userland's
1207 * address space.
1208 */
1209 static int
mmu_booke_decode_kernel_ptr(vm_offset_t addr,int * is_user,vm_offset_t * decoded_addr)1210 mmu_booke_decode_kernel_ptr(vm_offset_t addr, int *is_user,
1211 vm_offset_t *decoded_addr)
1212 {
1213
1214 if (trunc_page(addr) <= VM_MAXUSER_ADDRESS)
1215 *is_user = 1;
1216 else
1217 *is_user = 0;
1218
1219 *decoded_addr = addr;
1220 return (0);
1221 }
1222
1223 static boolean_t
mmu_booke_page_is_mapped(vm_page_t m)1224 mmu_booke_page_is_mapped(vm_page_t m)
1225 {
1226
1227 return (!TAILQ_EMPTY(&(m)->md.pv_list));
1228 }
1229
1230 static bool
mmu_booke_ps_enabled(pmap_t pmap __unused)1231 mmu_booke_ps_enabled(pmap_t pmap __unused)
1232 {
1233 return (false);
1234 }
1235
1236 /*
1237 * Initialize pmap associated with process 0.
1238 */
1239 static void
mmu_booke_pinit0(pmap_t pmap)1240 mmu_booke_pinit0(pmap_t pmap)
1241 {
1242
1243 PMAP_LOCK_INIT(pmap);
1244 mmu_booke_pinit(pmap);
1245 PCPU_SET(curpmap, pmap);
1246 }
1247
1248 /*
1249 * Insert the given physical page at the specified virtual address in the
1250 * target physical map with the protection requested. If specified the page
1251 * will be wired down.
1252 */
1253 static int
mmu_booke_enter(pmap_t pmap,vm_offset_t va,vm_page_t m,vm_prot_t prot,u_int flags,int8_t psind)1254 mmu_booke_enter(pmap_t pmap, vm_offset_t va, vm_page_t m,
1255 vm_prot_t prot, u_int flags, int8_t psind)
1256 {
1257 int error;
1258
1259 rw_wlock(&pvh_global_lock);
1260 PMAP_LOCK(pmap);
1261 error = mmu_booke_enter_locked(pmap, va, m, prot, flags, psind);
1262 PMAP_UNLOCK(pmap);
1263 rw_wunlock(&pvh_global_lock);
1264 return (error);
1265 }
1266
1267 static int
mmu_booke_enter_locked(pmap_t pmap,vm_offset_t va,vm_page_t m,vm_prot_t prot,u_int pmap_flags,int8_t psind __unused)1268 mmu_booke_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
1269 vm_prot_t prot, u_int pmap_flags, int8_t psind __unused)
1270 {
1271 pte_t *pte;
1272 vm_paddr_t pa;
1273 pte_t flags;
1274 int error, su, sync;
1275
1276 pa = VM_PAGE_TO_PHYS(m);
1277 su = (pmap == kernel_pmap);
1278 sync = 0;
1279
1280 //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x "
1281 // "pa=0x%08x prot=0x%08x flags=%#x)\n",
1282 // (u_int32_t)pmap, su, pmap->pm_tid,
1283 // (u_int32_t)m, va, pa, prot, flags);
1284
1285 if (su) {
1286 KASSERT(((va >= virtual_avail) &&
1287 (va <= VM_MAX_KERNEL_ADDRESS)),
1288 ("mmu_booke_enter_locked: kernel pmap, non kernel va"));
1289 } else {
1290 KASSERT((va <= VM_MAXUSER_ADDRESS),
1291 ("mmu_booke_enter_locked: user pmap, non user va"));
1292 }
1293 if ((m->oflags & VPO_UNMANAGED) == 0) {
1294 if ((pmap_flags & PMAP_ENTER_QUICK_LOCKED) == 0)
1295 VM_PAGE_OBJECT_BUSY_ASSERT(m);
1296 else
1297 VM_OBJECT_ASSERT_LOCKED(m->object);
1298 }
1299
1300 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1301
1302 /*
1303 * If there is an existing mapping, and the physical address has not
1304 * changed, must be protection or wiring change.
1305 */
1306 if (((pte = pte_find(pmap, va)) != NULL) &&
1307 (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) {
1308
1309 /*
1310 * Before actually updating pte->flags we calculate and
1311 * prepare its new value in a helper var.
1312 */
1313 flags = *pte;
1314 flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED);
1315
1316 /* Wiring change, just update stats. */
1317 if ((pmap_flags & PMAP_ENTER_WIRED) != 0) {
1318 if (!PTE_ISWIRED(pte)) {
1319 flags |= PTE_WIRED;
1320 pmap->pm_stats.wired_count++;
1321 }
1322 } else {
1323 if (PTE_ISWIRED(pte)) {
1324 flags &= ~PTE_WIRED;
1325 pmap->pm_stats.wired_count--;
1326 }
1327 }
1328
1329 if (prot & VM_PROT_WRITE) {
1330 /* Add write permissions. */
1331 flags |= PTE_SW;
1332 if (!su)
1333 flags |= PTE_UW;
1334
1335 if ((flags & PTE_MANAGED) != 0)
1336 vm_page_aflag_set(m, PGA_WRITEABLE);
1337 } else {
1338 /* Handle modified pages, sense modify status. */
1339
1340 /*
1341 * The PTE_MODIFIED flag could be set by underlying
1342 * TLB misses since we last read it (above), possibly
1343 * other CPUs could update it so we check in the PTE
1344 * directly rather than rely on that saved local flags
1345 * copy.
1346 */
1347 if (PTE_ISMODIFIED(pte))
1348 vm_page_dirty(m);
1349 }
1350
1351 if (prot & VM_PROT_EXECUTE) {
1352 flags |= PTE_SX;
1353 if (!su)
1354 flags |= PTE_UX;
1355
1356 /*
1357 * Check existing flags for execute permissions: if we
1358 * are turning execute permissions on, icache should
1359 * be flushed.
1360 */
1361 if ((*pte & (PTE_UX | PTE_SX)) == 0)
1362 sync++;
1363 }
1364
1365 flags &= ~PTE_REFERENCED;
1366
1367 /*
1368 * The new flags value is all calculated -- only now actually
1369 * update the PTE.
1370 */
1371 mtx_lock_spin(&tlbivax_mutex);
1372 tlb_miss_lock();
1373
1374 tlb0_flush_entry(va);
1375 *pte &= ~PTE_FLAGS_MASK;
1376 *pte |= flags;
1377
1378 tlb_miss_unlock();
1379 mtx_unlock_spin(&tlbivax_mutex);
1380
1381 } else {
1382 /*
1383 * If there is an existing mapping, but it's for a different
1384 * physical address, pte_enter() will delete the old mapping.
1385 */
1386 //if ((pte != NULL) && PTE_ISVALID(pte))
1387 // debugf("mmu_booke_enter_locked: replace\n");
1388 //else
1389 // debugf("mmu_booke_enter_locked: new\n");
1390
1391 /* Now set up the flags and install the new mapping. */
1392 flags = (PTE_SR | PTE_VALID);
1393 flags |= PTE_M;
1394
1395 if (!su)
1396 flags |= PTE_UR;
1397
1398 if (prot & VM_PROT_WRITE) {
1399 flags |= PTE_SW;
1400 if (!su)
1401 flags |= PTE_UW;
1402
1403 if ((m->oflags & VPO_UNMANAGED) == 0)
1404 vm_page_aflag_set(m, PGA_WRITEABLE);
1405 }
1406
1407 if (prot & VM_PROT_EXECUTE) {
1408 flags |= PTE_SX;
1409 if (!su)
1410 flags |= PTE_UX;
1411 }
1412
1413 /* If its wired update stats. */
1414 if ((pmap_flags & PMAP_ENTER_WIRED) != 0)
1415 flags |= PTE_WIRED;
1416
1417 error = pte_enter(pmap, m, va, flags,
1418 (pmap_flags & PMAP_ENTER_NOSLEEP) != 0);
1419 if (error != 0)
1420 return (KERN_RESOURCE_SHORTAGE);
1421
1422 if ((flags & PMAP_ENTER_WIRED) != 0)
1423 pmap->pm_stats.wired_count++;
1424
1425 /* Flush the real memory from the instruction cache. */
1426 if (prot & VM_PROT_EXECUTE)
1427 sync++;
1428 }
1429
1430 if (sync && (su || pmap == PCPU_GET(curpmap))) {
1431 __syncicache((void *)va, PAGE_SIZE);
1432 sync = 0;
1433 }
1434
1435 return (KERN_SUCCESS);
1436 }
1437
1438 /*
1439 * Maps a sequence of resident pages belonging to the same object.
1440 * The sequence begins with the given page m_start. This page is
1441 * mapped at the given virtual address start. Each subsequent page is
1442 * mapped at a virtual address that is offset from start by the same
1443 * amount as the page is offset from m_start within the object. The
1444 * last page in the sequence is the page with the largest offset from
1445 * m_start that can be mapped at a virtual address less than the given
1446 * virtual address end. Not every virtual page between start and end
1447 * is mapped; only those for which a resident page exists with the
1448 * corresponding offset from m_start are mapped.
1449 */
1450 static void
mmu_booke_enter_object(pmap_t pmap,vm_offset_t start,vm_offset_t end,vm_page_t m_start,vm_prot_t prot)1451 mmu_booke_enter_object(pmap_t pmap, vm_offset_t start,
1452 vm_offset_t end, vm_page_t m_start, vm_prot_t prot)
1453 {
1454 vm_page_t m;
1455 vm_pindex_t diff, psize;
1456
1457 VM_OBJECT_ASSERT_LOCKED(m_start->object);
1458
1459 psize = atop(end - start);
1460 m = m_start;
1461 rw_wlock(&pvh_global_lock);
1462 PMAP_LOCK(pmap);
1463 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1464 mmu_booke_enter_locked(pmap, start + ptoa(diff), m,
1465 prot & (VM_PROT_READ | VM_PROT_EXECUTE),
1466 PMAP_ENTER_NOSLEEP | PMAP_ENTER_QUICK_LOCKED, 0);
1467 m = TAILQ_NEXT(m, listq);
1468 }
1469 PMAP_UNLOCK(pmap);
1470 rw_wunlock(&pvh_global_lock);
1471 }
1472
1473 static void
mmu_booke_enter_quick(pmap_t pmap,vm_offset_t va,vm_page_t m,vm_prot_t prot)1474 mmu_booke_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m,
1475 vm_prot_t prot)
1476 {
1477
1478 rw_wlock(&pvh_global_lock);
1479 PMAP_LOCK(pmap);
1480 mmu_booke_enter_locked(pmap, va, m,
1481 prot & (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP |
1482 PMAP_ENTER_QUICK_LOCKED, 0);
1483 PMAP_UNLOCK(pmap);
1484 rw_wunlock(&pvh_global_lock);
1485 }
1486
1487 /*
1488 * Remove the given range of addresses from the specified map.
1489 *
1490 * It is assumed that the start and end are properly rounded to the page size.
1491 */
1492 static void
mmu_booke_remove(pmap_t pmap,vm_offset_t va,vm_offset_t endva)1493 mmu_booke_remove(pmap_t pmap, vm_offset_t va, vm_offset_t endva)
1494 {
1495 pte_t *pte;
1496 uint8_t hold_flag;
1497
1498 int su = (pmap == kernel_pmap);
1499
1500 //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n",
1501 // su, (u_int32_t)pmap, pmap->pm_tid, va, endva);
1502
1503 if (su) {
1504 KASSERT(((va >= virtual_avail) &&
1505 (va <= VM_MAX_KERNEL_ADDRESS)),
1506 ("mmu_booke_remove: kernel pmap, non kernel va"));
1507 } else {
1508 KASSERT((va <= VM_MAXUSER_ADDRESS),
1509 ("mmu_booke_remove: user pmap, non user va"));
1510 }
1511
1512 if (PMAP_REMOVE_DONE(pmap)) {
1513 //debugf("mmu_booke_remove: e (empty)\n");
1514 return;
1515 }
1516
1517 hold_flag = PTBL_HOLD_FLAG(pmap);
1518 //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag);
1519
1520 rw_wlock(&pvh_global_lock);
1521 PMAP_LOCK(pmap);
1522 for (; va < endva; va += PAGE_SIZE) {
1523 pte = pte_find_next(pmap, &va);
1524 if ((pte == NULL) || !PTE_ISVALID(pte))
1525 break;
1526 if (va >= endva)
1527 break;
1528 pte_remove(pmap, va, hold_flag);
1529 }
1530 PMAP_UNLOCK(pmap);
1531 rw_wunlock(&pvh_global_lock);
1532
1533 //debugf("mmu_booke_remove: e\n");
1534 }
1535
1536 /*
1537 * Remove physical page from all pmaps in which it resides.
1538 */
1539 static void
mmu_booke_remove_all(vm_page_t m)1540 mmu_booke_remove_all(vm_page_t m)
1541 {
1542 pv_entry_t pv, pvn;
1543 uint8_t hold_flag;
1544
1545 rw_wlock(&pvh_global_lock);
1546 TAILQ_FOREACH_SAFE(pv, &m->md.pv_list, pv_link, pvn) {
1547 PMAP_LOCK(pv->pv_pmap);
1548 hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap);
1549 pte_remove(pv->pv_pmap, pv->pv_va, hold_flag);
1550 PMAP_UNLOCK(pv->pv_pmap);
1551 }
1552 vm_page_aflag_clear(m, PGA_WRITEABLE);
1553 rw_wunlock(&pvh_global_lock);
1554 }
1555
1556 /*
1557 * Map a range of physical addresses into kernel virtual address space.
1558 */
1559 static vm_offset_t
mmu_booke_map(vm_offset_t * virt,vm_paddr_t pa_start,vm_paddr_t pa_end,int prot)1560 mmu_booke_map(vm_offset_t *virt, vm_paddr_t pa_start,
1561 vm_paddr_t pa_end, int prot)
1562 {
1563 vm_offset_t sva = *virt;
1564 vm_offset_t va = sva;
1565
1566 #ifdef __powerpc64__
1567 /* XXX: Handle memory not starting at 0x0. */
1568 if (pa_end < ctob(Maxmem))
1569 return (PHYS_TO_DMAP(pa_start));
1570 #endif
1571
1572 while (pa_start < pa_end) {
1573 mmu_booke_kenter(va, pa_start);
1574 va += PAGE_SIZE;
1575 pa_start += PAGE_SIZE;
1576 }
1577 *virt = va;
1578
1579 return (sva);
1580 }
1581
1582 /*
1583 * The pmap must be activated before it's address space can be accessed in any
1584 * way.
1585 */
1586 static void
mmu_booke_activate(struct thread * td)1587 mmu_booke_activate(struct thread *td)
1588 {
1589 pmap_t pmap;
1590 u_int cpuid;
1591
1592 pmap = &td->td_proc->p_vmspace->vm_pmap;
1593
1594 CTR5(KTR_PMAP, "%s: s (td = %p, proc = '%s', id = %d, pmap = 0x%"PRI0ptrX")",
1595 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap);
1596
1597 KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!"));
1598
1599 sched_pin();
1600
1601 cpuid = PCPU_GET(cpuid);
1602 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
1603 PCPU_SET(curpmap, pmap);
1604
1605 if (pmap->pm_tid[cpuid] == TID_NONE)
1606 tid_alloc(pmap);
1607
1608 /* Load PID0 register with pmap tid value. */
1609 mtspr(SPR_PID0, pmap->pm_tid[cpuid]);
1610 __asm __volatile("isync");
1611
1612 mtspr(SPR_DBCR0, td->td_pcb->pcb_cpu.booke.dbcr0);
1613
1614 sched_unpin();
1615
1616 CTR3(KTR_PMAP, "%s: e (tid = %d for '%s')", __func__,
1617 pmap->pm_tid[PCPU_GET(cpuid)], td->td_proc->p_comm);
1618 }
1619
1620 /*
1621 * Deactivate the specified process's address space.
1622 */
1623 static void
mmu_booke_deactivate(struct thread * td)1624 mmu_booke_deactivate(struct thread *td)
1625 {
1626 pmap_t pmap;
1627
1628 pmap = &td->td_proc->p_vmspace->vm_pmap;
1629
1630 CTR5(KTR_PMAP, "%s: td=%p, proc = '%s', id = %d, pmap = 0x%"PRI0ptrX,
1631 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap);
1632
1633 td->td_pcb->pcb_cpu.booke.dbcr0 = mfspr(SPR_DBCR0);
1634
1635 CPU_CLR_ATOMIC(PCPU_GET(cpuid), &pmap->pm_active);
1636 PCPU_SET(curpmap, NULL);
1637 }
1638
1639 /*
1640 * Copy the range specified by src_addr/len
1641 * from the source map to the range dst_addr/len
1642 * in the destination map.
1643 *
1644 * This routine is only advisory and need not do anything.
1645 */
1646 static void
mmu_booke_copy(pmap_t dst_pmap,pmap_t src_pmap,vm_offset_t dst_addr,vm_size_t len,vm_offset_t src_addr)1647 mmu_booke_copy(pmap_t dst_pmap, pmap_t src_pmap,
1648 vm_offset_t dst_addr, vm_size_t len, vm_offset_t src_addr)
1649 {
1650
1651 }
1652
1653 /*
1654 * Set the physical protection on the specified range of this map as requested.
1655 */
1656 static void
mmu_booke_protect(pmap_t pmap,vm_offset_t sva,vm_offset_t eva,vm_prot_t prot)1657 mmu_booke_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
1658 vm_prot_t prot)
1659 {
1660 vm_offset_t va;
1661 vm_page_t m;
1662 pte_t *pte;
1663
1664 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
1665 mmu_booke_remove(pmap, sva, eva);
1666 return;
1667 }
1668
1669 if (prot & VM_PROT_WRITE)
1670 return;
1671
1672 PMAP_LOCK(pmap);
1673 for (va = sva; va < eva; va += PAGE_SIZE) {
1674 if ((pte = pte_find(pmap, va)) != NULL) {
1675 if (PTE_ISVALID(pte)) {
1676 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
1677
1678 mtx_lock_spin(&tlbivax_mutex);
1679 tlb_miss_lock();
1680
1681 /* Handle modified pages. */
1682 if (PTE_ISMODIFIED(pte) && PTE_ISMANAGED(pte))
1683 vm_page_dirty(m);
1684
1685 tlb0_flush_entry(va);
1686 *pte &= ~(PTE_UW | PTE_SW | PTE_MODIFIED);
1687
1688 tlb_miss_unlock();
1689 mtx_unlock_spin(&tlbivax_mutex);
1690 }
1691 }
1692 }
1693 PMAP_UNLOCK(pmap);
1694 }
1695
1696 /*
1697 * Clear the write and modified bits in each of the given page's mappings.
1698 */
1699 static void
mmu_booke_remove_write(vm_page_t m)1700 mmu_booke_remove_write(vm_page_t m)
1701 {
1702 pv_entry_t pv;
1703 pte_t *pte;
1704
1705 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1706 ("mmu_booke_remove_write: page %p is not managed", m));
1707 vm_page_assert_busied(m);
1708
1709 if (!pmap_page_is_write_mapped(m))
1710 return;
1711 rw_wlock(&pvh_global_lock);
1712 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
1713 PMAP_LOCK(pv->pv_pmap);
1714 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL) {
1715 if (PTE_ISVALID(pte)) {
1716 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
1717
1718 mtx_lock_spin(&tlbivax_mutex);
1719 tlb_miss_lock();
1720
1721 /* Handle modified pages. */
1722 if (PTE_ISMODIFIED(pte))
1723 vm_page_dirty(m);
1724
1725 /* Flush mapping from TLB0. */
1726 *pte &= ~(PTE_UW | PTE_SW | PTE_MODIFIED);
1727
1728 tlb_miss_unlock();
1729 mtx_unlock_spin(&tlbivax_mutex);
1730 }
1731 }
1732 PMAP_UNLOCK(pv->pv_pmap);
1733 }
1734 vm_page_aflag_clear(m, PGA_WRITEABLE);
1735 rw_wunlock(&pvh_global_lock);
1736 }
1737
1738 /*
1739 * Atomically extract and hold the physical page with the given
1740 * pmap and virtual address pair if that mapping permits the given
1741 * protection.
1742 */
1743 static vm_page_t
mmu_booke_extract_and_hold(pmap_t pmap,vm_offset_t va,vm_prot_t prot)1744 mmu_booke_extract_and_hold(pmap_t pmap, vm_offset_t va,
1745 vm_prot_t prot)
1746 {
1747 pte_t *pte;
1748 vm_page_t m;
1749 uint32_t pte_wbit;
1750
1751 m = NULL;
1752 PMAP_LOCK(pmap);
1753 pte = pte_find(pmap, va);
1754 if ((pte != NULL) && PTE_ISVALID(pte)) {
1755 if (pmap == kernel_pmap)
1756 pte_wbit = PTE_SW;
1757 else
1758 pte_wbit = PTE_UW;
1759
1760 if ((*pte & pte_wbit) != 0 || (prot & VM_PROT_WRITE) == 0) {
1761 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
1762 if (!vm_page_wire_mapped(m))
1763 m = NULL;
1764 }
1765 }
1766 PMAP_UNLOCK(pmap);
1767 return (m);
1768 }
1769
1770 /*
1771 * Initialize a vm_page's machine-dependent fields.
1772 */
1773 static void
mmu_booke_page_init(vm_page_t m)1774 mmu_booke_page_init(vm_page_t m)
1775 {
1776
1777 m->md.pv_tracked = 0;
1778 TAILQ_INIT(&m->md.pv_list);
1779 }
1780
1781 /*
1782 * Return whether or not the specified physical page was modified
1783 * in any of physical maps.
1784 */
1785 static boolean_t
mmu_booke_is_modified(vm_page_t m)1786 mmu_booke_is_modified(vm_page_t m)
1787 {
1788 pte_t *pte;
1789 pv_entry_t pv;
1790 boolean_t rv;
1791
1792 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1793 ("mmu_booke_is_modified: page %p is not managed", m));
1794 rv = FALSE;
1795
1796 /*
1797 * If the page is not busied then this check is racy.
1798 */
1799 if (!pmap_page_is_write_mapped(m))
1800 return (FALSE);
1801
1802 rw_wlock(&pvh_global_lock);
1803 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
1804 PMAP_LOCK(pv->pv_pmap);
1805 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL &&
1806 PTE_ISVALID(pte)) {
1807 if (PTE_ISMODIFIED(pte))
1808 rv = TRUE;
1809 }
1810 PMAP_UNLOCK(pv->pv_pmap);
1811 if (rv)
1812 break;
1813 }
1814 rw_wunlock(&pvh_global_lock);
1815 return (rv);
1816 }
1817
1818 /*
1819 * Return whether or not the specified virtual address is eligible
1820 * for prefault.
1821 */
1822 static boolean_t
mmu_booke_is_prefaultable(pmap_t pmap,vm_offset_t addr)1823 mmu_booke_is_prefaultable(pmap_t pmap, vm_offset_t addr)
1824 {
1825
1826 return (FALSE);
1827 }
1828
1829 /*
1830 * Return whether or not the specified physical page was referenced
1831 * in any physical maps.
1832 */
1833 static boolean_t
mmu_booke_is_referenced(vm_page_t m)1834 mmu_booke_is_referenced(vm_page_t m)
1835 {
1836 pte_t *pte;
1837 pv_entry_t pv;
1838 boolean_t rv;
1839
1840 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1841 ("mmu_booke_is_referenced: page %p is not managed", m));
1842 rv = FALSE;
1843 rw_wlock(&pvh_global_lock);
1844 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
1845 PMAP_LOCK(pv->pv_pmap);
1846 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL &&
1847 PTE_ISVALID(pte)) {
1848 if (PTE_ISREFERENCED(pte))
1849 rv = TRUE;
1850 }
1851 PMAP_UNLOCK(pv->pv_pmap);
1852 if (rv)
1853 break;
1854 }
1855 rw_wunlock(&pvh_global_lock);
1856 return (rv);
1857 }
1858
1859 /*
1860 * Clear the modify bits on the specified physical page.
1861 */
1862 static void
mmu_booke_clear_modify(vm_page_t m)1863 mmu_booke_clear_modify(vm_page_t m)
1864 {
1865 pte_t *pte;
1866 pv_entry_t pv;
1867
1868 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1869 ("mmu_booke_clear_modify: page %p is not managed", m));
1870 vm_page_assert_busied(m);
1871
1872 if (!pmap_page_is_write_mapped(m))
1873 return;
1874
1875 rw_wlock(&pvh_global_lock);
1876 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
1877 PMAP_LOCK(pv->pv_pmap);
1878 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL &&
1879 PTE_ISVALID(pte)) {
1880 mtx_lock_spin(&tlbivax_mutex);
1881 tlb_miss_lock();
1882
1883 if (*pte & (PTE_SW | PTE_UW | PTE_MODIFIED)) {
1884 tlb0_flush_entry(pv->pv_va);
1885 *pte &= ~(PTE_SW | PTE_UW | PTE_MODIFIED |
1886 PTE_REFERENCED);
1887 }
1888
1889 tlb_miss_unlock();
1890 mtx_unlock_spin(&tlbivax_mutex);
1891 }
1892 PMAP_UNLOCK(pv->pv_pmap);
1893 }
1894 rw_wunlock(&pvh_global_lock);
1895 }
1896
1897 /*
1898 * Return a count of reference bits for a page, clearing those bits.
1899 * It is not necessary for every reference bit to be cleared, but it
1900 * is necessary that 0 only be returned when there are truly no
1901 * reference bits set.
1902 *
1903 * As an optimization, update the page's dirty field if a modified bit is
1904 * found while counting reference bits. This opportunistic update can be
1905 * performed at low cost and can eliminate the need for some future calls
1906 * to pmap_is_modified(). However, since this function stops after
1907 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
1908 * dirty pages. Those dirty pages will only be detected by a future call
1909 * to pmap_is_modified().
1910 */
1911 static int
mmu_booke_ts_referenced(vm_page_t m)1912 mmu_booke_ts_referenced(vm_page_t m)
1913 {
1914 pte_t *pte;
1915 pv_entry_t pv;
1916 int count;
1917
1918 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1919 ("mmu_booke_ts_referenced: page %p is not managed", m));
1920 count = 0;
1921 rw_wlock(&pvh_global_lock);
1922 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
1923 PMAP_LOCK(pv->pv_pmap);
1924 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL &&
1925 PTE_ISVALID(pte)) {
1926 if (PTE_ISMODIFIED(pte))
1927 vm_page_dirty(m);
1928 if (PTE_ISREFERENCED(pte)) {
1929 mtx_lock_spin(&tlbivax_mutex);
1930 tlb_miss_lock();
1931
1932 tlb0_flush_entry(pv->pv_va);
1933 *pte &= ~PTE_REFERENCED;
1934
1935 tlb_miss_unlock();
1936 mtx_unlock_spin(&tlbivax_mutex);
1937
1938 if (++count >= PMAP_TS_REFERENCED_MAX) {
1939 PMAP_UNLOCK(pv->pv_pmap);
1940 break;
1941 }
1942 }
1943 }
1944 PMAP_UNLOCK(pv->pv_pmap);
1945 }
1946 rw_wunlock(&pvh_global_lock);
1947 return (count);
1948 }
1949
1950 /*
1951 * Clear the wired attribute from the mappings for the specified range of
1952 * addresses in the given pmap. Every valid mapping within that range must
1953 * have the wired attribute set. In contrast, invalid mappings cannot have
1954 * the wired attribute set, so they are ignored.
1955 *
1956 * The wired attribute of the page table entry is not a hardware feature, so
1957 * there is no need to invalidate any TLB entries.
1958 */
1959 static void
mmu_booke_unwire(pmap_t pmap,vm_offset_t sva,vm_offset_t eva)1960 mmu_booke_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1961 {
1962 vm_offset_t va;
1963 pte_t *pte;
1964
1965 PMAP_LOCK(pmap);
1966 for (va = sva; va < eva; va += PAGE_SIZE) {
1967 if ((pte = pte_find(pmap, va)) != NULL &&
1968 PTE_ISVALID(pte)) {
1969 if (!PTE_ISWIRED(pte))
1970 panic("mmu_booke_unwire: pte %p isn't wired",
1971 pte);
1972 *pte &= ~PTE_WIRED;
1973 pmap->pm_stats.wired_count--;
1974 }
1975 }
1976 PMAP_UNLOCK(pmap);
1977
1978 }
1979
1980 /*
1981 * Return true if the pmap's pv is one of the first 16 pvs linked to from this
1982 * page. This count may be changed upwards or downwards in the future; it is
1983 * only necessary that true be returned for a small subset of pmaps for proper
1984 * page aging.
1985 */
1986 static boolean_t
mmu_booke_page_exists_quick(pmap_t pmap,vm_page_t m)1987 mmu_booke_page_exists_quick(pmap_t pmap, vm_page_t m)
1988 {
1989 pv_entry_t pv;
1990 int loops;
1991 boolean_t rv;
1992
1993 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1994 ("mmu_booke_page_exists_quick: page %p is not managed", m));
1995 loops = 0;
1996 rv = FALSE;
1997 rw_wlock(&pvh_global_lock);
1998 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
1999 if (pv->pv_pmap == pmap) {
2000 rv = TRUE;
2001 break;
2002 }
2003 if (++loops >= 16)
2004 break;
2005 }
2006 rw_wunlock(&pvh_global_lock);
2007 return (rv);
2008 }
2009
2010 /*
2011 * Return the number of managed mappings to the given physical page that are
2012 * wired.
2013 */
2014 static int
mmu_booke_page_wired_mappings(vm_page_t m)2015 mmu_booke_page_wired_mappings(vm_page_t m)
2016 {
2017 pv_entry_t pv;
2018 pte_t *pte;
2019 int count = 0;
2020
2021 if ((m->oflags & VPO_UNMANAGED) != 0)
2022 return (count);
2023 rw_wlock(&pvh_global_lock);
2024 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2025 PMAP_LOCK(pv->pv_pmap);
2026 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL)
2027 if (PTE_ISVALID(pte) && PTE_ISWIRED(pte))
2028 count++;
2029 PMAP_UNLOCK(pv->pv_pmap);
2030 }
2031 rw_wunlock(&pvh_global_lock);
2032 return (count);
2033 }
2034
2035 static int
mmu_booke_dev_direct_mapped(vm_paddr_t pa,vm_size_t size)2036 mmu_booke_dev_direct_mapped(vm_paddr_t pa, vm_size_t size)
2037 {
2038 int i;
2039 vm_offset_t va;
2040
2041 /*
2042 * This currently does not work for entries that
2043 * overlap TLB1 entries.
2044 */
2045 for (i = 0; i < TLB1_ENTRIES; i ++) {
2046 if (tlb1_iomapped(i, pa, size, &va) == 0)
2047 return (0);
2048 }
2049
2050 return (EFAULT);
2051 }
2052
2053 void
mmu_booke_dumpsys_map(vm_paddr_t pa,size_t sz,void ** va)2054 mmu_booke_dumpsys_map(vm_paddr_t pa, size_t sz, void **va)
2055 {
2056 vm_paddr_t ppa;
2057 vm_offset_t ofs;
2058 vm_size_t gran;
2059
2060 /* Minidumps are based on virtual memory addresses. */
2061 if (do_minidump) {
2062 *va = (void *)(vm_offset_t)pa;
2063 return;
2064 }
2065
2066 /* Raw physical memory dumps don't have a virtual address. */
2067 /* We always map a 256MB page at 256M. */
2068 gran = 256 * 1024 * 1024;
2069 ppa = rounddown2(pa, gran);
2070 ofs = pa - ppa;
2071 *va = (void *)gran;
2072 tlb1_set_entry((vm_offset_t)va, ppa, gran, _TLB_ENTRY_IO);
2073
2074 if (sz > (gran - ofs))
2075 tlb1_set_entry((vm_offset_t)(va + gran), ppa + gran, gran,
2076 _TLB_ENTRY_IO);
2077 }
2078
2079 void
mmu_booke_dumpsys_unmap(vm_paddr_t pa,size_t sz,void * va)2080 mmu_booke_dumpsys_unmap(vm_paddr_t pa, size_t sz, void *va)
2081 {
2082 vm_paddr_t ppa;
2083 vm_offset_t ofs;
2084 vm_size_t gran;
2085 tlb_entry_t e;
2086 int i;
2087
2088 /* Minidumps are based on virtual memory addresses. */
2089 /* Nothing to do... */
2090 if (do_minidump)
2091 return;
2092
2093 for (i = 0; i < TLB1_ENTRIES; i++) {
2094 tlb1_read_entry(&e, i);
2095 if (!(e.mas1 & MAS1_VALID))
2096 break;
2097 }
2098
2099 /* Raw physical memory dumps don't have a virtual address. */
2100 i--;
2101 e.mas1 = 0;
2102 e.mas2 = 0;
2103 e.mas3 = 0;
2104 tlb1_write_entry(&e, i);
2105
2106 gran = 256 * 1024 * 1024;
2107 ppa = rounddown2(pa, gran);
2108 ofs = pa - ppa;
2109 if (sz > (gran - ofs)) {
2110 i--;
2111 e.mas1 = 0;
2112 e.mas2 = 0;
2113 e.mas3 = 0;
2114 tlb1_write_entry(&e, i);
2115 }
2116 }
2117
2118 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1];
2119
2120 void
mmu_booke_scan_init()2121 mmu_booke_scan_init()
2122 {
2123 vm_offset_t va;
2124 pte_t *pte;
2125 int i;
2126
2127 if (!do_minidump) {
2128 /* Initialize phys. segments for dumpsys(). */
2129 memset(&dump_map, 0, sizeof(dump_map));
2130 mem_regions(&physmem_regions, &physmem_regions_sz, &availmem_regions,
2131 &availmem_regions_sz);
2132 for (i = 0; i < physmem_regions_sz; i++) {
2133 dump_map[i].pa_start = physmem_regions[i].mr_start;
2134 dump_map[i].pa_size = physmem_regions[i].mr_size;
2135 }
2136 return;
2137 }
2138
2139 /* Virtual segments for minidumps: */
2140 memset(&dump_map, 0, sizeof(dump_map));
2141
2142 /* 1st: kernel .data and .bss. */
2143 dump_map[0].pa_start = trunc_page((uintptr_t)_etext);
2144 dump_map[0].pa_size =
2145 round_page((uintptr_t)_end) - dump_map[0].pa_start;
2146
2147 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */
2148 dump_map[1].pa_start = data_start;
2149 dump_map[1].pa_size = data_end - data_start;
2150
2151 /* 3rd: kernel VM. */
2152 va = dump_map[1].pa_start + dump_map[1].pa_size;
2153 /* Find start of next chunk (from va). */
2154 while (va < virtual_end) {
2155 /* Don't dump the buffer cache. */
2156 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) {
2157 va = kmi.buffer_eva;
2158 continue;
2159 }
2160 pte = pte_find(kernel_pmap, va);
2161 if (pte != NULL && PTE_ISVALID(pte))
2162 break;
2163 va += PAGE_SIZE;
2164 }
2165 if (va < virtual_end) {
2166 dump_map[2].pa_start = va;
2167 va += PAGE_SIZE;
2168 /* Find last page in chunk. */
2169 while (va < virtual_end) {
2170 /* Don't run into the buffer cache. */
2171 if (va == kmi.buffer_sva)
2172 break;
2173 pte = pte_find(kernel_pmap, va);
2174 if (pte == NULL || !PTE_ISVALID(pte))
2175 break;
2176 va += PAGE_SIZE;
2177 }
2178 dump_map[2].pa_size = va - dump_map[2].pa_start;
2179 }
2180 }
2181
2182 /*
2183 * Map a set of physical memory pages into the kernel virtual address space.
2184 * Return a pointer to where it is mapped. This routine is intended to be used
2185 * for mapping device memory, NOT real memory.
2186 */
2187 static void *
mmu_booke_mapdev(vm_paddr_t pa,vm_size_t size)2188 mmu_booke_mapdev(vm_paddr_t pa, vm_size_t size)
2189 {
2190
2191 return (mmu_booke_mapdev_attr(pa, size, VM_MEMATTR_DEFAULT));
2192 }
2193
2194 static int
tlb1_find_pa(vm_paddr_t pa,tlb_entry_t * e)2195 tlb1_find_pa(vm_paddr_t pa, tlb_entry_t *e)
2196 {
2197 int i;
2198
2199 for (i = 0; i < TLB1_ENTRIES; i++) {
2200 tlb1_read_entry(e, i);
2201 if ((e->mas1 & MAS1_VALID) == 0)
2202 continue;
2203 if (e->phys == pa)
2204 return (i);
2205 }
2206 return (-1);
2207 }
2208
2209 static void *
mmu_booke_mapdev_attr(vm_paddr_t pa,vm_size_t size,vm_memattr_t ma)2210 mmu_booke_mapdev_attr(vm_paddr_t pa, vm_size_t size, vm_memattr_t ma)
2211 {
2212 tlb_entry_t e;
2213 vm_paddr_t tmppa;
2214 #ifndef __powerpc64__
2215 uintptr_t tmpva;
2216 #endif
2217 uintptr_t va, retva;
2218 vm_size_t sz;
2219 int i;
2220 int wimge;
2221
2222 /*
2223 * Check if this is premapped in TLB1.
2224 */
2225 sz = size;
2226 tmppa = pa;
2227 va = ~0;
2228 wimge = tlb_calc_wimg(pa, ma);
2229 for (i = 0; i < TLB1_ENTRIES; i++) {
2230 tlb1_read_entry(&e, i);
2231 if (!(e.mas1 & MAS1_VALID))
2232 continue;
2233 if (wimge != (e.mas2 & (MAS2_WIMGE_MASK & ~_TLB_ENTRY_SHARED)))
2234 continue;
2235 if (tmppa >= e.phys && tmppa < e.phys + e.size) {
2236 va = e.virt + (pa - e.phys);
2237 tmppa = e.phys + e.size;
2238 sz -= MIN(sz, e.size - (pa - e.phys));
2239 while (sz > 0 && (i = tlb1_find_pa(tmppa, &e)) != -1) {
2240 if (wimge != (e.mas2 & (MAS2_WIMGE_MASK & ~_TLB_ENTRY_SHARED)))
2241 break;
2242 sz -= MIN(sz, e.size);
2243 tmppa = e.phys + e.size;
2244 }
2245 if (sz != 0)
2246 break;
2247 return ((void *)va);
2248 }
2249 }
2250
2251 size = roundup(size, PAGE_SIZE);
2252
2253 #ifdef __powerpc64__
2254 KASSERT(pa < VM_MAPDEV_PA_MAX,
2255 ("Unsupported physical address! %lx", pa));
2256 va = VM_MAPDEV_BASE + pa;
2257 retva = va;
2258 #ifdef POW2_MAPPINGS
2259 /*
2260 * Align the mapping to a power of 2 size, taking into account that we
2261 * may need to increase the size multiple times to satisfy the size and
2262 * alignment requirements.
2263 *
2264 * This works in the general case because it's very rare (near never?)
2265 * to have different access properties (WIMG) within a single
2266 * power-of-two region. If a design does call for that, POW2_MAPPINGS
2267 * can be undefined, and exact mappings will be used instead.
2268 */
2269 sz = size;
2270 size = roundup2(size, 1 << ilog2(size));
2271 while (rounddown2(va, size) + size < va + sz)
2272 size <<= 1;
2273 va = rounddown2(va, size);
2274 pa = rounddown2(pa, size);
2275 #endif
2276 #else
2277 /*
2278 * The device mapping area is between VM_MAXUSER_ADDRESS and
2279 * VM_MIN_KERNEL_ADDRESS. This gives 1GB of device addressing.
2280 */
2281 #ifdef SPARSE_MAPDEV
2282 /*
2283 * With a sparse mapdev, align to the largest starting region. This
2284 * could feasibly be optimized for a 'best-fit' alignment, but that
2285 * calculation could be very costly.
2286 * Align to the smaller of:
2287 * - first set bit in overlap of (pa & size mask)
2288 * - largest size envelope
2289 *
2290 * It's possible the device mapping may start at a PA that's not larger
2291 * than the size mask, so we need to offset in to maximize the TLB entry
2292 * range and minimize the number of used TLB entries.
2293 */
2294 do {
2295 tmpva = tlb1_map_base;
2296 sz = ffsl((~((1 << flsl(size-1)) - 1)) & pa);
2297 sz = sz ? min(roundup(sz + 3, 4), flsl(size) - 1) : flsl(size) - 1;
2298 va = roundup(tlb1_map_base, 1 << sz) | (((1 << sz) - 1) & pa);
2299 } while (!atomic_cmpset_int(&tlb1_map_base, tmpva, va + size));
2300 #endif
2301 va = atomic_fetchadd_int(&tlb1_map_base, size);
2302 retva = va;
2303 #endif
2304
2305 if (tlb1_mapin_region(va, pa, size, tlb_calc_wimg(pa, ma)) != size)
2306 return (NULL);
2307
2308 return ((void *)retva);
2309 }
2310
2311 /*
2312 * 'Unmap' a range mapped by mmu_booke_mapdev().
2313 */
2314 static void
mmu_booke_unmapdev(vm_offset_t va,vm_size_t size)2315 mmu_booke_unmapdev(vm_offset_t va, vm_size_t size)
2316 {
2317 #ifdef SUPPORTS_SHRINKING_TLB1
2318 vm_offset_t base, offset;
2319
2320 /*
2321 * Unmap only if this is inside kernel virtual space.
2322 */
2323 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) {
2324 base = trunc_page(va);
2325 offset = va & PAGE_MASK;
2326 size = roundup(offset + size, PAGE_SIZE);
2327 mmu_booke_qremove(base, atop(size));
2328 kva_free(base, size);
2329 }
2330 #endif
2331 }
2332
2333 /*
2334 * mmu_booke_object_init_pt preloads the ptes for a given object into the
2335 * specified pmap. This eliminates the blast of soft faults on process startup
2336 * and immediately after an mmap.
2337 */
2338 static void
mmu_booke_object_init_pt(pmap_t pmap,vm_offset_t addr,vm_object_t object,vm_pindex_t pindex,vm_size_t size)2339 mmu_booke_object_init_pt(pmap_t pmap, vm_offset_t addr,
2340 vm_object_t object, vm_pindex_t pindex, vm_size_t size)
2341 {
2342
2343 VM_OBJECT_ASSERT_WLOCKED(object);
2344 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
2345 ("mmu_booke_object_init_pt: non-device object"));
2346 }
2347
2348 /*
2349 * Perform the pmap work for mincore.
2350 */
2351 static int
mmu_booke_mincore(pmap_t pmap,vm_offset_t addr,vm_paddr_t * pap)2352 mmu_booke_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap)
2353 {
2354
2355 /* XXX: this should be implemented at some point */
2356 return (0);
2357 }
2358
2359 static int
mmu_booke_change_attr(vm_offset_t addr,vm_size_t sz,vm_memattr_t mode)2360 mmu_booke_change_attr(vm_offset_t addr, vm_size_t sz, vm_memattr_t mode)
2361 {
2362 vm_offset_t va;
2363 pte_t *pte;
2364 int i, j;
2365 tlb_entry_t e;
2366
2367 addr = trunc_page(addr);
2368
2369 /* Only allow changes to mapped kernel addresses. This includes:
2370 * - KVA
2371 * - DMAP (powerpc64)
2372 * - Device mappings
2373 */
2374 if (addr <= VM_MAXUSER_ADDRESS ||
2375 #ifdef __powerpc64__
2376 (addr >= tlb1_map_base && addr < DMAP_BASE_ADDRESS) ||
2377 (addr > DMAP_MAX_ADDRESS && addr < VM_MIN_KERNEL_ADDRESS) ||
2378 #else
2379 (addr >= tlb1_map_base && addr < VM_MIN_KERNEL_ADDRESS) ||
2380 #endif
2381 (addr > VM_MAX_KERNEL_ADDRESS))
2382 return (EINVAL);
2383
2384 /* Check TLB1 mappings */
2385 for (i = 0; i < TLB1_ENTRIES; i++) {
2386 tlb1_read_entry(&e, i);
2387 if (!(e.mas1 & MAS1_VALID))
2388 continue;
2389 if (addr >= e.virt && addr < e.virt + e.size)
2390 break;
2391 }
2392 if (i < TLB1_ENTRIES) {
2393 /* Only allow full mappings to be modified for now. */
2394 /* Validate the range. */
2395 for (j = i, va = addr; va < addr + sz; va += e.size, j++) {
2396 tlb1_read_entry(&e, j);
2397 if (va != e.virt || (sz - (va - addr) < e.size))
2398 return (EINVAL);
2399 }
2400 for (va = addr; va < addr + sz; va += e.size, i++) {
2401 tlb1_read_entry(&e, i);
2402 e.mas2 &= ~MAS2_WIMGE_MASK;
2403 e.mas2 |= tlb_calc_wimg(e.phys, mode);
2404
2405 /*
2406 * Write it out to the TLB. Should really re-sync with other
2407 * cores.
2408 */
2409 tlb1_write_entry(&e, i);
2410 }
2411 return (0);
2412 }
2413
2414 /* Not in TLB1, try through pmap */
2415 /* First validate the range. */
2416 for (va = addr; va < addr + sz; va += PAGE_SIZE) {
2417 pte = pte_find(kernel_pmap, va);
2418 if (pte == NULL || !PTE_ISVALID(pte))
2419 return (EINVAL);
2420 }
2421
2422 mtx_lock_spin(&tlbivax_mutex);
2423 tlb_miss_lock();
2424 for (va = addr; va < addr + sz; va += PAGE_SIZE) {
2425 pte = pte_find(kernel_pmap, va);
2426 *pte &= ~(PTE_MAS2_MASK << PTE_MAS2_SHIFT);
2427 *pte |= tlb_calc_wimg(PTE_PA(pte), mode) << PTE_MAS2_SHIFT;
2428 tlb0_flush_entry(va);
2429 }
2430 tlb_miss_unlock();
2431 mtx_unlock_spin(&tlbivax_mutex);
2432
2433 return (0);
2434 }
2435
2436 static void
mmu_booke_page_array_startup(long pages)2437 mmu_booke_page_array_startup(long pages)
2438 {
2439 vm_page_array_size = pages;
2440 }
2441
2442 /**************************************************************************/
2443 /* TID handling */
2444 /**************************************************************************/
2445
2446 /*
2447 * Allocate a TID. If necessary, steal one from someone else.
2448 * The new TID is flushed from the TLB before returning.
2449 */
2450 static tlbtid_t
tid_alloc(pmap_t pmap)2451 tid_alloc(pmap_t pmap)
2452 {
2453 tlbtid_t tid;
2454 int thiscpu;
2455
2456 KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap"));
2457
2458 CTR2(KTR_PMAP, "%s: s (pmap = %p)", __func__, pmap);
2459
2460 thiscpu = PCPU_GET(cpuid);
2461
2462 tid = PCPU_GET(booke.tid_next);
2463 if (tid > TID_MAX)
2464 tid = TID_MIN;
2465 PCPU_SET(booke.tid_next, tid + 1);
2466
2467 /* If we are stealing TID then clear the relevant pmap's field */
2468 if (tidbusy[thiscpu][tid] != NULL) {
2469 CTR2(KTR_PMAP, "%s: warning: stealing tid %d", __func__, tid);
2470
2471 tidbusy[thiscpu][tid]->pm_tid[thiscpu] = TID_NONE;
2472
2473 /* Flush all entries from TLB0 matching this TID. */
2474 tid_flush(tid);
2475 }
2476
2477 tidbusy[thiscpu][tid] = pmap;
2478 pmap->pm_tid[thiscpu] = tid;
2479 __asm __volatile("msync; isync");
2480
2481 CTR3(KTR_PMAP, "%s: e (%02d next = %02d)", __func__, tid,
2482 PCPU_GET(booke.tid_next));
2483
2484 return (tid);
2485 }
2486
2487 /**************************************************************************/
2488 /* TLB0 handling */
2489 /**************************************************************************/
2490
2491 /* Convert TLB0 va and way number to tlb0[] table index. */
2492 static inline unsigned int
tlb0_tableidx(vm_offset_t va,unsigned int way)2493 tlb0_tableidx(vm_offset_t va, unsigned int way)
2494 {
2495 unsigned int idx;
2496
2497 idx = (way * TLB0_ENTRIES_PER_WAY);
2498 idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT;
2499 return (idx);
2500 }
2501
2502 /*
2503 * Invalidate TLB0 entry.
2504 */
2505 static inline void
tlb0_flush_entry(vm_offset_t va)2506 tlb0_flush_entry(vm_offset_t va)
2507 {
2508
2509 CTR2(KTR_PMAP, "%s: s va=0x%08x", __func__, va);
2510
2511 mtx_assert(&tlbivax_mutex, MA_OWNED);
2512
2513 __asm __volatile("tlbivax 0, %0" :: "r"(va & MAS2_EPN_MASK));
2514 __asm __volatile("isync; msync");
2515 __asm __volatile("tlbsync; msync");
2516
2517 CTR1(KTR_PMAP, "%s: e", __func__);
2518 }
2519
2520 /**************************************************************************/
2521 /* TLB1 handling */
2522 /**************************************************************************/
2523
2524 /*
2525 * TLB1 mapping notes:
2526 *
2527 * TLB1[0] Kernel text and data.
2528 * TLB1[1-15] Additional kernel text and data mappings (if required), PCI
2529 * windows, other devices mappings.
2530 */
2531
2532 /*
2533 * Read an entry from given TLB1 slot.
2534 */
2535 void
tlb1_read_entry(tlb_entry_t * entry,unsigned int slot)2536 tlb1_read_entry(tlb_entry_t *entry, unsigned int slot)
2537 {
2538 register_t msr;
2539 uint32_t mas0;
2540
2541 KASSERT((entry != NULL), ("%s(): Entry is NULL!", __func__));
2542
2543 msr = mfmsr();
2544 __asm __volatile("wrteei 0");
2545
2546 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(slot);
2547 mtspr(SPR_MAS0, mas0);
2548 __asm __volatile("isync; tlbre");
2549
2550 entry->mas1 = mfspr(SPR_MAS1);
2551 entry->mas2 = mfspr(SPR_MAS2);
2552 entry->mas3 = mfspr(SPR_MAS3);
2553
2554 switch ((mfpvr() >> 16) & 0xFFFF) {
2555 case FSL_E500v2:
2556 case FSL_E500mc:
2557 case FSL_E5500:
2558 case FSL_E6500:
2559 entry->mas7 = mfspr(SPR_MAS7);
2560 break;
2561 default:
2562 entry->mas7 = 0;
2563 break;
2564 }
2565 __asm __volatile("wrtee %0" :: "r"(msr));
2566
2567 entry->virt = entry->mas2 & MAS2_EPN_MASK;
2568 entry->phys = ((vm_paddr_t)(entry->mas7 & MAS7_RPN) << 32) |
2569 (entry->mas3 & MAS3_RPN);
2570 entry->size =
2571 tsize2size((entry->mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT);
2572 }
2573
2574 struct tlbwrite_args {
2575 tlb_entry_t *e;
2576 unsigned int idx;
2577 };
2578
2579 static uint32_t
tlb1_find_free(void)2580 tlb1_find_free(void)
2581 {
2582 tlb_entry_t e;
2583 int i;
2584
2585 for (i = 0; i < TLB1_ENTRIES; i++) {
2586 tlb1_read_entry(&e, i);
2587 if ((e.mas1 & MAS1_VALID) == 0)
2588 return (i);
2589 }
2590 return (-1);
2591 }
2592
2593 static void
tlb1_purge_va_range(vm_offset_t va,vm_size_t size)2594 tlb1_purge_va_range(vm_offset_t va, vm_size_t size)
2595 {
2596 tlb_entry_t e;
2597 int i;
2598
2599 for (i = 0; i < TLB1_ENTRIES; i++) {
2600 tlb1_read_entry(&e, i);
2601 if ((e.mas1 & MAS1_VALID) == 0)
2602 continue;
2603 if ((e.mas2 & MAS2_EPN_MASK) >= va &&
2604 (e.mas2 & MAS2_EPN_MASK) < va + size) {
2605 mtspr(SPR_MAS1, e.mas1 & ~MAS1_VALID);
2606 __asm __volatile("isync; tlbwe; isync; msync");
2607 }
2608 }
2609 }
2610
2611 static void
tlb1_write_entry_int(void * arg)2612 tlb1_write_entry_int(void *arg)
2613 {
2614 struct tlbwrite_args *args = arg;
2615 uint32_t idx, mas0;
2616
2617 idx = args->idx;
2618 if (idx == -1) {
2619 tlb1_purge_va_range(args->e->virt, args->e->size);
2620 idx = tlb1_find_free();
2621 if (idx == -1)
2622 panic("No free TLB1 entries!\n");
2623 }
2624 /* Select entry */
2625 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(idx);
2626
2627 mtspr(SPR_MAS0, mas0);
2628 mtspr(SPR_MAS1, args->e->mas1);
2629 mtspr(SPR_MAS2, args->e->mas2);
2630 mtspr(SPR_MAS3, args->e->mas3);
2631 switch ((mfpvr() >> 16) & 0xFFFF) {
2632 case FSL_E500mc:
2633 case FSL_E5500:
2634 case FSL_E6500:
2635 mtspr(SPR_MAS8, 0);
2636 /* FALLTHROUGH */
2637 case FSL_E500v2:
2638 mtspr(SPR_MAS7, args->e->mas7);
2639 break;
2640 default:
2641 break;
2642 }
2643
2644 __asm __volatile("isync; tlbwe; isync; msync");
2645
2646 }
2647
2648 static void
tlb1_write_entry_sync(void * arg)2649 tlb1_write_entry_sync(void *arg)
2650 {
2651 /* Empty synchronization point for smp_rendezvous(). */
2652 }
2653
2654 /*
2655 * Write given entry to TLB1 hardware.
2656 */
2657 static void
tlb1_write_entry(tlb_entry_t * e,unsigned int idx)2658 tlb1_write_entry(tlb_entry_t *e, unsigned int idx)
2659 {
2660 struct tlbwrite_args args;
2661
2662 args.e = e;
2663 args.idx = idx;
2664
2665 #ifdef SMP
2666 if ((e->mas2 & _TLB_ENTRY_SHARED) && smp_started) {
2667 mb();
2668 smp_rendezvous(tlb1_write_entry_sync,
2669 tlb1_write_entry_int,
2670 tlb1_write_entry_sync, &args);
2671 } else
2672 #endif
2673 {
2674 register_t msr;
2675
2676 msr = mfmsr();
2677 __asm __volatile("wrteei 0");
2678 tlb1_write_entry_int(&args);
2679 __asm __volatile("wrtee %0" :: "r"(msr));
2680 }
2681 }
2682
2683 /*
2684 * Convert TLB TSIZE value to mapped region size.
2685 */
2686 static vm_size_t
tsize2size(unsigned int tsize)2687 tsize2size(unsigned int tsize)
2688 {
2689
2690 /*
2691 * size = 4^tsize KB
2692 * size = 4^tsize * 2^10 = 2^(2 * tsize - 10)
2693 */
2694
2695 return ((1 << (2 * tsize)) * 1024);
2696 }
2697
2698 /*
2699 * Convert region size (must be power of 4) to TLB TSIZE value.
2700 */
2701 static unsigned int
size2tsize(vm_size_t size)2702 size2tsize(vm_size_t size)
2703 {
2704
2705 return (ilog2(size) / 2 - 5);
2706 }
2707
2708 /*
2709 * Register permanent kernel mapping in TLB1.
2710 *
2711 * Entries are created starting from index 0 (current free entry is
2712 * kept in tlb1_idx) and are not supposed to be invalidated.
2713 */
2714 int
tlb1_set_entry(vm_offset_t va,vm_paddr_t pa,vm_size_t size,uint32_t flags)2715 tlb1_set_entry(vm_offset_t va, vm_paddr_t pa, vm_size_t size,
2716 uint32_t flags)
2717 {
2718 tlb_entry_t e;
2719 uint32_t ts, tid;
2720 int tsize, index;
2721
2722 /* First try to update an existing entry. */
2723 for (index = 0; index < TLB1_ENTRIES; index++) {
2724 tlb1_read_entry(&e, index);
2725 /* Check if we're just updating the flags, and update them. */
2726 if (e.phys == pa && e.virt == va && e.size == size) {
2727 e.mas2 = (va & MAS2_EPN_MASK) | flags;
2728 tlb1_write_entry(&e, index);
2729 return (0);
2730 }
2731 }
2732
2733 /* Convert size to TSIZE */
2734 tsize = size2tsize(size);
2735
2736 tid = (TID_KERNEL << MAS1_TID_SHIFT) & MAS1_TID_MASK;
2737 /* XXX TS is hard coded to 0 for now as we only use single address space */
2738 ts = (0 << MAS1_TS_SHIFT) & MAS1_TS_MASK;
2739
2740 e.phys = pa;
2741 e.virt = va;
2742 e.size = size;
2743 e.mas1 = MAS1_VALID | MAS1_IPROT | ts | tid;
2744 e.mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK);
2745 e.mas2 = (va & MAS2_EPN_MASK) | flags;
2746
2747 /* Set supervisor RWX permission bits */
2748 e.mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX;
2749 e.mas7 = (pa >> 32) & MAS7_RPN;
2750
2751 tlb1_write_entry(&e, -1);
2752
2753 return (0);
2754 }
2755
2756 /*
2757 * Map in contiguous RAM region into the TLB1.
2758 */
2759 static vm_size_t
tlb1_mapin_region(vm_offset_t va,vm_paddr_t pa,vm_size_t size,int wimge)2760 tlb1_mapin_region(vm_offset_t va, vm_paddr_t pa, vm_size_t size, int wimge)
2761 {
2762 vm_offset_t base;
2763 vm_size_t mapped, sz, ssize;
2764
2765 mapped = 0;
2766 base = va;
2767 ssize = size;
2768
2769 while (size > 0) {
2770 sz = 1UL << (ilog2(size) & ~1);
2771 /* Align size to PA */
2772 if (pa % sz != 0) {
2773 do {
2774 sz >>= 2;
2775 } while (pa % sz != 0);
2776 }
2777 /* Now align from there to VA */
2778 if (va % sz != 0) {
2779 do {
2780 sz >>= 2;
2781 } while (va % sz != 0);
2782 }
2783 #ifdef __powerpc64__
2784 /*
2785 * Clamp TLB1 entries to 4G.
2786 *
2787 * While the e6500 supports up to 1TB mappings, the e5500
2788 * only supports up to 4G mappings. (0b1011)
2789 *
2790 * If any e6500 machines capable of supporting a very
2791 * large amount of memory appear in the future, we can
2792 * revisit this.
2793 *
2794 * For now, though, since we have plenty of space in TLB1,
2795 * always avoid creating entries larger than 4GB.
2796 */
2797 sz = MIN(sz, 1UL << 32);
2798 #endif
2799 if (bootverbose)
2800 printf("Wiring VA=%p to PA=%jx (size=%lx)\n",
2801 (void *)va, (uintmax_t)pa, (long)sz);
2802 if (tlb1_set_entry(va, pa, sz,
2803 _TLB_ENTRY_SHARED | wimge) < 0)
2804 return (mapped);
2805 size -= sz;
2806 pa += sz;
2807 va += sz;
2808 }
2809
2810 mapped = (va - base);
2811 if (bootverbose)
2812 printf("mapped size 0x%"PRIxPTR" (wasted space 0x%"PRIxPTR")\n",
2813 mapped, mapped - ssize);
2814
2815 return (mapped);
2816 }
2817
2818 /*
2819 * TLB1 initialization routine, to be called after the very first
2820 * assembler level setup done in locore.S.
2821 */
2822 void
tlb1_init()2823 tlb1_init()
2824 {
2825 vm_offset_t mas2;
2826 uint32_t mas0, mas1, mas3, mas7;
2827 uint32_t tsz;
2828
2829 tlb1_get_tlbconf();
2830
2831 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(0);
2832 mtspr(SPR_MAS0, mas0);
2833 __asm __volatile("isync; tlbre");
2834
2835 mas1 = mfspr(SPR_MAS1);
2836 mas2 = mfspr(SPR_MAS2);
2837 mas3 = mfspr(SPR_MAS3);
2838 mas7 = mfspr(SPR_MAS7);
2839
2840 kernload = ((vm_paddr_t)(mas7 & MAS7_RPN) << 32) |
2841 (mas3 & MAS3_RPN);
2842
2843 tsz = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
2844 kernsize += (tsz > 0) ? tsize2size(tsz) : 0;
2845 kernstart = trunc_page(mas2);
2846
2847 /* Setup TLB miss defaults */
2848 set_mas4_defaults();
2849 }
2850
2851 /*
2852 * pmap_early_io_unmap() should be used in short conjunction with
2853 * pmap_early_io_map(), as in the following snippet:
2854 *
2855 * x = pmap_early_io_map(...);
2856 * <do something with x>
2857 * pmap_early_io_unmap(x, size);
2858 *
2859 * And avoiding more allocations between.
2860 */
2861 void
pmap_early_io_unmap(vm_offset_t va,vm_size_t size)2862 pmap_early_io_unmap(vm_offset_t va, vm_size_t size)
2863 {
2864 int i;
2865 tlb_entry_t e;
2866 vm_size_t isize;
2867
2868 size = roundup(size, PAGE_SIZE);
2869 isize = size;
2870 for (i = 0; i < TLB1_ENTRIES && size > 0; i++) {
2871 tlb1_read_entry(&e, i);
2872 if (!(e.mas1 & MAS1_VALID))
2873 continue;
2874 if (va <= e.virt && (va + isize) >= (e.virt + e.size)) {
2875 size -= e.size;
2876 e.mas1 &= ~MAS1_VALID;
2877 tlb1_write_entry(&e, i);
2878 }
2879 }
2880 if (tlb1_map_base == va + isize)
2881 tlb1_map_base -= isize;
2882 }
2883
2884 vm_offset_t
pmap_early_io_map(vm_paddr_t pa,vm_size_t size)2885 pmap_early_io_map(vm_paddr_t pa, vm_size_t size)
2886 {
2887 vm_paddr_t pa_base;
2888 vm_offset_t va, sz;
2889 int i;
2890 tlb_entry_t e;
2891
2892 KASSERT(!pmap_bootstrapped, ("Do not use after PMAP is up!"));
2893
2894 for (i = 0; i < TLB1_ENTRIES; i++) {
2895 tlb1_read_entry(&e, i);
2896 if (!(e.mas1 & MAS1_VALID))
2897 continue;
2898 if (pa >= e.phys && (pa + size) <=
2899 (e.phys + e.size))
2900 return (e.virt + (pa - e.phys));
2901 }
2902
2903 pa_base = rounddown(pa, PAGE_SIZE);
2904 size = roundup(size + (pa - pa_base), PAGE_SIZE);
2905 tlb1_map_base = roundup2(tlb1_map_base, 1 << (ilog2(size) & ~1));
2906 va = tlb1_map_base + (pa - pa_base);
2907
2908 do {
2909 sz = 1 << (ilog2(size) & ~1);
2910 tlb1_set_entry(tlb1_map_base, pa_base, sz,
2911 _TLB_ENTRY_SHARED | _TLB_ENTRY_IO);
2912 size -= sz;
2913 pa_base += sz;
2914 tlb1_map_base += sz;
2915 } while (size > 0);
2916
2917 return (va);
2918 }
2919
2920 void
pmap_track_page(pmap_t pmap,vm_offset_t va)2921 pmap_track_page(pmap_t pmap, vm_offset_t va)
2922 {
2923 vm_paddr_t pa;
2924 vm_page_t page;
2925 struct pv_entry *pve;
2926
2927 va = trunc_page(va);
2928 pa = pmap_kextract(va);
2929 page = PHYS_TO_VM_PAGE(pa);
2930
2931 rw_wlock(&pvh_global_lock);
2932 PMAP_LOCK(pmap);
2933
2934 TAILQ_FOREACH(pve, &page->md.pv_list, pv_link) {
2935 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) {
2936 goto out;
2937 }
2938 }
2939 page->md.pv_tracked = true;
2940 pv_insert(pmap, va, page);
2941 out:
2942 PMAP_UNLOCK(pmap);
2943 rw_wunlock(&pvh_global_lock);
2944 }
2945
2946 /*
2947 * Setup MAS4 defaults.
2948 * These values are loaded to MAS0-2 on a TLB miss.
2949 */
2950 static void
set_mas4_defaults(void)2951 set_mas4_defaults(void)
2952 {
2953 uint32_t mas4;
2954
2955 /* Defaults: TLB0, PID0, TSIZED=4K */
2956 mas4 = MAS4_TLBSELD0;
2957 mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK;
2958 #ifdef SMP
2959 mas4 |= MAS4_MD;
2960 #endif
2961 mtspr(SPR_MAS4, mas4);
2962 __asm __volatile("isync");
2963 }
2964
2965 /*
2966 * Return 0 if the physical IO range is encompassed by one of the
2967 * the TLB1 entries, otherwise return related error code.
2968 */
2969 static int
tlb1_iomapped(int i,vm_paddr_t pa,vm_size_t size,vm_offset_t * va)2970 tlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va)
2971 {
2972 uint32_t prot;
2973 vm_paddr_t pa_start;
2974 vm_paddr_t pa_end;
2975 unsigned int entry_tsize;
2976 vm_size_t entry_size;
2977 tlb_entry_t e;
2978
2979 *va = (vm_offset_t)NULL;
2980
2981 tlb1_read_entry(&e, i);
2982 /* Skip invalid entries */
2983 if (!(e.mas1 & MAS1_VALID))
2984 return (EINVAL);
2985
2986 /*
2987 * The entry must be cache-inhibited, guarded, and r/w
2988 * so it can function as an i/o page
2989 */
2990 prot = e.mas2 & (MAS2_I | MAS2_G);
2991 if (prot != (MAS2_I | MAS2_G))
2992 return (EPERM);
2993
2994 prot = e.mas3 & (MAS3_SR | MAS3_SW);
2995 if (prot != (MAS3_SR | MAS3_SW))
2996 return (EPERM);
2997
2998 /* The address should be within the entry range. */
2999 entry_tsize = (e.mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
3000 KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize"));
3001
3002 entry_size = tsize2size(entry_tsize);
3003 pa_start = (((vm_paddr_t)e.mas7 & MAS7_RPN) << 32) |
3004 (e.mas3 & MAS3_RPN);
3005 pa_end = pa_start + entry_size;
3006
3007 if ((pa < pa_start) || ((pa + size) > pa_end))
3008 return (ERANGE);
3009
3010 /* Return virtual address of this mapping. */
3011 *va = (e.mas2 & MAS2_EPN_MASK) + (pa - pa_start);
3012 return (0);
3013 }
3014
3015 #ifdef DDB
3016 /* Print out contents of the MAS registers for each TLB0 entry */
3017 static void
3018 #ifdef __powerpc64__
tlb_print_entry(int i,uint32_t mas1,uint64_t mas2,uint32_t mas3,uint32_t mas7)3019 tlb_print_entry(int i, uint32_t mas1, uint64_t mas2, uint32_t mas3,
3020 #else
3021 tlb_print_entry(int i, uint32_t mas1, uint32_t mas2, uint32_t mas3,
3022 #endif
3023 uint32_t mas7)
3024 {
3025 int as;
3026 char desc[3];
3027 tlbtid_t tid;
3028 vm_size_t size;
3029 unsigned int tsize;
3030
3031 desc[2] = '\0';
3032 if (mas1 & MAS1_VALID)
3033 desc[0] = 'V';
3034 else
3035 desc[0] = ' ';
3036
3037 if (mas1 & MAS1_IPROT)
3038 desc[1] = 'P';
3039 else
3040 desc[1] = ' ';
3041
3042 as = (mas1 & MAS1_TS_MASK) ? 1 : 0;
3043 tid = MAS1_GETTID(mas1);
3044
3045 tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
3046 size = 0;
3047 if (tsize)
3048 size = tsize2size(tsize);
3049
3050 printf("%3d: (%s) [AS=%d] "
3051 "sz = 0x%jx tsz = %d tid = %d mas1 = 0x%08x "
3052 "mas2(va) = 0x%"PRI0ptrX" mas3(pa) = 0x%08x mas7 = 0x%08x\n",
3053 i, desc, as, (uintmax_t)size, tsize, tid, mas1, mas2, mas3, mas7);
3054 }
3055
DB_SHOW_COMMAND(tlb0,tlb0_print_tlbentries)3056 DB_SHOW_COMMAND(tlb0, tlb0_print_tlbentries)
3057 {
3058 uint32_t mas0, mas1, mas3, mas7;
3059 #ifdef __powerpc64__
3060 uint64_t mas2;
3061 #else
3062 uint32_t mas2;
3063 #endif
3064 int entryidx, way, idx;
3065
3066 printf("TLB0 entries:\n");
3067 for (way = 0; way < TLB0_WAYS; way ++)
3068 for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) {
3069 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way);
3070 mtspr(SPR_MAS0, mas0);
3071
3072 mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT;
3073 mtspr(SPR_MAS2, mas2);
3074
3075 __asm __volatile("isync; tlbre");
3076
3077 mas1 = mfspr(SPR_MAS1);
3078 mas2 = mfspr(SPR_MAS2);
3079 mas3 = mfspr(SPR_MAS3);
3080 mas7 = mfspr(SPR_MAS7);
3081
3082 idx = tlb0_tableidx(mas2, way);
3083 tlb_print_entry(idx, mas1, mas2, mas3, mas7);
3084 }
3085 }
3086
3087 /*
3088 * Print out contents of the MAS registers for each TLB1 entry
3089 */
DB_SHOW_COMMAND(tlb1,tlb1_print_tlbentries)3090 DB_SHOW_COMMAND(tlb1, tlb1_print_tlbentries)
3091 {
3092 uint32_t mas0, mas1, mas3, mas7;
3093 #ifdef __powerpc64__
3094 uint64_t mas2;
3095 #else
3096 uint32_t mas2;
3097 #endif
3098 int i;
3099
3100 printf("TLB1 entries:\n");
3101 for (i = 0; i < TLB1_ENTRIES; i++) {
3102 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i);
3103 mtspr(SPR_MAS0, mas0);
3104
3105 __asm __volatile("isync; tlbre");
3106
3107 mas1 = mfspr(SPR_MAS1);
3108 mas2 = mfspr(SPR_MAS2);
3109 mas3 = mfspr(SPR_MAS3);
3110 mas7 = mfspr(SPR_MAS7);
3111
3112 tlb_print_entry(i, mas1, mas2, mas3, mas7);
3113 }
3114 }
3115 #endif
3116