1 /* $NetBSD: uart.c,v 1.2 2007/03/23 20:05:47 dogcow Exp $ */
2
3 /*-
4 * Copyright (c) 2013, Alexander A. Mityaev <sansan@adm.ua>
5 * Copyright (c) 2010 Aleksandr Rybalko.
6 * Copyright (c) 2007 Ruslan Ermilov and Vsevolod Lobko.
7 * Copyright (c) 2007 Oleksandr Tymoshenko.
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer in the documentation and/or other materials provided
18 * with the distribution.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY
21 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
23 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
25 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
27 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
29 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
30 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
31 * OF SUCH DAMAGE.
32 */
33
34 #include <sys/cdefs.h>
35 #include "opt_ddb.h"
36
37 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/bus.h>
40 #include <sys/conf.h>
41 #include <sys/kdb.h>
42 #include <sys/reboot.h>
43 #include <sys/sysctl.h>
44 #include <sys/kernel.h>
45 #include <machine/bus.h>
46 #include <machine/fdt.h>
47
48 #include <dev/uart/uart.h>
49 #include <dev/uart/uart_cpu.h>
50 #include <dev/uart/uart_cpu_fdt.h>
51 #include <dev/uart/uart_bus.h>
52
53 #include <mips/mediatek/uart_dev_mtk.h>
54 #include <mips/mediatek/mtk_soc.h>
55 #include <mips/mediatek/mtk_sysctl.h>
56
57 #include "uart_if.h"
58
59 /* Set some reference clock value. Real value will be taken from FDT */
60 #define DEFAULT_RCLK (120 * 1000 * 1000)
61
62 /*
63 * Low-level UART interface.
64 */
65 static int mtk_uart_probe(struct uart_bas *bas);
66 static void mtk_uart_init(struct uart_bas *bas, int, int, int, int);
67 static void mtk_uart_term(struct uart_bas *bas);
68 static void mtk_uart_putc(struct uart_bas *bas, int);
69 static int mtk_uart_rxready(struct uart_bas *bas);
70 static int mtk_uart_getc(struct uart_bas *bas, struct mtx *);
71
72 static struct uart_ops uart_mtk_ops = {
73 .probe = mtk_uart_probe,
74 .init = mtk_uart_init,
75 .term = mtk_uart_term,
76 .putc = mtk_uart_putc,
77 .rxready = mtk_uart_rxready,
78 .getc = mtk_uart_getc,
79 };
80
81 static int uart_output = 1;
82 TUNABLE_INT("kern.uart_output", &uart_output);
83 SYSCTL_INT(_kern, OID_AUTO, uart_output, CTLFLAG_RW,
84 &uart_output, 0, "UART output enabled.");
85
86 static int
mtk_uart_probe(struct uart_bas * bas)87 mtk_uart_probe(struct uart_bas *bas)
88 {
89 return (0);
90 }
91
92 static void
mtk_uart_init(struct uart_bas * bas,int baudrate,int databits,int stopbits,int parity)93 mtk_uart_init(struct uart_bas *bas, int baudrate, int databits,
94 int stopbits, int parity)
95 {
96 /* CLKDIV = 384000000/ 3/ 16/ br */
97 /* for 384MHz CLKDIV = 8000000 / baudrate; */
98 switch (databits) {
99 case 5:
100 databits = UART_LCR_5B;
101 break;
102 case 6:
103 databits = UART_LCR_6B;
104 break;
105 case 7:
106 databits = UART_LCR_7B;
107 break;
108 case 8:
109 databits = UART_LCR_8B;
110 break;
111 default:
112 /* Unsupported */
113 return;
114 }
115 switch (parity) {
116 case UART_PARITY_EVEN: parity = (UART_LCR_PEN|UART_LCR_EVEN); break;
117 case UART_PARITY_ODD: parity = (UART_LCR_PEN); break;
118 case UART_PARITY_NONE: parity = 0; break;
119 /* Unsupported */
120 default: return;
121 }
122
123 if (bas->rclk && baudrate) {
124 uart_setreg(bas, UART_CDDL_REG, bas->rclk/16/baudrate);
125 uart_barrier(bas);
126 }
127
128 uart_setreg(bas, UART_LCR_REG, databits |
129 (stopbits==1?0:UART_LCR_STB_15) |
130 parity);
131 uart_barrier(bas);
132 }
133
134 static void
mtk_uart_term(struct uart_bas * bas)135 mtk_uart_term(struct uart_bas *bas)
136 {
137 uart_setreg(bas, UART_MCR_REG, 0);
138 uart_barrier(bas);
139 }
140
141 static void
mtk_uart_putc(struct uart_bas * bas,int c)142 mtk_uart_putc(struct uart_bas *bas, int c)
143 {
144 char chr;
145 if (!uart_output) return;
146 chr = c;
147 while (!(uart_getreg(bas, UART_LSR_REG) & UART_LSR_THRE));
148 uart_setreg(bas, UART_TX_REG, c);
149 uart_barrier(bas);
150 while (!(uart_getreg(bas, UART_LSR_REG) & UART_LSR_THRE));
151 }
152
153 static int
mtk_uart_rxready(struct uart_bas * bas)154 mtk_uart_rxready(struct uart_bas *bas)
155 {
156 if (uart_getreg(bas, UART_LSR_REG) & UART_LSR_DR)
157 return (1);
158 return (0);
159 }
160
161 static int
mtk_uart_getc(struct uart_bas * bas,struct mtx * hwmtx)162 mtk_uart_getc(struct uart_bas *bas, struct mtx *hwmtx)
163 {
164 int c;
165
166 uart_lock(hwmtx);
167
168 while (!(uart_getreg(bas, UART_LSR_REG) & UART_LSR_DR)) {
169 uart_unlock(hwmtx);
170 DELAY(10);
171 uart_lock(hwmtx);
172 }
173
174 c = uart_getreg(bas, UART_RX_REG);
175
176 uart_unlock(hwmtx);
177
178 return (c);
179 }
180
181 /*
182 * High-level UART interface.
183 */
184 struct uart_mtk_softc {
185 struct uart_softc base;
186 uint8_t ier_mask;
187 uint8_t ier;
188 };
189
190 static int mtk_uart_bus_attach(struct uart_softc *);
191 static int mtk_uart_bus_detach(struct uart_softc *);
192 static int mtk_uart_bus_flush(struct uart_softc *, int);
193 static int mtk_uart_bus_getsig(struct uart_softc *);
194 static int mtk_uart_bus_ioctl(struct uart_softc *, int, intptr_t);
195 static int mtk_uart_bus_ipend(struct uart_softc *);
196 static int mtk_uart_bus_param(struct uart_softc *, int, int, int, int);
197 static int mtk_uart_bus_probe(struct uart_softc *);
198 static int mtk_uart_bus_receive(struct uart_softc *);
199 static int mtk_uart_bus_setsig(struct uart_softc *, int);
200 static int mtk_uart_bus_transmit(struct uart_softc *);
201 static void mtk_uart_bus_grab(struct uart_softc *);
202 static void mtk_uart_bus_ungrab(struct uart_softc *);
203
204 static kobj_method_t uart_mtk_methods[] = {
205 KOBJMETHOD(uart_attach, mtk_uart_bus_attach),
206 KOBJMETHOD(uart_detach, mtk_uart_bus_detach),
207 KOBJMETHOD(uart_flush, mtk_uart_bus_flush),
208 KOBJMETHOD(uart_getsig, mtk_uart_bus_getsig),
209 KOBJMETHOD(uart_ioctl, mtk_uart_bus_ioctl),
210 KOBJMETHOD(uart_ipend, mtk_uart_bus_ipend),
211 KOBJMETHOD(uart_param, mtk_uart_bus_param),
212 KOBJMETHOD(uart_probe, mtk_uart_bus_probe),
213 KOBJMETHOD(uart_receive, mtk_uart_bus_receive),
214 KOBJMETHOD(uart_setsig, mtk_uart_bus_setsig),
215 KOBJMETHOD(uart_transmit, mtk_uart_bus_transmit),
216 KOBJMETHOD(uart_grab, mtk_uart_bus_grab),
217 KOBJMETHOD(uart_ungrab, mtk_uart_bus_ungrab),
218 { 0, 0 }
219 };
220
221 struct uart_class uart_mtk_class = {
222 "uart_mtk",
223 uart_mtk_methods,
224 sizeof(struct uart_mtk_softc),
225 .uc_ops = &uart_mtk_ops,
226 .uc_range = 1, /* use hinted range */
227 .uc_rclk = 0
228 };
229
230 static struct ofw_compat_data compat_data[] = {
231 { "ralink,rt2880-uart", (uintptr_t)&uart_mtk_class },
232 { "ralink,rt3050-uart", (uintptr_t)&uart_mtk_class },
233 { "ralink,rt3352-uart", (uintptr_t)&uart_mtk_class },
234 { "ralink,rt3883-uart", (uintptr_t)&uart_mtk_class },
235 { "ralink,rt5350-uart", (uintptr_t)&uart_mtk_class },
236 { "ralink,mt7620a-uart", (uintptr_t)&uart_mtk_class },
237 { NULL, (uintptr_t)NULL },
238 };
239 UART_FDT_CLASS_AND_DEVICE(compat_data);
240
241 #define SIGCHG(c, i, s, d) \
242 if (c) { \
243 i |= (i & s) ? s : s | d; \
244 } else { \
245 i = (i & s) ? (i & ~s) | d : i; \
246 }
247
248 /*
249 * Disable TX interrupt. uart should be locked
250 */
251 static __inline void
mtk_uart_disable_txintr(struct uart_softc * sc)252 mtk_uart_disable_txintr(struct uart_softc *sc)
253 {
254 struct uart_bas *bas = &sc->sc_bas;
255 uint8_t cr;
256
257 cr = uart_getreg(bas, UART_IER_REG);
258 cr &= ~UART_IER_ETBEI;
259 uart_setreg(bas, UART_IER_REG, cr);
260 uart_barrier(bas);
261 }
262
263 /*
264 * Enable TX interrupt. uart should be locked
265 */
266 static __inline void
mtk_uart_enable_txintr(struct uart_softc * sc)267 mtk_uart_enable_txintr(struct uart_softc *sc)
268 {
269 struct uart_bas *bas = &sc->sc_bas;
270 uint8_t cr;
271
272 cr = uart_getreg(bas, UART_IER_REG);
273 cr |= UART_IER_ETBEI;
274 uart_setreg(bas, UART_IER_REG, cr);
275 uart_barrier(bas);
276 }
277
278 static int
mtk_uart_bus_attach(struct uart_softc * sc)279 mtk_uart_bus_attach(struct uart_softc *sc)
280 {
281 struct uart_bas *bas;
282 struct uart_devinfo *di;
283 struct uart_mtk_softc *usc = (struct uart_mtk_softc *)sc;
284
285 bas = &sc->sc_bas;
286
287 if (!bas->rclk) {
288 bas->rclk = mtk_soc_get_uartclk();
289 }
290
291 if (sc->sc_sysdev != NULL) {
292 di = sc->sc_sysdev;
293 mtk_uart_init(bas, di->baudrate, di->databits, di->stopbits,
294 di->parity);
295 } else {
296 mtk_uart_init(bas, 57600, 8, 1, 0);
297 }
298
299 sc->sc_rxfifosz = 16;
300 sc->sc_txfifosz = 16;
301
302 (void)mtk_uart_bus_getsig(sc);
303
304 /* Enable FIFO */
305 uart_setreg(bas, UART_FCR_REG,
306 uart_getreg(bas, UART_FCR_REG) |
307 UART_FCR_FIFOEN | UART_FCR_TXTGR_1 | UART_FCR_RXTGR_1);
308 uart_barrier(bas);
309 /* Enable interrupts */
310 usc->ier_mask = 0xf0;
311 uart_setreg(bas, UART_IER_REG,
312 UART_IER_EDSSI | UART_IER_ELSI | UART_IER_ERBFI);
313 uart_barrier(bas);
314
315 return (0);
316 }
317
318 static int
mtk_uart_bus_detach(struct uart_softc * sc)319 mtk_uart_bus_detach(struct uart_softc *sc)
320 {
321 return (0);
322 }
323
324 static int
mtk_uart_bus_flush(struct uart_softc * sc,int what)325 mtk_uart_bus_flush(struct uart_softc *sc, int what)
326 {
327 struct uart_bas *bas = &sc->sc_bas;
328 uint32_t fcr = uart_getreg(bas, UART_FCR_REG);
329
330 if (what & UART_FLUSH_TRANSMITTER) {
331 uart_setreg(bas, UART_FCR_REG, fcr|UART_FCR_TXRST);
332 uart_barrier(bas);
333 }
334 if (what & UART_FLUSH_RECEIVER) {
335 uart_setreg(bas, UART_FCR_REG, fcr|UART_FCR_RXRST);
336 uart_barrier(bas);
337 }
338 uart_setreg(bas, UART_FCR_REG, fcr);
339 uart_barrier(bas);
340 return (0);
341 }
342
343 static int
mtk_uart_bus_getsig(struct uart_softc * sc)344 mtk_uart_bus_getsig(struct uart_softc *sc)
345 {
346 uint32_t new, old, sig;
347 uint8_t bes;
348
349 return(0);
350 do {
351 old = sc->sc_hwsig;
352 sig = old;
353 uart_lock(sc->sc_hwmtx);
354 bes = uart_getreg(&sc->sc_bas, UART_MSR_REG);
355 uart_unlock(sc->sc_hwmtx);
356 /* XXX: chip can show delta */
357 SIGCHG(bes & UART_MSR_CTS, sig, SER_CTS, SER_DCTS);
358 SIGCHG(bes & UART_MSR_DCD, sig, SER_DCD, SER_DDCD);
359 SIGCHG(bes & UART_MSR_DSR, sig, SER_DSR, SER_DDSR);
360 new = sig & ~SER_MASK_DELTA;
361 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
362
363 return (sig);
364 }
365
366 static int
mtk_uart_bus_ioctl(struct uart_softc * sc,int request,intptr_t data)367 mtk_uart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
368 {
369 struct uart_bas *bas;
370 int baudrate, divisor, error;
371
372 bas = &sc->sc_bas;
373 error = 0;
374 uart_lock(sc->sc_hwmtx);
375 switch (request) {
376 case UART_IOCTL_BREAK:
377 /* TODO: Send BREAK */
378 break;
379 case UART_IOCTL_BAUD:
380 divisor = uart_getreg(bas, UART_CDDL_REG);
381 baudrate = bas->rclk / (divisor * 16);
382 *(int*)data = baudrate;
383 break;
384 default:
385 error = EINVAL;
386 break;
387 }
388 uart_unlock(sc->sc_hwmtx);
389 return (error);
390 }
391
392 static int
mtk_uart_bus_ipend(struct uart_softc * sc)393 mtk_uart_bus_ipend(struct uart_softc *sc)
394 {
395 struct uart_bas *bas;
396 int ipend;
397 uint8_t iir, lsr, msr;
398
399 // breakpoint();
400
401 bas = &sc->sc_bas;
402 ipend = 0;
403
404 uart_lock(sc->sc_hwmtx);
405 iir = uart_getreg(&sc->sc_bas, UART_IIR_REG);
406 lsr = uart_getreg(&sc->sc_bas, UART_LSR_REG);
407 uart_setreg(&sc->sc_bas, UART_LSR_REG, lsr);
408 msr = uart_getreg(&sc->sc_bas, UART_MSR_REG);
409 uart_setreg(&sc->sc_bas, UART_MSR_REG, msr);
410 if (iir & UART_IIR_INTP) {
411 uart_unlock(sc->sc_hwmtx);
412 return (0);
413 }
414 switch ((iir >> 1) & 0x07) {
415 case UART_IIR_ID_THRE:
416 ipend |= SER_INT_TXIDLE;
417 break;
418 case UART_IIR_ID_DR2:
419 mtk_uart_bus_flush(sc, UART_FLUSH_RECEIVER);
420 /* passthrough */
421 case UART_IIR_ID_DR:
422 ipend |= SER_INT_RXREADY;
423 break;
424 case UART_IIR_ID_MST:
425 case UART_IIR_ID_LINESTATUS:
426 ipend |= SER_INT_SIGCHG;
427 if (lsr & UART_LSR_BI)
428 ipend |= SER_INT_BREAK;
429 if (lsr & UART_LSR_OE)
430 ipend |= SER_INT_OVERRUN;
431 break;
432 default:
433 /* XXX: maybe return error here */
434 break;
435 }
436
437 uart_unlock(sc->sc_hwmtx);
438
439 return (ipend);
440 }
441
442 static int
mtk_uart_bus_param(struct uart_softc * sc,int baudrate,int databits,int stopbits,int parity)443 mtk_uart_bus_param(struct uart_softc *sc, int baudrate, int databits,
444 int stopbits, int parity)
445 {
446 uart_lock(sc->sc_hwmtx);
447 mtk_uart_init(&sc->sc_bas, baudrate, databits, stopbits, parity);
448 uart_unlock(sc->sc_hwmtx);
449 return (0);
450 }
451
452 static int
mtk_uart_bus_probe(struct uart_softc * sc)453 mtk_uart_bus_probe(struct uart_softc *sc)
454 {
455 int error;
456
457 error = mtk_uart_probe(&sc->sc_bas);
458 if (error)
459 return (error);
460
461 device_set_desc(sc->sc_dev, "MTK UART Controller");
462
463 return (0);
464 }
465
466 static int
mtk_uart_bus_receive(struct uart_softc * sc)467 mtk_uart_bus_receive(struct uart_softc *sc)
468 {
469 struct uart_bas *bas;
470 int xc;
471 uint8_t lsr;
472
473 bas = &sc->sc_bas;
474 uart_lock(sc->sc_hwmtx);
475 lsr = uart_getreg(bas, UART_LSR_REG);
476 while ((lsr & UART_LSR_DR)) {
477 if (uart_rx_full(sc)) {
478 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
479 break;
480 }
481 xc = 0;
482 xc = uart_getreg(bas, UART_RX_REG);
483 if (lsr & UART_LSR_FE)
484 xc |= UART_STAT_FRAMERR;
485 if (lsr & UART_LSR_PE)
486 xc |= UART_STAT_PARERR;
487 if (lsr & UART_LSR_OE)
488 xc |= UART_STAT_OVERRUN;
489 uart_barrier(bas);
490 uart_rx_put(sc, xc);
491 lsr = uart_getreg(bas, UART_LSR_REG);
492 }
493
494 uart_unlock(sc->sc_hwmtx);
495 return (0);
496 }
497
498 static int
mtk_uart_bus_setsig(struct uart_softc * sc,int sig)499 mtk_uart_bus_setsig(struct uart_softc *sc, int sig)
500 {
501 /* TODO: implement (?) */
502 return (sig);
503 }
504
505 static int
mtk_uart_bus_transmit(struct uart_softc * sc)506 mtk_uart_bus_transmit(struct uart_softc *sc)
507 {
508 struct uart_bas *bas = &sc->sc_bas;
509 int i;
510
511 if (!uart_output) return (0);
512
513 bas = &sc->sc_bas;
514 uart_lock(sc->sc_hwmtx);
515 while ((uart_getreg(bas, UART_LSR_REG) & UART_LSR_THRE) == 0);
516 mtk_uart_enable_txintr(sc);
517 for (i = 0; i < sc->sc_txdatasz; i++) {
518 uart_setreg(bas, UART_TX_REG, sc->sc_txbuf[i]);
519 uart_barrier(bas);
520 }
521 sc->sc_txbusy = 1;
522 uart_unlock(sc->sc_hwmtx);
523 return (0);
524 }
525
526 void
mtk_uart_bus_grab(struct uart_softc * sc)527 mtk_uart_bus_grab(struct uart_softc *sc)
528 {
529 struct uart_bas *bas = &sc->sc_bas;
530 struct uart_mtk_softc *usc = (struct uart_mtk_softc *)sc;
531
532 uart_lock(sc->sc_hwmtx);
533 usc->ier = uart_getreg(bas, UART_IER_REG);
534 uart_setreg(bas, UART_IER_REG, usc->ier & usc->ier_mask);
535 uart_barrier(bas);
536 uart_unlock(sc->sc_hwmtx);
537 }
538
539 void
mtk_uart_bus_ungrab(struct uart_softc * sc)540 mtk_uart_bus_ungrab(struct uart_softc *sc)
541 {
542 struct uart_mtk_softc *usc = (struct uart_mtk_softc *)sc;
543 struct uart_bas *bas = &sc->sc_bas;
544
545 uart_lock(sc->sc_hwmtx);
546 uart_setreg(bas, UART_IER_REG, usc->ier);
547 uart_barrier(bas);
548 uart_unlock(sc->sc_hwmtx);
549 }
550