1 /* $NetBSD: cache.h,v 1.6 2003/02/17 11:35:01 simonb Exp $ */ 2 3 /*- 4 * SPDX-License-Identifier: BSD-4-Clause 5 * 6 * Copyright 2001 Wasabi Systems, Inc. 7 * All rights reserved. 8 * 9 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed for the NetBSD Project by 22 * Wasabi Systems, Inc. 23 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 24 * or promote products derived from this software without specific prior 25 * written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #ifndef _MACHINE_CACHE_H_ 41 #define _MACHINE_CACHE_H_ 42 43 /* 44 * Cache operations. 45 * 46 * We define the following primitives: 47 * 48 * --- Instruction cache synchronization (mandatory): 49 * 50 * icache_sync_all Synchronize I-cache 51 * 52 * icache_sync_range Synchronize I-cache range 53 * 54 * icache_sync_range_index (index ops) 55 * 56 * --- Primary data cache (mandatory): 57 * 58 * pdcache_wbinv_all Write-back Invalidate primary D-cache 59 * 60 * pdcache_wbinv_range Write-back Invalidate primary D-cache range 61 * 62 * pdcache_wbinv_range_index (index ops) 63 * 64 * pdcache_inv_range Invalidate primary D-cache range 65 * 66 * pdcache_wb_range Write-back primary D-cache range 67 * 68 * --- Secondary data cache (optional): 69 * 70 * sdcache_wbinv_all Write-back Invalidate secondary D-cache 71 * 72 * sdcache_wbinv_range Write-back Invalidate secondary D-cache range 73 * 74 * sdcache_wbinv_range_index (index ops) 75 * 76 * sdcache_inv_range Invalidate secondary D-cache range 77 * 78 * sdcache_wb_range Write-back secondary D-cache range 79 * 80 * There are some rules that must be followed: 81 * 82 * I-cache Synch (all or range): 83 * The goal is to synchronize the instruction stream, 84 * so you may need to write-back dirty data cache 85 * blocks first. If a range is requested, and you 86 * can't synchronize just a range, you have to hit 87 * the whole thing. 88 * 89 * D-cache Write-back Invalidate range: 90 * If you can't WB-Inv a range, you must WB-Inv the 91 * entire D-cache. 92 * 93 * D-cache Invalidate: 94 * If you can't Inv the D-cache without doing a 95 * Write-back, YOU MUST PANIC. This is to catch 96 * errors in calling code. Callers must be aware 97 * of this scenario, and must handle it appropriately 98 * (consider the bus_dma(9) operations). 99 * 100 * D-cache Write-back: 101 * If you can't Write-back without doing an invalidate, 102 * that's fine. Then treat this as a WB-Inv. Skipping 103 * the invalidate is merely an optimization. 104 * 105 * All operations: 106 * Valid virtual addresses must be passed to the 107 * cache operation. 108 * 109 * Finally, these primitives are grouped together in reasonable 110 * ways. For all operations described here, first the primary 111 * cache is frobbed, then the secondary cache frobbed, if the 112 * operation for the secondary cache exists. 113 * 114 * mips_icache_sync_all Synchronize I-cache 115 * 116 * mips_icache_sync_range Synchronize I-cache range 117 * 118 * mips_icache_sync_range_index (index ops) 119 * 120 * mips_dcache_wbinv_all Write-back Invalidate D-cache 121 * 122 * mips_dcache_wbinv_range Write-back Invalidate D-cache range 123 * 124 * mips_dcache_wbinv_range_index (index ops) 125 * 126 * mips_dcache_inv_range Invalidate D-cache range 127 * 128 * mips_dcache_wb_range Write-back D-cache range 129 */ 130 131 struct mips_cache_ops { 132 void (*mco_icache_sync_all)(void); 133 void (*mco_icache_sync_range)(vm_offset_t, vm_size_t); 134 void (*mco_icache_sync_range_index)(vm_offset_t, vm_size_t); 135 136 void (*mco_pdcache_wbinv_all)(void); 137 void (*mco_pdcache_wbinv_range)(vm_offset_t, vm_size_t); 138 void (*mco_pdcache_wbinv_range_index)(vm_offset_t, vm_size_t); 139 void (*mco_pdcache_inv_range)(vm_offset_t, vm_size_t); 140 void (*mco_pdcache_wb_range)(vm_offset_t, vm_size_t); 141 142 /* These are called only by the (mipsNN) icache functions. */ 143 void (*mco_intern_pdcache_wbinv_all)(void); 144 void (*mco_intern_pdcache_wbinv_range_index)(vm_offset_t, vm_size_t); 145 void (*mco_intern_pdcache_wb_range)(vm_offset_t, vm_size_t); 146 147 void (*mco_sdcache_wbinv_all)(void); 148 void (*mco_sdcache_wbinv_range)(vm_offset_t, vm_size_t); 149 void (*mco_sdcache_wbinv_range_index)(vm_offset_t, vm_size_t); 150 void (*mco_sdcache_inv_range)(vm_offset_t, vm_size_t); 151 void (*mco_sdcache_wb_range)(vm_offset_t, vm_size_t); 152 153 /* These are called only by the (mipsNN) icache functions. */ 154 void (*mco_intern_sdcache_wbinv_all)(void); 155 void (*mco_intern_sdcache_wbinv_range_index)(vm_offset_t, vm_size_t); 156 void (*mco_intern_sdcache_wb_range)(vm_offset_t, vm_size_t); 157 }; 158 159 extern struct mips_cache_ops mips_cache_ops; 160 161 /* PRIMARY CACHE VARIABLES */ 162 extern int mips_picache_linesize; 163 extern int mips_pdcache_linesize; 164 extern int mips_sdcache_linesize; 165 extern int mips_dcache_max_linesize; 166 167 #define __mco_noargs(prefix, x) \ 168 do { \ 169 (*mips_cache_ops.mco_ ## prefix ## p ## x )(); \ 170 if (*mips_cache_ops.mco_ ## prefix ## s ## x ) \ 171 (*mips_cache_ops.mco_ ## prefix ## s ## x )(); \ 172 } while (/*CONSTCOND*/0) 173 174 #define __mco_2args(prefix, x, a, b) \ 175 do { \ 176 (*mips_cache_ops.mco_ ## prefix ## p ## x )((a), (b)); \ 177 if (*mips_cache_ops.mco_ ## prefix ## s ## x ) \ 178 (*mips_cache_ops.mco_ ## prefix ## s ## x )((a), (b)); \ 179 } while (/*CONSTCOND*/0) 180 181 #define mips_icache_sync_all() \ 182 (*mips_cache_ops.mco_icache_sync_all)() 183 184 #define mips_icache_sync_range(v, s) \ 185 (*mips_cache_ops.mco_icache_sync_range)((v), (s)) 186 187 #define mips_icache_sync_range_index(v, s) \ 188 (*mips_cache_ops.mco_icache_sync_range_index)((v), (s)) 189 190 #define mips_dcache_wbinv_all() \ 191 __mco_noargs(, dcache_wbinv_all) 192 193 #define mips_dcache_wbinv_range(v, s) \ 194 __mco_2args(, dcache_wbinv_range, (v), (s)) 195 196 #define mips_dcache_wbinv_range_index(v, s) \ 197 __mco_2args(, dcache_wbinv_range_index, (v), (s)) 198 199 #define mips_dcache_inv_range(v, s) \ 200 __mco_2args(, dcache_inv_range, (v), (s)) 201 202 #define mips_dcache_wb_range(v, s) \ 203 __mco_2args(, dcache_wb_range, (v), (s)) 204 205 /* 206 * Private D-cache functions only called from (currently only the 207 * mipsNN) I-cache functions. 208 */ 209 #define mips_intern_dcache_wbinv_all() \ 210 __mco_noargs(intern_, dcache_wbinv_all) 211 212 #define mips_intern_dcache_wbinv_range_index(v, s) \ 213 __mco_2args(intern_, dcache_wbinv_range_index, (v), (s)) 214 215 #define mips_intern_dcache_wb_range(v, s) \ 216 __mco_2args(intern_, dcache_wb_range, (v), (s)) 217 218 /* forward declaration */ 219 struct mips_cpuinfo; 220 221 void mips_config_cache(struct mips_cpuinfo *); 222 223 #include <machine/cache_mipsNN.h> 224 #endif /* _MACHINE_CACHE_H_ */ 225