1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause AND BSD-2-Clause
3 *
4 * Copyright (c) 2003 Marcel Moolenaar
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 /*
30 * uart_dev_oct16550.c
31 *
32 * Derived from uart_dev_ns8250.c
33 *
34 * Redistribution and use in source and binary forms, with or without
35 * modification, are permitted provided that the following conditions
36 * are met:
37 *
38 * 1. Redistributions of source code must retain the above copyright
39 * notice, this list of conditions and the following disclaimer.
40 * 2. Redistributions in binary form must reproduce the above copyright
41 * notice, this list of conditions and the following disclaimer in the
42 * documentation and/or other materials provided with the distribution.
43 *
44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
45 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
46 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
47 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
48 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
49 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
53 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 */
55
56 #include <sys/cdefs.h>
57 #include <sys/param.h>
58 #include <sys/systm.h>
59 #include <sys/bus.h>
60 #include <sys/conf.h>
61 #include <machine/bus.h>
62 #include <machine/pcpu.h>
63
64 #include <dev/uart/uart.h>
65 #include <dev/uart/uart_cpu.h>
66 #include <dev/uart/uart_bus.h>
67
68 #include <dev/ic/ns16550.h>
69
70 #include <mips/cavium/octeon_pcmap_regs.h>
71
72 #include <contrib/octeon-sdk/cvmx.h>
73
74 #include "uart_if.h"
75
76 /*
77 * Clear pending interrupts. THRE is cleared by reading IIR. Data
78 * that may have been received gets lost here.
79 */
80 static void
oct16550_clrint(struct uart_bas * bas)81 oct16550_clrint (struct uart_bas *bas)
82 {
83 uint8_t iir;
84
85 iir = uart_getreg(bas, REG_IIR);
86 while ((iir & IIR_NOPEND) == 0) {
87 iir &= IIR_IMASK;
88 if (iir == IIR_RLS)
89 (void)uart_getreg(bas, REG_LSR);
90 else if (iir == IIR_RXRDY || iir == IIR_RXTOUT)
91 (void)uart_getreg(bas, REG_DATA);
92 else if (iir == IIR_MLSC)
93 (void)uart_getreg(bas, REG_MSR);
94 else if (iir == IIR_BUSY)
95 (void) uart_getreg(bas, REG_USR);
96 uart_barrier(bas);
97 iir = uart_getreg(bas, REG_IIR);
98 }
99 }
100
101 static int delay_changed = 1;
102
103 static int
oct16550_delay(struct uart_bas * bas)104 oct16550_delay (struct uart_bas *bas)
105 {
106 int divisor;
107 u_char lcr;
108 static int delay = 0;
109
110 if (!delay_changed) return delay;
111 delay_changed = 0;
112 lcr = uart_getreg(bas, REG_LCR);
113 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
114 uart_barrier(bas);
115 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8);
116 uart_barrier(bas);
117 uart_setreg(bas, REG_LCR, lcr);
118 uart_barrier(bas);
119
120 if(!bas->rclk)
121 return 10; /* return an approx delay value */
122
123 /* 1/10th the time to transmit 1 character (estimate). */
124 if (divisor <= 134)
125 return (16000000 * divisor / bas->rclk);
126 return (16000 * divisor / (bas->rclk / 1000));
127
128 }
129
130 static int
oct16550_divisor(int rclk,int baudrate)131 oct16550_divisor (int rclk, int baudrate)
132 {
133 int actual_baud, divisor;
134 int error;
135
136 if (baudrate == 0)
137 return (0);
138
139 divisor = (rclk / (baudrate << 3) + 1) >> 1;
140 if (divisor == 0 || divisor >= 65536)
141 return (0);
142 actual_baud = rclk / (divisor << 4);
143
144 /* 10 times error in percent: */
145 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1;
146
147 /* 3.0% maximum error tolerance: */
148 if (error < -30 || error > 30)
149 return (0);
150
151 return (divisor);
152 }
153
154 static int
oct16550_drain(struct uart_bas * bas,int what)155 oct16550_drain (struct uart_bas *bas, int what)
156 {
157 int delay, limit;
158
159 delay = oct16550_delay(bas);
160
161 if (what & UART_DRAIN_TRANSMITTER) {
162 /*
163 * Pick an arbitrary high limit to avoid getting stuck in
164 * an infinite loop when the hardware is broken. Make the
165 * limit high enough to handle large FIFOs.
166 */
167 limit = 10*10*10*1024;
168 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
169 DELAY(delay);
170 if (limit == 0) {
171 /* printf("oct16550: transmitter appears stuck... "); */
172 return (0);
173 }
174 }
175
176 if (what & UART_DRAIN_RECEIVER) {
177 /*
178 * Pick an arbitrary high limit to avoid getting stuck in
179 * an infinite loop when the hardware is broken. Make the
180 * limit high enough to handle large FIFOs and integrated
181 * UARTs. The HP rx2600 for example has 3 UARTs on the
182 * management board that tend to get a lot of data send
183 * to it when the UART is first activated.
184 */
185 limit=10*4096;
186 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) {
187 (void)uart_getreg(bas, REG_DATA);
188 uart_barrier(bas);
189 DELAY(delay << 2);
190 }
191 if (limit == 0) {
192 /* printf("oct16550: receiver appears broken... "); */
193 return (EIO);
194 }
195 }
196
197 return (0);
198 }
199
200 /*
201 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be
202 * drained. WARNING: this function clobbers the FIFO setting!
203 */
204 static void
oct16550_flush(struct uart_bas * bas,int what)205 oct16550_flush (struct uart_bas *bas, int what)
206 {
207 uint8_t fcr;
208
209 fcr = FCR_ENABLE;
210 if (what & UART_FLUSH_TRANSMITTER)
211 fcr |= FCR_XMT_RST;
212 if (what & UART_FLUSH_RECEIVER)
213 fcr |= FCR_RCV_RST;
214 uart_setreg(bas, REG_FCR, fcr);
215 uart_barrier(bas);
216 }
217
218 static int
oct16550_param(struct uart_bas * bas,int baudrate,int databits,int stopbits,int parity)219 oct16550_param (struct uart_bas *bas, int baudrate, int databits, int stopbits,
220 int parity)
221 {
222 int divisor;
223 uint8_t lcr;
224
225 lcr = 0;
226 if (databits >= 8)
227 lcr |= LCR_8BITS;
228 else if (databits == 7)
229 lcr |= LCR_7BITS;
230 else if (databits == 6)
231 lcr |= LCR_6BITS;
232 else
233 lcr |= LCR_5BITS;
234 if (stopbits > 1)
235 lcr |= LCR_STOPB;
236 lcr |= parity << 3;
237
238 /* Set baudrate. */
239 if (baudrate > 0) {
240 divisor = oct16550_divisor(bas->rclk, baudrate);
241 if (divisor == 0)
242 return (EINVAL);
243 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
244 uart_barrier(bas);
245 uart_setreg(bas, REG_DLL, divisor & 0xff);
246 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff);
247 uart_barrier(bas);
248 delay_changed = 1;
249 }
250
251 /* Set LCR and clear DLAB. */
252 uart_setreg(bas, REG_LCR, lcr);
253 uart_barrier(bas);
254 return (0);
255 }
256
257 /*
258 * Low-level UART interface.
259 */
260 static int oct16550_probe(struct uart_bas *bas);
261 static void oct16550_init(struct uart_bas *bas, int, int, int, int);
262 static void oct16550_term(struct uart_bas *bas);
263 static void oct16550_putc(struct uart_bas *bas, int);
264 static int oct16550_rxready(struct uart_bas *bas);
265 static int oct16550_getc(struct uart_bas *bas, struct mtx *);
266
267 struct uart_ops uart_oct16550_ops = {
268 .probe = oct16550_probe,
269 .init = oct16550_init,
270 .term = oct16550_term,
271 .putc = oct16550_putc,
272 .rxready = oct16550_rxready,
273 .getc = oct16550_getc,
274 };
275
276 static int
oct16550_probe(struct uart_bas * bas)277 oct16550_probe (struct uart_bas *bas)
278 {
279 u_char val;
280
281 /* Check known 0 bits that don't depend on DLAB. */
282 val = uart_getreg(bas, REG_IIR);
283 if (val & 0x30)
284 return (ENXIO);
285 val = uart_getreg(bas, REG_MCR);
286 if (val & 0xc0)
287 return (ENXIO);
288 val = uart_getreg(bas, REG_USR);
289 if (val & 0xe0)
290 return (ENXIO);
291 return (0);
292 }
293
294 static void
oct16550_init(struct uart_bas * bas,int baudrate,int databits,int stopbits,int parity)295 oct16550_init (struct uart_bas *bas, int baudrate, int databits, int stopbits,
296 int parity)
297 {
298 u_char ier;
299
300 oct16550_param(bas, baudrate, databits, stopbits, parity);
301
302 /* Disable all interrupt sources. */
303 ier = uart_getreg(bas, REG_IER) & 0x0;
304 uart_setreg(bas, REG_IER, ier);
305 uart_barrier(bas);
306
307 /* Disable the FIFO (if present). */
308 // uart_setreg(bas, REG_FCR, 0);
309 uart_barrier(bas);
310
311 /* Set RTS & DTR. */
312 uart_setreg(bas, REG_MCR, MCR_RTS | MCR_DTR);
313 uart_barrier(bas);
314
315 oct16550_clrint(bas);
316 }
317
318 static void
oct16550_term(struct uart_bas * bas)319 oct16550_term (struct uart_bas *bas)
320 {
321
322 /* Clear RTS & DTR. */
323 uart_setreg(bas, REG_MCR, 0);
324 uart_barrier(bas);
325 }
326
oct16550_wait_txhr_empty(struct uart_bas * bas,int limit,int delay)327 static inline void oct16550_wait_txhr_empty (struct uart_bas *bas, int limit, int delay)
328 {
329 while (((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) &&
330 ((uart_getreg(bas, REG_USR) & USR_TXFIFO_NOTFULL) == 0))
331 DELAY(delay);
332 }
333
334 static void
oct16550_putc(struct uart_bas * bas,int c)335 oct16550_putc (struct uart_bas *bas, int c)
336 {
337 int delay;
338
339 /* 1/10th the time to transmit 1 character (estimate). */
340 delay = oct16550_delay(bas);
341 oct16550_wait_txhr_empty(bas, 100, delay);
342 uart_setreg(bas, REG_DATA, c);
343 uart_barrier(bas);
344 oct16550_wait_txhr_empty(bas, 100, delay);
345 }
346
347 static int
oct16550_rxready(struct uart_bas * bas)348 oct16550_rxready (struct uart_bas *bas)
349 {
350
351 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0);
352 }
353
354 static int
oct16550_getc(struct uart_bas * bas,struct mtx * hwmtx)355 oct16550_getc (struct uart_bas *bas, struct mtx *hwmtx)
356 {
357 int c, delay;
358
359 uart_lock(hwmtx);
360
361 /* 1/10th the time to transmit 1 character (estimate). */
362 delay = oct16550_delay(bas);
363
364 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) {
365 uart_unlock(hwmtx);
366 DELAY(delay);
367 uart_lock(hwmtx);
368 }
369
370 c = uart_getreg(bas, REG_DATA);
371
372 uart_unlock(hwmtx);
373
374 return (c);
375 }
376
377 /*
378 * High-level UART interface.
379 */
380 struct oct16550_softc {
381 struct uart_softc base;
382 uint8_t fcr;
383 uint8_t ier;
384 uint8_t mcr;
385 };
386
387 static int oct16550_bus_attach(struct uart_softc *);
388 static int oct16550_bus_detach(struct uart_softc *);
389 static int oct16550_bus_flush(struct uart_softc *, int);
390 static int oct16550_bus_getsig(struct uart_softc *);
391 static int oct16550_bus_ioctl(struct uart_softc *, int, intptr_t);
392 static int oct16550_bus_ipend(struct uart_softc *);
393 static int oct16550_bus_param(struct uart_softc *, int, int, int, int);
394 static int oct16550_bus_probe(struct uart_softc *);
395 static int oct16550_bus_receive(struct uart_softc *);
396 static int oct16550_bus_setsig(struct uart_softc *, int);
397 static int oct16550_bus_transmit(struct uart_softc *);
398 static bool oct16550_bus_txbusy(struct uart_softc *);
399 static void oct16550_bus_grab(struct uart_softc *);
400 static void oct16550_bus_ungrab(struct uart_softc *);
401
402 static kobj_method_t oct16550_methods[] = {
403 KOBJMETHOD(uart_attach, oct16550_bus_attach),
404 KOBJMETHOD(uart_detach, oct16550_bus_detach),
405 KOBJMETHOD(uart_flush, oct16550_bus_flush),
406 KOBJMETHOD(uart_getsig, oct16550_bus_getsig),
407 KOBJMETHOD(uart_ioctl, oct16550_bus_ioctl),
408 KOBJMETHOD(uart_ipend, oct16550_bus_ipend),
409 KOBJMETHOD(uart_param, oct16550_bus_param),
410 KOBJMETHOD(uart_probe, oct16550_bus_probe),
411 KOBJMETHOD(uart_receive, oct16550_bus_receive),
412 KOBJMETHOD(uart_setsig, oct16550_bus_setsig),
413 KOBJMETHOD(uart_transmit, oct16550_bus_transmit),
414 KOBJMETHOD(uart_txbusy, oct16550_bus_txbusy),
415 KOBJMETHOD(uart_grab, oct16550_bus_grab),
416 KOBJMETHOD(uart_ungrab, oct16550_bus_ungrab),
417 KOBJMETHOD_END
418 };
419
420 struct uart_class uart_oct16550_class = {
421 "oct16550 class",
422 oct16550_methods,
423 sizeof(struct oct16550_softc),
424 .uc_ops = &uart_oct16550_ops,
425 .uc_range = 8 << 3,
426 .uc_rclk = 0,
427 .uc_rshift = 0
428 };
429
430 #define SIGCHG(c, i, s, d) \
431 if (c) { \
432 i |= (i & s) ? s : s | d; \
433 } else { \
434 i = (i & s) ? (i & ~s) | d : i; \
435 }
436
437 static int
oct16550_bus_attach(struct uart_softc * sc)438 oct16550_bus_attach (struct uart_softc *sc)
439 {
440 struct oct16550_softc *oct16550 = (struct oct16550_softc*)sc;
441 struct uart_bas *bas;
442 int unit;
443
444 unit = device_get_unit(sc->sc_dev);
445 bas = &sc->sc_bas;
446
447 oct16550_drain(bas, UART_DRAIN_TRANSMITTER);
448 oct16550->mcr = uart_getreg(bas, REG_MCR);
449 oct16550->fcr = FCR_ENABLE | FCR_RX_HIGH;
450 uart_setreg(bas, REG_FCR, oct16550->fcr);
451 uart_barrier(bas);
452 oct16550_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
453
454 if (oct16550->mcr & MCR_DTR)
455 sc->sc_hwsig |= SER_DTR;
456 if (oct16550->mcr & MCR_RTS)
457 sc->sc_hwsig |= SER_RTS;
458 oct16550_bus_getsig(sc);
459
460 oct16550_clrint(bas);
461 oct16550->ier = uart_getreg(bas, REG_IER) & 0xf0;
462 oct16550->ier |= IER_EMSC | IER_ERLS | IER_ERXRDY;
463 uart_setreg(bas, REG_IER, oct16550->ier);
464 uart_barrier(bas);
465
466 return (0);
467 }
468
469 static int
oct16550_bus_detach(struct uart_softc * sc)470 oct16550_bus_detach (struct uart_softc *sc)
471 {
472 struct uart_bas *bas;
473 u_char ier;
474
475 bas = &sc->sc_bas;
476 ier = uart_getreg(bas, REG_IER) & 0xf0;
477 uart_setreg(bas, REG_IER, ier);
478 uart_barrier(bas);
479 oct16550_clrint(bas);
480 return (0);
481 }
482
483 static int
oct16550_bus_flush(struct uart_softc * sc,int what)484 oct16550_bus_flush (struct uart_softc *sc, int what)
485 {
486 struct oct16550_softc *oct16550 = (struct oct16550_softc*)sc;
487 struct uart_bas *bas;
488 int error;
489
490 bas = &sc->sc_bas;
491 uart_lock(sc->sc_hwmtx);
492 if (sc->sc_rxfifosz > 1) {
493 oct16550_flush(bas, what);
494 uart_setreg(bas, REG_FCR, oct16550->fcr);
495 uart_barrier(bas);
496 error = 0;
497 } else
498 error = oct16550_drain(bas, what);
499 uart_unlock(sc->sc_hwmtx);
500 return (error);
501 }
502
503 static int
oct16550_bus_getsig(struct uart_softc * sc)504 oct16550_bus_getsig (struct uart_softc *sc)
505 {
506 uint32_t new, old, sig;
507 uint8_t msr;
508
509 do {
510 old = sc->sc_hwsig;
511 sig = old;
512 uart_lock(sc->sc_hwmtx);
513 msr = uart_getreg(&sc->sc_bas, REG_MSR);
514 uart_unlock(sc->sc_hwmtx);
515 SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR);
516 SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS);
517 SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD);
518 SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI);
519 new = sig & ~SER_MASK_DELTA;
520 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
521 return (sig);
522 }
523
524 static int
oct16550_bus_ioctl(struct uart_softc * sc,int request,intptr_t data)525 oct16550_bus_ioctl (struct uart_softc *sc, int request, intptr_t data)
526 {
527 struct uart_bas *bas;
528 int baudrate, divisor, error;
529 uint8_t efr, lcr;
530
531 bas = &sc->sc_bas;
532 error = 0;
533 uart_lock(sc->sc_hwmtx);
534 switch (request) {
535 case UART_IOCTL_BREAK:
536 lcr = uart_getreg(bas, REG_LCR);
537 if (data)
538 lcr |= LCR_SBREAK;
539 else
540 lcr &= ~LCR_SBREAK;
541 uart_setreg(bas, REG_LCR, lcr);
542 uart_barrier(bas);
543 break;
544 case UART_IOCTL_IFLOW:
545 lcr = uart_getreg(bas, REG_LCR);
546 uart_barrier(bas);
547 uart_setreg(bas, REG_LCR, 0xbf);
548 uart_barrier(bas);
549 efr = uart_getreg(bas, REG_EFR);
550 if (data)
551 efr |= EFR_RTS;
552 else
553 efr &= ~EFR_RTS;
554 uart_setreg(bas, REG_EFR, efr);
555 uart_barrier(bas);
556 uart_setreg(bas, REG_LCR, lcr);
557 uart_barrier(bas);
558 break;
559 case UART_IOCTL_OFLOW:
560 lcr = uart_getreg(bas, REG_LCR);
561 uart_barrier(bas);
562 uart_setreg(bas, REG_LCR, 0xbf);
563 uart_barrier(bas);
564 efr = uart_getreg(bas, REG_EFR);
565 if (data)
566 efr |= EFR_CTS;
567 else
568 efr &= ~EFR_CTS;
569 uart_setreg(bas, REG_EFR, efr);
570 uart_barrier(bas);
571 uart_setreg(bas, REG_LCR, lcr);
572 uart_barrier(bas);
573 break;
574 case UART_IOCTL_BAUD:
575 lcr = uart_getreg(bas, REG_LCR);
576 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
577 uart_barrier(bas);
578 divisor = uart_getreg(bas, REG_DLL) |
579 (uart_getreg(bas, REG_DLH) << 8);
580 uart_barrier(bas);
581 uart_setreg(bas, REG_LCR, lcr);
582 uart_barrier(bas);
583 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0;
584 delay_changed = 1;
585 if (baudrate > 0)
586 *(int*)data = baudrate;
587 else
588 error = ENXIO;
589 break;
590 default:
591 error = EINVAL;
592 break;
593 }
594 uart_unlock(sc->sc_hwmtx);
595 return (error);
596 }
597
598 static int
oct16550_bus_ipend(struct uart_softc * sc)599 oct16550_bus_ipend(struct uart_softc *sc)
600 {
601 struct uart_bas *bas;
602 int ipend = 0;
603 uint8_t iir, lsr;
604
605 bas = &sc->sc_bas;
606 uart_lock(sc->sc_hwmtx);
607
608 iir = uart_getreg(bas, REG_IIR) & IIR_IMASK;
609 if (iir != IIR_NOPEND) {
610 if (iir == IIR_RLS) {
611 lsr = uart_getreg(bas, REG_LSR);
612 if (lsr & LSR_OE)
613 ipend |= SER_INT_OVERRUN;
614 if (lsr & LSR_BI)
615 ipend |= SER_INT_BREAK;
616 if (lsr & LSR_RXRDY)
617 ipend |= SER_INT_RXREADY;
618
619 } else if (iir == IIR_RXRDY) {
620 ipend |= SER_INT_RXREADY;
621
622 } else if (iir == IIR_RXTOUT) {
623 ipend |= SER_INT_RXREADY;
624
625 } else if (iir == IIR_TXRDY) {
626 ipend |= SER_INT_TXIDLE;
627
628 } else if (iir == IIR_MLSC) {
629 ipend |= SER_INT_SIGCHG;
630
631 } else if (iir == IIR_BUSY) {
632 (void) uart_getreg(bas, REG_USR);
633 }
634 }
635 uart_unlock(sc->sc_hwmtx);
636
637 return (ipend);
638 }
639
640 static int
oct16550_bus_param(struct uart_softc * sc,int baudrate,int databits,int stopbits,int parity)641 oct16550_bus_param (struct uart_softc *sc, int baudrate, int databits,
642 int stopbits, int parity)
643 {
644 struct uart_bas *bas;
645 int error;
646
647 bas = &sc->sc_bas;
648 uart_lock(sc->sc_hwmtx);
649 error = oct16550_param(bas, baudrate, databits, stopbits, parity);
650 uart_unlock(sc->sc_hwmtx);
651 return (error);
652 }
653
654 static int
oct16550_bus_probe(struct uart_softc * sc)655 oct16550_bus_probe (struct uart_softc *sc)
656 {
657 struct uart_bas *bas;
658 int error;
659
660 bas = &sc->sc_bas;
661 bas->rclk = uart_oct16550_class.uc_rclk = cvmx_clock_get_rate(CVMX_CLOCK_SCLK);
662
663 error = oct16550_probe(bas);
664 if (error) {
665 return (error);
666 }
667
668 uart_setreg(bas, REG_MCR, (MCR_DTR | MCR_RTS));
669
670 /*
671 * Enable FIFOs. And check that the UART has them. If not, we're
672 * done. Since this is the first time we enable the FIFOs, we reset
673 * them.
674 */
675 oct16550_drain(bas, UART_DRAIN_TRANSMITTER);
676 #define ENABLE_OCTEON_FIFO 1
677 #ifdef ENABLE_OCTEON_FIFO
678 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST);
679 #endif
680 uart_barrier(bas);
681
682 oct16550_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
683
684 if (device_get_unit(sc->sc_dev)) {
685 device_set_desc(sc->sc_dev, "Octeon-16550 channel 1");
686 } else {
687 device_set_desc(sc->sc_dev, "Octeon-16550 channel 0");
688 }
689 #ifdef ENABLE_OCTEON_FIFO
690 sc->sc_rxfifosz = 64;
691 sc->sc_txfifosz = 64;
692 #else
693 sc->sc_rxfifosz = 1;
694 sc->sc_txfifosz = 1;
695 #endif
696
697 #if 0
698 /*
699 * XXX there are some issues related to hardware flow control and
700 * it's likely that uart(4) is the cause. This basicly needs more
701 * investigation, but we avoid using for hardware flow control
702 * until then.
703 */
704 /* 16650s or higher have automatic flow control. */
705 if (sc->sc_rxfifosz > 16) {
706 sc->sc_hwiflow = 1;
707 sc->sc_hwoflow = 1;
708 }
709 #endif
710
711 return (0);
712 }
713
714 static int
oct16550_bus_receive(struct uart_softc * sc)715 oct16550_bus_receive (struct uart_softc *sc)
716 {
717 struct uart_bas *bas;
718 int xc;
719 uint8_t lsr;
720
721 bas = &sc->sc_bas;
722 uart_lock(sc->sc_hwmtx);
723 lsr = uart_getreg(bas, REG_LSR);
724
725 while (lsr & LSR_RXRDY) {
726 if (uart_rx_full(sc)) {
727 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
728 break;
729 }
730 xc = uart_getreg(bas, REG_DATA);
731 if (lsr & LSR_FE)
732 xc |= UART_STAT_FRAMERR;
733 if (lsr & LSR_PE)
734 xc |= UART_STAT_PARERR;
735 uart_rx_put(sc, xc);
736 lsr = uart_getreg(bas, REG_LSR);
737 }
738 /* Discard everything left in the Rx FIFO. */
739 /*
740 * First do a dummy read/discard anyway, in case the UART was lying to us.
741 * This problem was seen on board, when IIR said RBR, but LSR said no RXRDY
742 * Results in a stuck ipend loop.
743 */
744 (void)uart_getreg(bas, REG_DATA);
745 while (lsr & LSR_RXRDY) {
746 (void)uart_getreg(bas, REG_DATA);
747 uart_barrier(bas);
748 lsr = uart_getreg(bas, REG_LSR);
749 }
750 uart_unlock(sc->sc_hwmtx);
751 return (0);
752 }
753
754 static int
oct16550_bus_setsig(struct uart_softc * sc,int sig)755 oct16550_bus_setsig (struct uart_softc *sc, int sig)
756 {
757 struct oct16550_softc *oct16550 = (struct oct16550_softc*)sc;
758 struct uart_bas *bas;
759 uint32_t new, old;
760
761 bas = &sc->sc_bas;
762 do {
763 old = sc->sc_hwsig;
764 new = old;
765 if (sig & SER_DDTR) {
766 SIGCHG(sig & SER_DTR, new, SER_DTR,
767 SER_DDTR);
768 }
769 if (sig & SER_DRTS) {
770 SIGCHG(sig & SER_RTS, new, SER_RTS,
771 SER_DRTS);
772 }
773 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
774 uart_lock(sc->sc_hwmtx);
775 oct16550->mcr &= ~(MCR_DTR|MCR_RTS);
776 if (new & SER_DTR)
777 oct16550->mcr |= MCR_DTR;
778 if (new & SER_RTS)
779 oct16550->mcr |= MCR_RTS;
780 uart_setreg(bas, REG_MCR, oct16550->mcr);
781 uart_barrier(bas);
782 uart_unlock(sc->sc_hwmtx);
783 return (0);
784 }
785
786 static int
oct16550_bus_transmit(struct uart_softc * sc)787 oct16550_bus_transmit (struct uart_softc *sc)
788 {
789 struct oct16550_softc *oct16550 = (struct oct16550_softc*)sc;
790 struct uart_bas *bas;
791 int i;
792
793 bas = &sc->sc_bas;
794 uart_lock(sc->sc_hwmtx);
795 #ifdef NO_UART_INTERRUPTS
796 for (i = 0; i < sc->sc_txdatasz; i++) {
797 oct16550_putc(bas, sc->sc_txbuf[i]);
798 }
799 #else
800
801 oct16550_wait_txhr_empty(bas, 100, oct16550_delay(bas));
802 uart_setreg(bas, REG_IER, oct16550->ier | IER_ETXRDY);
803 uart_barrier(bas);
804
805 for (i = 0; i < sc->sc_txdatasz; i++) {
806 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]);
807 uart_barrier(bas);
808 }
809 sc->sc_txbusy = 1;
810 #endif
811 uart_unlock(sc->sc_hwmtx);
812 return (0);
813 }
814
815 static bool
oct16550_bus_txbusy(struct uart_softc * sc)816 oct16550_bus_txbusy(struct uart_softc *sc)
817 {
818 struct uart_bas *bas = &sc->sc_bas;
819
820 if ((uart_getreg(bas, REG_LSR) & (LSR_TEMT | LSR_THRE)) !=
821 (LSR_TEMT | LSR_THRE))
822 return (true);
823 return (false);
824 }
825
826 static void
oct16550_bus_grab(struct uart_softc * sc)827 oct16550_bus_grab(struct uart_softc *sc)
828 {
829 struct uart_bas *bas = &sc->sc_bas;
830
831 /*
832 * turn off all interrupts to enter polling mode. Leave the
833 * saved mask alone. We'll restore whatever it was in ungrab.
834 * All pending interupt signals are reset when IER is set to 0.
835 */
836 uart_lock(sc->sc_hwmtx);
837 uart_setreg(bas, REG_IER, 0);
838 uart_barrier(bas);
839 uart_unlock(sc->sc_hwmtx);
840 }
841
842 static void
oct16550_bus_ungrab(struct uart_softc * sc)843 oct16550_bus_ungrab(struct uart_softc *sc)
844 {
845 struct oct16550_softc *oct16550 = (struct oct16550_softc*)sc;
846 struct uart_bas *bas = &sc->sc_bas;
847
848 /*
849 * Restore previous interrupt mask
850 */
851 uart_lock(sc->sc_hwmtx);
852 uart_setreg(bas, REG_IER, oct16550->ier);
853 uart_barrier(bas);
854 uart_unlock(sc->sc_hwmtx);
855 }
856