1 /*-
2 * Copyright (c) 2015 Adrian Chadd <adrian@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 #include "opt_ddb.h"
29
30 #include <sys/param.h>
31 #include <sys/conf.h>
32 #include <sys/kernel.h>
33 #include <sys/systm.h>
34 #include <sys/bus.h>
35 #include <sys/cons.h>
36 #include <sys/kdb.h>
37 #include <sys/reboot.h>
38
39 #include <vm/vm.h>
40 #include <vm/vm_page.h>
41
42 #include <net/ethernet.h>
43
44 #include <machine/clock.h>
45 #include <machine/cpu.h>
46 #include <machine/cpuregs.h>
47 #include <machine/hwfunc.h>
48 #include <machine/md_var.h>
49 #include <machine/trap.h>
50 #include <machine/vmparam.h>
51
52 #include <mips/atheros/ar71xxreg.h>
53 #include <mips/atheros/qca953xreg.h>
54
55 #include <mips/atheros/ar71xx_cpudef.h>
56 #include <mips/atheros/ar71xx_setup.h>
57
58 #include <mips/atheros/ar71xx_chip.h>
59
60 #include <mips/atheros/qca953x_chip.h>
61
62 static void
qca953x_chip_detect_mem_size(void)63 qca953x_chip_detect_mem_size(void)
64 {
65 }
66
67 static void
qca953x_chip_detect_sys_frequency(void)68 qca953x_chip_detect_sys_frequency(void)
69 {
70 unsigned long ref_rate;
71 unsigned long cpu_rate;
72 unsigned long ddr_rate;
73 unsigned long ahb_rate;
74 uint32_t pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
75 uint32_t cpu_pll, ddr_pll;
76 uint32_t bootstrap;
77
78 bootstrap = ATH_READ_REG(QCA953X_RESET_REG_BOOTSTRAP);
79 if (bootstrap & QCA953X_BOOTSTRAP_REF_CLK_40)
80 ref_rate = 40 * 1000 * 1000;
81 else
82 ref_rate = 25 * 1000 * 1000;
83
84 pll = ATH_READ_REG(QCA953X_PLL_CPU_CONFIG_REG);
85 out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
86 QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
87 ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
88 QCA953X_PLL_CPU_CONFIG_REFDIV_MASK;
89 nint = (pll >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) &
90 QCA953X_PLL_CPU_CONFIG_NINT_MASK;
91 frac = (pll >> QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
92 QCA953X_PLL_CPU_CONFIG_NFRAC_MASK;
93
94 cpu_pll = nint * ref_rate / ref_div;
95 cpu_pll += frac * (ref_rate >> 6) / ref_div;
96 cpu_pll /= (1 << out_div);
97
98 pll = ATH_READ_REG(QCA953X_PLL_DDR_CONFIG_REG);
99 out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
100 QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
101 ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
102 QCA953X_PLL_DDR_CONFIG_REFDIV_MASK;
103 nint = (pll >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT) &
104 QCA953X_PLL_DDR_CONFIG_NINT_MASK;
105 frac = (pll >> QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
106 QCA953X_PLL_DDR_CONFIG_NFRAC_MASK;
107
108 ddr_pll = nint * ref_rate / ref_div;
109 ddr_pll += frac * (ref_rate >> 6) / (ref_div << 4);
110 ddr_pll /= (1 << out_div);
111
112 clk_ctrl = ATH_READ_REG(QCA953X_PLL_CLK_CTRL_REG);
113
114 postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
115 QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
116
117 if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
118 cpu_rate = ref_rate;
119 else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
120 cpu_rate = cpu_pll / (postdiv + 1);
121 else
122 cpu_rate = ddr_pll / (postdiv + 1);
123
124 postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
125 QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
126
127 if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
128 ddr_rate = ref_rate;
129 else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
130 ddr_rate = ddr_pll / (postdiv + 1);
131 else
132 ddr_rate = cpu_pll / (postdiv + 1);
133
134 postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
135 QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
136
137 if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
138 ahb_rate = ref_rate;
139 else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
140 ahb_rate = ddr_pll / (postdiv + 1);
141 else
142 ahb_rate = cpu_pll / (postdiv + 1);
143
144 u_ar71xx_ddr_freq = ddr_rate;
145 u_ar71xx_cpu_freq = cpu_rate;
146 u_ar71xx_ahb_freq = ahb_rate;
147
148 u_ar71xx_wdt_freq = ref_rate;
149 u_ar71xx_uart_freq = ref_rate;
150 u_ar71xx_mdio_freq = ref_rate;
151 u_ar71xx_refclk = ref_rate;
152 }
153
154 static void
qca953x_chip_device_stop(uint32_t mask)155 qca953x_chip_device_stop(uint32_t mask)
156 {
157 uint32_t reg;
158
159 reg = ATH_READ_REG(QCA953X_RESET_REG_RESET_MODULE);
160 ATH_WRITE_REG(QCA953X_RESET_REG_RESET_MODULE, reg | mask);
161 }
162
163 static void
qca953x_chip_device_start(uint32_t mask)164 qca953x_chip_device_start(uint32_t mask)
165 {
166 uint32_t reg;
167
168 reg = ATH_READ_REG(QCA953X_RESET_REG_RESET_MODULE);
169 ATH_WRITE_REG(QCA953X_RESET_REG_RESET_MODULE, reg & ~mask);
170 }
171
172 static int
qca953x_chip_device_stopped(uint32_t mask)173 qca953x_chip_device_stopped(uint32_t mask)
174 {
175 uint32_t reg;
176
177 reg = ATH_READ_REG(QCA953X_RESET_REG_RESET_MODULE);
178 return ((reg & mask) == mask);
179 }
180
181 static void
qca953x_chip_set_mii_speed(uint32_t unit,uint32_t speed)182 qca953x_chip_set_mii_speed(uint32_t unit, uint32_t speed)
183 {
184
185 /* XXX TODO */
186 return;
187 }
188
189 static void
qca953x_chip_set_pll_ge(int unit,int speed,uint32_t pll)190 qca953x_chip_set_pll_ge(int unit, int speed, uint32_t pll)
191 {
192 switch (unit) {
193 case 0:
194 ATH_WRITE_REG(QCA953X_PLL_ETH_XMII_CONTROL_REG, pll);
195 break;
196 case 1:
197 /* nothing */
198 break;
199 default:
200 printf("%s: invalid PLL set for arge unit: %d\n",
201 __func__, unit);
202 return;
203 }
204 }
205
206 static void
qca953x_chip_ddr_flush(ar71xx_flush_ddr_id_t id)207 qca953x_chip_ddr_flush(ar71xx_flush_ddr_id_t id)
208 {
209
210 switch (id) {
211 case AR71XX_CPU_DDR_FLUSH_GE0:
212 ar71xx_ddr_flush(QCA953X_DDR_REG_FLUSH_GE0);
213 break;
214 case AR71XX_CPU_DDR_FLUSH_GE1:
215 ar71xx_ddr_flush(QCA953X_DDR_REG_FLUSH_GE1);
216 break;
217 case AR71XX_CPU_DDR_FLUSH_USB:
218 ar71xx_ddr_flush(QCA953X_DDR_REG_FLUSH_USB);
219 break;
220 case AR71XX_CPU_DDR_FLUSH_PCIE:
221 ar71xx_ddr_flush(QCA953X_DDR_REG_FLUSH_PCIE);
222 break;
223 case AR71XX_CPU_DDR_FLUSH_WMAC:
224 ar71xx_ddr_flush(QCA953X_DDR_REG_FLUSH_WMAC);
225 break;
226 default:
227 printf("%s: invalid flush (%d)\n", __func__, id);
228 }
229 }
230
231 static uint32_t
qca953x_chip_get_eth_pll(unsigned int mac,int speed)232 qca953x_chip_get_eth_pll(unsigned int mac, int speed)
233 {
234 uint32_t pll;
235
236 switch (speed) {
237 case 10:
238 pll = QCA953X_PLL_VAL_10;
239 break;
240 case 100:
241 pll = QCA953X_PLL_VAL_100;
242 break;
243 case 1000:
244 pll = QCA953X_PLL_VAL_1000;
245 break;
246 default:
247 printf("%s%d: invalid speed %d\n", __func__, mac, speed);
248 pll = 0;
249 }
250 return (pll);
251 }
252
253 static void
qca953x_chip_reset_ethernet_switch(void)254 qca953x_chip_reset_ethernet_switch(void)
255 {
256 }
257
258 static void
qca953x_configure_gmac(uint32_t gmac_cfg)259 qca953x_configure_gmac(uint32_t gmac_cfg)
260 {
261 uint32_t reg;
262
263 reg = ATH_READ_REG(QCA953X_GMAC_REG_ETH_CFG);
264 printf("%s: ETH_CFG=0x%08x\n", __func__, reg);
265 reg &= ~(QCA953X_ETH_CFG_SW_ONLY_MODE |
266 QCA953X_ETH_CFG_SW_PHY_SWAP |
267 QCA953X_ETH_CFG_SW_APB_ACCESS |
268 QCA953X_ETH_CFG_SW_ACC_MSB_FIRST);
269
270 reg |= gmac_cfg;
271 ATH_WRITE_REG(QCA953X_GMAC_REG_ETH_CFG, reg);
272 }
273
274 static void
qca953x_chip_init_usb_peripheral(void)275 qca953x_chip_init_usb_peripheral(void)
276 {
277 uint32_t bootstrap;
278
279 bootstrap = ATH_READ_REG(QCA953X_RESET_REG_BOOTSTRAP);
280
281 ar71xx_device_stop(QCA953X_RESET_USBSUS_OVERRIDE);
282 DELAY(1000);
283
284 ar71xx_device_start(QCA953X_RESET_USB_PHY);
285 DELAY(1000);
286
287 ar71xx_device_start(QCA953X_RESET_USB_PHY_ANALOG);
288 DELAY(1000);
289
290 ar71xx_device_start(QCA953X_RESET_USB_HOST);
291 DELAY(1000);
292 }
293
294 static void
qca953x_chip_set_mii_if(uint32_t unit,uint32_t mii_mode)295 qca953x_chip_set_mii_if(uint32_t unit, uint32_t mii_mode)
296 {
297
298 /*
299 * XXX !
300 *
301 * Nothing to see here; although gmac0 can have its
302 * MII configuration changed, the register values
303 * are slightly different.
304 */
305 }
306
307 /*
308 * XXX TODO: fetch default MII divider configuration
309 */
310
311 static void
qca953x_chip_reset_wmac(void)312 qca953x_chip_reset_wmac(void)
313 {
314
315 /* XXX TODO */
316 }
317
318 static void
qca953x_chip_init_gmac(void)319 qca953x_chip_init_gmac(void)
320 {
321 long gmac_cfg;
322
323 if (resource_long_value("qca953x_gmac", 0, "gmac_cfg",
324 &gmac_cfg) == 0) {
325 printf("%s: gmac_cfg=0x%08lx\n",
326 __func__,
327 (long) gmac_cfg);
328 qca953x_configure_gmac((uint32_t) gmac_cfg);
329 }
330 }
331
332 /*
333 * Reset the NAND Flash Controller.
334 *
335 * + active=1 means "make it active".
336 * + active=0 means "make it inactive".
337 */
338 static void
qca953x_chip_reset_nfc(int active)339 qca953x_chip_reset_nfc(int active)
340 {
341 }
342
343 /*
344 * Configure the GPIO output mux setup.
345 *
346 * The QCA953x has an output mux which allowed
347 * certain functions to be configured on any pin.
348 * Specifically, the switch PHY link LEDs and
349 * WMAC external RX LNA switches are not limited to
350 * a specific GPIO pin.
351 */
352 static void
qca953x_chip_gpio_output_configure(int gpio,uint8_t func)353 qca953x_chip_gpio_output_configure(int gpio, uint8_t func)
354 {
355 uint32_t reg, s;
356 uint32_t t;
357
358 if (gpio > QCA953X_GPIO_COUNT)
359 return;
360
361 reg = QCA953X_GPIO_REG_OUT_FUNC0 + rounddown(gpio, 4);
362 s = 8 * (gpio % 4);
363
364 /* read-modify-write */
365 t = ATH_READ_REG(AR71XX_GPIO_BASE + reg);
366 t &= ~(0xff << s);
367 t |= func << s;
368 ATH_WRITE_REG(AR71XX_GPIO_BASE + reg, t);
369
370 /* flush write */
371 ATH_READ_REG(AR71XX_GPIO_BASE + reg);
372 }
373
374 struct ar71xx_cpu_def qca953x_chip_def = {
375 &qca953x_chip_detect_mem_size,
376 &qca953x_chip_detect_sys_frequency,
377 &qca953x_chip_device_stop,
378 &qca953x_chip_device_start,
379 &qca953x_chip_device_stopped,
380 &qca953x_chip_set_pll_ge,
381 &qca953x_chip_set_mii_speed,
382 &qca953x_chip_set_mii_if,
383 &qca953x_chip_get_eth_pll,
384 &qca953x_chip_ddr_flush,
385 &qca953x_chip_init_usb_peripheral,
386 &qca953x_chip_reset_ethernet_switch,
387 &qca953x_chip_reset_wmac,
388 &qca953x_chip_init_gmac,
389 &qca953x_chip_reset_nfc,
390 &qca953x_chip_gpio_output_configure,
391 };
392