1 /*-
2 * Copyright (c) 2016 Hiroki Mori
3 * Copyright (c) 2010 Adrian Chadd
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 #include <sys/cdefs.h>
29 #include "opt_ddb.h"
30
31 #include <sys/param.h>
32 #include <sys/conf.h>
33 #include <sys/kernel.h>
34 #include <sys/socket.h>
35 #include <sys/systm.h>
36 #include <sys/bus.h>
37 #include <sys/cons.h>
38 #include <sys/kdb.h>
39 #include <sys/reboot.h>
40
41 #include <vm/vm.h>
42 #include <vm/vm_page.h>
43
44 #include <net/ethernet.h>
45
46 #include <machine/clock.h>
47 #include <machine/cpu.h>
48 #include <machine/cpuregs.h>
49 #include <machine/hwfunc.h>
50 #include <machine/md_var.h>
51 #include <machine/trap.h>
52 #include <machine/vmparam.h>
53
54 #include <mips/atheros/ar531x/ar5312reg.h>
55 #include <mips/atheros/ar531x/ar5315reg.h>
56 #include <mips/atheros/ar531x/ar5315_cpudef.h>
57 #include <mips/atheros/ar531x/ar5315_setup.h>
58
59 static void
ar5312_chip_detect_mem_size(void)60 ar5312_chip_detect_mem_size(void)
61 {
62 uint32_t memsize;
63 uint32_t memcfg, bank0, bank1;
64
65 /*
66 * Determine the memory size as established by system
67 * firmware.
68 *
69 * NB: we allow compile time override
70 */
71 memcfg = ATH_READ_REG(AR5312_SDRAMCTL_BASE + AR5312_SDRAMCTL_MEM_CFG1);
72 bank0 = __SHIFTOUT(memcfg, AR5312_MEM_CFG1_BANK0);
73 bank1 = __SHIFTOUT(memcfg, AR5312_MEM_CFG1_BANK1);
74
75 memsize = (bank0 ? (1 << (bank0 + 1)) : 0) +
76 (bank1 ? (1 << (bank1 + 1)) : 0);
77 memsize <<= 20;
78
79 realmem = memsize;
80 }
81
82 static void
ar5312_chip_detect_sys_frequency(void)83 ar5312_chip_detect_sys_frequency(void)
84 {
85 uint32_t predivisor;
86 uint32_t multiplier;
87
88 const uint32_t clockctl = ATH_READ_REG(AR5312_SYSREG_BASE + AR5312_SYSREG_CLOCKCTL);
89 if(ar531x_soc == AR531X_SOC_AR5313) {
90 predivisor = __SHIFTOUT(clockctl, AR2313_CLOCKCTL_PREDIVIDE);
91 multiplier = __SHIFTOUT(clockctl, AR2313_CLOCKCTL_MULTIPLIER);
92 } else {
93 predivisor = __SHIFTOUT(clockctl, AR5312_CLOCKCTL_PREDIVIDE);
94 multiplier = __SHIFTOUT(clockctl, AR5312_CLOCKCTL_MULTIPLIER);
95 }
96
97 const uint32_t divisor = (0x5421 >> (predivisor * 4)) & 15;
98
99 const uint32_t cpufreq = (40000000 / divisor) * multiplier;
100
101 u_ar531x_cpu_freq = cpufreq;
102 u_ar531x_ahb_freq = cpufreq / 4;
103 u_ar531x_ddr_freq = 0;
104 }
105
106 /*
107 * This does not lock the CPU whilst doing the work!
108 */
109 static void
ar5312_chip_device_reset(void)110 ar5312_chip_device_reset(void)
111 {
112 ATH_WRITE_REG(AR5312_SYSREG_BASE + AR5312_SYSREG_RESETCTL,
113 AR5312_RESET_SYSTEM);
114 }
115
116 static void
ar5312_chip_device_start(void)117 ar5312_chip_device_start(void)
118 {
119 uint32_t cfg0, cfg1;
120 uint32_t bank0, bank1;
121 uint32_t size0, size1;
122
123 cfg0 = ATH_READ_REG(AR5312_SDRAMCTL_BASE + AR5312_SDRAMCTL_MEM_CFG0);
124 cfg1 = ATH_READ_REG(AR5312_SDRAMCTL_BASE + AR5312_SDRAMCTL_MEM_CFG1);
125
126 bank0 = __SHIFTOUT(cfg1, AR5312_MEM_CFG1_BANK0);
127 bank1 = __SHIFTOUT(cfg1, AR5312_MEM_CFG1_BANK1);
128
129 size0 = bank0 ? (1 << (bank0 + 1)) : 0;
130 size1 = bank1 ? (1 << (bank1 + 1)) : 0;
131
132 size0 <<= 20;
133 size1 <<= 20;
134
135 printf("SDRMCTL %x %x %x %x\n", cfg0, cfg1, size0, size1);
136
137 ATH_READ_REG(AR5312_SYSREG_BASE + AR5312_SYSREG_AHBPERR);
138 ATH_READ_REG(AR5312_SYSREG_BASE + AR5312_SYSREG_AHBDMAE);
139 // ATH_WRITE_REG(AR5312_SYSREG_BASE + AR5312_SYSREG_WDOG_CTL, 0);
140 ATH_WRITE_REG(AR5312_SYSREG_BASE + AR5312_SYSREG_ENABLE, 0);
141
142 ATH_WRITE_REG(AR5312_SYSREG_BASE+AR5312_SYSREG_ENABLE,
143 ATH_READ_REG(AR5312_SYSREG_BASE+AR5312_SYSREG_ENABLE) |
144 AR5312_ENABLE_ENET0 | AR5312_ENABLE_ENET1);
145
146 }
147
148 static int
ar5312_chip_device_stopped(uint32_t mask)149 ar5312_chip_device_stopped(uint32_t mask)
150 {
151 uint32_t reg;
152
153 reg = ATH_READ_REG(AR5312_SYSREG_BASE + AR5312_SYSREG_RESETCTL);
154 return ((reg & mask) == mask);
155 }
156
157 static void
ar5312_chip_set_mii_speed(uint32_t unit,uint32_t speed)158 ar5312_chip_set_mii_speed(uint32_t unit, uint32_t speed)
159 {
160 }
161
162 /* Speed is either 10, 100 or 1000 */
163 static void
ar5312_chip_set_pll_ge(int unit,int speed)164 ar5312_chip_set_pll_ge(int unit, int speed)
165 {
166 }
167
168 static void
ar5312_chip_ddr_flush_ge(int unit)169 ar5312_chip_ddr_flush_ge(int unit)
170 {
171 }
172
173 static void
ar5312_chip_soc_init(void)174 ar5312_chip_soc_init(void)
175 {
176
177 u_ar531x_uart_addr = MIPS_PHYS_TO_KSEG1(AR5312_UART0_BASE);
178
179 u_ar531x_gpio_di = AR5312_GPIO_DI;
180 u_ar531x_gpio_do = AR5312_GPIO_DO;
181 u_ar531x_gpio_cr = AR5312_GPIO_CR;
182 u_ar531x_gpio_pins = AR5312_GPIO_PINS;
183
184 u_ar531x_wdog_ctl = AR5312_SYSREG_WDOG_CTL;
185 u_ar531x_wdog_timer = AR5312_SYSREG_WDOG_TIMER;
186
187 }
188
189 static uint32_t
ar5312_chip_get_eth_pll(unsigned int mac,int speed)190 ar5312_chip_get_eth_pll(unsigned int mac, int speed)
191 {
192 return 0;
193 }
194
195 struct ar5315_cpu_def ar5312_chip_def = {
196 &ar5312_chip_detect_mem_size,
197 &ar5312_chip_detect_sys_frequency,
198 &ar5312_chip_device_reset,
199 &ar5312_chip_device_start,
200 &ar5312_chip_device_stopped,
201 &ar5312_chip_set_pll_ge,
202 &ar5312_chip_set_mii_speed,
203 &ar5312_chip_ddr_flush_ge,
204 &ar5312_chip_get_eth_pll,
205 &ar5312_chip_soc_init,
206 };
207