1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2020 Alstom Group.
5 * Copyright (c) 2020 Semihalf.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 /* eSDHC controller driver for NXP QorIQ Layerscape SoCs. */
30
31 #include <sys/cdefs.h>
32 #include <sys/param.h>
33 #include <sys/endian.h>
34 #include <sys/kernel.h>
35 #include <sys/module.h>
36 #include <sys/rman.h>
37 #include <sys/sysctl.h>
38 #include <sys/taskqueue.h>
39
40 #include <machine/bus.h>
41 #include <machine/resource.h>
42
43 #include <dev/extres/clk/clk.h>
44 #include <dev/mmc/bridge.h>
45 #include <dev/mmc/mmcbrvar.h>
46 #include <dev/ofw/ofw_bus.h>
47 #include <dev/ofw/ofw_bus_subr.h>
48 #include <dev/sdhci/sdhci.h>
49 #include <dev/sdhci/sdhci_fdt_gpio.h>
50
51 #include "mmcbr_if.h"
52 #include "sdhci_if.h"
53
54 #define RD4 (sc->read)
55 #define WR4 (sc->write)
56
57 #define SDHCI_FSL_PRES_STATE 0x24
58 #define SDHCI_FSL_PRES_SDSTB (1 << 3)
59 #define SDHCI_FSL_PRES_COMPAT_MASK 0x000f0f07
60
61 #define SDHCI_FSL_PROT_CTRL 0x28
62 #define SDHCI_FSL_PROT_CTRL_WIDTH_1BIT (0 << 1)
63 #define SDHCI_FSL_PROT_CTRL_WIDTH_4BIT (1 << 1)
64 #define SDHCI_FSL_PROT_CTRL_WIDTH_8BIT (2 << 1)
65 #define SDHCI_FSL_PROT_CTRL_WIDTH_MASK (3 << 1)
66 #define SDHCI_FSL_PROT_CTRL_BYTE_SWAP (0 << 4)
67 #define SDHCI_FSL_PROT_CTRL_BYTE_NATIVE (2 << 4)
68 #define SDHCI_FSL_PROT_CTRL_BYTE_MASK (3 << 4)
69 #define SDHCI_FSL_PROT_CTRL_DMA_MASK (3 << 8)
70
71 #define SDHCI_FSL_SYS_CTRL 0x2c
72 #define SDHCI_FSL_CLK_IPGEN (1 << 0)
73 #define SDHCI_FSL_CLK_SDCLKEN (1 << 3)
74 #define SDHCI_FSL_CLK_DIVIDER_MASK 0x000000f0
75 #define SDHCI_FSL_CLK_DIVIDER_SHIFT 4
76 #define SDHCI_FSL_CLK_PRESCALE_MASK 0x0000ff00
77 #define SDHCI_FSL_CLK_PRESCALE_SHIFT 8
78
79 #define SDHCI_FSL_WTMK_LVL 0x44
80 #define SDHCI_FSL_WTMK_RD_512B (0 << 0)
81 #define SDHCI_FSL_WTMK_WR_512B (0 << 15)
82
83 #define SDHCI_FSL_HOST_VERSION 0xfc
84 #define SDHCI_FSL_CAPABILITIES2 0x114
85
86 #define SDHCI_FSL_ESDHC_CTRL 0x40c
87 #define SDHCI_FSL_ESDHC_CTRL_SNOOP (1 << 6)
88 #define SDHCI_FSL_ESDHC_CTRL_CLK_DIV2 (1 << 19)
89
90 struct sdhci_fsl_fdt_softc {
91 device_t dev;
92 const struct sdhci_fsl_fdt_soc_data *soc_data;
93 struct resource *mem_res;
94 struct resource *irq_res;
95 void *irq_cookie;
96 uint32_t baseclk_hz;
97 struct sdhci_fdt_gpio *gpio;
98 struct sdhci_slot slot;
99 bool slot_init_done;
100 uint32_t cmd_and_mode;
101 uint16_t sdclk_bits;
102
103 uint32_t (* read)(struct sdhci_fsl_fdt_softc *, bus_size_t);
104 void (* write)(struct sdhci_fsl_fdt_softc *, bus_size_t, uint32_t);
105 };
106
107 struct sdhci_fsl_fdt_soc_data {
108 int quirks;
109 };
110
111 static const struct sdhci_fsl_fdt_soc_data sdhci_fsl_fdt_ls1046a_soc_data = {
112 .quirks = SDHCI_QUIRK_DONT_SET_HISPD_BIT | SDHCI_QUIRK_BROKEN_AUTO_STOP
113 };
114
115 static const struct sdhci_fsl_fdt_soc_data sdhci_fsl_fdt_gen_data = {
116 .quirks = 0,
117 };
118
119 static const struct ofw_compat_data sdhci_fsl_fdt_compat_data[] = {
120 {"fsl,ls1046a-esdhc", (uintptr_t)&sdhci_fsl_fdt_ls1046a_soc_data},
121 {"fsl,esdhc", (uintptr_t)&sdhci_fsl_fdt_gen_data},
122 {NULL, 0}
123 };
124
125 static uint32_t
read_be(struct sdhci_fsl_fdt_softc * sc,bus_size_t off)126 read_be(struct sdhci_fsl_fdt_softc *sc, bus_size_t off)
127 {
128
129 return (be32toh(bus_read_4(sc->mem_res, off)));
130 }
131
132 static void
write_be(struct sdhci_fsl_fdt_softc * sc,bus_size_t off,uint32_t val)133 write_be(struct sdhci_fsl_fdt_softc *sc, bus_size_t off, uint32_t val)
134 {
135
136 bus_write_4(sc->mem_res, off, htobe32(val));
137 }
138
139 static uint32_t
read_le(struct sdhci_fsl_fdt_softc * sc,bus_size_t off)140 read_le(struct sdhci_fsl_fdt_softc *sc, bus_size_t off)
141 {
142
143 return (bus_read_4(sc->mem_res, off));
144 }
145
146 static void
write_le(struct sdhci_fsl_fdt_softc * sc,bus_size_t off,uint32_t val)147 write_le(struct sdhci_fsl_fdt_softc *sc, bus_size_t off, uint32_t val)
148 {
149
150 bus_write_4(sc->mem_res, off, val);
151 }
152
153
154 static uint16_t
sdhci_fsl_fdt_get_clock(struct sdhci_fsl_fdt_softc * sc)155 sdhci_fsl_fdt_get_clock(struct sdhci_fsl_fdt_softc *sc)
156 {
157 uint16_t val;
158
159 val = sc->sdclk_bits | SDHCI_CLOCK_INT_EN;
160 if (RD4(sc, SDHCI_FSL_PRES_STATE) & SDHCI_FSL_PRES_SDSTB)
161 val |= SDHCI_CLOCK_INT_STABLE;
162 if (RD4(sc, SDHCI_FSL_SYS_CTRL) & SDHCI_FSL_CLK_SDCLKEN)
163 val |= SDHCI_CLOCK_CARD_EN;
164
165 return (val);
166 }
167
168 static void
fsl_sdhc_fdt_set_clock(struct sdhci_fsl_fdt_softc * sc,uint16_t val)169 fsl_sdhc_fdt_set_clock(struct sdhci_fsl_fdt_softc *sc, uint16_t val)
170 {
171 uint32_t div, freq, prescale, val32;
172
173 sc->sdclk_bits = val & SDHCI_DIVIDERS_MASK;
174 val32 = RD4(sc, SDHCI_CLOCK_CONTROL);
175
176 if ((val & SDHCI_CLOCK_CARD_EN) == 0) {
177 WR4(sc, SDHCI_CLOCK_CONTROL, val32 & ~SDHCI_FSL_CLK_SDCLKEN);
178 return;
179 }
180
181 div = ((val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK) |
182 ((val >> SDHCI_DIVIDER_HI_SHIFT) & SDHCI_DIVIDER_HI_MASK) <<
183 SDHCI_DIVIDER_MASK_LEN;
184 if (div == 0)
185 freq = sc->baseclk_hz;
186 else
187 freq = sc->baseclk_hz / (2 * div);
188
189 for (prescale = 2; freq < sc->baseclk_hz / (prescale * 16); )
190 prescale <<= 1;
191 for (div = 1; freq < sc->baseclk_hz / (prescale * div); )
192 ++div;
193
194 #ifdef DEBUG
195 device_printf(sc->dev,
196 "Desired SD/MMC freq: %d, actual: %d; base %d prescale %d divisor %d\n",
197 freq, sc->baseclk_hz / (prescale * div),
198 sc->baseclk_hz, prescale, div);
199 #endif
200
201 prescale >>= 1;
202 div -= 1;
203
204 val32 &= ~(SDHCI_FSL_CLK_DIVIDER_MASK | SDHCI_FSL_CLK_PRESCALE_MASK);
205 val32 |= div << SDHCI_FSL_CLK_DIVIDER_SHIFT;
206 val32 |= prescale << SDHCI_FSL_CLK_PRESCALE_SHIFT;
207 val32 |= SDHCI_FSL_CLK_IPGEN | SDHCI_FSL_CLK_SDCLKEN;
208 WR4(sc, SDHCI_CLOCK_CONTROL, val32);
209 }
210
211 static uint8_t
sdhci_fsl_fdt_read_1(device_t dev,struct sdhci_slot * slot,bus_size_t off)212 sdhci_fsl_fdt_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off)
213 {
214 struct sdhci_fsl_fdt_softc *sc;
215 uint32_t wrk32, val32;
216
217 sc = device_get_softc(dev);
218
219 switch (off) {
220 case SDHCI_HOST_CONTROL:
221 wrk32 = RD4(sc, SDHCI_FSL_PROT_CTRL);
222 val32 = wrk32 & (SDHCI_CTRL_LED | SDHCI_CTRL_CARD_DET |
223 SDHCI_CTRL_FORCE_CARD);
224 if (wrk32 & SDHCI_FSL_PROT_CTRL_WIDTH_4BIT)
225 val32 |= SDHCI_CTRL_4BITBUS;
226 else if (wrk32 & SDHCI_FSL_PROT_CTRL_WIDTH_8BIT)
227 val32 |= SDHCI_CTRL_8BITBUS;
228 return (val32);
229 case SDHCI_POWER_CONTROL:
230 return (SDHCI_POWER_ON | SDHCI_POWER_300);
231 default:
232 break;
233 }
234
235 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & UINT8_MAX);
236 }
237
238 static uint16_t
sdhci_fsl_fdt_read_2(device_t dev,struct sdhci_slot * slot,bus_size_t off)239 sdhci_fsl_fdt_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
240 {
241 struct sdhci_fsl_fdt_softc *sc;
242 uint32_t val32;
243
244 sc = device_get_softc(dev);
245
246 switch (off) {
247 case SDHCI_CLOCK_CONTROL:
248 return (sdhci_fsl_fdt_get_clock(sc));
249 case SDHCI_HOST_VERSION:
250 return (RD4(sc, SDHCI_FSL_HOST_VERSION) & UINT16_MAX);
251 case SDHCI_TRANSFER_MODE:
252 return (sc->cmd_and_mode & UINT16_MAX);
253 case SDHCI_COMMAND_FLAGS:
254 return (sc->cmd_and_mode >> 16);
255 case SDHCI_SLOT_INT_STATUS:
256 /*
257 * eSDHC hardware manages only a single slot.
258 * Synthesize a slot interrupt status register for slot 1 below.
259 */
260 val32 = RD4(sc, SDHCI_INT_STATUS);
261 val32 &= RD4(sc, SDHCI_SIGNAL_ENABLE);
262 return (!!val32);
263 default:
264 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & UINT16_MAX);
265 }
266 }
267
268 static uint32_t
sdhci_fsl_fdt_read_4(device_t dev,struct sdhci_slot * slot,bus_size_t off)269 sdhci_fsl_fdt_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off)
270 {
271 struct sdhci_fsl_fdt_softc *sc;
272 uint32_t wrk32, val32;
273
274 sc = device_get_softc(dev);
275
276 if (off == SDHCI_BUFFER)
277 return (bus_read_4(sc->mem_res, off));
278 if (off == SDHCI_CAPABILITIES2)
279 off = SDHCI_FSL_CAPABILITIES2;
280
281 val32 = RD4(sc, off);
282
283 switch (off) {
284 case SDHCI_CAPABILITIES:
285 val32 &= ~(SDHCI_CAN_DO_SUSPEND | SDHCI_CAN_VDD_180);
286 break;
287 case SDHCI_PRESENT_STATE:
288 wrk32 = val32;
289 val32 &= SDHCI_FSL_PRES_COMPAT_MASK;
290 val32 |= (wrk32 >> 4) & SDHCI_STATE_DAT_MASK;
291 val32 |= (wrk32 << 1) & SDHCI_STATE_CMD;
292 break;
293 default:
294 break;
295 }
296
297 return (val32);
298 }
299
300 static void
sdhci_fsl_fdt_read_multi_4(device_t dev,struct sdhci_slot * slot,bus_size_t off,uint32_t * data,bus_size_t count)301 sdhci_fsl_fdt_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
302 uint32_t *data, bus_size_t count)
303 {
304 struct sdhci_fsl_fdt_softc *sc;
305
306 sc = device_get_softc(dev);
307 bus_read_multi_4(sc->mem_res, off, data, count);
308 }
309
310 static void
sdhci_fsl_fdt_write_1(device_t dev,struct sdhci_slot * slot,bus_size_t off,uint8_t val)311 sdhci_fsl_fdt_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off,
312 uint8_t val)
313 {
314 struct sdhci_fsl_fdt_softc *sc;
315 uint32_t val32;
316
317 sc = device_get_softc(dev);
318
319 switch (off) {
320 case SDHCI_HOST_CONTROL:
321 val32 = RD4(sc, SDHCI_FSL_PROT_CTRL);
322 val32 &= ~SDHCI_FSL_PROT_CTRL_WIDTH_MASK;
323 val32 |= (val & SDHCI_CTRL_LED);
324
325 if (val & SDHCI_CTRL_8BITBUS)
326 val32 |= SDHCI_FSL_PROT_CTRL_WIDTH_8BIT;
327 else
328 /* Bus width is 1-bit when this flag is not set. */
329 val32 |= (val & SDHCI_CTRL_4BITBUS);
330 /* Enable SDMA by masking out this field. */
331 val32 &= ~SDHCI_FSL_PROT_CTRL_DMA_MASK;
332 val32 &= ~(SDHCI_CTRL_CARD_DET | SDHCI_CTRL_FORCE_CARD);
333 val32 |= (val & (SDHCI_CTRL_CARD_DET |
334 SDHCI_CTRL_FORCE_CARD));
335 WR4(sc, SDHCI_FSL_PROT_CTRL, val32);
336 return;
337 case SDHCI_POWER_CONTROL:
338 return;
339 case SDHCI_SOFTWARE_RESET:
340 val &= ~SDHCI_RESET_ALL;
341 /* FALLTHROUGH. */
342 default:
343 val32 = RD4(sc, off & ~3);
344 val32 &= ~(UINT8_MAX << (off & 3) * 8);
345 val32 |= (val << (off & 3) * 8);
346 WR4(sc, off & ~3, val32);
347 return;
348 }
349 }
350
351 static void
sdhci_fsl_fdt_write_2(device_t dev,struct sdhci_slot * slot,bus_size_t off,uint16_t val)352 sdhci_fsl_fdt_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off,
353 uint16_t val)
354 {
355 struct sdhci_fsl_fdt_softc *sc;
356 uint32_t val32;
357
358 sc = device_get_softc(dev);
359
360 switch (off) {
361 case SDHCI_CLOCK_CONTROL:
362 fsl_sdhc_fdt_set_clock(sc, val);
363 return;
364 /*
365 * eSDHC hardware combines command and mode into a single
366 * register. Cache it here, so that command isn't written
367 * until after mode.
368 */
369 case SDHCI_TRANSFER_MODE:
370 sc->cmd_and_mode = val;
371 return;
372 case SDHCI_COMMAND_FLAGS:
373 sc->cmd_and_mode =
374 (sc->cmd_and_mode & UINT16_MAX) | (val << 16);
375 WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode);
376 sc->cmd_and_mode = 0;
377 return;
378 default:
379 val32 = RD4(sc, off & ~3);
380 val32 &= ~(UINT16_MAX << (off & 3) * 8);
381 val32 |= ((val & UINT16_MAX) << (off & 3) * 8);
382 WR4(sc, off & ~3, val32);
383 return;
384 }
385 }
386
387 static void
sdhci_fsl_fdt_write_4(device_t dev,struct sdhci_slot * slot,bus_size_t off,uint32_t val)388 sdhci_fsl_fdt_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
389 uint32_t val)
390 {
391 struct sdhci_fsl_fdt_softc *sc;
392
393 sc = device_get_softc(dev);
394
395 switch (off) {
396 case SDHCI_BUFFER:
397 bus_write_4(sc->mem_res, off, val);
398 return;
399 /*
400 * eSDHC hardware lacks support for the SDMA buffer boundary
401 * feature and instead generates SDHCI_INT_DMA_END interrupts
402 * after each completed DMA data transfer.
403 * Since this duplicates the SDHCI_INT_DATA_END functionality,
404 * mask out the unneeded SDHCI_INT_DMA_END interrupt.
405 */
406 case SDHCI_INT_ENABLE:
407 case SDHCI_SIGNAL_ENABLE:
408 val &= ~SDHCI_INT_DMA_END;
409 /* FALLTHROUGH. */
410 default:
411 WR4(sc, off, val);
412 return;
413 }
414 }
415
416 static void
sdhci_fsl_fdt_write_multi_4(device_t dev,struct sdhci_slot * slot,bus_size_t off,uint32_t * data,bus_size_t count)417 sdhci_fsl_fdt_write_multi_4(device_t dev, struct sdhci_slot *slot,
418 bus_size_t off, uint32_t *data, bus_size_t count)
419 {
420 struct sdhci_fsl_fdt_softc *sc;
421
422 sc = device_get_softc(dev);
423 bus_write_multi_4(sc->mem_res, off, data, count);
424 }
425
426 static void
sdhci_fsl_fdt_irq(void * arg)427 sdhci_fsl_fdt_irq(void *arg)
428 {
429 struct sdhci_fsl_fdt_softc *sc;
430
431 sc = arg;
432 sdhci_generic_intr(&sc->slot);
433 return;
434 }
435
436 static int
sdhci_fsl_fdt_get_ro(device_t bus,device_t child)437 sdhci_fsl_fdt_get_ro(device_t bus, device_t child)
438 {
439 struct sdhci_fsl_fdt_softc *sc;
440
441 sc = device_get_softc(bus);
442 return (sdhci_fdt_gpio_get_readonly(sc->gpio));
443 }
444
445 static bool
sdhci_fsl_fdt_get_card_present(device_t dev,struct sdhci_slot * slot)446 sdhci_fsl_fdt_get_card_present(device_t dev, struct sdhci_slot *slot)
447 {
448 struct sdhci_fsl_fdt_softc *sc;
449
450 sc = device_get_softc(dev);
451 return (sdhci_fdt_gpio_get_present(sc->gpio));
452 }
453
454 static int
sdhci_fsl_fdt_attach(device_t dev)455 sdhci_fsl_fdt_attach(device_t dev)
456 {
457 struct sdhci_fsl_fdt_softc *sc;
458 uint32_t val, buf_order;
459 uintptr_t ocd_data;
460 uint64_t clk_hz;
461 phandle_t node;
462 int rid, ret;
463 clk_t clk;
464
465 node = ofw_bus_get_node(dev);
466 sc = device_get_softc(dev);
467 ocd_data = ofw_bus_search_compatible(dev,
468 sdhci_fsl_fdt_compat_data)->ocd_data;
469 sc->soc_data = (struct sdhci_fsl_fdt_soc_data *)ocd_data;
470 sc->dev = dev;
471 sc->slot.quirks = sc->soc_data->quirks;
472
473 rid = 0;
474 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
475 RF_ACTIVE);
476 if (sc->mem_res == NULL) {
477 device_printf(dev,
478 "Could not allocate resources for controller\n");
479 return (ENOMEM);
480 }
481
482 rid = 0;
483 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
484 RF_ACTIVE);
485 if (sc->irq_res == NULL) {
486 device_printf(dev,
487 "Could not allocate irq resources for controller\n");
488 ret = ENOMEM;
489 goto err_free_mem;
490 }
491
492 ret = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
493 NULL, sdhci_fsl_fdt_irq, sc, &sc->irq_cookie);
494 if (ret != 0) {
495 device_printf(dev, "Could not setup IRQ handler\n");
496 goto err_free_irq_res;
497 }
498
499 ret = clk_get_by_ofw_index(dev, node, 0, &clk);
500 if (ret != 0) {
501 device_printf(dev, "Parent clock not found\n");
502 goto err_free_irq;
503 }
504
505 ret = clk_get_freq(clk, &clk_hz);
506 if (ret != 0) {
507 device_printf(dev,
508 "Could not get parent clock frequency\n");
509 goto err_free_irq;
510 }
511
512 sc->baseclk_hz = clk_hz / 2;
513
514 /* Figure out eSDHC block endianness before we touch any HW regs. */
515 if (OF_hasprop(node, "little-endian")) {
516 sc->read = read_le;
517 sc->write = write_le;
518 buf_order = SDHCI_FSL_PROT_CTRL_BYTE_NATIVE;
519 } else {
520 sc->read = read_be;
521 sc->write = write_be;
522 buf_order = SDHCI_FSL_PROT_CTRL_BYTE_SWAP;
523 }
524
525 /*
526 * Setting this register affects byte order in SDHCI_BUFFER only.
527 * If the eSDHC block is connected over a big-endian bus, the data
528 * read from/written to the buffer will be already byte swapped.
529 * In such a case, setting SDHCI_FSL_PROT_CTRL_BYTE_SWAP will convert
530 * the byte order again, resulting in a native byte order.
531 * The read/write callbacks accommodate for this behavior.
532 */
533 val = RD4(sc, SDHCI_FSL_PROT_CTRL);
534 val &= ~SDHCI_FSL_PROT_CTRL_BYTE_MASK;
535 WR4(sc, SDHCI_FSL_PROT_CTRL, val | buf_order);
536
537 /*
538 * Gate the SD clock and set its source to peripheral clock / 2.
539 * The frequency in baseclk_hz is set to match this.
540 */
541 val = RD4(sc, SDHCI_CLOCK_CONTROL);
542 WR4(sc, SDHCI_CLOCK_CONTROL, val & ~SDHCI_FSL_CLK_SDCLKEN);
543 val = RD4(sc, SDHCI_FSL_ESDHC_CTRL);
544 WR4(sc, SDHCI_FSL_ESDHC_CTRL, val | SDHCI_FSL_ESDHC_CTRL_CLK_DIV2);
545 sc->slot.max_clk = sc->baseclk_hz;
546 sc->gpio = sdhci_fdt_gpio_setup(dev, &sc->slot);
547
548 /*
549 * Set the buffer watermark level to 128 words (512 bytes) for both
550 * read and write. The hardware has a restriction that when the read or
551 * write ready status is asserted, that means you can read exactly the
552 * number of words set in the watermark register before you have to
553 * re-check the status and potentially wait for more data. The main
554 * sdhci driver provides no hook for doing status checking on less than
555 * a full block boundary, so we set the watermark level to be a full
556 * block. Reads and writes where the block size is less than the
557 * watermark size will work correctly too, no need to change the
558 * watermark for different size blocks. However, 128 is the maximum
559 * allowed for the watermark, so PIO is limitted to 512 byte blocks.
560 */
561 WR4(sc, SDHCI_FSL_WTMK_LVL, SDHCI_FSL_WTMK_WR_512B |
562 SDHCI_FSL_WTMK_RD_512B);
563
564 ret = sdhci_init_slot(dev, &sc->slot, 0);
565 if (ret != 0)
566 goto err_free_gpio;
567 sc->slot_init_done = true;
568 sdhci_start_slot(&sc->slot);
569
570 return (bus_generic_attach(dev));
571
572 err_free_gpio:
573 sdhci_fdt_gpio_teardown(sc->gpio);
574 err_free_irq:
575 bus_teardown_intr(dev, sc->irq_res, sc->irq_cookie);
576 err_free_irq_res:
577 bus_free_resource(dev, SYS_RES_IRQ, sc->irq_res);
578 err_free_mem:
579 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res);
580 return (ret);
581 }
582
583 static int
sdhci_fsl_fdt_detach(device_t dev)584 sdhci_fsl_fdt_detach(device_t dev)
585 {
586 struct sdhci_fsl_fdt_softc *sc;
587
588 sc = device_get_softc(dev);
589 if (sc->slot_init_done)
590 sdhci_cleanup_slot(&sc->slot);
591 if (sc->gpio != NULL)
592 sdhci_fdt_gpio_teardown(sc->gpio);
593 if (sc->irq_cookie != NULL)
594 bus_teardown_intr(dev, sc->irq_res, sc->irq_cookie);
595 if (sc->irq_res != NULL)
596 bus_free_resource(dev, SYS_RES_IRQ, sc->irq_res);
597 if (sc->mem_res != NULL)
598 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res);
599 return (0);
600 }
601
602 static int
sdhci_fsl_fdt_probe(device_t dev)603 sdhci_fsl_fdt_probe(device_t dev)
604 {
605
606 if (!ofw_bus_status_okay(dev))
607 return (ENXIO);
608
609 if (!ofw_bus_search_compatible(dev,
610 sdhci_fsl_fdt_compat_data)->ocd_data)
611 return (ENXIO);
612
613 device_set_desc(dev, "NXP QorIQ Layerscape eSDHC controller");
614 return (BUS_PROBE_DEFAULT);
615 }
616
617 static int
sdhci_fsl_fdt_read_ivar(device_t bus,device_t child,int which,uintptr_t * result)618 sdhci_fsl_fdt_read_ivar(device_t bus, device_t child, int which,
619 uintptr_t *result)
620 {
621 struct sdhci_slot *slot = device_get_ivars(child);
622
623 if (which == MMCBR_IVAR_MAX_DATA && (slot->opt & SDHCI_HAVE_DMA)) {
624 /*
625 * In the absence of SDMA buffer boundary functionality,
626 * limit the maximum data length per read/write command
627 * to bounce buffer size.
628 */
629 *result = howmany(slot->sdma_bbufsz, 512);
630 return (0);
631 }
632 return (sdhci_generic_read_ivar(bus, child, which, result));
633 }
634
635 static const device_method_t sdhci_fsl_fdt_methods[] = {
636 /* Device interface. */
637 DEVMETHOD(device_probe, sdhci_fsl_fdt_probe),
638 DEVMETHOD(device_attach, sdhci_fsl_fdt_attach),
639 DEVMETHOD(device_detach, sdhci_fsl_fdt_detach),
640
641 /* Bus interface. */
642 DEVMETHOD(bus_read_ivar, sdhci_fsl_fdt_read_ivar),
643 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar),
644
645 /* MMC bridge interface. */
646 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios),
647 DEVMETHOD(mmcbr_request, sdhci_generic_request),
648 DEVMETHOD(mmcbr_get_ro, sdhci_fsl_fdt_get_ro),
649 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
650 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
651
652 /* SDHCI accessors. */
653 DEVMETHOD(sdhci_read_1, sdhci_fsl_fdt_read_1),
654 DEVMETHOD(sdhci_read_2, sdhci_fsl_fdt_read_2),
655 DEVMETHOD(sdhci_read_4, sdhci_fsl_fdt_read_4),
656 DEVMETHOD(sdhci_read_multi_4, sdhci_fsl_fdt_read_multi_4),
657 DEVMETHOD(sdhci_write_1, sdhci_fsl_fdt_write_1),
658 DEVMETHOD(sdhci_write_2, sdhci_fsl_fdt_write_2),
659 DEVMETHOD(sdhci_write_4, sdhci_fsl_fdt_write_4),
660 DEVMETHOD(sdhci_write_multi_4, sdhci_fsl_fdt_write_multi_4),
661 DEVMETHOD(sdhci_get_card_present, sdhci_fsl_fdt_get_card_present),
662 DEVMETHOD_END
663 };
664
665 static devclass_t sdhci_fsl_fdt_devclass;
666 static driver_t sdhci_fsl_fdt_driver = {
667 "sdhci_fsl_fdt",
668 sdhci_fsl_fdt_methods,
669 sizeof(struct sdhci_fsl_fdt_softc),
670 };
671
672 DRIVER_MODULE(sdhci_fsl_fdt, simplebus, sdhci_fsl_fdt_driver,
673 sdhci_fsl_fdt_devclass, NULL, NULL);
674 SDHCI_DEPEND(sdhci_fsl_fdt);
675
676 #ifndef MMCCAM
677 MMC_DECLARE_BRIDGE(sdhci_fsl_fdt);
678 #endif
679