1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2015-2016, Stanislav Galabov
5 * Copyright (c) 2014, Aleksandr A. Mityaev
6 * Copyright (c) 2011, Aleksandr Rybalko
7 * based on hard work
8 * by Alexander Egorenkov <egorenar@gmail.com>
9 * and by Damien Bergamini <damien.bergamini@free.fr>
10 * All rights reserved.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice unmodified, this list of conditions, and the following
17 * disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 */
34
35 #include <sys/cdefs.h>
36 #include "if_rtvar.h"
37 #include "if_rtreg.h"
38
39 #include <sys/kenv.h>
40
41 #include <net/if.h>
42 #include <net/if_var.h>
43 #include <net/if_arp.h>
44 #include <net/ethernet.h>
45 #include <net/if_dl.h>
46 #include <net/if_media.h>
47 #include <net/if_types.h>
48 #include <net/if_vlan_var.h>
49
50 #include <net/bpf.h>
51
52 #include <machine/bus.h>
53 #include <machine/cache.h>
54 #include <machine/cpufunc.h>
55 #include <machine/resource.h>
56 #include <vm/vm_param.h>
57 #include <vm/vm.h>
58 #include <vm/pmap.h>
59 #include <machine/pmap.h>
60 #include <sys/bus.h>
61 #include <sys/rman.h>
62
63 #include "opt_platform.h"
64 #include "opt_rt305x.h"
65
66 #ifdef FDT
67 #include <dev/ofw/openfirm.h>
68 #include <dev/ofw/ofw_bus.h>
69 #include <dev/ofw/ofw_bus_subr.h>
70 #endif
71
72 #include <dev/mii/mii.h>
73 #include <dev/mii/miivar.h>
74
75 #ifdef RT_MDIO
76 #include <dev/mdio/mdio.h>
77 #include <dev/etherswitch/miiproxy.h>
78 #include "mdio_if.h"
79 #endif
80
81 #if 0
82 #include <mips/rt305x/rt305x_sysctlvar.h>
83 #include <mips/rt305x/rt305xreg.h>
84 #endif
85
86 #ifdef IF_RT_PHY_SUPPORT
87 #include "miibus_if.h"
88 #endif
89
90 /*
91 * Defines and macros
92 */
93 #define RT_MAX_AGG_SIZE 3840
94
95 #define RT_TX_DATA_SEG0_SIZE MJUMPAGESIZE
96
97 #define RT_MS(_v, _f) (((_v) & _f) >> _f##_S)
98 #define RT_SM(_v, _f) (((_v) << _f##_S) & _f)
99
100 #define RT_TX_WATCHDOG_TIMEOUT 5
101
102 #define RT_CHIPID_RT2880 0x2880
103 #define RT_CHIPID_RT3050 0x3050
104 #define RT_CHIPID_RT3883 0x3883
105 #define RT_CHIPID_RT5350 0x5350
106 #define RT_CHIPID_MT7620 0x7620
107 #define RT_CHIPID_MT7621 0x7621
108
109 #ifdef FDT
110 /* more specific and new models should go first */
111 static const struct ofw_compat_data rt_compat_data[] = {
112 { "ralink,rt2880-eth", RT_CHIPID_RT2880 },
113 { "ralink,rt3050-eth", RT_CHIPID_RT3050 },
114 { "ralink,rt3352-eth", RT_CHIPID_RT3050 },
115 { "ralink,rt3883-eth", RT_CHIPID_RT3883 },
116 { "ralink,rt5350-eth", RT_CHIPID_RT5350 },
117 { "ralink,mt7620a-eth", RT_CHIPID_MT7620 },
118 { "mediatek,mt7620-eth", RT_CHIPID_MT7620 },
119 { "ralink,mt7621-eth", RT_CHIPID_MT7621 },
120 { "mediatek,mt7621-eth", RT_CHIPID_MT7621 },
121 { NULL, 0 }
122 };
123 #endif
124
125 /*
126 * Static function prototypes
127 */
128 static int rt_probe(device_t dev);
129 static int rt_attach(device_t dev);
130 static int rt_detach(device_t dev);
131 static int rt_shutdown(device_t dev);
132 static int rt_suspend(device_t dev);
133 static int rt_resume(device_t dev);
134 static void rt_init_locked(void *priv);
135 static void rt_init(void *priv);
136 static void rt_stop_locked(void *priv);
137 static void rt_stop(void *priv);
138 static void rt_start(struct ifnet *ifp);
139 static int rt_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data);
140 static void rt_periodic(void *arg);
141 static void rt_tx_watchdog(void *arg);
142 static void rt_intr(void *arg);
143 static void rt_rt5350_intr(void *arg);
144 static void rt_tx_coherent_intr(struct rt_softc *sc);
145 static void rt_rx_coherent_intr(struct rt_softc *sc);
146 static void rt_rx_delay_intr(struct rt_softc *sc);
147 static void rt_tx_delay_intr(struct rt_softc *sc);
148 static void rt_rx_intr(struct rt_softc *sc, int qid);
149 static void rt_tx_intr(struct rt_softc *sc, int qid);
150 static void rt_rx_done_task(void *context, int pending);
151 static void rt_tx_done_task(void *context, int pending);
152 static void rt_periodic_task(void *context, int pending);
153 static int rt_rx_eof(struct rt_softc *sc,
154 struct rt_softc_rx_ring *ring, int limit);
155 static void rt_tx_eof(struct rt_softc *sc,
156 struct rt_softc_tx_ring *ring);
157 static void rt_update_stats(struct rt_softc *sc);
158 static void rt_watchdog(struct rt_softc *sc);
159 static void rt_update_raw_counters(struct rt_softc *sc);
160 static void rt_intr_enable(struct rt_softc *sc, uint32_t intr_mask);
161 static void rt_intr_disable(struct rt_softc *sc, uint32_t intr_mask);
162 static int rt_txrx_enable(struct rt_softc *sc);
163 static int rt_alloc_rx_ring(struct rt_softc *sc,
164 struct rt_softc_rx_ring *ring, int qid);
165 static void rt_reset_rx_ring(struct rt_softc *sc,
166 struct rt_softc_rx_ring *ring);
167 static void rt_free_rx_ring(struct rt_softc *sc,
168 struct rt_softc_rx_ring *ring);
169 static int rt_alloc_tx_ring(struct rt_softc *sc,
170 struct rt_softc_tx_ring *ring, int qid);
171 static void rt_reset_tx_ring(struct rt_softc *sc,
172 struct rt_softc_tx_ring *ring);
173 static void rt_free_tx_ring(struct rt_softc *sc,
174 struct rt_softc_tx_ring *ring);
175 static void rt_dma_map_addr(void *arg, bus_dma_segment_t *segs,
176 int nseg, int error);
177 static void rt_sysctl_attach(struct rt_softc *sc);
178 #ifdef IF_RT_PHY_SUPPORT
179 void rt_miibus_statchg(device_t);
180 #endif
181 #if defined(IF_RT_PHY_SUPPORT) || defined(RT_MDIO)
182 static int rt_miibus_readreg(device_t, int, int);
183 static int rt_miibus_writereg(device_t, int, int, int);
184 #endif
185 static int rt_ifmedia_upd(struct ifnet *);
186 static void rt_ifmedia_sts(struct ifnet *, struct ifmediareq *);
187
188 static SYSCTL_NODE(_hw, OID_AUTO, rt, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
189 "RT driver parameters");
190 #ifdef IF_RT_DEBUG
191 static int rt_debug = 0;
192 SYSCTL_INT(_hw_rt, OID_AUTO, debug, CTLFLAG_RWTUN, &rt_debug, 0,
193 "RT debug level");
194 #endif
195
196 static int
rt_probe(device_t dev)197 rt_probe(device_t dev)
198 {
199 struct rt_softc *sc = device_get_softc(dev);
200 char buf[80];
201 #ifdef FDT
202 const struct ofw_compat_data * cd;
203
204 cd = ofw_bus_search_compatible(dev, rt_compat_data);
205 if (cd->ocd_data == 0)
206 return (ENXIO);
207
208 sc->rt_chipid = (unsigned int)(cd->ocd_data);
209 #else
210 #if defined(MT7620)
211 sc->rt_chipid = RT_CHIPID_MT7620;
212 #elif defined(MT7621)
213 sc->rt_chipid = RT_CHIPID_MT7621;
214 #elif defined(RT5350)
215 sc->rt_chipid = RT_CHIPID_RT5350;
216 #else
217 sc->rt_chipid = RT_CHIPID_RT3050;
218 #endif
219 #endif
220 snprintf(buf, sizeof(buf), "Ralink %cT%x onChip Ethernet driver",
221 sc->rt_chipid >= 0x7600 ? 'M' : 'R', sc->rt_chipid);
222 device_set_desc_copy(dev, buf);
223 return (BUS_PROBE_GENERIC);
224 }
225
226 /*
227 * macaddr_atoi - translate string MAC address to uint8_t array
228 */
229 static int
macaddr_atoi(const char * str,uint8_t * mac)230 macaddr_atoi(const char *str, uint8_t *mac)
231 {
232 int count, i;
233 unsigned int amac[ETHER_ADDR_LEN]; /* Aligned version */
234
235 count = sscanf(str, "%x%*c%x%*c%x%*c%x%*c%x%*c%x",
236 &amac[0], &amac[1], &amac[2],
237 &amac[3], &amac[4], &amac[5]);
238 if (count < ETHER_ADDR_LEN) {
239 memset(mac, 0, ETHER_ADDR_LEN);
240 return (1);
241 }
242
243 /* Copy aligned to result */
244 for (i = 0; i < ETHER_ADDR_LEN; i ++)
245 mac[i] = (amac[i] & 0xff);
246
247 return (0);
248 }
249
250 #ifdef USE_GENERATED_MAC_ADDRESS
251 /*
252 * generate_mac(uin8_t *mac)
253 * This is MAC address generator for cases when real device MAC address
254 * unknown or not yet accessible.
255 * Use 'b','s','d' signature and 3 octets from CRC32 on kenv.
256 * MAC = 'b', 's', 'd', CRC[3]^CRC[2], CRC[1], CRC[0]
257 *
258 * Output - MAC address, that do not change between reboots, if hints or
259 * bootloader info unchange.
260 */
261 static void
generate_mac(uint8_t * mac)262 generate_mac(uint8_t *mac)
263 {
264 unsigned char *cp;
265 int i = 0;
266 uint32_t crc = 0xffffffff;
267
268 /* Generate CRC32 on kenv */
269 for (cp = kenvp[0]; cp != NULL; cp = kenvp[++i]) {
270 crc = calculate_crc32c(crc, cp, strlen(cp) + 1);
271 }
272 crc = ~crc;
273
274 mac[0] = 'b';
275 mac[1] = 's';
276 mac[2] = 'd';
277 mac[3] = (crc >> 24) ^ ((crc >> 16) & 0xff);
278 mac[4] = (crc >> 8) & 0xff;
279 mac[5] = crc & 0xff;
280 }
281 #endif
282
283 /*
284 * ether_request_mac - try to find usable MAC address.
285 */
286 static int
ether_request_mac(device_t dev,uint8_t * mac)287 ether_request_mac(device_t dev, uint8_t *mac)
288 {
289 char *var;
290
291 /*
292 * "ethaddr" is passed via envp on RedBoot platforms
293 * "kmac" is passed via argv on RouterBOOT platforms
294 */
295 #if defined(RT305X_UBOOT) || defined(__REDBOOT__) || defined(__ROUTERBOOT__)
296 if ((var = kern_getenv("ethaddr")) != NULL ||
297 (var = kern_getenv("kmac")) != NULL ) {
298 if(!macaddr_atoi(var, mac)) {
299 printf("%s: use %s macaddr from KENV\n",
300 device_get_nameunit(dev), var);
301 freeenv(var);
302 return (0);
303 }
304 freeenv(var);
305 }
306 #endif
307
308 /*
309 * Try from hints
310 * hint.[dev].[unit].macaddr
311 */
312 if (!resource_string_value(device_get_name(dev),
313 device_get_unit(dev), "macaddr", (const char **)&var)) {
314 if(!macaddr_atoi(var, mac)) {
315 printf("%s: use %s macaddr from hints\n",
316 device_get_nameunit(dev), var);
317 return (0);
318 }
319 }
320
321 #ifdef USE_GENERATED_MAC_ADDRESS
322 generate_mac(mac);
323
324 device_printf(dev, "use generated %02x:%02x:%02x:%02x:%02x:%02x "
325 "macaddr\n", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
326 #else
327 /* Hardcoded */
328 mac[0] = 0x00;
329 mac[1] = 0x18;
330 mac[2] = 0xe7;
331 mac[3] = 0xd5;
332 mac[4] = 0x83;
333 mac[5] = 0x90;
334
335 device_printf(dev, "use hardcoded 00:18:e7:d5:83:90 macaddr\n");
336 #endif
337
338 return (0);
339 }
340
341 /*
342 * Reset hardware
343 */
344 static void
reset_freng(struct rt_softc * sc)345 reset_freng(struct rt_softc *sc)
346 {
347 /* XXX hard reset kills everything so skip it ... */
348 return;
349 }
350
351 static int
rt_attach(device_t dev)352 rt_attach(device_t dev)
353 {
354 struct rt_softc *sc;
355 struct ifnet *ifp;
356 int error, i;
357 #ifdef FDT
358 phandle_t node;
359 char fdtval[32];
360 #endif
361
362 sc = device_get_softc(dev);
363 sc->dev = dev;
364
365 #ifdef FDT
366 node = ofw_bus_get_node(sc->dev);
367 #endif
368
369 mtx_init(&sc->lock, device_get_nameunit(dev), MTX_NETWORK_LOCK,
370 MTX_DEF | MTX_RECURSE);
371
372 sc->mem_rid = 0;
373 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
374 RF_ACTIVE | RF_SHAREABLE);
375 if (sc->mem == NULL) {
376 device_printf(dev, "could not allocate memory resource\n");
377 error = ENXIO;
378 goto fail;
379 }
380
381 sc->bst = rman_get_bustag(sc->mem);
382 sc->bsh = rman_get_bushandle(sc->mem);
383
384 sc->irq_rid = 0;
385 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid,
386 RF_ACTIVE);
387 if (sc->irq == NULL) {
388 device_printf(dev,
389 "could not allocate interrupt resource\n");
390 error = ENXIO;
391 goto fail;
392 }
393
394 #ifdef IF_RT_DEBUG
395 sc->debug = rt_debug;
396
397 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
398 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
399 "debug", CTLFLAG_RW, &sc->debug, 0, "rt debug level");
400 #endif
401
402 /* Reset hardware */
403 reset_freng(sc);
404
405 if (sc->rt_chipid == RT_CHIPID_MT7620) {
406 sc->csum_fail_ip = MT7620_RXD_SRC_IP_CSUM_FAIL;
407 sc->csum_fail_l4 = MT7620_RXD_SRC_L4_CSUM_FAIL;
408 } else if (sc->rt_chipid == RT_CHIPID_MT7621) {
409 sc->csum_fail_ip = MT7621_RXD_SRC_IP_CSUM_FAIL;
410 sc->csum_fail_l4 = MT7621_RXD_SRC_L4_CSUM_FAIL;
411 } else {
412 sc->csum_fail_ip = RT305X_RXD_SRC_IP_CSUM_FAIL;
413 sc->csum_fail_l4 = RT305X_RXD_SRC_L4_CSUM_FAIL;
414 }
415
416 /* Fill in soc-specific registers map */
417 switch(sc->rt_chipid) {
418 case RT_CHIPID_MT7620:
419 case RT_CHIPID_MT7621:
420 sc->gdma1_base = MT7620_GDMA1_BASE;
421 /* fallthrough */
422 case RT_CHIPID_RT5350:
423 device_printf(dev, "%cT%x Ethernet MAC (rev 0x%08x)\n",
424 sc->rt_chipid >= 0x7600 ? 'M' : 'R',
425 sc->rt_chipid, sc->mac_rev);
426 /* RT5350: No GDMA, PSE, CDMA, PPE */
427 RT_WRITE(sc, GE_PORT_BASE + 0x0C00, // UDPCS, TCPCS, IPCS=1
428 RT_READ(sc, GE_PORT_BASE + 0x0C00) | (0x7<<16));
429 sc->delay_int_cfg=RT5350_PDMA_BASE+RT5350_DELAY_INT_CFG;
430 sc->fe_int_status=RT5350_FE_INT_STATUS;
431 sc->fe_int_enable=RT5350_FE_INT_ENABLE;
432 sc->pdma_glo_cfg=RT5350_PDMA_BASE+RT5350_PDMA_GLO_CFG;
433 sc->pdma_rst_idx=RT5350_PDMA_BASE+RT5350_PDMA_RST_IDX;
434 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) {
435 sc->tx_base_ptr[i]=RT5350_PDMA_BASE+RT5350_TX_BASE_PTR(i);
436 sc->tx_max_cnt[i]=RT5350_PDMA_BASE+RT5350_TX_MAX_CNT(i);
437 sc->tx_ctx_idx[i]=RT5350_PDMA_BASE+RT5350_TX_CTX_IDX(i);
438 sc->tx_dtx_idx[i]=RT5350_PDMA_BASE+RT5350_TX_DTX_IDX(i);
439 }
440 sc->rx_ring_count=2;
441 sc->rx_base_ptr[0]=RT5350_PDMA_BASE+RT5350_RX_BASE_PTR0;
442 sc->rx_max_cnt[0]=RT5350_PDMA_BASE+RT5350_RX_MAX_CNT0;
443 sc->rx_calc_idx[0]=RT5350_PDMA_BASE+RT5350_RX_CALC_IDX0;
444 sc->rx_drx_idx[0]=RT5350_PDMA_BASE+RT5350_RX_DRX_IDX0;
445 sc->rx_base_ptr[1]=RT5350_PDMA_BASE+RT5350_RX_BASE_PTR1;
446 sc->rx_max_cnt[1]=RT5350_PDMA_BASE+RT5350_RX_MAX_CNT1;
447 sc->rx_calc_idx[1]=RT5350_PDMA_BASE+RT5350_RX_CALC_IDX1;
448 sc->rx_drx_idx[1]=RT5350_PDMA_BASE+RT5350_RX_DRX_IDX1;
449 sc->int_rx_done_mask=RT5350_INT_RXQ0_DONE;
450 sc->int_tx_done_mask=RT5350_INT_TXQ0_DONE;
451 break;
452 default:
453 device_printf(dev, "RT305XF Ethernet MAC (rev 0x%08x)\n",
454 sc->mac_rev);
455 sc->gdma1_base = GDMA1_BASE;
456 sc->delay_int_cfg=PDMA_BASE+DELAY_INT_CFG;
457 sc->fe_int_status=GE_PORT_BASE+FE_INT_STATUS;
458 sc->fe_int_enable=GE_PORT_BASE+FE_INT_ENABLE;
459 sc->pdma_glo_cfg=PDMA_BASE+PDMA_GLO_CFG;
460 sc->pdma_rst_idx=PDMA_BASE+PDMA_RST_IDX;
461 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) {
462 sc->tx_base_ptr[i]=PDMA_BASE+TX_BASE_PTR(i);
463 sc->tx_max_cnt[i]=PDMA_BASE+TX_MAX_CNT(i);
464 sc->tx_ctx_idx[i]=PDMA_BASE+TX_CTX_IDX(i);
465 sc->tx_dtx_idx[i]=PDMA_BASE+TX_DTX_IDX(i);
466 }
467 sc->rx_ring_count=1;
468 sc->rx_base_ptr[0]=PDMA_BASE+RX_BASE_PTR0;
469 sc->rx_max_cnt[0]=PDMA_BASE+RX_MAX_CNT0;
470 sc->rx_calc_idx[0]=PDMA_BASE+RX_CALC_IDX0;
471 sc->rx_drx_idx[0]=PDMA_BASE+RX_DRX_IDX0;
472 sc->int_rx_done_mask=INT_RX_DONE;
473 sc->int_tx_done_mask=INT_TXQ0_DONE;
474 }
475
476 if (sc->gdma1_base != 0)
477 RT_WRITE(sc, sc->gdma1_base + GDMA_FWD_CFG,
478 (
479 GDM_ICS_EN | /* Enable IP Csum */
480 GDM_TCS_EN | /* Enable TCP Csum */
481 GDM_UCS_EN | /* Enable UDP Csum */
482 GDM_STRPCRC | /* Strip CRC from packet */
483 GDM_DST_PORT_CPU << GDM_UFRC_P_SHIFT | /* fwd UCast to CPU */
484 GDM_DST_PORT_CPU << GDM_BFRC_P_SHIFT | /* fwd BCast to CPU */
485 GDM_DST_PORT_CPU << GDM_MFRC_P_SHIFT | /* fwd MCast to CPU */
486 GDM_DST_PORT_CPU << GDM_OFRC_P_SHIFT /* fwd Other to CPU */
487 ));
488
489 #ifdef FDT
490 if (sc->rt_chipid == RT_CHIPID_RT2880 ||
491 sc->rt_chipid == RT_CHIPID_RT3883) {
492 if (OF_getprop(node, "port-mode", fdtval, sizeof(fdtval)) > 0 &&
493 strcmp(fdtval, "gigasw") == 0)
494 RT_WRITE(sc, MDIO_CFG, MDIO_2880_GIGA_INIT);
495 else
496 RT_WRITE(sc, MDIO_CFG, MDIO_2880_100T_INIT);
497 }
498 #endif
499
500 /* allocate Tx and Rx rings */
501 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) {
502 error = rt_alloc_tx_ring(sc, &sc->tx_ring[i], i);
503 if (error != 0) {
504 device_printf(dev, "could not allocate Tx ring #%d\n",
505 i);
506 goto fail;
507 }
508 }
509
510 sc->tx_ring_mgtqid = 5;
511 for (i = 0; i < sc->rx_ring_count; i++) {
512 error = rt_alloc_rx_ring(sc, &sc->rx_ring[i], i);
513 if (error != 0) {
514 device_printf(dev, "could not allocate Rx ring\n");
515 goto fail;
516 }
517 }
518
519 callout_init(&sc->periodic_ch, 0);
520 callout_init_mtx(&sc->tx_watchdog_ch, &sc->lock, 0);
521
522 ifp = sc->ifp = if_alloc(IFT_ETHER);
523 if (ifp == NULL) {
524 device_printf(dev, "could not if_alloc()\n");
525 error = ENOMEM;
526 goto fail;
527 }
528
529 ifp->if_softc = sc;
530 if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev));
531 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
532 ifp->if_init = rt_init;
533 ifp->if_ioctl = rt_ioctl;
534 ifp->if_start = rt_start;
535 #define RT_TX_QLEN 256
536
537 IFQ_SET_MAXLEN(&ifp->if_snd, RT_TX_QLEN);
538 ifp->if_snd.ifq_drv_maxlen = RT_TX_QLEN;
539 IFQ_SET_READY(&ifp->if_snd);
540
541 #ifdef IF_RT_PHY_SUPPORT
542 error = mii_attach(dev, &sc->rt_miibus, ifp, rt_ifmedia_upd,
543 rt_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
544 if (error != 0) {
545 device_printf(dev, "attaching PHYs failed\n");
546 error = ENXIO;
547 goto fail;
548 }
549 #else
550 ifmedia_init(&sc->rt_ifmedia, 0, rt_ifmedia_upd, rt_ifmedia_sts);
551 ifmedia_add(&sc->rt_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 0,
552 NULL);
553 ifmedia_set(&sc->rt_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX);
554
555 #endif /* IF_RT_PHY_SUPPORT */
556
557 ether_request_mac(dev, sc->mac_addr);
558 ether_ifattach(ifp, sc->mac_addr);
559
560 /*
561 * Tell the upper layer(s) we support long frames.
562 */
563 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
564 ifp->if_capabilities |= IFCAP_VLAN_MTU;
565 ifp->if_capenable |= IFCAP_VLAN_MTU;
566 ifp->if_capabilities |= IFCAP_RXCSUM|IFCAP_TXCSUM;
567 ifp->if_capenable |= IFCAP_RXCSUM|IFCAP_TXCSUM;
568
569 /* init task queue */
570 NET_TASK_INIT(&sc->rx_done_task, 0, rt_rx_done_task, sc);
571 TASK_INIT(&sc->tx_done_task, 0, rt_tx_done_task, sc);
572 TASK_INIT(&sc->periodic_task, 0, rt_periodic_task, sc);
573
574 sc->rx_process_limit = 100;
575
576 sc->taskqueue = taskqueue_create("rt_taskq", M_NOWAIT,
577 taskqueue_thread_enqueue, &sc->taskqueue);
578
579 taskqueue_start_threads(&sc->taskqueue, 1, PI_NET, "%s taskq",
580 device_get_nameunit(sc->dev));
581
582 rt_sysctl_attach(sc);
583
584 /* set up interrupt */
585 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE,
586 NULL, (sc->rt_chipid == RT_CHIPID_RT5350 ||
587 sc->rt_chipid == RT_CHIPID_MT7620 ||
588 sc->rt_chipid == RT_CHIPID_MT7621) ? rt_rt5350_intr : rt_intr,
589 sc, &sc->irqh);
590 if (error != 0) {
591 printf("%s: could not set up interrupt\n",
592 device_get_nameunit(dev));
593 goto fail;
594 }
595 #ifdef IF_RT_DEBUG
596 device_printf(dev, "debug var at %#08x\n", (u_int)&(sc->debug));
597 #endif
598
599 return (0);
600
601 fail:
602 /* free Tx and Rx rings */
603 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++)
604 rt_free_tx_ring(sc, &sc->tx_ring[i]);
605
606 for (i = 0; i < sc->rx_ring_count; i++)
607 rt_free_rx_ring(sc, &sc->rx_ring[i]);
608
609 mtx_destroy(&sc->lock);
610
611 if (sc->mem != NULL)
612 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid,
613 sc->mem);
614
615 if (sc->irq != NULL)
616 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid,
617 sc->irq);
618
619 return (error);
620 }
621
622 /*
623 * Set media options.
624 */
625 static int
rt_ifmedia_upd(struct ifnet * ifp)626 rt_ifmedia_upd(struct ifnet *ifp)
627 {
628 struct rt_softc *sc;
629 #ifdef IF_RT_PHY_SUPPORT
630 struct mii_data *mii;
631 struct mii_softc *miisc;
632 int error = 0;
633
634 sc = ifp->if_softc;
635 RT_SOFTC_LOCK(sc);
636
637 mii = device_get_softc(sc->rt_miibus);
638 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
639 PHY_RESET(miisc);
640 error = mii_mediachg(mii);
641 RT_SOFTC_UNLOCK(sc);
642
643 return (error);
644
645 #else /* !IF_RT_PHY_SUPPORT */
646
647 struct ifmedia *ifm;
648 struct ifmedia_entry *ife;
649
650 sc = ifp->if_softc;
651 ifm = &sc->rt_ifmedia;
652 ife = ifm->ifm_cur;
653
654 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
655 return (EINVAL);
656
657 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
658 device_printf(sc->dev,
659 "AUTO is not supported for multiphy MAC");
660 return (EINVAL);
661 }
662
663 /*
664 * Ignore everything
665 */
666 return (0);
667 #endif /* IF_RT_PHY_SUPPORT */
668 }
669
670 /*
671 * Report current media status.
672 */
673 static void
rt_ifmedia_sts(struct ifnet * ifp,struct ifmediareq * ifmr)674 rt_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
675 {
676 #ifdef IF_RT_PHY_SUPPORT
677 struct rt_softc *sc;
678 struct mii_data *mii;
679
680 sc = ifp->if_softc;
681
682 RT_SOFTC_LOCK(sc);
683 mii = device_get_softc(sc->rt_miibus);
684 mii_pollstat(mii);
685 ifmr->ifm_active = mii->mii_media_active;
686 ifmr->ifm_status = mii->mii_media_status;
687 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
688 ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE;
689 RT_SOFTC_UNLOCK(sc);
690 #else /* !IF_RT_PHY_SUPPORT */
691
692 ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE;
693 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
694 #endif /* IF_RT_PHY_SUPPORT */
695 }
696
697 static int
rt_detach(device_t dev)698 rt_detach(device_t dev)
699 {
700 struct rt_softc *sc;
701 struct ifnet *ifp;
702 int i;
703
704 sc = device_get_softc(dev);
705 ifp = sc->ifp;
706
707 RT_DPRINTF(sc, RT_DEBUG_ANY, "detaching\n");
708
709 RT_SOFTC_LOCK(sc);
710
711 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
712
713 callout_stop(&sc->periodic_ch);
714 callout_stop(&sc->tx_watchdog_ch);
715
716 taskqueue_drain(sc->taskqueue, &sc->rx_done_task);
717 taskqueue_drain(sc->taskqueue, &sc->tx_done_task);
718 taskqueue_drain(sc->taskqueue, &sc->periodic_task);
719
720 /* free Tx and Rx rings */
721 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++)
722 rt_free_tx_ring(sc, &sc->tx_ring[i]);
723 for (i = 0; i < sc->rx_ring_count; i++)
724 rt_free_rx_ring(sc, &sc->rx_ring[i]);
725
726 RT_SOFTC_UNLOCK(sc);
727
728 #ifdef IF_RT_PHY_SUPPORT
729 if (sc->rt_miibus != NULL)
730 device_delete_child(dev, sc->rt_miibus);
731 #endif
732
733 ether_ifdetach(ifp);
734 if_free(ifp);
735
736 taskqueue_free(sc->taskqueue);
737
738 mtx_destroy(&sc->lock);
739
740 bus_generic_detach(dev);
741 bus_teardown_intr(dev, sc->irq, sc->irqh);
742 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, sc->irq);
743 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem);
744
745 return (0);
746 }
747
748 static int
rt_shutdown(device_t dev)749 rt_shutdown(device_t dev)
750 {
751 struct rt_softc *sc;
752
753 sc = device_get_softc(dev);
754 RT_DPRINTF(sc, RT_DEBUG_ANY, "shutting down\n");
755 rt_stop(sc);
756
757 return (0);
758 }
759
760 static int
rt_suspend(device_t dev)761 rt_suspend(device_t dev)
762 {
763 struct rt_softc *sc;
764
765 sc = device_get_softc(dev);
766 RT_DPRINTF(sc, RT_DEBUG_ANY, "suspending\n");
767 rt_stop(sc);
768
769 return (0);
770 }
771
772 static int
rt_resume(device_t dev)773 rt_resume(device_t dev)
774 {
775 struct rt_softc *sc;
776 struct ifnet *ifp;
777
778 sc = device_get_softc(dev);
779 ifp = sc->ifp;
780
781 RT_DPRINTF(sc, RT_DEBUG_ANY, "resuming\n");
782
783 if (ifp->if_flags & IFF_UP)
784 rt_init(sc);
785
786 return (0);
787 }
788
789 /*
790 * rt_init_locked - Run initialization process having locked mtx.
791 */
792 static void
rt_init_locked(void * priv)793 rt_init_locked(void *priv)
794 {
795 struct rt_softc *sc;
796 struct ifnet *ifp;
797 #ifdef IF_RT_PHY_SUPPORT
798 struct mii_data *mii;
799 #endif
800 int i, ntries;
801 uint32_t tmp;
802
803 sc = priv;
804 ifp = sc->ifp;
805 #ifdef IF_RT_PHY_SUPPORT
806 mii = device_get_softc(sc->rt_miibus);
807 #endif
808
809 RT_DPRINTF(sc, RT_DEBUG_ANY, "initializing\n");
810
811 RT_SOFTC_ASSERT_LOCKED(sc);
812
813 /* hardware reset */
814 //RT_WRITE(sc, GE_PORT_BASE + FE_RST_GLO, PSE_RESET);
815 //rt305x_sysctl_set(SYSCTL_RSTCTRL, SYSCTL_RSTCTRL_FRENG);
816
817 /* Fwd to CPU (uni|broad|multi)cast and Unknown */
818 if (sc->gdma1_base != 0)
819 RT_WRITE(sc, sc->gdma1_base + GDMA_FWD_CFG,
820 (
821 GDM_ICS_EN | /* Enable IP Csum */
822 GDM_TCS_EN | /* Enable TCP Csum */
823 GDM_UCS_EN | /* Enable UDP Csum */
824 GDM_STRPCRC | /* Strip CRC from packet */
825 GDM_DST_PORT_CPU << GDM_UFRC_P_SHIFT | /* fwd UCast to CPU */
826 GDM_DST_PORT_CPU << GDM_BFRC_P_SHIFT | /* fwd BCast to CPU */
827 GDM_DST_PORT_CPU << GDM_MFRC_P_SHIFT | /* fwd MCast to CPU */
828 GDM_DST_PORT_CPU << GDM_OFRC_P_SHIFT /* fwd Other to CPU */
829 ));
830
831 /* disable DMA engine */
832 RT_WRITE(sc, sc->pdma_glo_cfg, 0);
833 RT_WRITE(sc, sc->pdma_rst_idx, 0xffffffff);
834
835 /* wait while DMA engine is busy */
836 for (ntries = 0; ntries < 100; ntries++) {
837 tmp = RT_READ(sc, sc->pdma_glo_cfg);
838 if (!(tmp & (FE_TX_DMA_BUSY | FE_RX_DMA_BUSY)))
839 break;
840 DELAY(1000);
841 }
842
843 if (ntries == 100) {
844 device_printf(sc->dev, "timeout waiting for DMA engine\n");
845 goto fail;
846 }
847
848 /* reset Rx and Tx rings */
849 tmp = FE_RST_DRX_IDX0 |
850 FE_RST_DTX_IDX3 |
851 FE_RST_DTX_IDX2 |
852 FE_RST_DTX_IDX1 |
853 FE_RST_DTX_IDX0;
854
855 RT_WRITE(sc, sc->pdma_rst_idx, tmp);
856
857 /* XXX switch set mac address */
858 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++)
859 rt_reset_tx_ring(sc, &sc->tx_ring[i]);
860
861 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) {
862 /* update TX_BASE_PTRx */
863 RT_WRITE(sc, sc->tx_base_ptr[i],
864 sc->tx_ring[i].desc_phys_addr);
865 RT_WRITE(sc, sc->tx_max_cnt[i],
866 RT_SOFTC_TX_RING_DESC_COUNT);
867 RT_WRITE(sc, sc->tx_ctx_idx[i], 0);
868 }
869
870 /* init Rx ring */
871 for (i = 0; i < sc->rx_ring_count; i++)
872 rt_reset_rx_ring(sc, &sc->rx_ring[i]);
873
874 /* update RX_BASE_PTRx */
875 for (i = 0; i < sc->rx_ring_count; i++) {
876 RT_WRITE(sc, sc->rx_base_ptr[i],
877 sc->rx_ring[i].desc_phys_addr);
878 RT_WRITE(sc, sc->rx_max_cnt[i],
879 RT_SOFTC_RX_RING_DATA_COUNT);
880 RT_WRITE(sc, sc->rx_calc_idx[i],
881 RT_SOFTC_RX_RING_DATA_COUNT - 1);
882 }
883
884 /* write back DDONE, 16byte burst enable RX/TX DMA */
885 tmp = FE_TX_WB_DDONE | FE_DMA_BT_SIZE16 | FE_RX_DMA_EN | FE_TX_DMA_EN;
886 if (sc->rt_chipid == RT_CHIPID_MT7620 ||
887 sc->rt_chipid == RT_CHIPID_MT7621)
888 tmp |= (1<<31);
889 RT_WRITE(sc, sc->pdma_glo_cfg, tmp);
890
891 /* disable interrupts mitigation */
892 RT_WRITE(sc, sc->delay_int_cfg, 0);
893
894 /* clear pending interrupts */
895 RT_WRITE(sc, sc->fe_int_status, 0xffffffff);
896
897 /* enable interrupts */
898 if (sc->rt_chipid == RT_CHIPID_RT5350 ||
899 sc->rt_chipid == RT_CHIPID_MT7620 ||
900 sc->rt_chipid == RT_CHIPID_MT7621)
901 tmp = RT5350_INT_TX_COHERENT |
902 RT5350_INT_RX_COHERENT |
903 RT5350_INT_TXQ3_DONE |
904 RT5350_INT_TXQ2_DONE |
905 RT5350_INT_TXQ1_DONE |
906 RT5350_INT_TXQ0_DONE |
907 RT5350_INT_RXQ1_DONE |
908 RT5350_INT_RXQ0_DONE;
909 else
910 tmp = CNT_PPE_AF |
911 CNT_GDM_AF |
912 PSE_P2_FC |
913 GDM_CRC_DROP |
914 PSE_BUF_DROP |
915 GDM_OTHER_DROP |
916 PSE_P1_FC |
917 PSE_P0_FC |
918 PSE_FQ_EMPTY |
919 INT_TX_COHERENT |
920 INT_RX_COHERENT |
921 INT_TXQ3_DONE |
922 INT_TXQ2_DONE |
923 INT_TXQ1_DONE |
924 INT_TXQ0_DONE |
925 INT_RX_DONE;
926
927 sc->intr_enable_mask = tmp;
928
929 RT_WRITE(sc, sc->fe_int_enable, tmp);
930
931 if (rt_txrx_enable(sc) != 0)
932 goto fail;
933
934 #ifdef IF_RT_PHY_SUPPORT
935 if (mii) mii_mediachg(mii);
936 #endif /* IF_RT_PHY_SUPPORT */
937
938 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
939 ifp->if_drv_flags |= IFF_DRV_RUNNING;
940
941 sc->periodic_round = 0;
942
943 callout_reset(&sc->periodic_ch, hz / 10, rt_periodic, sc);
944
945 return;
946
947 fail:
948 rt_stop_locked(sc);
949 }
950
951 /*
952 * rt_init - lock and initialize device.
953 */
954 static void
rt_init(void * priv)955 rt_init(void *priv)
956 {
957 struct rt_softc *sc;
958
959 sc = priv;
960 RT_SOFTC_LOCK(sc);
961 rt_init_locked(sc);
962 RT_SOFTC_UNLOCK(sc);
963 }
964
965 /*
966 * rt_stop_locked - stop TX/RX w/ lock
967 */
968 static void
rt_stop_locked(void * priv)969 rt_stop_locked(void *priv)
970 {
971 struct rt_softc *sc;
972 struct ifnet *ifp;
973
974 sc = priv;
975 ifp = sc->ifp;
976
977 RT_DPRINTF(sc, RT_DEBUG_ANY, "stopping\n");
978
979 RT_SOFTC_ASSERT_LOCKED(sc);
980 sc->tx_timer = 0;
981 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
982 callout_stop(&sc->periodic_ch);
983 callout_stop(&sc->tx_watchdog_ch);
984 RT_SOFTC_UNLOCK(sc);
985 taskqueue_block(sc->taskqueue);
986
987 /*
988 * Sometime rt_stop_locked called from isr and we get panic
989 * When found, I fix it
990 */
991 #ifdef notyet
992 taskqueue_drain(sc->taskqueue, &sc->rx_done_task);
993 taskqueue_drain(sc->taskqueue, &sc->tx_done_task);
994 taskqueue_drain(sc->taskqueue, &sc->periodic_task);
995 #endif
996 RT_SOFTC_LOCK(sc);
997
998 /* disable interrupts */
999 RT_WRITE(sc, sc->fe_int_enable, 0);
1000
1001 if(sc->rt_chipid != RT_CHIPID_RT5350 &&
1002 sc->rt_chipid != RT_CHIPID_MT7620 &&
1003 sc->rt_chipid != RT_CHIPID_MT7621) {
1004 /* reset adapter */
1005 RT_WRITE(sc, GE_PORT_BASE + FE_RST_GLO, PSE_RESET);
1006 }
1007
1008 if (sc->gdma1_base != 0)
1009 RT_WRITE(sc, sc->gdma1_base + GDMA_FWD_CFG,
1010 (
1011 GDM_ICS_EN | /* Enable IP Csum */
1012 GDM_TCS_EN | /* Enable TCP Csum */
1013 GDM_UCS_EN | /* Enable UDP Csum */
1014 GDM_STRPCRC | /* Strip CRC from packet */
1015 GDM_DST_PORT_CPU << GDM_UFRC_P_SHIFT | /* fwd UCast to CPU */
1016 GDM_DST_PORT_CPU << GDM_BFRC_P_SHIFT | /* fwd BCast to CPU */
1017 GDM_DST_PORT_CPU << GDM_MFRC_P_SHIFT | /* fwd MCast to CPU */
1018 GDM_DST_PORT_CPU << GDM_OFRC_P_SHIFT /* fwd Other to CPU */
1019 ));
1020 }
1021
1022 static void
rt_stop(void * priv)1023 rt_stop(void *priv)
1024 {
1025 struct rt_softc *sc;
1026
1027 sc = priv;
1028 RT_SOFTC_LOCK(sc);
1029 rt_stop_locked(sc);
1030 RT_SOFTC_UNLOCK(sc);
1031 }
1032
1033 /*
1034 * rt_tx_data - transmit packet.
1035 */
1036 static int
rt_tx_data(struct rt_softc * sc,struct mbuf * m,int qid)1037 rt_tx_data(struct rt_softc *sc, struct mbuf *m, int qid)
1038 {
1039 struct ifnet *ifp;
1040 struct rt_softc_tx_ring *ring;
1041 struct rt_softc_tx_data *data;
1042 struct rt_txdesc *desc;
1043 struct mbuf *m_d;
1044 bus_dma_segment_t dma_seg[RT_SOFTC_MAX_SCATTER];
1045 int error, ndmasegs, ndescs, i;
1046
1047 KASSERT(qid >= 0 && qid < RT_SOFTC_TX_RING_COUNT,
1048 ("%s: Tx data: invalid qid=%d\n",
1049 device_get_nameunit(sc->dev), qid));
1050
1051 RT_SOFTC_TX_RING_ASSERT_LOCKED(&sc->tx_ring[qid]);
1052
1053 ifp = sc->ifp;
1054 ring = &sc->tx_ring[qid];
1055 desc = &ring->desc[ring->desc_cur];
1056 data = &ring->data[ring->data_cur];
1057
1058 error = bus_dmamap_load_mbuf_sg(ring->data_dma_tag, data->dma_map, m,
1059 dma_seg, &ndmasegs, 0);
1060 if (error != 0) {
1061 /* too many fragments, linearize */
1062
1063 RT_DPRINTF(sc, RT_DEBUG_TX,
1064 "could not load mbuf DMA map, trying to linearize "
1065 "mbuf: ndmasegs=%d, len=%d, error=%d\n",
1066 ndmasegs, m->m_pkthdr.len, error);
1067
1068 m_d = m_collapse(m, M_NOWAIT, 16);
1069 if (m_d == NULL) {
1070 m_freem(m);
1071 m = NULL;
1072 return (ENOMEM);
1073 }
1074 m = m_d;
1075
1076 sc->tx_defrag_packets++;
1077
1078 error = bus_dmamap_load_mbuf_sg(ring->data_dma_tag,
1079 data->dma_map, m, dma_seg, &ndmasegs, 0);
1080 if (error != 0) {
1081 device_printf(sc->dev, "could not load mbuf DMA map: "
1082 "ndmasegs=%d, len=%d, error=%d\n",
1083 ndmasegs, m->m_pkthdr.len, error);
1084 m_freem(m);
1085 return (error);
1086 }
1087 }
1088
1089 if (m->m_pkthdr.len == 0)
1090 ndmasegs = 0;
1091
1092 /* determine how many Tx descs are required */
1093 ndescs = 1 + ndmasegs / 2;
1094 if ((ring->desc_queued + ndescs) >
1095 (RT_SOFTC_TX_RING_DESC_COUNT - 2)) {
1096 RT_DPRINTF(sc, RT_DEBUG_TX,
1097 "there are not enough Tx descs\n");
1098
1099 sc->no_tx_desc_avail++;
1100
1101 bus_dmamap_unload(ring->data_dma_tag, data->dma_map);
1102 m_freem(m);
1103 return (EFBIG);
1104 }
1105
1106 data->m = m;
1107
1108 /* set up Tx descs */
1109 for (i = 0; i < ndmasegs; i += 2) {
1110 /* TODO: this needs to be refined as MT7620 for example has
1111 * a different word3 layout than RT305x and RT5350 (the last
1112 * one doesn't use word3 at all). And so does MT7621...
1113 */
1114
1115 if (sc->rt_chipid != RT_CHIPID_MT7621) {
1116 /* Set destination */
1117 if (sc->rt_chipid != RT_CHIPID_MT7620)
1118 desc->dst = (TXDSCR_DST_PORT_GDMA1);
1119
1120 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
1121 desc->dst |= (TXDSCR_IP_CSUM_GEN |
1122 TXDSCR_UDP_CSUM_GEN | TXDSCR_TCP_CSUM_GEN);
1123 /* Set queue id */
1124 desc->qn = qid;
1125 /* No PPPoE */
1126 desc->pppoe = 0;
1127 /* No VLAN */
1128 desc->vid = 0;
1129 } else {
1130 desc->vid = 0;
1131 desc->pppoe = 0;
1132 desc->qn = 0;
1133 desc->dst = 2;
1134 }
1135
1136 desc->sdp0 = htole32(dma_seg[i].ds_addr);
1137 desc->sdl0 = htole16(dma_seg[i].ds_len |
1138 ( ((i+1) == ndmasegs )?RT_TXDESC_SDL0_LASTSEG:0 ));
1139
1140 if ((i+1) < ndmasegs) {
1141 desc->sdp1 = htole32(dma_seg[i+1].ds_addr);
1142 desc->sdl1 = htole16(dma_seg[i+1].ds_len |
1143 ( ((i+2) == ndmasegs )?RT_TXDESC_SDL1_LASTSEG:0 ));
1144 } else {
1145 desc->sdp1 = 0;
1146 desc->sdl1 = 0;
1147 }
1148
1149 if ((i+2) < ndmasegs) {
1150 ring->desc_queued++;
1151 ring->desc_cur = (ring->desc_cur + 1) %
1152 RT_SOFTC_TX_RING_DESC_COUNT;
1153 }
1154 desc = &ring->desc[ring->desc_cur];
1155 }
1156
1157 RT_DPRINTF(sc, RT_DEBUG_TX, "sending data: len=%d, ndmasegs=%d, "
1158 "DMA ds_len=%d/%d/%d/%d/%d\n",
1159 m->m_pkthdr.len, ndmasegs,
1160 (int) dma_seg[0].ds_len,
1161 (int) dma_seg[1].ds_len,
1162 (int) dma_seg[2].ds_len,
1163 (int) dma_seg[3].ds_len,
1164 (int) dma_seg[4].ds_len);
1165
1166 bus_dmamap_sync(ring->seg0_dma_tag, ring->seg0_dma_map,
1167 BUS_DMASYNC_PREWRITE);
1168 bus_dmamap_sync(ring->data_dma_tag, data->dma_map,
1169 BUS_DMASYNC_PREWRITE);
1170 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
1171 BUS_DMASYNC_PREWRITE);
1172
1173 ring->desc_queued++;
1174 ring->desc_cur = (ring->desc_cur + 1) % RT_SOFTC_TX_RING_DESC_COUNT;
1175
1176 ring->data_queued++;
1177 ring->data_cur = (ring->data_cur + 1) % RT_SOFTC_TX_RING_DATA_COUNT;
1178
1179 /* kick Tx */
1180 RT_WRITE(sc, sc->tx_ctx_idx[qid], ring->desc_cur);
1181
1182 return (0);
1183 }
1184
1185 /*
1186 * rt_start - start Transmit/Receive
1187 */
1188 static void
rt_start(struct ifnet * ifp)1189 rt_start(struct ifnet *ifp)
1190 {
1191 struct rt_softc *sc;
1192 struct mbuf *m;
1193 int qid = 0 /* XXX must check QoS priority */;
1194
1195 sc = ifp->if_softc;
1196
1197 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1198 return;
1199
1200 for (;;) {
1201 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
1202 if (m == NULL)
1203 break;
1204
1205 m->m_pkthdr.rcvif = NULL;
1206
1207 RT_SOFTC_TX_RING_LOCK(&sc->tx_ring[qid]);
1208
1209 if (sc->tx_ring[qid].data_queued >=
1210 RT_SOFTC_TX_RING_DATA_COUNT) {
1211 RT_SOFTC_TX_RING_UNLOCK(&sc->tx_ring[qid]);
1212
1213 RT_DPRINTF(sc, RT_DEBUG_TX,
1214 "if_start: Tx ring with qid=%d is full\n", qid);
1215
1216 m_freem(m);
1217
1218 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1219 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1220
1221 sc->tx_data_queue_full[qid]++;
1222
1223 break;
1224 }
1225
1226 if (rt_tx_data(sc, m, qid) != 0) {
1227 RT_SOFTC_TX_RING_UNLOCK(&sc->tx_ring[qid]);
1228
1229 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1230
1231 break;
1232 }
1233
1234 RT_SOFTC_TX_RING_UNLOCK(&sc->tx_ring[qid]);
1235 sc->tx_timer = RT_TX_WATCHDOG_TIMEOUT;
1236 callout_reset(&sc->tx_watchdog_ch, hz, rt_tx_watchdog, sc);
1237 }
1238 }
1239
1240 /*
1241 * rt_update_promisc - set/clear promiscuous mode. Unused yet, because
1242 * filtering done by attached Ethernet switch.
1243 */
1244 static void
rt_update_promisc(struct ifnet * ifp)1245 rt_update_promisc(struct ifnet *ifp)
1246 {
1247 struct rt_softc *sc;
1248
1249 sc = ifp->if_softc;
1250 printf("%s: %s promiscuous mode\n",
1251 device_get_nameunit(sc->dev),
1252 (ifp->if_flags & IFF_PROMISC) ? "entering" : "leaving");
1253 }
1254
1255 /*
1256 * rt_ioctl - ioctl handler.
1257 */
1258 static int
rt_ioctl(struct ifnet * ifp,u_long cmd,caddr_t data)1259 rt_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1260 {
1261 struct rt_softc *sc;
1262 struct ifreq *ifr;
1263 #ifdef IF_RT_PHY_SUPPORT
1264 struct mii_data *mii;
1265 #endif /* IF_RT_PHY_SUPPORT */
1266 int error, startall;
1267
1268 sc = ifp->if_softc;
1269 ifr = (struct ifreq *) data;
1270
1271 error = 0;
1272
1273 switch (cmd) {
1274 case SIOCSIFFLAGS:
1275 startall = 0;
1276 RT_SOFTC_LOCK(sc);
1277 if (ifp->if_flags & IFF_UP) {
1278 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1279 if ((ifp->if_flags ^ sc->if_flags) &
1280 IFF_PROMISC)
1281 rt_update_promisc(ifp);
1282 } else {
1283 rt_init_locked(sc);
1284 startall = 1;
1285 }
1286 } else {
1287 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1288 rt_stop_locked(sc);
1289 }
1290 sc->if_flags = ifp->if_flags;
1291 RT_SOFTC_UNLOCK(sc);
1292 break;
1293 case SIOCGIFMEDIA:
1294 case SIOCSIFMEDIA:
1295 #ifdef IF_RT_PHY_SUPPORT
1296 mii = device_get_softc(sc->rt_miibus);
1297 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1298 #else
1299 error = ifmedia_ioctl(ifp, ifr, &sc->rt_ifmedia, cmd);
1300 #endif /* IF_RT_PHY_SUPPORT */
1301 break;
1302 default:
1303 error = ether_ioctl(ifp, cmd, data);
1304 break;
1305 }
1306 return (error);
1307 }
1308
1309 /*
1310 * rt_periodic - Handler of PERIODIC interrupt
1311 */
1312 static void
rt_periodic(void * arg)1313 rt_periodic(void *arg)
1314 {
1315 struct rt_softc *sc;
1316
1317 sc = arg;
1318 RT_DPRINTF(sc, RT_DEBUG_PERIODIC, "periodic\n");
1319 taskqueue_enqueue(sc->taskqueue, &sc->periodic_task);
1320 }
1321
1322 /*
1323 * rt_tx_watchdog - Handler of TX Watchdog
1324 */
1325 static void
rt_tx_watchdog(void * arg)1326 rt_tx_watchdog(void *arg)
1327 {
1328 struct rt_softc *sc;
1329 struct ifnet *ifp;
1330
1331 sc = arg;
1332 ifp = sc->ifp;
1333
1334 if (sc->tx_timer == 0)
1335 return;
1336
1337 if (--sc->tx_timer == 0) {
1338 device_printf(sc->dev, "Tx watchdog timeout: resetting\n");
1339 #ifdef notyet
1340 /*
1341 * XXX: Commented out, because reset break input.
1342 */
1343 rt_stop_locked(sc);
1344 rt_init_locked(sc);
1345 #endif
1346 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1347 sc->tx_watchdog_timeouts++;
1348 }
1349 callout_reset(&sc->tx_watchdog_ch, hz, rt_tx_watchdog, sc);
1350 }
1351
1352 /*
1353 * rt_cnt_ppe_af - Handler of PPE Counter Table Almost Full interrupt
1354 */
1355 static void
rt_cnt_ppe_af(struct rt_softc * sc)1356 rt_cnt_ppe_af(struct rt_softc *sc)
1357 {
1358
1359 RT_DPRINTF(sc, RT_DEBUG_INTR, "PPE Counter Table Almost Full\n");
1360 }
1361
1362 /*
1363 * rt_cnt_gdm_af - Handler of GDMA 1 & 2 Counter Table Almost Full interrupt
1364 */
1365 static void
rt_cnt_gdm_af(struct rt_softc * sc)1366 rt_cnt_gdm_af(struct rt_softc *sc)
1367 {
1368
1369 RT_DPRINTF(sc, RT_DEBUG_INTR,
1370 "GDMA 1 & 2 Counter Table Almost Full\n");
1371 }
1372
1373 /*
1374 * rt_pse_p2_fc - Handler of PSE port2 (GDMA 2) flow control interrupt
1375 */
1376 static void
rt_pse_p2_fc(struct rt_softc * sc)1377 rt_pse_p2_fc(struct rt_softc *sc)
1378 {
1379
1380 RT_DPRINTF(sc, RT_DEBUG_INTR,
1381 "PSE port2 (GDMA 2) flow control asserted.\n");
1382 }
1383
1384 /*
1385 * rt_gdm_crc_drop - Handler of GDMA 1/2 discard a packet due to CRC error
1386 * interrupt
1387 */
1388 static void
rt_gdm_crc_drop(struct rt_softc * sc)1389 rt_gdm_crc_drop(struct rt_softc *sc)
1390 {
1391
1392 RT_DPRINTF(sc, RT_DEBUG_INTR,
1393 "GDMA 1 & 2 discard a packet due to CRC error\n");
1394 }
1395
1396 /*
1397 * rt_pse_buf_drop - Handler of buffer sharing limitation interrupt
1398 */
1399 static void
rt_pse_buf_drop(struct rt_softc * sc)1400 rt_pse_buf_drop(struct rt_softc *sc)
1401 {
1402
1403 RT_DPRINTF(sc, RT_DEBUG_INTR,
1404 "PSE discards a packet due to buffer sharing limitation\n");
1405 }
1406
1407 /*
1408 * rt_gdm_other_drop - Handler of discard on other reason interrupt
1409 */
1410 static void
rt_gdm_other_drop(struct rt_softc * sc)1411 rt_gdm_other_drop(struct rt_softc *sc)
1412 {
1413
1414 RT_DPRINTF(sc, RT_DEBUG_INTR,
1415 "GDMA 1 & 2 discard a packet due to other reason\n");
1416 }
1417
1418 /*
1419 * rt_pse_p1_fc - Handler of PSE port1 (GDMA 1) flow control interrupt
1420 */
1421 static void
rt_pse_p1_fc(struct rt_softc * sc)1422 rt_pse_p1_fc(struct rt_softc *sc)
1423 {
1424
1425 RT_DPRINTF(sc, RT_DEBUG_INTR,
1426 "PSE port1 (GDMA 1) flow control asserted.\n");
1427 }
1428
1429 /*
1430 * rt_pse_p0_fc - Handler of PSE port0 (CDMA) flow control interrupt
1431 */
1432 static void
rt_pse_p0_fc(struct rt_softc * sc)1433 rt_pse_p0_fc(struct rt_softc *sc)
1434 {
1435
1436 RT_DPRINTF(sc, RT_DEBUG_INTR,
1437 "PSE port0 (CDMA) flow control asserted.\n");
1438 }
1439
1440 /*
1441 * rt_pse_fq_empty - Handler of PSE free Q empty threshold reached interrupt
1442 */
1443 static void
rt_pse_fq_empty(struct rt_softc * sc)1444 rt_pse_fq_empty(struct rt_softc *sc)
1445 {
1446
1447 RT_DPRINTF(sc, RT_DEBUG_INTR,
1448 "PSE free Q empty threshold reached & forced drop "
1449 "condition occurred.\n");
1450 }
1451
1452 /*
1453 * rt_intr - main ISR
1454 */
1455 static void
rt_intr(void * arg)1456 rt_intr(void *arg)
1457 {
1458 struct rt_softc *sc;
1459 struct ifnet *ifp;
1460 uint32_t status;
1461
1462 sc = arg;
1463 ifp = sc->ifp;
1464
1465 /* acknowledge interrupts */
1466 status = RT_READ(sc, sc->fe_int_status);
1467 RT_WRITE(sc, sc->fe_int_status, status);
1468
1469 RT_DPRINTF(sc, RT_DEBUG_INTR, "interrupt: status=0x%08x\n", status);
1470
1471 if (status == 0xffffffff || /* device likely went away */
1472 status == 0) /* not for us */
1473 return;
1474
1475 sc->interrupts++;
1476
1477 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1478 return;
1479
1480 if (status & CNT_PPE_AF)
1481 rt_cnt_ppe_af(sc);
1482
1483 if (status & CNT_GDM_AF)
1484 rt_cnt_gdm_af(sc);
1485
1486 if (status & PSE_P2_FC)
1487 rt_pse_p2_fc(sc);
1488
1489 if (status & GDM_CRC_DROP)
1490 rt_gdm_crc_drop(sc);
1491
1492 if (status & PSE_BUF_DROP)
1493 rt_pse_buf_drop(sc);
1494
1495 if (status & GDM_OTHER_DROP)
1496 rt_gdm_other_drop(sc);
1497
1498 if (status & PSE_P1_FC)
1499 rt_pse_p1_fc(sc);
1500
1501 if (status & PSE_P0_FC)
1502 rt_pse_p0_fc(sc);
1503
1504 if (status & PSE_FQ_EMPTY)
1505 rt_pse_fq_empty(sc);
1506
1507 if (status & INT_TX_COHERENT)
1508 rt_tx_coherent_intr(sc);
1509
1510 if (status & INT_RX_COHERENT)
1511 rt_rx_coherent_intr(sc);
1512
1513 if (status & RX_DLY_INT)
1514 rt_rx_delay_intr(sc);
1515
1516 if (status & TX_DLY_INT)
1517 rt_tx_delay_intr(sc);
1518
1519 if (status & INT_RX_DONE)
1520 rt_rx_intr(sc, 0);
1521
1522 if (status & INT_TXQ3_DONE)
1523 rt_tx_intr(sc, 3);
1524
1525 if (status & INT_TXQ2_DONE)
1526 rt_tx_intr(sc, 2);
1527
1528 if (status & INT_TXQ1_DONE)
1529 rt_tx_intr(sc, 1);
1530
1531 if (status & INT_TXQ0_DONE)
1532 rt_tx_intr(sc, 0);
1533 }
1534
1535 /*
1536 * rt_rt5350_intr - main ISR for Ralink 5350 SoC
1537 */
1538 static void
rt_rt5350_intr(void * arg)1539 rt_rt5350_intr(void *arg)
1540 {
1541 struct rt_softc *sc;
1542 struct ifnet *ifp;
1543 uint32_t status;
1544
1545 sc = arg;
1546 ifp = sc->ifp;
1547
1548 /* acknowledge interrupts */
1549 status = RT_READ(sc, sc->fe_int_status);
1550 RT_WRITE(sc, sc->fe_int_status, status);
1551
1552 RT_DPRINTF(sc, RT_DEBUG_INTR, "interrupt: status=0x%08x\n", status);
1553
1554 if (status == 0xffffffff || /* device likely went away */
1555 status == 0) /* not for us */
1556 return;
1557
1558 sc->interrupts++;
1559
1560 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1561 return;
1562
1563 if (status & RT5350_INT_TX_COHERENT)
1564 rt_tx_coherent_intr(sc);
1565 if (status & RT5350_INT_RX_COHERENT)
1566 rt_rx_coherent_intr(sc);
1567 if (status & RT5350_RX_DLY_INT)
1568 rt_rx_delay_intr(sc);
1569 if (status & RT5350_TX_DLY_INT)
1570 rt_tx_delay_intr(sc);
1571 if (status & RT5350_INT_RXQ1_DONE)
1572 rt_rx_intr(sc, 1);
1573 if (status & RT5350_INT_RXQ0_DONE)
1574 rt_rx_intr(sc, 0);
1575 if (status & RT5350_INT_TXQ3_DONE)
1576 rt_tx_intr(sc, 3);
1577 if (status & RT5350_INT_TXQ2_DONE)
1578 rt_tx_intr(sc, 2);
1579 if (status & RT5350_INT_TXQ1_DONE)
1580 rt_tx_intr(sc, 1);
1581 if (status & RT5350_INT_TXQ0_DONE)
1582 rt_tx_intr(sc, 0);
1583 }
1584
1585 static void
rt_tx_coherent_intr(struct rt_softc * sc)1586 rt_tx_coherent_intr(struct rt_softc *sc)
1587 {
1588 uint32_t tmp;
1589 int i;
1590
1591 RT_DPRINTF(sc, RT_DEBUG_INTR, "Tx coherent interrupt\n");
1592
1593 sc->tx_coherent_interrupts++;
1594
1595 /* restart DMA engine */
1596 tmp = RT_READ(sc, sc->pdma_glo_cfg);
1597 tmp &= ~(FE_TX_WB_DDONE | FE_TX_DMA_EN);
1598 RT_WRITE(sc, sc->pdma_glo_cfg, tmp);
1599
1600 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++)
1601 rt_reset_tx_ring(sc, &sc->tx_ring[i]);
1602
1603 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) {
1604 RT_WRITE(sc, sc->tx_base_ptr[i],
1605 sc->tx_ring[i].desc_phys_addr);
1606 RT_WRITE(sc, sc->tx_max_cnt[i],
1607 RT_SOFTC_TX_RING_DESC_COUNT);
1608 RT_WRITE(sc, sc->tx_ctx_idx[i], 0);
1609 }
1610
1611 rt_txrx_enable(sc);
1612 }
1613
1614 /*
1615 * rt_rx_coherent_intr
1616 */
1617 static void
rt_rx_coherent_intr(struct rt_softc * sc)1618 rt_rx_coherent_intr(struct rt_softc *sc)
1619 {
1620 uint32_t tmp;
1621 int i;
1622
1623 RT_DPRINTF(sc, RT_DEBUG_INTR, "Rx coherent interrupt\n");
1624
1625 sc->rx_coherent_interrupts++;
1626
1627 /* restart DMA engine */
1628 tmp = RT_READ(sc, sc->pdma_glo_cfg);
1629 tmp &= ~(FE_RX_DMA_EN);
1630 RT_WRITE(sc, sc->pdma_glo_cfg, tmp);
1631
1632 /* init Rx ring */
1633 for (i = 0; i < sc->rx_ring_count; i++)
1634 rt_reset_rx_ring(sc, &sc->rx_ring[i]);
1635
1636 for (i = 0; i < sc->rx_ring_count; i++) {
1637 RT_WRITE(sc, sc->rx_base_ptr[i],
1638 sc->rx_ring[i].desc_phys_addr);
1639 RT_WRITE(sc, sc->rx_max_cnt[i],
1640 RT_SOFTC_RX_RING_DATA_COUNT);
1641 RT_WRITE(sc, sc->rx_calc_idx[i],
1642 RT_SOFTC_RX_RING_DATA_COUNT - 1);
1643 }
1644
1645 rt_txrx_enable(sc);
1646 }
1647
1648 /*
1649 * rt_rx_intr - a packet received
1650 */
1651 static void
rt_rx_intr(struct rt_softc * sc,int qid)1652 rt_rx_intr(struct rt_softc *sc, int qid)
1653 {
1654 KASSERT(qid >= 0 && qid < sc->rx_ring_count,
1655 ("%s: Rx interrupt: invalid qid=%d\n",
1656 device_get_nameunit(sc->dev), qid));
1657
1658 RT_DPRINTF(sc, RT_DEBUG_INTR, "Rx interrupt\n");
1659 sc->rx_interrupts[qid]++;
1660 RT_SOFTC_LOCK(sc);
1661
1662 if (!(sc->intr_disable_mask & (sc->int_rx_done_mask << qid))) {
1663 rt_intr_disable(sc, (sc->int_rx_done_mask << qid));
1664 taskqueue_enqueue(sc->taskqueue, &sc->rx_done_task);
1665 }
1666
1667 sc->intr_pending_mask |= (sc->int_rx_done_mask << qid);
1668 RT_SOFTC_UNLOCK(sc);
1669 }
1670
1671 static void
rt_rx_delay_intr(struct rt_softc * sc)1672 rt_rx_delay_intr(struct rt_softc *sc)
1673 {
1674
1675 RT_DPRINTF(sc, RT_DEBUG_INTR, "Rx delay interrupt\n");
1676 sc->rx_delay_interrupts++;
1677 }
1678
1679 static void
rt_tx_delay_intr(struct rt_softc * sc)1680 rt_tx_delay_intr(struct rt_softc *sc)
1681 {
1682
1683 RT_DPRINTF(sc, RT_DEBUG_INTR, "Tx delay interrupt\n");
1684 sc->tx_delay_interrupts++;
1685 }
1686
1687 /*
1688 * rt_tx_intr - Transsmition of packet done
1689 */
1690 static void
rt_tx_intr(struct rt_softc * sc,int qid)1691 rt_tx_intr(struct rt_softc *sc, int qid)
1692 {
1693
1694 KASSERT(qid >= 0 && qid < RT_SOFTC_TX_RING_COUNT,
1695 ("%s: Tx interrupt: invalid qid=%d\n",
1696 device_get_nameunit(sc->dev), qid));
1697
1698 RT_DPRINTF(sc, RT_DEBUG_INTR, "Tx interrupt: qid=%d\n", qid);
1699
1700 sc->tx_interrupts[qid]++;
1701 RT_SOFTC_LOCK(sc);
1702
1703 if (!(sc->intr_disable_mask & (sc->int_tx_done_mask << qid))) {
1704 rt_intr_disable(sc, (sc->int_tx_done_mask << qid));
1705 taskqueue_enqueue(sc->taskqueue, &sc->tx_done_task);
1706 }
1707
1708 sc->intr_pending_mask |= (sc->int_tx_done_mask << qid);
1709 RT_SOFTC_UNLOCK(sc);
1710 }
1711
1712 /*
1713 * rt_rx_done_task - run RX task
1714 */
1715 static void
rt_rx_done_task(void * context,int pending)1716 rt_rx_done_task(void *context, int pending)
1717 {
1718 struct rt_softc *sc;
1719 struct ifnet *ifp;
1720 int again;
1721
1722 sc = context;
1723 ifp = sc->ifp;
1724
1725 RT_DPRINTF(sc, RT_DEBUG_RX, "Rx done task\n");
1726
1727 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1728 return;
1729
1730 sc->intr_pending_mask &= ~sc->int_rx_done_mask;
1731
1732 again = rt_rx_eof(sc, &sc->rx_ring[0], sc->rx_process_limit);
1733
1734 RT_SOFTC_LOCK(sc);
1735
1736 if ((sc->intr_pending_mask & sc->int_rx_done_mask) || again) {
1737 RT_DPRINTF(sc, RT_DEBUG_RX,
1738 "Rx done task: scheduling again\n");
1739 taskqueue_enqueue(sc->taskqueue, &sc->rx_done_task);
1740 } else {
1741 rt_intr_enable(sc, sc->int_rx_done_mask);
1742 }
1743
1744 RT_SOFTC_UNLOCK(sc);
1745 }
1746
1747 /*
1748 * rt_tx_done_task - check for pending TX task in all queues
1749 */
1750 static void
rt_tx_done_task(void * context,int pending)1751 rt_tx_done_task(void *context, int pending)
1752 {
1753 struct rt_softc *sc;
1754 struct ifnet *ifp;
1755 uint32_t intr_mask;
1756 int i;
1757
1758 sc = context;
1759 ifp = sc->ifp;
1760
1761 RT_DPRINTF(sc, RT_DEBUG_TX, "Tx done task\n");
1762
1763 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1764 return;
1765
1766 for (i = RT_SOFTC_TX_RING_COUNT - 1; i >= 0; i--) {
1767 if (sc->intr_pending_mask & (sc->int_tx_done_mask << i)) {
1768 sc->intr_pending_mask &= ~(sc->int_tx_done_mask << i);
1769 rt_tx_eof(sc, &sc->tx_ring[i]);
1770 }
1771 }
1772
1773 sc->tx_timer = 0;
1774
1775 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1776
1777 if(sc->rt_chipid == RT_CHIPID_RT5350 ||
1778 sc->rt_chipid == RT_CHIPID_MT7620 ||
1779 sc->rt_chipid == RT_CHIPID_MT7621)
1780 intr_mask = (
1781 RT5350_INT_TXQ3_DONE |
1782 RT5350_INT_TXQ2_DONE |
1783 RT5350_INT_TXQ1_DONE |
1784 RT5350_INT_TXQ0_DONE);
1785 else
1786 intr_mask = (
1787 INT_TXQ3_DONE |
1788 INT_TXQ2_DONE |
1789 INT_TXQ1_DONE |
1790 INT_TXQ0_DONE);
1791
1792 RT_SOFTC_LOCK(sc);
1793
1794 rt_intr_enable(sc, ~sc->intr_pending_mask &
1795 (sc->intr_disable_mask & intr_mask));
1796
1797 if (sc->intr_pending_mask & intr_mask) {
1798 RT_DPRINTF(sc, RT_DEBUG_TX,
1799 "Tx done task: scheduling again\n");
1800 taskqueue_enqueue(sc->taskqueue, &sc->tx_done_task);
1801 }
1802
1803 RT_SOFTC_UNLOCK(sc);
1804
1805 if (!IFQ_IS_EMPTY(&ifp->if_snd))
1806 rt_start(ifp);
1807 }
1808
1809 /*
1810 * rt_periodic_task - run periodic task
1811 */
1812 static void
rt_periodic_task(void * context,int pending)1813 rt_periodic_task(void *context, int pending)
1814 {
1815 struct rt_softc *sc;
1816 struct ifnet *ifp;
1817
1818 sc = context;
1819 ifp = sc->ifp;
1820
1821 RT_DPRINTF(sc, RT_DEBUG_PERIODIC, "periodic task: round=%lu\n",
1822 sc->periodic_round);
1823
1824 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1825 return;
1826
1827 RT_SOFTC_LOCK(sc);
1828 sc->periodic_round++;
1829 rt_update_stats(sc);
1830
1831 if ((sc->periodic_round % 10) == 0) {
1832 rt_update_raw_counters(sc);
1833 rt_watchdog(sc);
1834 }
1835
1836 RT_SOFTC_UNLOCK(sc);
1837 callout_reset(&sc->periodic_ch, hz / 10, rt_periodic, sc);
1838 }
1839
1840 /*
1841 * rt_rx_eof - check for frames that done by DMA engine and pass it into
1842 * network subsystem.
1843 */
1844 static int
rt_rx_eof(struct rt_softc * sc,struct rt_softc_rx_ring * ring,int limit)1845 rt_rx_eof(struct rt_softc *sc, struct rt_softc_rx_ring *ring, int limit)
1846 {
1847 struct ifnet *ifp;
1848 /* struct rt_softc_rx_ring *ring; */
1849 struct rt_rxdesc *desc;
1850 struct rt_softc_rx_data *data;
1851 struct mbuf *m, *mnew;
1852 bus_dma_segment_t segs[1];
1853 bus_dmamap_t dma_map;
1854 uint32_t index, desc_flags;
1855 int error, nsegs, len, nframes;
1856
1857 ifp = sc->ifp;
1858 /* ring = &sc->rx_ring[0]; */
1859
1860 nframes = 0;
1861
1862 while (limit != 0) {
1863 index = RT_READ(sc, sc->rx_drx_idx[0]);
1864 if (ring->cur == index)
1865 break;
1866
1867 desc = &ring->desc[ring->cur];
1868 data = &ring->data[ring->cur];
1869
1870 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
1871 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1872
1873 #ifdef IF_RT_DEBUG
1874 if ( sc->debug & RT_DEBUG_RX ) {
1875 printf("\nRX Descriptor[%#08x] dump:\n", (u_int)desc);
1876 hexdump(desc, 16, 0, 0);
1877 printf("-----------------------------------\n");
1878 }
1879 #endif
1880
1881 /* XXX Sometime device don`t set DDONE bit */
1882 #ifdef DDONE_FIXED
1883 if (!(desc->sdl0 & htole16(RT_RXDESC_SDL0_DDONE))) {
1884 RT_DPRINTF(sc, RT_DEBUG_RX, "DDONE=0, try next\n");
1885 break;
1886 }
1887 #endif
1888
1889 len = le16toh(desc->sdl0) & 0x3fff;
1890 RT_DPRINTF(sc, RT_DEBUG_RX, "new frame len=%d\n", len);
1891
1892 nframes++;
1893
1894 mnew = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR,
1895 MJUMPAGESIZE);
1896 if (mnew == NULL) {
1897 sc->rx_mbuf_alloc_errors++;
1898 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1899 goto skip;
1900 }
1901
1902 mnew->m_len = mnew->m_pkthdr.len = MJUMPAGESIZE;
1903
1904 error = bus_dmamap_load_mbuf_sg(ring->data_dma_tag,
1905 ring->spare_dma_map, mnew, segs, &nsegs, BUS_DMA_NOWAIT);
1906 if (error != 0) {
1907 RT_DPRINTF(sc, RT_DEBUG_RX,
1908 "could not load Rx mbuf DMA map: "
1909 "error=%d, nsegs=%d\n",
1910 error, nsegs);
1911
1912 m_freem(mnew);
1913
1914 sc->rx_mbuf_dmamap_errors++;
1915 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1916
1917 goto skip;
1918 }
1919
1920 KASSERT(nsegs == 1, ("%s: too many DMA segments",
1921 device_get_nameunit(sc->dev)));
1922
1923 bus_dmamap_sync(ring->data_dma_tag, data->dma_map,
1924 BUS_DMASYNC_POSTREAD);
1925 bus_dmamap_unload(ring->data_dma_tag, data->dma_map);
1926
1927 dma_map = data->dma_map;
1928 data->dma_map = ring->spare_dma_map;
1929 ring->spare_dma_map = dma_map;
1930
1931 bus_dmamap_sync(ring->data_dma_tag, data->dma_map,
1932 BUS_DMASYNC_PREREAD);
1933
1934 m = data->m;
1935 desc_flags = desc->word3;
1936
1937 data->m = mnew;
1938 /* Add 2 for proper align of RX IP header */
1939 desc->sdp0 = htole32(segs[0].ds_addr+2);
1940 desc->sdl0 = htole32(segs[0].ds_len-2);
1941 desc->word3 = 0;
1942
1943 RT_DPRINTF(sc, RT_DEBUG_RX,
1944 "Rx frame: rxdesc flags=0x%08x\n", desc_flags);
1945
1946 m->m_pkthdr.rcvif = ifp;
1947 /* Add 2 to fix data align, after sdp0 = addr + 2 */
1948 m->m_data += 2;
1949 m->m_pkthdr.len = m->m_len = len;
1950
1951 /* check for crc errors */
1952 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) {
1953 /*check for valid checksum*/
1954 if (desc_flags & (sc->csum_fail_ip|sc->csum_fail_l4)) {
1955 RT_DPRINTF(sc, RT_DEBUG_RX,
1956 "rxdesc: crc error\n");
1957
1958 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1959
1960 if (!(ifp->if_flags & IFF_PROMISC)) {
1961 m_freem(m);
1962 goto skip;
1963 }
1964 }
1965 if ((desc_flags & sc->csum_fail_ip) == 0) {
1966 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1967 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1968 m->m_pkthdr.csum_data = 0xffff;
1969 }
1970 m->m_flags &= ~M_HASFCS;
1971 }
1972
1973 (*ifp->if_input)(ifp, m);
1974 skip:
1975 desc->sdl0 &= ~htole16(RT_RXDESC_SDL0_DDONE);
1976
1977 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
1978 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1979
1980 ring->cur = (ring->cur + 1) % RT_SOFTC_RX_RING_DATA_COUNT;
1981
1982 limit--;
1983 }
1984
1985 if (ring->cur == 0)
1986 RT_WRITE(sc, sc->rx_calc_idx[0],
1987 RT_SOFTC_RX_RING_DATA_COUNT - 1);
1988 else
1989 RT_WRITE(sc, sc->rx_calc_idx[0],
1990 ring->cur - 1);
1991
1992 RT_DPRINTF(sc, RT_DEBUG_RX, "Rx eof: nframes=%d\n", nframes);
1993
1994 sc->rx_packets += nframes;
1995
1996 return (limit == 0);
1997 }
1998
1999 /*
2000 * rt_tx_eof - check for successful transmitted frames and mark their
2001 * descriptor as free.
2002 */
2003 static void
rt_tx_eof(struct rt_softc * sc,struct rt_softc_tx_ring * ring)2004 rt_tx_eof(struct rt_softc *sc, struct rt_softc_tx_ring *ring)
2005 {
2006 struct ifnet *ifp;
2007 struct rt_txdesc *desc;
2008 struct rt_softc_tx_data *data;
2009 uint32_t index;
2010 int ndescs, nframes;
2011
2012 ifp = sc->ifp;
2013
2014 ndescs = 0;
2015 nframes = 0;
2016
2017 for (;;) {
2018 index = RT_READ(sc, sc->tx_dtx_idx[ring->qid]);
2019 if (ring->desc_next == index)
2020 break;
2021
2022 ndescs++;
2023
2024 desc = &ring->desc[ring->desc_next];
2025
2026 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
2027 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2028
2029 if (desc->sdl0 & htole16(RT_TXDESC_SDL0_LASTSEG) ||
2030 desc->sdl1 & htole16(RT_TXDESC_SDL1_LASTSEG)) {
2031 nframes++;
2032
2033 data = &ring->data[ring->data_next];
2034
2035 bus_dmamap_sync(ring->data_dma_tag, data->dma_map,
2036 BUS_DMASYNC_POSTWRITE);
2037 bus_dmamap_unload(ring->data_dma_tag, data->dma_map);
2038
2039 m_freem(data->m);
2040
2041 data->m = NULL;
2042
2043 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
2044
2045 RT_SOFTC_TX_RING_LOCK(ring);
2046 ring->data_queued--;
2047 ring->data_next = (ring->data_next + 1) %
2048 RT_SOFTC_TX_RING_DATA_COUNT;
2049 RT_SOFTC_TX_RING_UNLOCK(ring);
2050 }
2051
2052 desc->sdl0 &= ~htole16(RT_TXDESC_SDL0_DDONE);
2053
2054 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
2055 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2056
2057 RT_SOFTC_TX_RING_LOCK(ring);
2058 ring->desc_queued--;
2059 ring->desc_next = (ring->desc_next + 1) %
2060 RT_SOFTC_TX_RING_DESC_COUNT;
2061 RT_SOFTC_TX_RING_UNLOCK(ring);
2062 }
2063
2064 RT_DPRINTF(sc, RT_DEBUG_TX,
2065 "Tx eof: qid=%d, ndescs=%d, nframes=%d\n", ring->qid, ndescs,
2066 nframes);
2067 }
2068
2069 /*
2070 * rt_update_stats - query statistics counters and update related variables.
2071 */
2072 static void
rt_update_stats(struct rt_softc * sc)2073 rt_update_stats(struct rt_softc *sc)
2074 {
2075 struct ifnet *ifp;
2076
2077 ifp = sc->ifp;
2078 RT_DPRINTF(sc, RT_DEBUG_STATS, "update statistic: \n");
2079 /* XXX do update stats here */
2080 }
2081
2082 /*
2083 * rt_watchdog - reinit device on watchdog event.
2084 */
2085 static void
rt_watchdog(struct rt_softc * sc)2086 rt_watchdog(struct rt_softc *sc)
2087 {
2088 uint32_t tmp;
2089 #ifdef notyet
2090 int ntries;
2091 #endif
2092 if(sc->rt_chipid != RT_CHIPID_RT5350 &&
2093 sc->rt_chipid != RT_CHIPID_MT7620 &&
2094 sc->rt_chipid != RT_CHIPID_MT7621) {
2095 tmp = RT_READ(sc, PSE_BASE + CDMA_OQ_STA);
2096
2097 RT_DPRINTF(sc, RT_DEBUG_WATCHDOG,
2098 "watchdog: PSE_IQ_STA=0x%08x\n", tmp);
2099 }
2100 /* XXX: do not reset */
2101 #ifdef notyet
2102 if (((tmp >> P0_IQ_PCNT_SHIFT) & 0xff) != 0) {
2103 sc->tx_queue_not_empty[0]++;
2104
2105 for (ntries = 0; ntries < 10; ntries++) {
2106 tmp = RT_READ(sc, PSE_BASE + PSE_IQ_STA);
2107 if (((tmp >> P0_IQ_PCNT_SHIFT) & 0xff) == 0)
2108 break;
2109
2110 DELAY(1);
2111 }
2112 }
2113
2114 if (((tmp >> P1_IQ_PCNT_SHIFT) & 0xff) != 0) {
2115 sc->tx_queue_not_empty[1]++;
2116
2117 for (ntries = 0; ntries < 10; ntries++) {
2118 tmp = RT_READ(sc, PSE_BASE + PSE_IQ_STA);
2119 if (((tmp >> P1_IQ_PCNT_SHIFT) & 0xff) == 0)
2120 break;
2121
2122 DELAY(1);
2123 }
2124 }
2125 #endif
2126 }
2127
2128 /*
2129 * rt_update_raw_counters - update counters.
2130 */
2131 static void
rt_update_raw_counters(struct rt_softc * sc)2132 rt_update_raw_counters(struct rt_softc *sc)
2133 {
2134
2135 sc->tx_bytes += RT_READ(sc, CNTR_BASE + GDMA_TX_GBCNT0);
2136 sc->tx_packets += RT_READ(sc, CNTR_BASE + GDMA_TX_GPCNT0);
2137 sc->tx_skip += RT_READ(sc, CNTR_BASE + GDMA_TX_SKIPCNT0);
2138 sc->tx_collision+= RT_READ(sc, CNTR_BASE + GDMA_TX_COLCNT0);
2139
2140 sc->rx_bytes += RT_READ(sc, CNTR_BASE + GDMA_RX_GBCNT0);
2141 sc->rx_packets += RT_READ(sc, CNTR_BASE + GDMA_RX_GPCNT0);
2142 sc->rx_crc_err += RT_READ(sc, CNTR_BASE + GDMA_RX_CSUM_ERCNT0);
2143 sc->rx_short_err+= RT_READ(sc, CNTR_BASE + GDMA_RX_SHORT_ERCNT0);
2144 sc->rx_long_err += RT_READ(sc, CNTR_BASE + GDMA_RX_LONG_ERCNT0);
2145 sc->rx_phy_err += RT_READ(sc, CNTR_BASE + GDMA_RX_FERCNT0);
2146 sc->rx_fifo_overflows+= RT_READ(sc, CNTR_BASE + GDMA_RX_OERCNT0);
2147 }
2148
2149 static void
rt_intr_enable(struct rt_softc * sc,uint32_t intr_mask)2150 rt_intr_enable(struct rt_softc *sc, uint32_t intr_mask)
2151 {
2152 uint32_t tmp;
2153
2154 sc->intr_disable_mask &= ~intr_mask;
2155 tmp = sc->intr_enable_mask & ~sc->intr_disable_mask;
2156 RT_WRITE(sc, sc->fe_int_enable, tmp);
2157 }
2158
2159 static void
rt_intr_disable(struct rt_softc * sc,uint32_t intr_mask)2160 rt_intr_disable(struct rt_softc *sc, uint32_t intr_mask)
2161 {
2162 uint32_t tmp;
2163
2164 sc->intr_disable_mask |= intr_mask;
2165 tmp = sc->intr_enable_mask & ~sc->intr_disable_mask;
2166 RT_WRITE(sc, sc->fe_int_enable, tmp);
2167 }
2168
2169 /*
2170 * rt_txrx_enable - enable TX/RX DMA
2171 */
2172 static int
rt_txrx_enable(struct rt_softc * sc)2173 rt_txrx_enable(struct rt_softc *sc)
2174 {
2175 struct ifnet *ifp;
2176 uint32_t tmp;
2177 int ntries;
2178
2179 ifp = sc->ifp;
2180
2181 /* enable Tx/Rx DMA engine */
2182 for (ntries = 0; ntries < 200; ntries++) {
2183 tmp = RT_READ(sc, sc->pdma_glo_cfg);
2184 if (!(tmp & (FE_TX_DMA_BUSY | FE_RX_DMA_BUSY)))
2185 break;
2186
2187 DELAY(1000);
2188 }
2189
2190 if (ntries == 200) {
2191 device_printf(sc->dev, "timeout waiting for DMA engine\n");
2192 return (-1);
2193 }
2194
2195 DELAY(50);
2196
2197 tmp |= FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN;
2198 RT_WRITE(sc, sc->pdma_glo_cfg, tmp);
2199
2200 /* XXX set Rx filter */
2201 return (0);
2202 }
2203
2204 /*
2205 * rt_alloc_rx_ring - allocate RX DMA ring buffer
2206 */
2207 static int
rt_alloc_rx_ring(struct rt_softc * sc,struct rt_softc_rx_ring * ring,int qid)2208 rt_alloc_rx_ring(struct rt_softc *sc, struct rt_softc_rx_ring *ring, int qid)
2209 {
2210 struct rt_rxdesc *desc;
2211 struct rt_softc_rx_data *data;
2212 bus_dma_segment_t segs[1];
2213 int i, nsegs, error;
2214
2215 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0,
2216 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
2217 RT_SOFTC_RX_RING_DATA_COUNT * sizeof(struct rt_rxdesc), 1,
2218 RT_SOFTC_RX_RING_DATA_COUNT * sizeof(struct rt_rxdesc),
2219 0, NULL, NULL, &ring->desc_dma_tag);
2220 if (error != 0) {
2221 device_printf(sc->dev,
2222 "could not create Rx desc DMA tag\n");
2223 goto fail;
2224 }
2225
2226 error = bus_dmamem_alloc(ring->desc_dma_tag, (void **) &ring->desc,
2227 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_dma_map);
2228 if (error != 0) {
2229 device_printf(sc->dev,
2230 "could not allocate Rx desc DMA memory\n");
2231 goto fail;
2232 }
2233
2234 error = bus_dmamap_load(ring->desc_dma_tag, ring->desc_dma_map,
2235 ring->desc,
2236 RT_SOFTC_RX_RING_DATA_COUNT * sizeof(struct rt_rxdesc),
2237 rt_dma_map_addr, &ring->desc_phys_addr, 0);
2238 if (error != 0) {
2239 device_printf(sc->dev, "could not load Rx desc DMA map\n");
2240 goto fail;
2241 }
2242
2243 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0,
2244 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
2245 MJUMPAGESIZE, 1, MJUMPAGESIZE, 0, NULL, NULL,
2246 &ring->data_dma_tag);
2247 if (error != 0) {
2248 device_printf(sc->dev,
2249 "could not create Rx data DMA tag\n");
2250 goto fail;
2251 }
2252
2253 for (i = 0; i < RT_SOFTC_RX_RING_DATA_COUNT; i++) {
2254 desc = &ring->desc[i];
2255 data = &ring->data[i];
2256
2257 error = bus_dmamap_create(ring->data_dma_tag, 0,
2258 &data->dma_map);
2259 if (error != 0) {
2260 device_printf(sc->dev, "could not create Rx data DMA "
2261 "map\n");
2262 goto fail;
2263 }
2264
2265 data->m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR,
2266 MJUMPAGESIZE);
2267 if (data->m == NULL) {
2268 device_printf(sc->dev, "could not allocate Rx mbuf\n");
2269 error = ENOMEM;
2270 goto fail;
2271 }
2272
2273 data->m->m_len = data->m->m_pkthdr.len = MJUMPAGESIZE;
2274
2275 error = bus_dmamap_load_mbuf_sg(ring->data_dma_tag,
2276 data->dma_map, data->m, segs, &nsegs, BUS_DMA_NOWAIT);
2277 if (error != 0) {
2278 device_printf(sc->dev,
2279 "could not load Rx mbuf DMA map\n");
2280 goto fail;
2281 }
2282
2283 KASSERT(nsegs == 1, ("%s: too many DMA segments",
2284 device_get_nameunit(sc->dev)));
2285
2286 /* Add 2 for proper align of RX IP header */
2287 desc->sdp0 = htole32(segs[0].ds_addr+2);
2288 desc->sdl0 = htole32(segs[0].ds_len-2);
2289 }
2290
2291 error = bus_dmamap_create(ring->data_dma_tag, 0,
2292 &ring->spare_dma_map);
2293 if (error != 0) {
2294 device_printf(sc->dev,
2295 "could not create Rx spare DMA map\n");
2296 goto fail;
2297 }
2298
2299 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
2300 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2301 ring->qid = qid;
2302 return (0);
2303
2304 fail:
2305 rt_free_rx_ring(sc, ring);
2306 return (error);
2307 }
2308
2309 /*
2310 * rt_reset_rx_ring - reset RX ring buffer
2311 */
2312 static void
rt_reset_rx_ring(struct rt_softc * sc,struct rt_softc_rx_ring * ring)2313 rt_reset_rx_ring(struct rt_softc *sc, struct rt_softc_rx_ring *ring)
2314 {
2315 struct rt_rxdesc *desc;
2316 int i;
2317
2318 for (i = 0; i < RT_SOFTC_RX_RING_DATA_COUNT; i++) {
2319 desc = &ring->desc[i];
2320 desc->sdl0 &= ~htole16(RT_RXDESC_SDL0_DDONE);
2321 }
2322
2323 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
2324 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2325 ring->cur = 0;
2326 }
2327
2328 /*
2329 * rt_free_rx_ring - free memory used by RX ring buffer
2330 */
2331 static void
rt_free_rx_ring(struct rt_softc * sc,struct rt_softc_rx_ring * ring)2332 rt_free_rx_ring(struct rt_softc *sc, struct rt_softc_rx_ring *ring)
2333 {
2334 struct rt_softc_rx_data *data;
2335 int i;
2336
2337 if (ring->desc != NULL) {
2338 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
2339 BUS_DMASYNC_POSTWRITE);
2340 bus_dmamap_unload(ring->desc_dma_tag, ring->desc_dma_map);
2341 bus_dmamem_free(ring->desc_dma_tag, ring->desc,
2342 ring->desc_dma_map);
2343 }
2344
2345 if (ring->desc_dma_tag != NULL)
2346 bus_dma_tag_destroy(ring->desc_dma_tag);
2347
2348 for (i = 0; i < RT_SOFTC_RX_RING_DATA_COUNT; i++) {
2349 data = &ring->data[i];
2350
2351 if (data->m != NULL) {
2352 bus_dmamap_sync(ring->data_dma_tag, data->dma_map,
2353 BUS_DMASYNC_POSTREAD);
2354 bus_dmamap_unload(ring->data_dma_tag, data->dma_map);
2355 m_freem(data->m);
2356 }
2357
2358 if (data->dma_map != NULL)
2359 bus_dmamap_destroy(ring->data_dma_tag, data->dma_map);
2360 }
2361
2362 if (ring->spare_dma_map != NULL)
2363 bus_dmamap_destroy(ring->data_dma_tag, ring->spare_dma_map);
2364
2365 if (ring->data_dma_tag != NULL)
2366 bus_dma_tag_destroy(ring->data_dma_tag);
2367 }
2368
2369 /*
2370 * rt_alloc_tx_ring - allocate TX ring buffer
2371 */
2372 static int
rt_alloc_tx_ring(struct rt_softc * sc,struct rt_softc_tx_ring * ring,int qid)2373 rt_alloc_tx_ring(struct rt_softc *sc, struct rt_softc_tx_ring *ring, int qid)
2374 {
2375 struct rt_softc_tx_data *data;
2376 int error, i;
2377
2378 mtx_init(&ring->lock, device_get_nameunit(sc->dev), NULL, MTX_DEF);
2379
2380 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0,
2381 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
2382 RT_SOFTC_TX_RING_DESC_COUNT * sizeof(struct rt_txdesc), 1,
2383 RT_SOFTC_TX_RING_DESC_COUNT * sizeof(struct rt_txdesc),
2384 0, NULL, NULL, &ring->desc_dma_tag);
2385 if (error != 0) {
2386 device_printf(sc->dev,
2387 "could not create Tx desc DMA tag\n");
2388 goto fail;
2389 }
2390
2391 error = bus_dmamem_alloc(ring->desc_dma_tag, (void **) &ring->desc,
2392 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_dma_map);
2393 if (error != 0) {
2394 device_printf(sc->dev,
2395 "could not allocate Tx desc DMA memory\n");
2396 goto fail;
2397 }
2398
2399 error = bus_dmamap_load(ring->desc_dma_tag, ring->desc_dma_map,
2400 ring->desc, (RT_SOFTC_TX_RING_DESC_COUNT *
2401 sizeof(struct rt_txdesc)), rt_dma_map_addr,
2402 &ring->desc_phys_addr, 0);
2403 if (error != 0) {
2404 device_printf(sc->dev, "could not load Tx desc DMA map\n");
2405 goto fail;
2406 }
2407
2408 ring->desc_queued = 0;
2409 ring->desc_cur = 0;
2410 ring->desc_next = 0;
2411
2412 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0,
2413 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
2414 RT_SOFTC_TX_RING_DATA_COUNT * RT_TX_DATA_SEG0_SIZE, 1,
2415 RT_SOFTC_TX_RING_DATA_COUNT * RT_TX_DATA_SEG0_SIZE,
2416 0, NULL, NULL, &ring->seg0_dma_tag);
2417 if (error != 0) {
2418 device_printf(sc->dev,
2419 "could not create Tx seg0 DMA tag\n");
2420 goto fail;
2421 }
2422
2423 error = bus_dmamem_alloc(ring->seg0_dma_tag, (void **) &ring->seg0,
2424 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->seg0_dma_map);
2425 if (error != 0) {
2426 device_printf(sc->dev,
2427 "could not allocate Tx seg0 DMA memory\n");
2428 goto fail;
2429 }
2430
2431 error = bus_dmamap_load(ring->seg0_dma_tag, ring->seg0_dma_map,
2432 ring->seg0,
2433 RT_SOFTC_TX_RING_DATA_COUNT * RT_TX_DATA_SEG0_SIZE,
2434 rt_dma_map_addr, &ring->seg0_phys_addr, 0);
2435 if (error != 0) {
2436 device_printf(sc->dev, "could not load Tx seg0 DMA map\n");
2437 goto fail;
2438 }
2439
2440 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0,
2441 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
2442 MJUMPAGESIZE, RT_SOFTC_MAX_SCATTER, MJUMPAGESIZE, 0, NULL, NULL,
2443 &ring->data_dma_tag);
2444 if (error != 0) {
2445 device_printf(sc->dev,
2446 "could not create Tx data DMA tag\n");
2447 goto fail;
2448 }
2449
2450 for (i = 0; i < RT_SOFTC_TX_RING_DATA_COUNT; i++) {
2451 data = &ring->data[i];
2452
2453 error = bus_dmamap_create(ring->data_dma_tag, 0,
2454 &data->dma_map);
2455 if (error != 0) {
2456 device_printf(sc->dev, "could not create Tx data DMA "
2457 "map\n");
2458 goto fail;
2459 }
2460 }
2461
2462 ring->data_queued = 0;
2463 ring->data_cur = 0;
2464 ring->data_next = 0;
2465
2466 ring->qid = qid;
2467 return (0);
2468
2469 fail:
2470 rt_free_tx_ring(sc, ring);
2471 return (error);
2472 }
2473
2474 /*
2475 * rt_reset_tx_ring - reset TX ring buffer to empty state
2476 */
2477 static void
rt_reset_tx_ring(struct rt_softc * sc,struct rt_softc_tx_ring * ring)2478 rt_reset_tx_ring(struct rt_softc *sc, struct rt_softc_tx_ring *ring)
2479 {
2480 struct rt_softc_tx_data *data;
2481 struct rt_txdesc *desc;
2482 int i;
2483
2484 for (i = 0; i < RT_SOFTC_TX_RING_DESC_COUNT; i++) {
2485 desc = &ring->desc[i];
2486
2487 desc->sdl0 = 0;
2488 desc->sdl1 = 0;
2489 }
2490
2491 ring->desc_queued = 0;
2492 ring->desc_cur = 0;
2493 ring->desc_next = 0;
2494
2495 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
2496 BUS_DMASYNC_PREWRITE);
2497
2498 bus_dmamap_sync(ring->seg0_dma_tag, ring->seg0_dma_map,
2499 BUS_DMASYNC_PREWRITE);
2500
2501 for (i = 0; i < RT_SOFTC_TX_RING_DATA_COUNT; i++) {
2502 data = &ring->data[i];
2503
2504 if (data->m != NULL) {
2505 bus_dmamap_sync(ring->data_dma_tag, data->dma_map,
2506 BUS_DMASYNC_POSTWRITE);
2507 bus_dmamap_unload(ring->data_dma_tag, data->dma_map);
2508 m_freem(data->m);
2509 data->m = NULL;
2510 }
2511 }
2512
2513 ring->data_queued = 0;
2514 ring->data_cur = 0;
2515 ring->data_next = 0;
2516 }
2517
2518 /*
2519 * rt_free_tx_ring - free RX ring buffer
2520 */
2521 static void
rt_free_tx_ring(struct rt_softc * sc,struct rt_softc_tx_ring * ring)2522 rt_free_tx_ring(struct rt_softc *sc, struct rt_softc_tx_ring *ring)
2523 {
2524 struct rt_softc_tx_data *data;
2525 int i;
2526
2527 if (ring->desc != NULL) {
2528 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
2529 BUS_DMASYNC_POSTWRITE);
2530 bus_dmamap_unload(ring->desc_dma_tag, ring->desc_dma_map);
2531 bus_dmamem_free(ring->desc_dma_tag, ring->desc,
2532 ring->desc_dma_map);
2533 }
2534
2535 if (ring->desc_dma_tag != NULL)
2536 bus_dma_tag_destroy(ring->desc_dma_tag);
2537
2538 if (ring->seg0 != NULL) {
2539 bus_dmamap_sync(ring->seg0_dma_tag, ring->seg0_dma_map,
2540 BUS_DMASYNC_POSTWRITE);
2541 bus_dmamap_unload(ring->seg0_dma_tag, ring->seg0_dma_map);
2542 bus_dmamem_free(ring->seg0_dma_tag, ring->seg0,
2543 ring->seg0_dma_map);
2544 }
2545
2546 if (ring->seg0_dma_tag != NULL)
2547 bus_dma_tag_destroy(ring->seg0_dma_tag);
2548
2549 for (i = 0; i < RT_SOFTC_TX_RING_DATA_COUNT; i++) {
2550 data = &ring->data[i];
2551
2552 if (data->m != NULL) {
2553 bus_dmamap_sync(ring->data_dma_tag, data->dma_map,
2554 BUS_DMASYNC_POSTWRITE);
2555 bus_dmamap_unload(ring->data_dma_tag, data->dma_map);
2556 m_freem(data->m);
2557 }
2558
2559 if (data->dma_map != NULL)
2560 bus_dmamap_destroy(ring->data_dma_tag, data->dma_map);
2561 }
2562
2563 if (ring->data_dma_tag != NULL)
2564 bus_dma_tag_destroy(ring->data_dma_tag);
2565
2566 mtx_destroy(&ring->lock);
2567 }
2568
2569 /*
2570 * rt_dma_map_addr - get address of busdma segment
2571 */
2572 static void
rt_dma_map_addr(void * arg,bus_dma_segment_t * segs,int nseg,int error)2573 rt_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2574 {
2575 if (error != 0)
2576 return;
2577
2578 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
2579
2580 *(bus_addr_t *) arg = segs[0].ds_addr;
2581 }
2582
2583 /*
2584 * rt_sysctl_attach - attach sysctl nodes for NIC counters.
2585 */
2586 static void
rt_sysctl_attach(struct rt_softc * sc)2587 rt_sysctl_attach(struct rt_softc *sc)
2588 {
2589 struct sysctl_ctx_list *ctx;
2590 struct sysctl_oid *tree;
2591 struct sysctl_oid *stats;
2592
2593 ctx = device_get_sysctl_ctx(sc->dev);
2594 tree = device_get_sysctl_tree(sc->dev);
2595
2596 /* statistic counters */
2597 stats = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
2598 "stats", CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "statistic");
2599
2600 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2601 "interrupts", CTLFLAG_RD, &sc->interrupts,
2602 "all interrupts");
2603
2604 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2605 "tx_coherent_interrupts", CTLFLAG_RD, &sc->tx_coherent_interrupts,
2606 "Tx coherent interrupts");
2607
2608 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2609 "rx_coherent_interrupts", CTLFLAG_RD, &sc->rx_coherent_interrupts,
2610 "Rx coherent interrupts");
2611
2612 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2613 "rx_interrupts", CTLFLAG_RD, &sc->rx_interrupts[0],
2614 "Rx interrupts");
2615
2616 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2617 "rx_delay_interrupts", CTLFLAG_RD, &sc->rx_delay_interrupts,
2618 "Rx delay interrupts");
2619
2620 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2621 "TXQ3_interrupts", CTLFLAG_RD, &sc->tx_interrupts[3],
2622 "Tx AC3 interrupts");
2623
2624 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2625 "TXQ2_interrupts", CTLFLAG_RD, &sc->tx_interrupts[2],
2626 "Tx AC2 interrupts");
2627
2628 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2629 "TXQ1_interrupts", CTLFLAG_RD, &sc->tx_interrupts[1],
2630 "Tx AC1 interrupts");
2631
2632 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2633 "TXQ0_interrupts", CTLFLAG_RD, &sc->tx_interrupts[0],
2634 "Tx AC0 interrupts");
2635
2636 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2637 "tx_delay_interrupts", CTLFLAG_RD, &sc->tx_delay_interrupts,
2638 "Tx delay interrupts");
2639
2640 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2641 "TXQ3_desc_queued", CTLFLAG_RD, &sc->tx_ring[3].desc_queued,
2642 0, "Tx AC3 descriptors queued");
2643
2644 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2645 "TXQ3_data_queued", CTLFLAG_RD, &sc->tx_ring[3].data_queued,
2646 0, "Tx AC3 data queued");
2647
2648 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2649 "TXQ2_desc_queued", CTLFLAG_RD, &sc->tx_ring[2].desc_queued,
2650 0, "Tx AC2 descriptors queued");
2651
2652 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2653 "TXQ2_data_queued", CTLFLAG_RD, &sc->tx_ring[2].data_queued,
2654 0, "Tx AC2 data queued");
2655
2656 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2657 "TXQ1_desc_queued", CTLFLAG_RD, &sc->tx_ring[1].desc_queued,
2658 0, "Tx AC1 descriptors queued");
2659
2660 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2661 "TXQ1_data_queued", CTLFLAG_RD, &sc->tx_ring[1].data_queued,
2662 0, "Tx AC1 data queued");
2663
2664 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2665 "TXQ0_desc_queued", CTLFLAG_RD, &sc->tx_ring[0].desc_queued,
2666 0, "Tx AC0 descriptors queued");
2667
2668 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2669 "TXQ0_data_queued", CTLFLAG_RD, &sc->tx_ring[0].data_queued,
2670 0, "Tx AC0 data queued");
2671
2672 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2673 "TXQ3_data_queue_full", CTLFLAG_RD, &sc->tx_data_queue_full[3],
2674 "Tx AC3 data queue full");
2675
2676 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2677 "TXQ2_data_queue_full", CTLFLAG_RD, &sc->tx_data_queue_full[2],
2678 "Tx AC2 data queue full");
2679
2680 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2681 "TXQ1_data_queue_full", CTLFLAG_RD, &sc->tx_data_queue_full[1],
2682 "Tx AC1 data queue full");
2683
2684 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2685 "TXQ0_data_queue_full", CTLFLAG_RD, &sc->tx_data_queue_full[0],
2686 "Tx AC0 data queue full");
2687
2688 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2689 "tx_watchdog_timeouts", CTLFLAG_RD, &sc->tx_watchdog_timeouts,
2690 "Tx watchdog timeouts");
2691
2692 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2693 "tx_defrag_packets", CTLFLAG_RD, &sc->tx_defrag_packets,
2694 "Tx defragmented packets");
2695
2696 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2697 "no_tx_desc_avail", CTLFLAG_RD, &sc->no_tx_desc_avail,
2698 "no Tx descriptors available");
2699
2700 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2701 "rx_mbuf_alloc_errors", CTLFLAG_RD, &sc->rx_mbuf_alloc_errors,
2702 "Rx mbuf allocation errors");
2703
2704 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2705 "rx_mbuf_dmamap_errors", CTLFLAG_RD, &sc->rx_mbuf_dmamap_errors,
2706 "Rx mbuf DMA mapping errors");
2707
2708 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2709 "tx_queue_0_not_empty", CTLFLAG_RD, &sc->tx_queue_not_empty[0],
2710 "Tx queue 0 not empty");
2711
2712 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2713 "tx_queue_1_not_empty", CTLFLAG_RD, &sc->tx_queue_not_empty[1],
2714 "Tx queue 1 not empty");
2715
2716 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2717 "rx_packets", CTLFLAG_RD, &sc->rx_packets,
2718 "Rx packets");
2719
2720 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2721 "rx_crc_errors", CTLFLAG_RD, &sc->rx_crc_err,
2722 "Rx CRC errors");
2723
2724 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2725 "rx_phy_errors", CTLFLAG_RD, &sc->rx_phy_err,
2726 "Rx PHY errors");
2727
2728 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2729 "rx_dup_packets", CTLFLAG_RD, &sc->rx_dup_packets,
2730 "Rx duplicate packets");
2731
2732 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2733 "rx_fifo_overflows", CTLFLAG_RD, &sc->rx_fifo_overflows,
2734 "Rx FIFO overflows");
2735
2736 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2737 "rx_bytes", CTLFLAG_RD, &sc->rx_bytes,
2738 "Rx bytes");
2739
2740 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2741 "rx_long_err", CTLFLAG_RD, &sc->rx_long_err,
2742 "Rx too long frame errors");
2743
2744 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2745 "rx_short_err", CTLFLAG_RD, &sc->rx_short_err,
2746 "Rx too short frame errors");
2747
2748 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2749 "tx_bytes", CTLFLAG_RD, &sc->tx_bytes,
2750 "Tx bytes");
2751
2752 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2753 "tx_packets", CTLFLAG_RD, &sc->tx_packets,
2754 "Tx packets");
2755
2756 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2757 "tx_skip", CTLFLAG_RD, &sc->tx_skip,
2758 "Tx skip count for GDMA ports");
2759
2760 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2761 "tx_collision", CTLFLAG_RD, &sc->tx_collision,
2762 "Tx collision count for GDMA ports");
2763 }
2764
2765 #if defined(IF_RT_PHY_SUPPORT) || defined(RT_MDIO)
2766 /* This code is only work RT2880 and same chip. */
2767 /* TODO: make RT3052 and later support code. But nobody need it? */
2768 static int
rt_miibus_readreg(device_t dev,int phy,int reg)2769 rt_miibus_readreg(device_t dev, int phy, int reg)
2770 {
2771 struct rt_softc *sc = device_get_softc(dev);
2772 int dat;
2773
2774 /*
2775 * PSEUDO_PHYAD is a special value for indicate switch attached.
2776 * No one PHY use PSEUDO_PHYAD (0x1e) address.
2777 */
2778 #ifndef RT_MDIO
2779 if (phy == 31) {
2780 /* Fake PHY ID for bfeswitch attach */
2781 switch (reg) {
2782 case MII_BMSR:
2783 return (BMSR_EXTSTAT|BMSR_MEDIAMASK);
2784 case MII_PHYIDR1:
2785 return (0x40); /* As result of faking */
2786 case MII_PHYIDR2: /* PHY will detect as */
2787 return (0x6250); /* bfeswitch */
2788 }
2789 }
2790 #endif
2791
2792 /* Wait prev command done if any */
2793 while (RT_READ(sc, MDIO_ACCESS) & MDIO_CMD_ONGO);
2794 dat = ((phy << MDIO_PHY_ADDR_SHIFT) & MDIO_PHY_ADDR_MASK) |
2795 ((reg << MDIO_PHYREG_ADDR_SHIFT) & MDIO_PHYREG_ADDR_MASK);
2796 RT_WRITE(sc, MDIO_ACCESS, dat);
2797 RT_WRITE(sc, MDIO_ACCESS, dat | MDIO_CMD_ONGO);
2798 while (RT_READ(sc, MDIO_ACCESS) & MDIO_CMD_ONGO);
2799
2800 return (RT_READ(sc, MDIO_ACCESS) & MDIO_PHY_DATA_MASK);
2801 }
2802
2803 static int
rt_miibus_writereg(device_t dev,int phy,int reg,int val)2804 rt_miibus_writereg(device_t dev, int phy, int reg, int val)
2805 {
2806 struct rt_softc *sc = device_get_softc(dev);
2807 int dat;
2808
2809 /* Wait prev command done if any */
2810 while (RT_READ(sc, MDIO_ACCESS) & MDIO_CMD_ONGO);
2811 dat = MDIO_CMD_WR |
2812 ((phy << MDIO_PHY_ADDR_SHIFT) & MDIO_PHY_ADDR_MASK) |
2813 ((reg << MDIO_PHYREG_ADDR_SHIFT) & MDIO_PHYREG_ADDR_MASK) |
2814 (val & MDIO_PHY_DATA_MASK);
2815 RT_WRITE(sc, MDIO_ACCESS, dat);
2816 RT_WRITE(sc, MDIO_ACCESS, dat | MDIO_CMD_ONGO);
2817 while (RT_READ(sc, MDIO_ACCESS) & MDIO_CMD_ONGO);
2818
2819 return (0);
2820 }
2821 #endif
2822
2823 #ifdef IF_RT_PHY_SUPPORT
2824 void
rt_miibus_statchg(device_t dev)2825 rt_miibus_statchg(device_t dev)
2826 {
2827 struct rt_softc *sc = device_get_softc(dev);
2828 struct mii_data *mii;
2829
2830 mii = device_get_softc(sc->rt_miibus);
2831
2832 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
2833 (IFM_ACTIVE | IFM_AVALID)) {
2834 switch (IFM_SUBTYPE(mii->mii_media_active)) {
2835 case IFM_10_T:
2836 case IFM_100_TX:
2837 /* XXX check link here */
2838 sc->flags |= 1;
2839 break;
2840 default:
2841 break;
2842 }
2843 }
2844 }
2845 #endif /* IF_RT_PHY_SUPPORT */
2846
2847 static device_method_t rt_dev_methods[] =
2848 {
2849 DEVMETHOD(device_probe, rt_probe),
2850 DEVMETHOD(device_attach, rt_attach),
2851 DEVMETHOD(device_detach, rt_detach),
2852 DEVMETHOD(device_shutdown, rt_shutdown),
2853 DEVMETHOD(device_suspend, rt_suspend),
2854 DEVMETHOD(device_resume, rt_resume),
2855
2856 #ifdef IF_RT_PHY_SUPPORT
2857 /* MII interface */
2858 DEVMETHOD(miibus_readreg, rt_miibus_readreg),
2859 DEVMETHOD(miibus_writereg, rt_miibus_writereg),
2860 DEVMETHOD(miibus_statchg, rt_miibus_statchg),
2861 #endif
2862
2863 DEVMETHOD_END
2864 };
2865
2866 static driver_t rt_driver =
2867 {
2868 "rt",
2869 rt_dev_methods,
2870 sizeof(struct rt_softc)
2871 };
2872
2873 static devclass_t rt_dev_class;
2874
2875 DRIVER_MODULE(rt, nexus, rt_driver, rt_dev_class, 0, 0);
2876 #ifdef FDT
2877 DRIVER_MODULE(rt, simplebus, rt_driver, rt_dev_class, 0, 0);
2878 #endif
2879
2880 MODULE_DEPEND(rt, ether, 1, 1, 1);
2881 MODULE_DEPEND(rt, miibus, 1, 1, 1);
2882
2883 #ifdef RT_MDIO
2884 MODULE_DEPEND(rt, mdio, 1, 1, 1);
2885
2886 static int rtmdio_probe(device_t);
2887 static int rtmdio_attach(device_t);
2888 static int rtmdio_detach(device_t);
2889
2890 static struct mtx miibus_mtx;
2891
2892 MTX_SYSINIT(miibus_mtx, &miibus_mtx, "rt mii lock", MTX_DEF);
2893
2894 /*
2895 * Declare an additional, separate driver for accessing the MDIO bus.
2896 */
2897 static device_method_t rtmdio_methods[] = {
2898 /* Device interface */
2899 DEVMETHOD(device_probe, rtmdio_probe),
2900 DEVMETHOD(device_attach, rtmdio_attach),
2901 DEVMETHOD(device_detach, rtmdio_detach),
2902
2903 /* bus interface */
2904 DEVMETHOD(bus_add_child, device_add_child_ordered),
2905
2906 /* MDIO access */
2907 DEVMETHOD(mdio_readreg, rt_miibus_readreg),
2908 DEVMETHOD(mdio_writereg, rt_miibus_writereg),
2909 };
2910
2911 DEFINE_CLASS_0(rtmdio, rtmdio_driver, rtmdio_methods,
2912 sizeof(struct rt_softc));
2913 static devclass_t rtmdio_devclass;
2914
2915 DRIVER_MODULE(miiproxy, rt, miiproxy_driver, miiproxy_devclass, 0, 0);
2916 DRIVER_MODULE(rtmdio, simplebus, rtmdio_driver, rtmdio_devclass, 0, 0);
2917 DRIVER_MODULE(mdio, rtmdio, mdio_driver, mdio_devclass, 0, 0);
2918
2919 static int
rtmdio_probe(device_t dev)2920 rtmdio_probe(device_t dev)
2921 {
2922 if (!ofw_bus_status_okay(dev))
2923 return (ENXIO);
2924
2925 if (!ofw_bus_is_compatible(dev, "ralink,rt2880-mdio"))
2926 return (ENXIO);
2927
2928 device_set_desc(dev, "RT built-in ethernet interface, MDIO controller");
2929 return(0);
2930 }
2931
2932 static int
rtmdio_attach(device_t dev)2933 rtmdio_attach(device_t dev)
2934 {
2935 struct rt_softc *sc;
2936 int error;
2937
2938 sc = device_get_softc(dev);
2939 sc->dev = dev;
2940 sc->mem_rid = 0;
2941 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
2942 &sc->mem_rid, RF_ACTIVE | RF_SHAREABLE);
2943 if (sc->mem == NULL) {
2944 device_printf(dev, "couldn't map memory\n");
2945 error = ENXIO;
2946 goto fail;
2947 }
2948
2949 sc->bst = rman_get_bustag(sc->mem);
2950 sc->bsh = rman_get_bushandle(sc->mem);
2951
2952 bus_generic_probe(dev);
2953 bus_enumerate_hinted_children(dev);
2954 error = bus_generic_attach(dev);
2955 fail:
2956 return(error);
2957 }
2958
2959 static int
rtmdio_detach(device_t dev)2960 rtmdio_detach(device_t dev)
2961 {
2962 return(0);
2963 }
2964 #endif
2965