1 /*
2 * Copyright (c) 2018-2019 Cavium, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 #ifndef __QLNXR_CM_H__
29 #define __QLNXR_CM_H__
30
31 /* ECORE LL2 has a limit to the number of buffers it can handle.
32 * FYI, OFED used 512 and 128 for recv and send.
33 */
34 #define QLNXR_GSI_MAX_RECV_WR (4096)
35 #define QLNXR_GSI_MAX_SEND_WR (4096)
36
37 #define QLNXR_GSI_MAX_RECV_SGE (1) /* LL2 FW limitation */
38
39 /* future OFED/kernel will have these */
40 #define ETH_P_ROCE (0x8915)
41 #define QLNXR_ROCE_V2_UDP_SPORT (0000)
42
43 #if __FreeBSD_version >= 1102000
44
45 #define rdma_wr(_wr) rdma_wr(_wr)
46 #define ud_wr(_wr) ud_wr(_wr)
47 #define atomic_wr(_wr) atomic_wr(_wr)
48
49 #else
50
51 #define rdma_wr(_wr) (&(_wr->wr.rdma))
52 #define ud_wr(_wr) (&(_wr->wr.ud))
53 #define atomic_wr(_wr) (&(_wr->wr.atomic))
54
55 #endif /* #if __FreeBSD_version >= 1102000 */
56
qlnxr_get_ipv4_from_gid(u8 * gid)57 static inline u32 qlnxr_get_ipv4_from_gid(u8 *gid)
58 {
59 return *(u32 *)(void *)&gid[12];
60 }
61
62 struct ecore_roce_ll2_header {
63 void *vaddr;
64 dma_addr_t baddr;
65 size_t len;
66 };
67
68 struct ecore_roce_ll2_buffer {
69 dma_addr_t baddr;
70 size_t len;
71 };
72
73 struct ecore_roce_ll2_packet {
74 struct ecore_roce_ll2_header header;
75 int n_seg;
76 struct ecore_roce_ll2_buffer payload[RDMA_MAX_SGE_PER_SQ_WQE];
77 int roce_mode;
78 enum ecore_roce_ll2_tx_dest tx_dest;
79 };
80
81 /* RDMA CM */
82
83 extern int qlnxr_gsi_poll_cq(struct ib_cq *ibcq,
84 int num_entries,
85 struct ib_wc *wc);
86
87 extern int qlnxr_gsi_post_recv(struct ib_qp *ibqp,
88 const struct ib_recv_wr *wr,
89 const struct ib_recv_wr **bad_wr);
90
91 extern int qlnxr_gsi_post_send(struct ib_qp *ibqp,
92 const struct ib_send_wr *wr,
93 const struct ib_send_wr **bad_wr);
94
95 extern struct ib_qp* qlnxr_create_gsi_qp(struct qlnxr_dev *dev,
96 struct ib_qp_init_attr *attrs,
97 struct qlnxr_qp *qp);
98
99 extern void qlnxr_store_gsi_qp_cq(struct qlnxr_dev *dev,
100 struct qlnxr_qp *qp,
101 struct ib_qp_init_attr *attrs);
102
103 extern void qlnxr_inc_sw_gsi_cons(struct qlnxr_qp_hwq_info *info);
104
105 extern int qlnxr_destroy_gsi_qp(struct qlnxr_dev *dev);
106
107 #endif /* #ifndef __QLNXR_CM_H__ */
108