1 /* SPDX-License-Identifier: BSD-2-Clause AND BSD-3-Clause */
2 /*
3 * Copyright (c) 2020 Rubicon Communications, LLC (Netgate)
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in
12 * the documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 /*
28 * Copyright(c) 2014 - 2020 Intel Corporation.
29 * Redistribution and use in source and binary forms, with or without
30 * modification, are permitted provided that the following conditions
31 * are met:
32 *
33 * * Redistributions of source code must retain the above copyright
34 * notice, this list of conditions and the following disclaimer.
35 * * Redistributions in binary form must reproduce the above copyright
36 * notice, this list of conditions and the following disclaimer in
37 * the documentation and/or other materials provided with the
38 * distribution.
39 * * Neither the name of Intel Corporation nor the names of its
40 * contributors may be used to endorse or promote products derived
41 * from this software without specific prior written permission.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 */
55
56 #include <sys/cdefs.h>
57 #include <sys/param.h>
58 #include <sys/bus.h>
59
60 #include <machine/bus.h>
61
62 #include <dev/pci/pcireg.h>
63 #include <dev/pci/pcivar.h>
64
65 #include "qatreg.h"
66 #include "qatvar.h"
67 #include "qat_hw17reg.h"
68 #include "qat_hw17var.h"
69 #include "qat_dh895xccreg.h"
70
71 static uint32_t
qat_dh895xcc_get_accel_mask(struct qat_softc * sc)72 qat_dh895xcc_get_accel_mask(struct qat_softc *sc)
73 {
74 uint32_t fusectl, strap;
75
76 fusectl = pci_read_config(sc->sc_dev, FUSECTL_REG, 4);
77 strap = pci_read_config(sc->sc_dev, SOFTSTRAP_REG_DH895XCC, 4);
78
79 return (((~(fusectl | strap)) >> ACCEL_REG_OFFSET_DH895XCC) &
80 ACCEL_MASK_DH895XCC);
81 }
82
83 static uint32_t
qat_dh895xcc_get_ae_mask(struct qat_softc * sc)84 qat_dh895xcc_get_ae_mask(struct qat_softc *sc)
85 {
86 uint32_t fusectl, strap;
87
88 fusectl = pci_read_config(sc->sc_dev, FUSECTL_REG, 4);
89 strap = pci_read_config(sc->sc_dev, SOFTSTRAP_REG_DH895XCC, 4);
90
91 return (~(fusectl | strap)) & AE_MASK_DH895XCC;
92 }
93
94 static enum qat_sku
qat_dh895xcc_get_sku(struct qat_softc * sc)95 qat_dh895xcc_get_sku(struct qat_softc *sc)
96 {
97 uint32_t fusectl, sku;
98
99 fusectl = pci_read_config(sc->sc_dev, FUSECTL_REG, 4);
100 sku = (fusectl & FUSECTL_SKU_MASK_DH895XCC) >>
101 FUSECTL_SKU_SHIFT_DH895XCC;
102 switch (sku) {
103 case FUSECTL_SKU_1_DH895XCC:
104 return QAT_SKU_1;
105 case FUSECTL_SKU_2_DH895XCC:
106 return QAT_SKU_2;
107 case FUSECTL_SKU_3_DH895XCC:
108 return QAT_SKU_3;
109 case FUSECTL_SKU_4_DH895XCC:
110 return QAT_SKU_4;
111 default:
112 return QAT_SKU_UNKNOWN;
113 }
114 }
115
116 static uint32_t
qat_dh895xcc_get_accel_cap(struct qat_softc * sc)117 qat_dh895xcc_get_accel_cap(struct qat_softc *sc)
118 {
119 uint32_t cap, legfuse;
120
121 legfuse = pci_read_config(sc->sc_dev, LEGFUSE_REG, 4);
122
123 cap = QAT_ACCEL_CAP_CRYPTO_SYMMETRIC +
124 QAT_ACCEL_CAP_CRYPTO_ASYMMETRIC +
125 QAT_ACCEL_CAP_CIPHER +
126 QAT_ACCEL_CAP_AUTHENTICATION +
127 QAT_ACCEL_CAP_COMPRESSION +
128 QAT_ACCEL_CAP_ZUC +
129 QAT_ACCEL_CAP_SHA3;
130
131 if (legfuse & LEGFUSE_ACCEL_MASK_CIPHER_SLICE) {
132 cap &= ~QAT_ACCEL_CAP_CRYPTO_SYMMETRIC;
133 cap &= ~QAT_ACCEL_CAP_CIPHER;
134 }
135 if (legfuse & LEGFUSE_ACCEL_MASK_AUTH_SLICE)
136 cap &= ~QAT_ACCEL_CAP_AUTHENTICATION;
137 if (legfuse & LEGFUSE_ACCEL_MASK_PKE_SLICE)
138 cap &= ~QAT_ACCEL_CAP_CRYPTO_ASYMMETRIC;
139 if (legfuse & LEGFUSE_ACCEL_MASK_COMPRESS_SLICE)
140 cap &= ~QAT_ACCEL_CAP_COMPRESSION;
141 if (legfuse & LEGFUSE_ACCEL_MASK_EIA3_SLICE)
142 cap &= ~QAT_ACCEL_CAP_ZUC;
143
144 return cap;
145 }
146
147 static const char *
qat_dh895xcc_get_fw_uof_name(struct qat_softc * sc)148 qat_dh895xcc_get_fw_uof_name(struct qat_softc *sc)
149 {
150 return AE_FW_UOF_NAME_DH895XCC;
151 }
152
153 static void
qat_dh895xcc_enable_intr(struct qat_softc * sc)154 qat_dh895xcc_enable_intr(struct qat_softc *sc)
155 {
156 /* Enable bundle and misc interrupts */
157 qat_misc_write_4(sc, SMIAPF0_DH895XCC, SMIA0_MASK_DH895XCC);
158 qat_misc_write_4(sc, SMIAPF1_DH895XCC, SMIA1_MASK_DH895XCC);
159 }
160
161 /* Worker thread to service arbiter mappings based on dev SKUs */
162 static uint32_t thrd_to_arb_map_sku4[] = {
163 0x12222AAA, 0x11666666, 0x12222AAA, 0x11666666,
164 0x12222AAA, 0x11222222, 0x12222AAA, 0x11222222,
165 0x00000000, 0x00000000, 0x00000000, 0x00000000,
166 };
167
168 static uint32_t thrd_to_arb_map_sku6[] = {
169 0x12222AAA, 0x11666666, 0x12222AAA, 0x11666666,
170 0x12222AAA, 0x11222222, 0x12222AAA, 0x11222222,
171 0x12222AAA, 0x11222222, 0x12222AAA, 0x11222222,
172 };
173
174 static void
qat_dh895xcc_get_arb_mapping(struct qat_softc * sc,const uint32_t ** arb_map_config)175 qat_dh895xcc_get_arb_mapping(struct qat_softc *sc,
176 const uint32_t **arb_map_config)
177 {
178 uint32_t *map, sku;
179 int i;
180
181 sku = qat_dh895xcc_get_sku(sc);
182 switch (sku) {
183 case QAT_SKU_1:
184 map = thrd_to_arb_map_sku4;
185 break;
186 case QAT_SKU_2:
187 case QAT_SKU_4:
188 map = thrd_to_arb_map_sku6;
189 break;
190 default:
191 *arb_map_config = NULL;
192 return;
193 }
194
195 for (i = 1; i < MAX_AE_DH895XCC; i++) {
196 if ((~sc->sc_ae_mask) & (1 << i))
197 map[i] = 0;
198 }
199 *arb_map_config = map;
200 }
201
202 static void
qat_dh895xcc_enable_error_correction(struct qat_softc * sc)203 qat_dh895xcc_enable_error_correction(struct qat_softc *sc)
204 {
205 uint32_t mask;
206 u_int i;
207
208 /* Enable Accel Engine error detection & correction */
209 for (i = 0, mask = sc->sc_ae_mask; mask; i++, mask >>= 1) {
210 if (!(mask & 1))
211 continue;
212 qat_misc_read_write_or_4(sc, AE_CTX_ENABLES_DH895XCC(i),
213 ENABLE_AE_ECC_ERR_DH895XCC);
214 qat_misc_read_write_or_4(sc, AE_MISC_CONTROL_DH895XCC(i),
215 ENABLE_AE_ECC_PARITY_CORR_DH895XCC);
216 }
217
218 /* Enable shared memory error detection & correction */
219 for (i = 0, mask = sc->sc_accel_mask; mask; i++, mask >>= 1) {
220 if (!(mask & 1))
221 continue;
222
223 qat_misc_read_write_or_4(sc, UERRSSMSH(i), ERRSSMSH_EN_DH895XCC);
224 qat_misc_read_write_or_4(sc, CERRSSMSH(i), ERRSSMSH_EN_DH895XCC);
225 qat_misc_read_write_or_4(sc, PPERR(i), PPERR_EN_DH895XCC);
226 }
227 }
228
229 const struct qat_hw qat_hw_dh895xcc = {
230 .qhw_sram_bar_id = BAR_SRAM_ID_DH895XCC,
231 .qhw_misc_bar_id = BAR_PMISC_ID_DH895XCC,
232 .qhw_etr_bar_id = BAR_ETR_ID_DH895XCC,
233 .qhw_cap_global_offset = CAP_GLOBAL_OFFSET_DH895XCC,
234 .qhw_ae_offset = AE_OFFSET_DH895XCC,
235 .qhw_ae_local_offset = AE_LOCAL_OFFSET_DH895XCC,
236 .qhw_etr_bundle_size = ETR_BUNDLE_SIZE_DH895XCC,
237 .qhw_num_banks = ETR_MAX_BANKS_DH895XCC,
238 .qhw_num_rings_per_bank = ETR_MAX_RINGS_PER_BANK,
239 .qhw_num_accel = MAX_ACCEL_DH895XCC,
240 .qhw_num_engines = MAX_AE_DH895XCC,
241 .qhw_tx_rx_gap = ETR_TX_RX_GAP_DH895XCC,
242 .qhw_tx_rings_mask = ETR_TX_RINGS_MASK_DH895XCC,
243 .qhw_clock_per_sec = CLOCK_PER_SEC_DH895XCC,
244 .qhw_fw_auth = false,
245 .qhw_fw_req_size = FW_REQ_DEFAULT_SZ_HW17,
246 .qhw_fw_resp_size = FW_RESP_DEFAULT_SZ_HW17,
247 .qhw_ring_asym_tx = 0,
248 .qhw_ring_asym_rx = 8,
249 .qhw_ring_sym_tx = 2,
250 .qhw_ring_sym_rx = 10,
251 .qhw_mof_fwname = AE_FW_MOF_NAME_DH895XCC,
252 .qhw_mmp_fwname = AE_FW_MMP_NAME_DH895XCC,
253 .qhw_prod_type = AE_FW_PROD_TYPE_DH895XCC,
254 .qhw_get_accel_mask = qat_dh895xcc_get_accel_mask,
255 .qhw_get_ae_mask = qat_dh895xcc_get_ae_mask,
256 .qhw_get_sku = qat_dh895xcc_get_sku,
257 .qhw_get_accel_cap = qat_dh895xcc_get_accel_cap,
258 .qhw_get_fw_uof_name = qat_dh895xcc_get_fw_uof_name,
259 .qhw_enable_intr = qat_dh895xcc_enable_intr,
260 .qhw_init_admin_comms = qat_adm_mailbox_init,
261 .qhw_send_admin_init = qat_adm_mailbox_send_init,
262 .qhw_init_arb = qat_arb_init,
263 .qhw_get_arb_mapping = qat_dh895xcc_get_arb_mapping,
264 .qhw_enable_error_correction = qat_dh895xcc_enable_error_correction,
265 .qhw_check_slice_hang = qat_check_slice_hang,
266 .qhw_crypto_setup_desc = qat_hw17_crypto_setup_desc,
267 .qhw_crypto_setup_req_params = qat_hw17_crypto_setup_req_params,
268 .qhw_crypto_opaque_offset = offsetof(struct fw_la_resp, opaque_data),
269 };
270