1 /*-
2 * Copyright (c) 2015, 2020 Ruslan Bukin <br@bsdpad.com>
3 * Copyright (c) 2014 The FreeBSD Foundation
4 * All rights reserved.
5 *
6 * This software was developed by Semihalf under
7 * the sponsorship of the FreeBSD Foundation.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31 /* Generic ECAM PCIe driver */
32
33 #include <sys/cdefs.h>
34 #include "opt_platform.h"
35
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/malloc.h>
39 #include <sys/kernel.h>
40 #include <sys/rman.h>
41 #include <sys/module.h>
42 #include <sys/bus.h>
43 #include <sys/endian.h>
44
45 #include <dev/pci/pcivar.h>
46 #include <dev/pci/pcireg.h>
47 #include <dev/pci/pcib_private.h>
48 #include <dev/pci/pci_host_generic.h>
49
50 #include <machine/bus.h>
51 #include <machine/intr.h>
52
53 #include "pcib_if.h"
54
55 /* Forward prototypes */
56
57 static uint32_t generic_pcie_read_config(device_t dev, u_int bus, u_int slot,
58 u_int func, u_int reg, int bytes);
59 static void generic_pcie_write_config(device_t dev, u_int bus, u_int slot,
60 u_int func, u_int reg, uint32_t val, int bytes);
61 static int generic_pcie_maxslots(device_t dev);
62 static int generic_pcie_read_ivar(device_t dev, device_t child, int index,
63 uintptr_t *result);
64 static int generic_pcie_write_ivar(device_t dev, device_t child, int index,
65 uintptr_t value);
66
67 int
pci_host_generic_core_attach(device_t dev)68 pci_host_generic_core_attach(device_t dev)
69 {
70 struct generic_pcie_core_softc *sc;
71 uint64_t phys_base;
72 uint64_t pci_base;
73 uint64_t size;
74 int error;
75 int rid, tuple;
76
77 sc = device_get_softc(dev);
78 sc->dev = dev;
79
80 /* Create the parent DMA tag to pass down the coherent flag */
81 error = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
82 1, 0, /* alignment, bounds */
83 BUS_SPACE_MAXADDR, /* lowaddr */
84 BUS_SPACE_MAXADDR, /* highaddr */
85 NULL, NULL, /* filter, filterarg */
86 BUS_SPACE_MAXSIZE, /* maxsize */
87 BUS_SPACE_UNRESTRICTED, /* nsegments */
88 BUS_SPACE_MAXSIZE, /* maxsegsize */
89 sc->coherent ? BUS_DMA_COHERENT : 0, /* flags */
90 NULL, NULL, /* lockfunc, lockarg */
91 &sc->dmat);
92 if (error != 0)
93 return (error);
94
95 rid = 0;
96 sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
97 if (sc->res == NULL) {
98 device_printf(dev, "could not allocate memory.\n");
99 error = ENXIO;
100 goto err_resource;
101 }
102
103 sc->bst = rman_get_bustag(sc->res);
104 sc->bsh = rman_get_bushandle(sc->res);
105
106 sc->has_pmem = false;
107 sc->pmem_rman.rm_type = RMAN_ARRAY;
108 sc->pmem_rman.rm_descr = "PCIe Prefetch Memory";
109
110 sc->mem_rman.rm_type = RMAN_ARRAY;
111 sc->mem_rman.rm_descr = "PCIe Memory";
112
113 sc->io_rman.rm_type = RMAN_ARRAY;
114 sc->io_rman.rm_descr = "PCIe IO window";
115
116 /* Initialize rman and allocate memory regions */
117 error = rman_init(&sc->pmem_rman);
118 if (error) {
119 device_printf(dev, "rman_init() failed. error = %d\n", error);
120 goto err_pmem_rman;
121 }
122
123 error = rman_init(&sc->mem_rman);
124 if (error) {
125 device_printf(dev, "rman_init() failed. error = %d\n", error);
126 goto err_mem_rman;
127 }
128
129 error = rman_init(&sc->io_rman);
130 if (error) {
131 device_printf(dev, "rman_init() failed. error = %d\n", error);
132 goto err_io_rman;
133 }
134
135 for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) {
136 phys_base = sc->ranges[tuple].phys_base;
137 pci_base = sc->ranges[tuple].pci_base;
138 size = sc->ranges[tuple].size;
139 if (phys_base == 0 || size == 0)
140 continue; /* empty range element */
141 switch (FLAG_TYPE(sc->ranges[tuple].flags)) {
142 case FLAG_TYPE_PMEM:
143 sc->has_pmem = true;
144 error = rman_manage_region(&sc->pmem_rman,
145 pci_base, pci_base + size - 1);
146 break;
147 case FLAG_TYPE_MEM:
148 error = rman_manage_region(&sc->mem_rman,
149 pci_base, pci_base + size - 1);
150 break;
151 case FLAG_TYPE_IO:
152 error = rman_manage_region(&sc->io_rman,
153 pci_base, pci_base + size - 1);
154 break;
155 default:
156 continue;
157 }
158 if (error) {
159 device_printf(dev, "rman_manage_region() failed."
160 "error = %d\n", error);
161 goto err_rman_manage;
162 }
163 }
164
165 return (0);
166
167 err_rman_manage:
168 rman_fini(&sc->io_rman);
169 err_io_rman:
170 rman_fini(&sc->mem_rman);
171 err_mem_rman:
172 rman_fini(&sc->pmem_rman);
173 err_pmem_rman:
174 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->res);
175 err_resource:
176 bus_dma_tag_destroy(sc->dmat);
177 return (error);
178 }
179
180 int
pci_host_generic_core_detach(device_t dev)181 pci_host_generic_core_detach(device_t dev)
182 {
183 struct generic_pcie_core_softc *sc;
184 int error;
185
186 sc = device_get_softc(dev);
187
188 error = bus_generic_detach(dev);
189 if (error != 0)
190 return (error);
191
192 rman_fini(&sc->io_rman);
193 rman_fini(&sc->mem_rman);
194 rman_fini(&sc->pmem_rman);
195 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->res);
196 bus_dma_tag_destroy(sc->dmat);
197
198 return (0);
199 }
200
201 static uint32_t
generic_pcie_read_config(device_t dev,u_int bus,u_int slot,u_int func,u_int reg,int bytes)202 generic_pcie_read_config(device_t dev, u_int bus, u_int slot,
203 u_int func, u_int reg, int bytes)
204 {
205 struct generic_pcie_core_softc *sc;
206 bus_space_handle_t h;
207 bus_space_tag_t t;
208 uint64_t offset;
209 uint32_t data;
210
211 sc = device_get_softc(dev);
212 if ((bus < sc->bus_start) || (bus > sc->bus_end))
213 return (~0U);
214 if ((slot > PCI_SLOTMAX) || (func > PCI_FUNCMAX) ||
215 (reg > PCIE_REGMAX))
216 return (~0U);
217 if ((sc->quirks & PCIE_ECAM_DESIGNWARE_QUIRK) && bus == 0 && slot > 0)
218 return (~0U);
219
220 offset = PCIE_ADDR_OFFSET(bus - sc->bus_start, slot, func, reg);
221 t = sc->bst;
222 h = sc->bsh;
223
224 switch (bytes) {
225 case 1:
226 data = bus_space_read_1(t, h, offset);
227 break;
228 case 2:
229 data = le16toh(bus_space_read_2(t, h, offset));
230 break;
231 case 4:
232 data = le32toh(bus_space_read_4(t, h, offset));
233 break;
234 default:
235 return (~0U);
236 }
237
238 return (data);
239 }
240
241 static void
generic_pcie_write_config(device_t dev,u_int bus,u_int slot,u_int func,u_int reg,uint32_t val,int bytes)242 generic_pcie_write_config(device_t dev, u_int bus, u_int slot,
243 u_int func, u_int reg, uint32_t val, int bytes)
244 {
245 struct generic_pcie_core_softc *sc;
246 bus_space_handle_t h;
247 bus_space_tag_t t;
248 uint64_t offset;
249
250 sc = device_get_softc(dev);
251 if ((bus < sc->bus_start) || (bus > sc->bus_end))
252 return;
253 if ((slot > PCI_SLOTMAX) || (func > PCI_FUNCMAX) ||
254 (reg > PCIE_REGMAX))
255 return;
256
257 offset = PCIE_ADDR_OFFSET(bus - sc->bus_start, slot, func, reg);
258
259 t = sc->bst;
260 h = sc->bsh;
261
262 switch (bytes) {
263 case 1:
264 bus_space_write_1(t, h, offset, val);
265 break;
266 case 2:
267 bus_space_write_2(t, h, offset, htole16(val));
268 break;
269 case 4:
270 bus_space_write_4(t, h, offset, htole32(val));
271 break;
272 default:
273 return;
274 }
275 }
276
277 static int
generic_pcie_maxslots(device_t dev)278 generic_pcie_maxslots(device_t dev)
279 {
280
281 return (31); /* max slots per bus acc. to standard */
282 }
283
284 static int
generic_pcie_read_ivar(device_t dev,device_t child,int index,uintptr_t * result)285 generic_pcie_read_ivar(device_t dev, device_t child, int index,
286 uintptr_t *result)
287 {
288 struct generic_pcie_core_softc *sc;
289
290 sc = device_get_softc(dev);
291
292 if (index == PCIB_IVAR_BUS) {
293 *result = sc->bus_start;
294 return (0);
295 }
296
297 if (index == PCIB_IVAR_DOMAIN) {
298 *result = sc->ecam;
299 return (0);
300 }
301
302 if (bootverbose)
303 device_printf(dev, "ERROR: Unknown index %d.\n", index);
304 return (ENOENT);
305 }
306
307 static int
generic_pcie_write_ivar(device_t dev,device_t child,int index,uintptr_t value)308 generic_pcie_write_ivar(device_t dev, device_t child, int index,
309 uintptr_t value)
310 {
311
312 return (ENOENT);
313 }
314
315 static struct rman *
generic_pcie_rman(struct generic_pcie_core_softc * sc,int type,int flags)316 generic_pcie_rman(struct generic_pcie_core_softc *sc, int type, int flags)
317 {
318
319 switch (type) {
320 case SYS_RES_IOPORT:
321 return (&sc->io_rman);
322 case SYS_RES_MEMORY:
323 if (sc->has_pmem && (flags & RF_PREFETCHABLE) != 0)
324 return (&sc->pmem_rman);
325 return (&sc->mem_rman);
326 default:
327 break;
328 }
329
330 return (NULL);
331 }
332
333 int
pci_host_generic_core_release_resource(device_t dev,device_t child,int type,int rid,struct resource * res)334 pci_host_generic_core_release_resource(device_t dev, device_t child, int type,
335 int rid, struct resource *res)
336 {
337 struct generic_pcie_core_softc *sc;
338 struct rman *rm;
339
340 sc = device_get_softc(dev);
341
342 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
343 if (type == PCI_RES_BUS) {
344 return (pci_domain_release_bus(sc->ecam, child, rid, res));
345 }
346 #endif
347
348 rm = generic_pcie_rman(sc, type, rman_get_flags(res));
349 if (rm != NULL) {
350 KASSERT(rman_is_region_manager(res, rm), ("rman mismatch"));
351 rman_release_resource(res);
352 }
353
354 return (bus_generic_release_resource(dev, child, type, rid, res));
355 }
356
357 static bool
generic_pcie_translate_resource(device_t dev,int type,rman_res_t start,rman_res_t end,rman_res_t * new_start,rman_res_t * new_end)358 generic_pcie_translate_resource(device_t dev, int type, rman_res_t start,
359 rman_res_t end, rman_res_t *new_start, rman_res_t *new_end)
360 {
361 struct generic_pcie_core_softc *sc;
362 uint64_t phys_base;
363 uint64_t pci_base;
364 uint64_t size;
365 int i, space;
366 bool found;
367
368 sc = device_get_softc(dev);
369 /* Translate the address from a PCI address to a physical address */
370 switch (type) {
371 case SYS_RES_IOPORT:
372 case SYS_RES_MEMORY:
373 found = false;
374 for (i = 0; i < MAX_RANGES_TUPLES; i++) {
375 pci_base = sc->ranges[i].pci_base;
376 phys_base = sc->ranges[i].phys_base;
377 size = sc->ranges[i].size;
378
379 if (start < pci_base || start >= pci_base + size)
380 continue;
381
382 switch (FLAG_TYPE(sc->ranges[i].flags)) {
383 case FLAG_TYPE_MEM:
384 case FLAG_TYPE_PMEM:
385 space = SYS_RES_MEMORY;
386 break;
387 case FLAG_TYPE_IO:
388 space = SYS_RES_IOPORT;
389 break;
390 default:
391 space = -1;
392 continue;
393 }
394
395 if (type == space) {
396 *new_start = start - pci_base + phys_base;
397 *new_end = end - pci_base + phys_base;
398 found = true;
399 break;
400 }
401 }
402 break;
403 default:
404 /* No translation for non-memory types */
405 *new_start = start;
406 *new_end = end;
407 found = true;
408 break;
409 }
410
411 return (found);
412 }
413
414 struct resource *
pci_host_generic_core_alloc_resource(device_t dev,device_t child,int type,int * rid,rman_res_t start,rman_res_t end,rman_res_t count,u_int flags)415 pci_host_generic_core_alloc_resource(device_t dev, device_t child, int type,
416 int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
417 {
418 struct generic_pcie_core_softc *sc;
419 struct resource *res;
420 struct rman *rm;
421
422 sc = device_get_softc(dev);
423
424 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
425 if (type == PCI_RES_BUS) {
426 return (pci_domain_alloc_bus(sc->ecam, child, rid, start, end,
427 count, flags));
428 }
429 #endif
430
431 rm = generic_pcie_rman(sc, type, flags);
432 if (rm == NULL)
433 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
434 type, rid, start, end, count, flags));
435
436 if (bootverbose) {
437 device_printf(dev,
438 "rman_reserve_resource: start=%#jx, end=%#jx, count=%#jx\n",
439 start, end, count);
440 }
441
442 res = rman_reserve_resource(rm, start, end, count, flags, child);
443 if (res == NULL)
444 goto fail;
445
446 rman_set_rid(res, *rid);
447
448 if (flags & RF_ACTIVE)
449 if (bus_activate_resource(child, type, *rid, res)) {
450 rman_release_resource(res);
451 goto fail;
452 }
453
454 return (res);
455
456 fail:
457 device_printf(dev, "%s FAIL: type=%d, rid=%d, "
458 "start=%016jx, end=%016jx, count=%016jx, flags=%x\n",
459 __func__, type, *rid, start, end, count, flags);
460
461 return (NULL);
462 }
463
464 static int
generic_pcie_activate_resource(device_t dev,device_t child,int type,int rid,struct resource * r)465 generic_pcie_activate_resource(device_t dev, device_t child, int type,
466 int rid, struct resource *r)
467 {
468 struct generic_pcie_core_softc *sc;
469 rman_res_t start, end;
470 int res;
471
472 sc = device_get_softc(dev);
473
474 if ((res = rman_activate_resource(r)) != 0)
475 return (res);
476
477 start = rman_get_start(r);
478 end = rman_get_end(r);
479 if (!generic_pcie_translate_resource(dev, type, start, end, &start,
480 &end))
481 return (EINVAL);
482 rman_set_start(r, start);
483 rman_set_end(r, end);
484
485 return (BUS_ACTIVATE_RESOURCE(device_get_parent(dev), child, type,
486 rid, r));
487 }
488
489 static int
generic_pcie_deactivate_resource(device_t dev,device_t child,int type,int rid,struct resource * r)490 generic_pcie_deactivate_resource(device_t dev, device_t child, int type,
491 int rid, struct resource *r)
492 {
493 int res;
494
495 if ((res = rman_deactivate_resource(r)) != 0)
496 return (res);
497
498 switch (type) {
499 case SYS_RES_IOPORT:
500 case SYS_RES_MEMORY:
501 case SYS_RES_IRQ:
502 res = BUS_DEACTIVATE_RESOURCE(device_get_parent(dev), child,
503 type, rid, r);
504 break;
505 default:
506 break;
507 }
508
509 return (res);
510 }
511
512 static int
generic_pcie_adjust_resource(device_t dev,device_t child,int type,struct resource * res,rman_res_t start,rman_res_t end)513 generic_pcie_adjust_resource(device_t dev, device_t child, int type,
514 struct resource *res, rman_res_t start, rman_res_t end)
515 {
516 struct generic_pcie_core_softc *sc;
517 struct rman *rm;
518
519 sc = device_get_softc(dev);
520 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
521 if (type == PCI_RES_BUS)
522 return (pci_domain_adjust_bus(sc->ecam, child, res, start,
523 end));
524 #endif
525
526 rm = generic_pcie_rman(sc, type, rman_get_flags(res));
527 if (rm != NULL)
528 return (rman_adjust_resource(res, start, end));
529 return (bus_generic_adjust_resource(dev, child, type, res, start, end));
530 }
531
532 static bus_dma_tag_t
generic_pcie_get_dma_tag(device_t dev,device_t child)533 generic_pcie_get_dma_tag(device_t dev, device_t child)
534 {
535 struct generic_pcie_core_softc *sc;
536
537 sc = device_get_softc(dev);
538 return (sc->dmat);
539 }
540
541 static device_method_t generic_pcie_methods[] = {
542 DEVMETHOD(device_attach, pci_host_generic_core_attach),
543 DEVMETHOD(device_detach, pci_host_generic_core_detach),
544
545 DEVMETHOD(bus_read_ivar, generic_pcie_read_ivar),
546 DEVMETHOD(bus_write_ivar, generic_pcie_write_ivar),
547 DEVMETHOD(bus_alloc_resource, pci_host_generic_core_alloc_resource),
548 DEVMETHOD(bus_adjust_resource, generic_pcie_adjust_resource),
549 DEVMETHOD(bus_activate_resource, generic_pcie_activate_resource),
550 DEVMETHOD(bus_deactivate_resource, generic_pcie_deactivate_resource),
551 DEVMETHOD(bus_release_resource, pci_host_generic_core_release_resource),
552 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
553 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
554
555 DEVMETHOD(bus_get_dma_tag, generic_pcie_get_dma_tag),
556
557 /* pcib interface */
558 DEVMETHOD(pcib_maxslots, generic_pcie_maxslots),
559 DEVMETHOD(pcib_read_config, generic_pcie_read_config),
560 DEVMETHOD(pcib_write_config, generic_pcie_write_config),
561
562 DEVMETHOD_END
563 };
564
565 DEFINE_CLASS_0(pcib, generic_pcie_core_driver,
566 generic_pcie_methods, sizeof(struct generic_pcie_core_softc));
567