1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
3 *
4 * Copyright (C) 2013 Emulex
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the Emulex Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived from
19 * this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 *
33 * Contact Information:
34 * freebsd-drivers@emulex.com
35 *
36 * Emulex
37 * 3333 Susan Street
38 * Costa Mesa, CA 92626
39 */
40
41
42 #include "oce_if.h"
43
44 int
oce_wait_ready(POCE_SOFTC sc)45 oce_wait_ready(POCE_SOFTC sc)
46 {
47 #define SLIPORT_READY_TIMEOUT 30000
48 uint32_t sliport_status, i;
49
50 if (!IS_XE201(sc))
51 return (-1);
52
53 for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) {
54 sliport_status = OCE_READ_REG32(sc, db, SLIPORT_STATUS_OFFSET);
55 if (sliport_status & SLIPORT_STATUS_RDY_MASK)
56 return 0;
57
58 if (sliport_status & SLIPORT_STATUS_ERR_MASK &&
59 !(sliport_status & SLIPORT_STATUS_RN_MASK)) {
60 device_printf(sc->dev, "Error detected in the card\n");
61 return EIO;
62 }
63
64 DELAY(1000);
65 }
66
67 device_printf(sc->dev, "Firmware wait timed out\n");
68
69 return (-1);
70 }
71
72 /**
73 * @brief Reset (firmware) common function
74 * @param sc software handle to the device
75 * @returns 0 on success, ETIMEDOUT on failure
76 */
77 int
oce_reset_fun(POCE_SOFTC sc)78 oce_reset_fun(POCE_SOFTC sc)
79 {
80 struct oce_mbx *mbx;
81 struct oce_bmbx *mb;
82 struct ioctl_common_function_reset *fwcmd;
83 int rc = 0;
84
85 if (IS_XE201(sc)) {
86 OCE_WRITE_REG32(sc, db, SLIPORT_CONTROL_OFFSET,
87 SLI_PORT_CONTROL_IP_MASK);
88
89 rc = oce_wait_ready(sc);
90 if (rc) {
91 device_printf(sc->dev, "Firmware reset Failed\n");
92 }
93
94 return rc;
95 }
96
97 mb = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx);
98 mbx = &mb->mbx;
99 bzero(mbx, sizeof(struct oce_mbx));
100
101 fwcmd = (struct ioctl_common_function_reset *)&mbx->payload;
102 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
103 MBX_SUBSYSTEM_COMMON,
104 OPCODE_COMMON_FUNCTION_RESET,
105 10, /* MBX_TIMEOUT_SEC */
106 sizeof(struct
107 ioctl_common_function_reset),
108 OCE_MBX_VER_V0);
109
110 mbx->u0.s.embedded = 1;
111 mbx->payload_length =
112 sizeof(struct ioctl_common_function_reset);
113
114 rc = oce_mbox_dispatch(sc, 2);
115
116 return rc;
117 }
118
119 /**
120 * @brief This functions tells firmware we are
121 * done with commands.
122 * @param sc software handle to the device
123 * @returns 0 on success, ETIMEDOUT on failure
124 */
125 int
oce_fw_clean(POCE_SOFTC sc)126 oce_fw_clean(POCE_SOFTC sc)
127 {
128 struct oce_bmbx *mbx;
129 uint8_t *ptr;
130 int ret = 0;
131
132 mbx = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx);
133 ptr = (uint8_t *) &mbx->mbx;
134
135 /* Endian Signature */
136 *ptr++ = 0xff;
137 *ptr++ = 0xaa;
138 *ptr++ = 0xbb;
139 *ptr++ = 0xff;
140 *ptr++ = 0xff;
141 *ptr++ = 0xcc;
142 *ptr++ = 0xdd;
143 *ptr = 0xff;
144
145 ret = oce_mbox_dispatch(sc, 2);
146
147 return ret;
148 }
149
150 /**
151 * @brief Mailbox wait
152 * @param sc software handle to the device
153 * @param tmo_sec timeout in seconds
154 */
155 static int
oce_mbox_wait(POCE_SOFTC sc,uint32_t tmo_sec)156 oce_mbox_wait(POCE_SOFTC sc, uint32_t tmo_sec)
157 {
158 tmo_sec *= 10000;
159 pd_mpu_mbox_db_t mbox_db;
160
161 for (;;) {
162 if (tmo_sec != 0) {
163 if (--tmo_sec == 0)
164 break;
165 }
166
167 mbox_db.dw0 = OCE_READ_REG32(sc, db, PD_MPU_MBOX_DB);
168
169 if (mbox_db.bits.ready)
170 return 0;
171
172 DELAY(100);
173 }
174
175 device_printf(sc->dev, "Mailbox timed out\n");
176
177 return ETIMEDOUT;
178 }
179
180 /**
181 * @brief Mailbox dispatch
182 * @param sc software handle to the device
183 * @param tmo_sec timeout in seconds
184 */
185 int
oce_mbox_dispatch(POCE_SOFTC sc,uint32_t tmo_sec)186 oce_mbox_dispatch(POCE_SOFTC sc, uint32_t tmo_sec)
187 {
188 pd_mpu_mbox_db_t mbox_db;
189 uint32_t pa;
190 int rc;
191
192 oce_dma_sync(&sc->bsmbx, BUS_DMASYNC_PREWRITE);
193 pa = (uint32_t) ((uint64_t) sc->bsmbx.paddr >> 34);
194 bzero(&mbox_db, sizeof(pd_mpu_mbox_db_t));
195 mbox_db.bits.ready = 0;
196 mbox_db.bits.hi = 1;
197 mbox_db.bits.address = pa;
198
199 rc = oce_mbox_wait(sc, tmo_sec);
200 if (rc == 0) {
201 OCE_WRITE_REG32(sc, db, PD_MPU_MBOX_DB, mbox_db.dw0);
202
203 pa = (uint32_t) ((uint64_t) sc->bsmbx.paddr >> 4) & 0x3fffffff;
204 mbox_db.bits.ready = 0;
205 mbox_db.bits.hi = 0;
206 mbox_db.bits.address = pa;
207
208 rc = oce_mbox_wait(sc, tmo_sec);
209
210 if (rc == 0) {
211 OCE_WRITE_REG32(sc, db, PD_MPU_MBOX_DB, mbox_db.dw0);
212
213 rc = oce_mbox_wait(sc, tmo_sec);
214
215 oce_dma_sync(&sc->bsmbx, BUS_DMASYNC_POSTWRITE);
216 }
217 }
218
219 return rc;
220 }
221
222 /**
223 * @brief Mailbox common request header initialization
224 * @param hdr mailbox header
225 * @param dom domain
226 * @param port port
227 * @param subsys subsystem
228 * @param opcode opcode
229 * @param timeout timeout
230 * @param pyld_len payload length
231 */
232 void
mbx_common_req_hdr_init(struct mbx_hdr * hdr,uint8_t dom,uint8_t port,uint8_t subsys,uint8_t opcode,uint32_t timeout,uint32_t pyld_len,uint8_t version)233 mbx_common_req_hdr_init(struct mbx_hdr *hdr,
234 uint8_t dom, uint8_t port,
235 uint8_t subsys, uint8_t opcode,
236 uint32_t timeout, uint32_t pyld_len,
237 uint8_t version)
238 {
239 hdr->u0.req.opcode = opcode;
240 hdr->u0.req.subsystem = subsys;
241 hdr->u0.req.port_number = port;
242 hdr->u0.req.domain = dom;
243
244 hdr->u0.req.timeout = timeout;
245 hdr->u0.req.request_length = pyld_len - sizeof(struct mbx_hdr);
246 hdr->u0.req.version = version;
247 }
248
249 /**
250 * @brief Function to initialize the hw with host endian information
251 * @param sc software handle to the device
252 * @returns 0 on success, ETIMEDOUT on failure
253 */
254 int
oce_mbox_init(POCE_SOFTC sc)255 oce_mbox_init(POCE_SOFTC sc)
256 {
257 struct oce_bmbx *mbx;
258 uint8_t *ptr;
259 int ret = 0;
260
261 if (sc->flags & OCE_FLAGS_MBOX_ENDIAN_RQD) {
262 mbx = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx);
263 ptr = (uint8_t *) &mbx->mbx;
264
265 /* Endian Signature */
266 *ptr++ = 0xff;
267 *ptr++ = 0x12;
268 *ptr++ = 0x34;
269 *ptr++ = 0xff;
270 *ptr++ = 0xff;
271 *ptr++ = 0x56;
272 *ptr++ = 0x78;
273 *ptr = 0xff;
274
275 ret = oce_mbox_dispatch(sc, 0);
276 }
277
278 return ret;
279 }
280
281 /**
282 * @brief Function to get the firmware version
283 * @param sc software handle to the device
284 * @returns 0 on success, EIO on failure
285 */
286 int
oce_get_fw_version(POCE_SOFTC sc)287 oce_get_fw_version(POCE_SOFTC sc)
288 {
289 struct oce_mbx mbx;
290 struct mbx_get_common_fw_version *fwcmd;
291 int ret = 0;
292
293 bzero(&mbx, sizeof(struct oce_mbx));
294
295 fwcmd = (struct mbx_get_common_fw_version *)&mbx.payload;
296 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
297 MBX_SUBSYSTEM_COMMON,
298 OPCODE_COMMON_GET_FW_VERSION,
299 MBX_TIMEOUT_SEC,
300 sizeof(struct mbx_get_common_fw_version),
301 OCE_MBX_VER_V0);
302
303 mbx.u0.s.embedded = 1;
304 mbx.payload_length = sizeof(struct mbx_get_common_fw_version);
305 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
306
307 ret = oce_mbox_post(sc, &mbx, NULL);
308 if (!ret)
309 ret = fwcmd->hdr.u0.rsp.status;
310 if (ret) {
311 device_printf(sc->dev,
312 "%s failed - cmd status: %d addi status: %d\n",
313 __FUNCTION__, ret,
314 fwcmd->hdr.u0.rsp.additional_status);
315 goto error;
316 }
317
318 bcopy(fwcmd->params.rsp.fw_ver_str, sc->fw_version, 32);
319 error:
320 return ret;
321 }
322
323 /**
324 * @brief Firmware will send gracious notifications during
325 * attach only after sending first mcc commnad. We
326 * use MCC queue only for getting async and mailbox
327 * for sending cmds. So to get gracious notifications
328 * atleast send one dummy command on mcc.
329 */
330 int
oce_first_mcc_cmd(POCE_SOFTC sc)331 oce_first_mcc_cmd(POCE_SOFTC sc)
332 {
333 struct oce_mbx *mbx;
334 struct oce_mq *mq = sc->mq;
335 struct mbx_get_common_fw_version *fwcmd;
336 uint32_t reg_value;
337
338 mbx = RING_GET_PRODUCER_ITEM_VA(mq->ring, struct oce_mbx);
339 bzero(mbx, sizeof(struct oce_mbx));
340
341 fwcmd = (struct mbx_get_common_fw_version *)&mbx->payload;
342 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
343 MBX_SUBSYSTEM_COMMON,
344 OPCODE_COMMON_GET_FW_VERSION,
345 MBX_TIMEOUT_SEC,
346 sizeof(struct mbx_get_common_fw_version),
347 OCE_MBX_VER_V0);
348 mbx->u0.s.embedded = 1;
349 mbx->payload_length = sizeof(struct mbx_get_common_fw_version);
350 bus_dmamap_sync(mq->ring->dma.tag, mq->ring->dma.map,
351 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
352 RING_PUT(mq->ring, 1);
353 reg_value = (1 << 16) | mq->mq_id;
354 OCE_WRITE_REG32(sc, db, PD_MQ_DB, reg_value);
355
356 return 0;
357 }
358
359 /**
360 * @brief Function to post a MBX to the mbox
361 * @param sc software handle to the device
362 * @param mbx pointer to the MBX to send
363 * @param mbxctx pointer to the mbx context structure
364 * @returns 0 on success, error on failure
365 */
366 int
oce_mbox_post(POCE_SOFTC sc,struct oce_mbx * mbx,struct oce_mbx_ctx * mbxctx)367 oce_mbox_post(POCE_SOFTC sc, struct oce_mbx *mbx, struct oce_mbx_ctx *mbxctx)
368 {
369 struct oce_mbx *mb_mbx = NULL;
370 struct oce_mq_cqe *mb_cqe = NULL;
371 struct oce_bmbx *mb = NULL;
372 int rc = 0;
373 uint32_t tmo = 0;
374 uint32_t cstatus = 0;
375 uint32_t xstatus = 0;
376
377 LOCK(&sc->bmbx_lock);
378
379 mb = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx);
380 mb_mbx = &mb->mbx;
381
382 /* get the tmo */
383 tmo = mbx->tag[0];
384 mbx->tag[0] = 0;
385
386 /* copy mbx into mbox */
387 bcopy(mbx, mb_mbx, sizeof(struct oce_mbx));
388
389 /* now dispatch */
390 rc = oce_mbox_dispatch(sc, tmo);
391 if (rc == 0) {
392 /*
393 * the command completed successfully. Now get the
394 * completion queue entry
395 */
396 mb_cqe = &mb->cqe;
397 DW_SWAP(u32ptr(&mb_cqe->u0.dw[0]), sizeof(struct oce_mq_cqe));
398
399 /* copy mbox mbx back */
400 bcopy(mb_mbx, mbx, sizeof(struct oce_mbx));
401
402 /* pick up the mailbox status */
403 cstatus = mb_cqe->u0.s.completion_status;
404 xstatus = mb_cqe->u0.s.extended_status;
405
406 /*
407 * store the mbx context in the cqe tag section so that
408 * the upper layer handling the cqe can associate the mbx
409 * with the response
410 */
411 if (cstatus == 0 && mbxctx) {
412 /* save context */
413 mbxctx->mbx = mb_mbx;
414 bcopy(&mbxctx, mb_cqe->u0.s.mq_tag,
415 sizeof(struct oce_mbx_ctx *));
416 }
417 }
418
419 UNLOCK(&sc->bmbx_lock);
420
421 return rc;
422 }
423
424 /**
425 * @brief Function to read the mac address associated with an interface
426 * @param sc software handle to the device
427 * @param if_id interface id to read the address from
428 * @param perm set to 1 if reading the factory mac address.
429 * In this case if_id is ignored
430 * @param type type of the mac address, whether network or storage
431 * @param[out] mac [OUTPUT] pointer to a buffer containing the
432 * mac address when the command succeeds.
433 * @returns 0 on success, EIO on failure
434 */
435 int
oce_read_mac_addr(POCE_SOFTC sc,uint32_t if_id,uint8_t perm,uint8_t type,struct mac_address_format * mac)436 oce_read_mac_addr(POCE_SOFTC sc, uint32_t if_id,
437 uint8_t perm, uint8_t type, struct mac_address_format *mac)
438 {
439 struct oce_mbx mbx;
440 struct mbx_query_common_iface_mac *fwcmd;
441 int ret = 0;
442
443 bzero(&mbx, sizeof(struct oce_mbx));
444
445 fwcmd = (struct mbx_query_common_iface_mac *)&mbx.payload;
446 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
447 MBX_SUBSYSTEM_COMMON,
448 OPCODE_COMMON_QUERY_IFACE_MAC,
449 MBX_TIMEOUT_SEC,
450 sizeof(struct mbx_query_common_iface_mac),
451 OCE_MBX_VER_V0);
452
453 fwcmd->params.req.permanent = perm;
454 if (!perm)
455 fwcmd->params.req.if_id = (uint16_t) if_id;
456 else
457 fwcmd->params.req.if_id = 0;
458
459 fwcmd->params.req.type = type;
460
461 mbx.u0.s.embedded = 1;
462 mbx.payload_length = sizeof(struct mbx_query_common_iface_mac);
463 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
464
465 ret = oce_mbox_post(sc, &mbx, NULL);
466 if (!ret)
467 ret = fwcmd->hdr.u0.rsp.status;
468 if (ret) {
469 device_printf(sc->dev,
470 "%s failed - cmd status: %d addi status: %d\n",
471 __FUNCTION__, ret,
472 fwcmd->hdr.u0.rsp.additional_status);
473 goto error;
474 }
475
476 /* copy the mac address in the output parameter */
477 mac->size_of_struct = fwcmd->params.rsp.mac.size_of_struct;
478 bcopy(&fwcmd->params.rsp.mac.mac_addr[0], &mac->mac_addr[0],
479 mac->size_of_struct);
480 error:
481 return ret;
482 }
483
484 /**
485 * @brief Function to query the fw attributes from the hw
486 * @param sc software handle to the device
487 * @returns 0 on success, EIO on failure
488 */
489 int
oce_get_fw_config(POCE_SOFTC sc)490 oce_get_fw_config(POCE_SOFTC sc)
491 {
492 struct oce_mbx mbx;
493 struct mbx_common_query_fw_config *fwcmd;
494 int ret = 0;
495
496 bzero(&mbx, sizeof(struct oce_mbx));
497
498 fwcmd = (struct mbx_common_query_fw_config *)&mbx.payload;
499 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
500 MBX_SUBSYSTEM_COMMON,
501 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG,
502 MBX_TIMEOUT_SEC,
503 sizeof(struct mbx_common_query_fw_config),
504 OCE_MBX_VER_V0);
505
506 mbx.u0.s.embedded = 1;
507 mbx.payload_length = sizeof(struct mbx_common_query_fw_config);
508 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
509
510 ret = oce_mbox_post(sc, &mbx, NULL);
511 if (!ret)
512 ret = fwcmd->hdr.u0.rsp.status;
513 if (ret) {
514 device_printf(sc->dev,
515 "%s failed - cmd status: %d addi status: %d\n",
516 __FUNCTION__, ret,
517 fwcmd->hdr.u0.rsp.additional_status);
518 goto error;
519 }
520
521 DW_SWAP(u32ptr(fwcmd), sizeof(struct mbx_common_query_fw_config));
522
523 sc->config_number = HOST_32(fwcmd->params.rsp.config_number);
524 sc->asic_revision = HOST_32(fwcmd->params.rsp.asic_revision);
525 sc->port_id = HOST_32(fwcmd->params.rsp.port_id);
526 sc->function_mode = HOST_32(fwcmd->params.rsp.function_mode);
527 if ((sc->function_mode & (ULP_NIC_MODE | ULP_RDMA_MODE)) ==
528 (ULP_NIC_MODE | ULP_RDMA_MODE)) {
529 sc->rdma_flags = OCE_RDMA_FLAG_SUPPORTED;
530 }
531 sc->function_caps = HOST_32(fwcmd->params.rsp.function_caps);
532
533 if (fwcmd->params.rsp.ulp[0].ulp_mode & ULP_NIC_MODE) {
534 sc->max_tx_rings = HOST_32(fwcmd->params.rsp.ulp[0].nic_wq_tot);
535 sc->max_rx_rings = HOST_32(fwcmd->params.rsp.ulp[0].lro_rqid_tot);
536 } else {
537 sc->max_tx_rings = HOST_32(fwcmd->params.rsp.ulp[1].nic_wq_tot);
538 sc->max_rx_rings = HOST_32(fwcmd->params.rsp.ulp[1].lro_rqid_tot);
539 }
540
541 error:
542 return ret;
543
544 }
545
546 /**
547 *
548 * @brief function to create a device interface
549 * @param sc software handle to the device
550 * @param cap_flags capability flags
551 * @param en_flags enable capability flags
552 * @param vlan_tag optional vlan tag to associate with the if
553 * @param mac_addr pointer to a buffer containing the mac address
554 * @param[out] if_id [OUTPUT] pointer to an integer to hold the ID of the
555 interface created
556 * @returns 0 on success, EIO on failure
557 */
558 int
oce_if_create(POCE_SOFTC sc,uint32_t cap_flags,uint32_t en_flags,uint16_t vlan_tag,uint8_t * mac_addr,uint32_t * if_id)559 oce_if_create(POCE_SOFTC sc,
560 uint32_t cap_flags,
561 uint32_t en_flags,
562 uint16_t vlan_tag,
563 uint8_t *mac_addr,
564 uint32_t *if_id)
565 {
566 struct oce_mbx mbx;
567 struct mbx_create_common_iface *fwcmd;
568 int rc = 0;
569
570 bzero(&mbx, sizeof(struct oce_mbx));
571
572 fwcmd = (struct mbx_create_common_iface *)&mbx.payload;
573 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
574 MBX_SUBSYSTEM_COMMON,
575 OPCODE_COMMON_CREATE_IFACE,
576 MBX_TIMEOUT_SEC,
577 sizeof(struct mbx_create_common_iface),
578 OCE_MBX_VER_V0);
579 DW_SWAP(u32ptr(&fwcmd->hdr), sizeof(struct mbx_hdr));
580
581 fwcmd->params.req.version = 0;
582 fwcmd->params.req.cap_flags = LE_32(cap_flags);
583 fwcmd->params.req.enable_flags = LE_32(en_flags);
584 if (mac_addr != NULL) {
585 bcopy(mac_addr, &fwcmd->params.req.mac_addr[0], 6);
586 fwcmd->params.req.vlan_tag.u0.normal.vtag = LE_16(vlan_tag);
587 fwcmd->params.req.mac_invalid = 0;
588 } else {
589 fwcmd->params.req.mac_invalid = 1;
590 }
591
592 mbx.u0.s.embedded = 1;
593 mbx.payload_length = sizeof(struct mbx_create_common_iface);
594 DW_SWAP(u32ptr(&mbx), OCE_BMBX_RHDR_SZ);
595
596 rc = oce_mbox_post(sc, &mbx, NULL);
597 if (!rc)
598 rc = fwcmd->hdr.u0.rsp.status;
599 if (rc) {
600 device_printf(sc->dev,
601 "%s failed - cmd status: %d addi status: %d\n",
602 __FUNCTION__, rc,
603 fwcmd->hdr.u0.rsp.additional_status);
604 goto error;
605 }
606
607 *if_id = HOST_32(fwcmd->params.rsp.if_id);
608
609 if (mac_addr != NULL)
610 sc->pmac_id = HOST_32(fwcmd->params.rsp.pmac_id);
611 error:
612 return rc;
613 }
614
615 /**
616 * @brief Function to delete an interface
617 * @param sc software handle to the device
618 * @param if_id ID of the interface to delete
619 * @returns 0 on success, EIO on failure
620 */
621 int
oce_if_del(POCE_SOFTC sc,uint32_t if_id)622 oce_if_del(POCE_SOFTC sc, uint32_t if_id)
623 {
624 struct oce_mbx mbx;
625 struct mbx_destroy_common_iface *fwcmd;
626 int rc = 0;
627
628 bzero(&mbx, sizeof(struct oce_mbx));
629
630 fwcmd = (struct mbx_destroy_common_iface *)&mbx.payload;
631 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
632 MBX_SUBSYSTEM_COMMON,
633 OPCODE_COMMON_DESTROY_IFACE,
634 MBX_TIMEOUT_SEC,
635 sizeof(struct mbx_destroy_common_iface),
636 OCE_MBX_VER_V0);
637
638 fwcmd->params.req.if_id = if_id;
639
640 mbx.u0.s.embedded = 1;
641 mbx.payload_length = sizeof(struct mbx_destroy_common_iface);
642 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
643
644 rc = oce_mbox_post(sc, &mbx, NULL);
645 if (!rc)
646 rc = fwcmd->hdr.u0.rsp.status;
647 if (rc)
648 device_printf(sc->dev,
649 "%s failed - cmd status: %d addi status: %d\n",
650 __FUNCTION__, rc,
651 fwcmd->hdr.u0.rsp.additional_status);
652 return rc;
653 }
654
655 /**
656 * @brief Function to send the mbx command to configure vlan
657 * @param sc software handle to the device
658 * @param if_id interface identifier index
659 * @param vtag_arr array of vlan tags
660 * @param vtag_cnt number of elements in array
661 * @param untagged boolean TRUE/FLASE
662 * @param enable_promisc flag to enable/disable VLAN promiscuous mode
663 * @returns 0 on success, EIO on failure
664 */
665 int
oce_config_vlan(POCE_SOFTC sc,uint32_t if_id,struct normal_vlan * vtag_arr,uint8_t vtag_cnt,uint32_t untagged,uint32_t enable_promisc)666 oce_config_vlan(POCE_SOFTC sc,
667 uint32_t if_id,
668 struct normal_vlan *vtag_arr,
669 uint8_t vtag_cnt, uint32_t untagged, uint32_t enable_promisc)
670 {
671 struct oce_mbx mbx;
672 struct mbx_common_config_vlan *fwcmd;
673 int rc = 0;
674
675 if (sc->vlans_added > sc->max_vlans)
676 goto vlan_promisc;
677
678 bzero(&mbx, sizeof(struct oce_mbx));
679 fwcmd = (struct mbx_common_config_vlan *)&mbx.payload;
680
681 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
682 MBX_SUBSYSTEM_COMMON,
683 OPCODE_COMMON_CONFIG_IFACE_VLAN,
684 MBX_TIMEOUT_SEC,
685 sizeof(struct mbx_common_config_vlan),
686 OCE_MBX_VER_V0);
687
688 fwcmd->params.req.if_id = (uint8_t) if_id;
689 fwcmd->params.req.promisc = (uint8_t) enable_promisc;
690 fwcmd->params.req.untagged = (uint8_t) untagged;
691 fwcmd->params.req.num_vlans = vtag_cnt;
692
693 if (!enable_promisc) {
694 bcopy(vtag_arr, fwcmd->params.req.tags.normal_vlans,
695 vtag_cnt * sizeof(struct normal_vlan));
696 }
697 mbx.u0.s.embedded = 1;
698 mbx.payload_length = sizeof(struct mbx_common_config_vlan);
699 DW_SWAP(u32ptr(&mbx), (OCE_BMBX_RHDR_SZ + mbx.payload_length));
700
701 rc = oce_mbox_post(sc, &mbx, NULL);
702 if (!rc)
703 rc = fwcmd->hdr.u0.rsp.status;
704 if (rc)
705 device_printf(sc->dev,
706 "%s failed - cmd status: %d addi status: %d\n",
707 __FUNCTION__, rc,
708 fwcmd->hdr.u0.rsp.additional_status);
709
710 goto done;
711
712 vlan_promisc:
713 /* Enable Vlan Promis */
714 oce_rxf_set_promiscuous(sc, (1 << 1));
715 device_printf(sc->dev,"Enabling Vlan Promisc Mode\n");
716 done:
717 return rc;
718
719 }
720
721 /**
722 * @brief Function to set flow control capability in the hardware
723 * @param sc software handle to the device
724 * @param flow_control flow control flags to set
725 * @returns 0 on success, EIO on failure
726 */
727 int
oce_set_flow_control(POCE_SOFTC sc,uint32_t flow_control)728 oce_set_flow_control(POCE_SOFTC sc, uint32_t flow_control)
729 {
730 struct oce_mbx mbx;
731 struct mbx_common_get_set_flow_control *fwcmd =
732 (struct mbx_common_get_set_flow_control *)&mbx.payload;
733 int rc;
734
735 bzero(&mbx, sizeof(struct oce_mbx));
736
737 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
738 MBX_SUBSYSTEM_COMMON,
739 OPCODE_COMMON_SET_FLOW_CONTROL,
740 MBX_TIMEOUT_SEC,
741 sizeof(struct mbx_common_get_set_flow_control),
742 OCE_MBX_VER_V0);
743
744 if (flow_control & OCE_FC_TX)
745 fwcmd->tx_flow_control = 1;
746
747 if (flow_control & OCE_FC_RX)
748 fwcmd->rx_flow_control = 1;
749
750 mbx.u0.s.embedded = 1;
751 mbx.payload_length = sizeof(struct mbx_common_get_set_flow_control);
752 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
753
754 rc = oce_mbox_post(sc, &mbx, NULL);
755 if (!rc)
756 rc = fwcmd->hdr.u0.rsp.status;
757 if (rc)
758 device_printf(sc->dev,
759 "%s failed - cmd status: %d addi status: %d\n",
760 __FUNCTION__, rc,
761 fwcmd->hdr.u0.rsp.additional_status);
762 return rc;
763 }
764
765 /**
766 * @brief Initialize the RSS CPU indirection table
767 *
768 * The table is used to choose the queue to place the incomming packets.
769 * Incomming packets are hashed. The lowest bits in the hash result
770 * are used as the index into the CPU indirection table.
771 * Each entry in the table contains the RSS CPU-ID returned by the NIC
772 * create. Based on the CPU ID, the receive completion is routed to
773 * the corresponding RSS CQs. (Non-RSS packets are always completed
774 * on the default (0) CQ).
775 *
776 * @param sc software handle to the device
777 * @param *fwcmd pointer to the rss mbox command
778 * @returns none
779 */
780 static int
oce_rss_itbl_init(POCE_SOFTC sc,struct mbx_config_nic_rss * fwcmd)781 oce_rss_itbl_init(POCE_SOFTC sc, struct mbx_config_nic_rss *fwcmd)
782 {
783 int i = 0, j = 0, rc = 0;
784 uint8_t *tbl = fwcmd->params.req.cputable;
785 struct oce_rq *rq = NULL;
786
787 for (j = 0; j < INDIRECTION_TABLE_ENTRIES ; j += (sc->nrqs - 1)) {
788 for_all_rss_queues(sc, rq, i) {
789 if ((j + i) >= INDIRECTION_TABLE_ENTRIES)
790 break;
791 tbl[j + i] = rq->rss_cpuid;
792 }
793 }
794 if (i == 0) {
795 device_printf(sc->dev, "error: Invalid number of RSS RQ's\n");
796 rc = ENXIO;
797
798 }
799
800 /* fill log2 value indicating the size of the CPU table */
801 if (rc == 0)
802 fwcmd->params.req.cpu_tbl_sz_log2 = LE_16(OCE_LOG2(INDIRECTION_TABLE_ENTRIES));
803
804 return rc;
805 }
806
807 /**
808 * @brief Function to set flow control capability in the hardware
809 * @param sc software handle to the device
810 * @param if_id interface id to read the address from
811 * @param enable_rss 0=disable, RSS_ENABLE_xxx flags otherwise
812 * @returns 0 on success, EIO on failure
813 */
814 int
oce_config_nic_rss(POCE_SOFTC sc,uint32_t if_id,uint16_t enable_rss)815 oce_config_nic_rss(POCE_SOFTC sc, uint32_t if_id, uint16_t enable_rss)
816 {
817 int rc;
818 struct oce_mbx mbx;
819 struct mbx_config_nic_rss *fwcmd =
820 (struct mbx_config_nic_rss *)&mbx.payload;
821 int version;
822
823 bzero(&mbx, sizeof(struct oce_mbx));
824
825 if (IS_XE201(sc) || IS_SH(sc)) {
826 version = OCE_MBX_VER_V1;
827 fwcmd->params.req.enable_rss = RSS_ENABLE_UDP_IPV4 |
828 RSS_ENABLE_UDP_IPV6;
829 } else
830 version = OCE_MBX_VER_V0;
831
832 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
833 MBX_SUBSYSTEM_NIC,
834 NIC_CONFIG_RSS,
835 MBX_TIMEOUT_SEC,
836 sizeof(struct mbx_config_nic_rss),
837 version);
838 if (enable_rss)
839 fwcmd->params.req.enable_rss |= (RSS_ENABLE_IPV4 |
840 RSS_ENABLE_TCP_IPV4 |
841 RSS_ENABLE_IPV6 |
842 RSS_ENABLE_TCP_IPV6);
843
844 if(!sc->enable_hwlro)
845 fwcmd->params.req.flush = OCE_FLUSH;
846 else
847 fwcmd->params.req.flush = 0;
848
849 fwcmd->params.req.if_id = LE_32(if_id);
850
851 read_random(fwcmd->params.req.hash, sizeof(fwcmd->params.req.hash));
852
853 rc = oce_rss_itbl_init(sc, fwcmd);
854 if (rc == 0) {
855 mbx.u0.s.embedded = 1;
856 mbx.payload_length = sizeof(struct mbx_config_nic_rss);
857 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
858
859 rc = oce_mbox_post(sc, &mbx, NULL);
860 if (!rc)
861 rc = fwcmd->hdr.u0.rsp.status;
862 if (rc)
863 device_printf(sc->dev,
864 "%s failed - cmd status: %d addi status: %d\n",
865 __FUNCTION__, rc,
866 fwcmd->hdr.u0.rsp.additional_status);
867 }
868 return rc;
869 }
870
871 /**
872 * @brief RXF function to enable/disable device promiscuous mode
873 * @param sc software handle to the device
874 * @param enable enable/disable flag
875 * @returns 0 on success, EIO on failure
876 * @note
877 * The NIC_CONFIG_PROMISCUOUS command deprecated for Lancer.
878 * This function uses the COMMON_SET_IFACE_RX_FILTER command instead.
879 */
880 int
oce_rxf_set_promiscuous(POCE_SOFTC sc,uint8_t enable)881 oce_rxf_set_promiscuous(POCE_SOFTC sc, uint8_t enable)
882 {
883 struct mbx_set_common_iface_rx_filter *fwcmd;
884 int sz = sizeof(struct mbx_set_common_iface_rx_filter);
885 iface_rx_filter_ctx_t *req;
886 OCE_DMA_MEM sgl;
887 int rc;
888
889 /* allocate mbx payload's dma scatter/gather memory */
890 rc = oce_dma_alloc(sc, sz, &sgl, 0);
891 if (rc)
892 return rc;
893
894 fwcmd = OCE_DMAPTR(&sgl, struct mbx_set_common_iface_rx_filter);
895
896 req = &fwcmd->params.req;
897 req->iface_flags_mask = MBX_RX_IFACE_FLAGS_PROMISCUOUS |
898 MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS;
899 /* Bit 0 Mac promisc, Bit 1 Vlan promisc */
900 if (enable & 0x01)
901 req->iface_flags = MBX_RX_IFACE_FLAGS_PROMISCUOUS;
902
903 if (enable & 0x02)
904 req->iface_flags |= MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS;
905
906 req->if_id = sc->if_id;
907
908 rc = oce_set_common_iface_rx_filter(sc, &sgl);
909 oce_dma_free(sc, &sgl);
910
911 return rc;
912 }
913
914 /**
915 * @brief Function modify and select rx filter options
916 * @param sc software handle to the device
917 * @param sgl scatter/gather request/response
918 * @returns 0 on success, error code on failure
919 */
920 int
oce_set_common_iface_rx_filter(POCE_SOFTC sc,POCE_DMA_MEM sgl)921 oce_set_common_iface_rx_filter(POCE_SOFTC sc, POCE_DMA_MEM sgl)
922 {
923 struct oce_mbx mbx;
924 int mbx_sz = sizeof(struct mbx_set_common_iface_rx_filter);
925 struct mbx_set_common_iface_rx_filter *fwcmd;
926 int rc;
927
928 bzero(&mbx, sizeof(struct oce_mbx));
929 fwcmd = OCE_DMAPTR(sgl, struct mbx_set_common_iface_rx_filter);
930
931 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
932 MBX_SUBSYSTEM_COMMON,
933 OPCODE_COMMON_SET_IFACE_RX_FILTER,
934 MBX_TIMEOUT_SEC,
935 mbx_sz,
936 OCE_MBX_VER_V0);
937
938 oce_dma_sync(sgl, BUS_DMASYNC_PREWRITE);
939 mbx.u0.s.embedded = 0;
940 mbx.u0.s.sge_count = 1;
941 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(sgl->paddr);
942 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(sgl->paddr);
943 mbx.payload.u0.u1.sgl[0].length = mbx_sz;
944 mbx.payload_length = mbx_sz;
945 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
946
947 rc = oce_mbox_post(sc, &mbx, NULL);
948 if (!rc)
949 rc = fwcmd->hdr.u0.rsp.status;
950 if (rc)
951 device_printf(sc->dev,
952 "%s failed - cmd status: %d addi status: %d\n",
953 __FUNCTION__, rc,
954 fwcmd->hdr.u0.rsp.additional_status);
955 return rc;
956 }
957
958 /**
959 * @brief Function to query the link status from the hardware
960 * @param sc software handle to the device
961 * @param[out] link pointer to the structure returning link attributes
962 * @returns 0 on success, EIO on failure
963 */
964 int
oce_get_link_status(POCE_SOFTC sc,struct link_status * link)965 oce_get_link_status(POCE_SOFTC sc, struct link_status *link)
966 {
967 struct oce_mbx mbx;
968 struct mbx_query_common_link_config *fwcmd;
969 int rc = 0, version;
970
971 bzero(&mbx, sizeof(struct oce_mbx));
972
973 IS_BE2(sc) ? (version = OCE_MBX_VER_V0) : (version = OCE_MBX_VER_V1);
974
975 fwcmd = (struct mbx_query_common_link_config *)&mbx.payload;
976 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
977 MBX_SUBSYSTEM_COMMON,
978 OPCODE_COMMON_QUERY_LINK_CONFIG,
979 MBX_TIMEOUT_SEC,
980 sizeof(struct mbx_query_common_link_config),
981 version);
982
983 mbx.u0.s.embedded = 1;
984 mbx.payload_length = sizeof(struct mbx_query_common_link_config);
985 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
986
987 rc = oce_mbox_post(sc, &mbx, NULL);
988
989 if (!rc)
990 rc = fwcmd->hdr.u0.rsp.status;
991 if (rc) {
992 device_printf(sc->dev,
993 "%s failed - cmd status: %d addi status: %d\n",
994 __FUNCTION__, rc,
995 fwcmd->hdr.u0.rsp.additional_status);
996 goto error;
997 }
998 /* interpret response */
999 link->qos_link_speed = HOST_16(fwcmd->params.rsp.qos_link_speed);
1000 link->phys_port_speed = fwcmd->params.rsp.physical_port_speed;
1001 link->logical_link_status = fwcmd->params.rsp.logical_link_status;
1002 error:
1003 return rc;
1004 }
1005
1006 /**
1007 * @brief Function to get NIC statistics
1008 * @param sc software handle to the device
1009 * @param *stats pointer to where to store statistics
1010 * @param reset_stats resets statistics of set
1011 * @returns 0 on success, EIO on failure
1012 * @note command depricated in Lancer
1013 */
1014 #define OCE_MBOX_GET_NIC_STATS(sc, pstats_dma_mem, version) \
1015 int \
1016 oce_mbox_get_nic_stats_v##version(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem) \
1017 { \
1018 struct oce_mbx mbx; \
1019 struct mbx_get_nic_stats_v##version *fwcmd; \
1020 int rc = 0; \
1021 \
1022 bzero(&mbx, sizeof(struct oce_mbx)); \
1023 fwcmd = OCE_DMAPTR(pstats_dma_mem, struct mbx_get_nic_stats_v##version); \
1024 bzero(fwcmd, sizeof(*fwcmd)); \
1025 \
1026 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, \
1027 MBX_SUBSYSTEM_NIC, \
1028 NIC_GET_STATS, \
1029 MBX_TIMEOUT_SEC, \
1030 sizeof(*fwcmd), \
1031 OCE_MBX_VER_V##version); \
1032 \
1033 mbx.u0.s.embedded = 0; /* stats too large for embedded mbx rsp */ \
1034 mbx.u0.s.sge_count = 1; /* using scatter gather instead */ \
1035 \
1036 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_PREWRITE); \
1037 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(pstats_dma_mem->paddr); \
1038 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(pstats_dma_mem->paddr); \
1039 mbx.payload.u0.u1.sgl[0].length = sizeof(*fwcmd); \
1040 mbx.payload_length = sizeof(*fwcmd); \
1041 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); \
1042 \
1043 rc = oce_mbox_post(sc, &mbx, NULL); \
1044 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_POSTWRITE); \
1045 if (!rc) \
1046 rc = fwcmd->hdr.u0.rsp.status; \
1047 if (rc) \
1048 device_printf(sc->dev, \
1049 "%s failed - cmd status: %d addi status: %d\n", \
1050 __FUNCTION__, rc, \
1051 fwcmd->hdr.u0.rsp.additional_status); \
1052 return rc; \
1053 }
1054
1055 OCE_MBOX_GET_NIC_STATS(sc, pstats_dma_mem, 0);
1056 OCE_MBOX_GET_NIC_STATS(sc, pstats_dma_mem, 1);
1057 OCE_MBOX_GET_NIC_STATS(sc, pstats_dma_mem, 2);
1058
1059 /**
1060 * @brief Function to get pport (physical port) statistics
1061 * @param sc software handle to the device
1062 * @param *stats pointer to where to store statistics
1063 * @param reset_stats resets statistics of set
1064 * @returns 0 on success, EIO on failure
1065 */
1066 int
oce_mbox_get_pport_stats(POCE_SOFTC sc,POCE_DMA_MEM pstats_dma_mem,uint32_t reset_stats)1067 oce_mbox_get_pport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem,
1068 uint32_t reset_stats)
1069 {
1070 struct oce_mbx mbx;
1071 struct mbx_get_pport_stats *fwcmd;
1072 int rc = 0;
1073
1074 bzero(&mbx, sizeof(struct oce_mbx));
1075 fwcmd = OCE_DMAPTR(pstats_dma_mem, struct mbx_get_pport_stats);
1076 bzero(fwcmd, sizeof(struct mbx_get_pport_stats));
1077
1078 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1079 MBX_SUBSYSTEM_NIC,
1080 NIC_GET_PPORT_STATS,
1081 MBX_TIMEOUT_SEC,
1082 sizeof(struct mbx_get_pport_stats),
1083 OCE_MBX_VER_V0);
1084
1085 fwcmd->params.req.reset_stats = reset_stats;
1086 fwcmd->params.req.port_number = sc->port_id;
1087
1088 mbx.u0.s.embedded = 0; /* stats too large for embedded mbx rsp */
1089 mbx.u0.s.sge_count = 1; /* using scatter gather instead */
1090
1091 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_PREWRITE);
1092 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(pstats_dma_mem->paddr);
1093 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(pstats_dma_mem->paddr);
1094 mbx.payload.u0.u1.sgl[0].length = sizeof(struct mbx_get_pport_stats);
1095
1096 mbx.payload_length = sizeof(struct mbx_get_pport_stats);
1097 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1098
1099 rc = oce_mbox_post(sc, &mbx, NULL);
1100 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_POSTWRITE);
1101
1102 if (!rc)
1103 rc = fwcmd->hdr.u0.rsp.status;
1104 if (rc)
1105 device_printf(sc->dev,
1106 "%s failed - cmd status: %d addi status: %d\n",
1107 __FUNCTION__, rc,
1108 fwcmd->hdr.u0.rsp.additional_status);
1109 return rc;
1110 }
1111
1112 /**
1113 * @brief Function to get vport (virtual port) statistics
1114 * @param sc software handle to the device
1115 * @param *stats pointer to where to store statistics
1116 * @param reset_stats resets statistics of set
1117 * @returns 0 on success, EIO on failure
1118 */
1119 int
oce_mbox_get_vport_stats(POCE_SOFTC sc,POCE_DMA_MEM pstats_dma_mem,uint32_t req_size,uint32_t reset_stats)1120 oce_mbox_get_vport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem,
1121 uint32_t req_size, uint32_t reset_stats)
1122 {
1123 struct oce_mbx mbx;
1124 struct mbx_get_vport_stats *fwcmd;
1125 int rc = 0;
1126
1127 bzero(&mbx, sizeof(struct oce_mbx));
1128
1129 fwcmd = OCE_DMAPTR(pstats_dma_mem, struct mbx_get_vport_stats);
1130 bzero(fwcmd, sizeof(struct mbx_get_vport_stats));
1131
1132 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1133 MBX_SUBSYSTEM_NIC,
1134 NIC_GET_VPORT_STATS,
1135 MBX_TIMEOUT_SEC,
1136 sizeof(struct mbx_get_vport_stats),
1137 OCE_MBX_VER_V0);
1138
1139 fwcmd->params.req.reset_stats = reset_stats;
1140 fwcmd->params.req.vport_number = sc->if_id;
1141
1142 mbx.u0.s.embedded = 0; /* stats too large for embedded mbx rsp */
1143 mbx.u0.s.sge_count = 1; /* using scatter gather instead */
1144
1145 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_PREWRITE);
1146 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(pstats_dma_mem->paddr);
1147 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(pstats_dma_mem->paddr);
1148 mbx.payload.u0.u1.sgl[0].length = sizeof(struct mbx_get_vport_stats);
1149
1150 mbx.payload_length = sizeof(struct mbx_get_vport_stats);
1151 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1152
1153 rc = oce_mbox_post(sc, &mbx, NULL);
1154 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_POSTWRITE);
1155
1156 if (!rc)
1157 rc = fwcmd->hdr.u0.rsp.status;
1158 if (rc)
1159 device_printf(sc->dev,
1160 "%s failed - cmd status: %d addi status: %d\n",
1161 __FUNCTION__, rc,
1162 fwcmd->hdr.u0.rsp.additional_status);
1163 return rc;
1164 }
1165
1166 /**
1167 * @brief Function to update the muticast filter with
1168 * values in dma_mem
1169 * @param sc software handle to the device
1170 * @param dma_mem pointer to dma memory region
1171 * @returns 0 on success, EIO on failure
1172 */
1173 int
oce_update_multicast(POCE_SOFTC sc,POCE_DMA_MEM pdma_mem)1174 oce_update_multicast(POCE_SOFTC sc, POCE_DMA_MEM pdma_mem)
1175 {
1176 struct oce_mbx mbx;
1177 struct oce_mq_sge *sgl;
1178 struct mbx_set_common_iface_multicast *req = NULL;
1179 int rc = 0;
1180
1181 req = OCE_DMAPTR(pdma_mem, struct mbx_set_common_iface_multicast);
1182 mbx_common_req_hdr_init(&req->hdr, 0, 0,
1183 MBX_SUBSYSTEM_COMMON,
1184 OPCODE_COMMON_SET_IFACE_MULTICAST,
1185 MBX_TIMEOUT_SEC,
1186 sizeof(struct mbx_set_common_iface_multicast),
1187 OCE_MBX_VER_V0);
1188
1189 bzero(&mbx, sizeof(struct oce_mbx));
1190
1191 mbx.u0.s.embedded = 0; /*Non embeded*/
1192 mbx.payload_length = sizeof(struct mbx_set_common_iface_multicast);
1193 mbx.u0.s.sge_count = 1;
1194 sgl = &mbx.payload.u0.u1.sgl[0];
1195 sgl->pa_hi = htole32(upper_32_bits(pdma_mem->paddr));
1196 sgl->pa_lo = htole32((pdma_mem->paddr) & 0xFFFFFFFF);
1197 sgl->length = htole32(mbx.payload_length);
1198
1199 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1200
1201 rc = oce_mbox_post(sc, &mbx, NULL);
1202 if (!rc)
1203 rc = req->hdr.u0.rsp.status;
1204 if (rc)
1205 device_printf(sc->dev,
1206 "%s failed - cmd status: %d addi status: %d\n",
1207 __FUNCTION__, rc,
1208 req->hdr.u0.rsp.additional_status);
1209 return rc;
1210 }
1211
1212 /**
1213 * @brief Function to send passthrough Ioctls
1214 * @param sc software handle to the device
1215 * @param dma_mem pointer to dma memory region
1216 * @param req_size size of dma_mem
1217 * @returns 0 on success, EIO on failure
1218 */
1219 int
oce_pass_through_mbox(POCE_SOFTC sc,POCE_DMA_MEM dma_mem,uint32_t req_size)1220 oce_pass_through_mbox(POCE_SOFTC sc, POCE_DMA_MEM dma_mem, uint32_t req_size)
1221 {
1222 struct oce_mbx mbx;
1223 struct oce_mq_sge *sgl;
1224 int rc = 0;
1225
1226 bzero(&mbx, sizeof(struct oce_mbx));
1227
1228 mbx.u0.s.embedded = 0; /*Non embeded*/
1229 mbx.payload_length = req_size;
1230 mbx.u0.s.sge_count = 1;
1231 sgl = &mbx.payload.u0.u1.sgl[0];
1232 sgl->pa_hi = htole32(upper_32_bits(dma_mem->paddr));
1233 sgl->pa_lo = htole32((dma_mem->paddr) & 0xFFFFFFFF);
1234 sgl->length = htole32(req_size);
1235
1236 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1237
1238 rc = oce_mbox_post(sc, &mbx, NULL);
1239 return rc;
1240 }
1241
1242 int
oce_mbox_macaddr_add(POCE_SOFTC sc,uint8_t * mac_addr,uint32_t if_id,uint32_t * pmac_id)1243 oce_mbox_macaddr_add(POCE_SOFTC sc, uint8_t *mac_addr,
1244 uint32_t if_id, uint32_t *pmac_id)
1245 {
1246 struct oce_mbx mbx;
1247 struct mbx_add_common_iface_mac *fwcmd;
1248 int rc = 0;
1249
1250 bzero(&mbx, sizeof(struct oce_mbx));
1251
1252 fwcmd = (struct mbx_add_common_iface_mac *)&mbx.payload;
1253 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1254 MBX_SUBSYSTEM_COMMON,
1255 OPCODE_COMMON_ADD_IFACE_MAC,
1256 MBX_TIMEOUT_SEC,
1257 sizeof(struct mbx_add_common_iface_mac),
1258 OCE_MBX_VER_V0);
1259
1260 fwcmd->params.req.if_id = (uint16_t) if_id;
1261 bcopy(mac_addr, fwcmd->params.req.mac_address, 6);
1262
1263 mbx.u0.s.embedded = 1;
1264 mbx.payload_length = sizeof(struct mbx_add_common_iface_mac);
1265 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1266 rc = oce_mbox_post(sc, &mbx, NULL);
1267 if (!rc)
1268 rc = fwcmd->hdr.u0.rsp.status;
1269 if (rc) {
1270 device_printf(sc->dev,
1271 "%s failed - cmd status: %d addi status: %d\n",
1272 __FUNCTION__, rc,
1273 fwcmd->hdr.u0.rsp.additional_status);
1274 goto error;
1275 }
1276 *pmac_id = fwcmd->params.rsp.pmac_id;
1277 error:
1278 return rc;
1279 }
1280
1281 int
oce_mbox_macaddr_del(POCE_SOFTC sc,uint32_t if_id,uint32_t pmac_id)1282 oce_mbox_macaddr_del(POCE_SOFTC sc, uint32_t if_id, uint32_t pmac_id)
1283 {
1284 struct oce_mbx mbx;
1285 struct mbx_del_common_iface_mac *fwcmd;
1286 int rc = 0;
1287
1288 bzero(&mbx, sizeof(struct oce_mbx));
1289
1290 fwcmd = (struct mbx_del_common_iface_mac *)&mbx.payload;
1291 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1292 MBX_SUBSYSTEM_COMMON,
1293 OPCODE_COMMON_DEL_IFACE_MAC,
1294 MBX_TIMEOUT_SEC,
1295 sizeof(struct mbx_del_common_iface_mac),
1296 OCE_MBX_VER_V0);
1297
1298 fwcmd->params.req.if_id = (uint16_t)if_id;
1299 fwcmd->params.req.pmac_id = pmac_id;
1300
1301 mbx.u0.s.embedded = 1;
1302 mbx.payload_length = sizeof(struct mbx_del_common_iface_mac);
1303 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1304
1305 rc = oce_mbox_post(sc, &mbx, NULL);
1306 if (!rc)
1307 rc = fwcmd->hdr.u0.rsp.status;
1308 if (rc)
1309 device_printf(sc->dev,
1310 "%s failed - cmd status: %d addi status: %d\n",
1311 __FUNCTION__, rc,
1312 fwcmd->hdr.u0.rsp.additional_status);
1313 return rc;
1314 }
1315
1316 int
oce_mbox_check_native_mode(POCE_SOFTC sc)1317 oce_mbox_check_native_mode(POCE_SOFTC sc)
1318 {
1319 struct oce_mbx mbx;
1320 struct mbx_common_set_function_cap *fwcmd;
1321 int rc = 0;
1322
1323 bzero(&mbx, sizeof(struct oce_mbx));
1324
1325 fwcmd = (struct mbx_common_set_function_cap *)&mbx.payload;
1326 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1327 MBX_SUBSYSTEM_COMMON,
1328 OPCODE_COMMON_SET_FUNCTIONAL_CAPS,
1329 MBX_TIMEOUT_SEC,
1330 sizeof(struct mbx_common_set_function_cap),
1331 OCE_MBX_VER_V0);
1332
1333 fwcmd->params.req.valid_capability_flags = CAP_SW_TIMESTAMPS |
1334 CAP_BE3_NATIVE_ERX_API;
1335
1336 fwcmd->params.req.capability_flags = CAP_BE3_NATIVE_ERX_API;
1337
1338 mbx.u0.s.embedded = 1;
1339 mbx.payload_length = sizeof(struct mbx_common_set_function_cap);
1340 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1341
1342 rc = oce_mbox_post(sc, &mbx, NULL);
1343 if (!rc)
1344 rc = fwcmd->hdr.u0.rsp.status;
1345 if (rc) {
1346 device_printf(sc->dev,
1347 "%s failed - cmd status: %d addi status: %d\n",
1348 __FUNCTION__, rc,
1349 fwcmd->hdr.u0.rsp.additional_status);
1350 goto error;
1351 }
1352 sc->be3_native = HOST_32(fwcmd->params.rsp.capability_flags)
1353 & CAP_BE3_NATIVE_ERX_API;
1354
1355 error:
1356 return 0;
1357 }
1358
1359 int
oce_mbox_cmd_set_loopback(POCE_SOFTC sc,uint8_t port_num,uint8_t loopback_type,uint8_t enable)1360 oce_mbox_cmd_set_loopback(POCE_SOFTC sc, uint8_t port_num,
1361 uint8_t loopback_type, uint8_t enable)
1362 {
1363 struct oce_mbx mbx;
1364 struct mbx_lowlevel_set_loopback_mode *fwcmd;
1365 int rc = 0;
1366
1367 bzero(&mbx, sizeof(struct oce_mbx));
1368
1369 fwcmd = (struct mbx_lowlevel_set_loopback_mode *)&mbx.payload;
1370 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1371 MBX_SUBSYSTEM_LOWLEVEL,
1372 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
1373 MBX_TIMEOUT_SEC,
1374 sizeof(struct mbx_lowlevel_set_loopback_mode),
1375 OCE_MBX_VER_V0);
1376
1377 fwcmd->params.req.src_port = port_num;
1378 fwcmd->params.req.dest_port = port_num;
1379 fwcmd->params.req.loopback_type = loopback_type;
1380 fwcmd->params.req.loopback_state = enable;
1381
1382 mbx.u0.s.embedded = 1;
1383 mbx.payload_length = sizeof(struct mbx_lowlevel_set_loopback_mode);
1384 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1385
1386 rc = oce_mbox_post(sc, &mbx, NULL);
1387 if (!rc)
1388 rc = fwcmd->hdr.u0.rsp.status;
1389 if (rc)
1390 device_printf(sc->dev,
1391 "%s failed - cmd status: %d addi status: %d\n",
1392 __FUNCTION__, rc,
1393 fwcmd->hdr.u0.rsp.additional_status);
1394
1395 return rc;
1396
1397 }
1398
1399 int
oce_mbox_cmd_test_loopback(POCE_SOFTC sc,uint32_t port_num,uint32_t loopback_type,uint32_t pkt_size,uint32_t num_pkts,uint64_t pattern)1400 oce_mbox_cmd_test_loopback(POCE_SOFTC sc, uint32_t port_num,
1401 uint32_t loopback_type, uint32_t pkt_size, uint32_t num_pkts,
1402 uint64_t pattern)
1403 {
1404
1405 struct oce_mbx mbx;
1406 struct mbx_lowlevel_test_loopback_mode *fwcmd;
1407 int rc = 0;
1408
1409 bzero(&mbx, sizeof(struct oce_mbx));
1410
1411 fwcmd = (struct mbx_lowlevel_test_loopback_mode *)&mbx.payload;
1412 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1413 MBX_SUBSYSTEM_LOWLEVEL,
1414 OPCODE_LOWLEVEL_TEST_LOOPBACK,
1415 MBX_TIMEOUT_SEC,
1416 sizeof(struct mbx_lowlevel_test_loopback_mode),
1417 OCE_MBX_VER_V0);
1418
1419 fwcmd->params.req.pattern = pattern;
1420 fwcmd->params.req.src_port = port_num;
1421 fwcmd->params.req.dest_port = port_num;
1422 fwcmd->params.req.pkt_size = pkt_size;
1423 fwcmd->params.req.num_pkts = num_pkts;
1424 fwcmd->params.req.loopback_type = loopback_type;
1425
1426 mbx.u0.s.embedded = 1;
1427 mbx.payload_length = sizeof(struct mbx_lowlevel_test_loopback_mode);
1428 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1429
1430 rc = oce_mbox_post(sc, &mbx, NULL);
1431 if (!rc)
1432 rc = fwcmd->hdr.u0.rsp.status;
1433 if (rc)
1434 device_printf(sc->dev,
1435 "%s failed - cmd status: %d addi status: %d\n",
1436 __FUNCTION__, rc,
1437 fwcmd->hdr.u0.rsp.additional_status);
1438
1439 return rc;
1440 }
1441
1442 int
oce_mbox_write_flashrom(POCE_SOFTC sc,uint32_t optype,uint32_t opcode,POCE_DMA_MEM pdma_mem,uint32_t num_bytes)1443 oce_mbox_write_flashrom(POCE_SOFTC sc, uint32_t optype,uint32_t opcode,
1444 POCE_DMA_MEM pdma_mem, uint32_t num_bytes)
1445 {
1446
1447 struct oce_mbx mbx;
1448 struct oce_mq_sge *sgl = NULL;
1449 struct mbx_common_read_write_flashrom *fwcmd = NULL;
1450 int rc = 0, payload_len = 0;
1451
1452 bzero(&mbx, sizeof(struct oce_mbx));
1453 fwcmd = OCE_DMAPTR(pdma_mem, struct mbx_common_read_write_flashrom);
1454 payload_len = sizeof(struct mbx_common_read_write_flashrom) + 32*1024;
1455
1456 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1457 MBX_SUBSYSTEM_COMMON,
1458 OPCODE_COMMON_WRITE_FLASHROM,
1459 LONG_TIMEOUT,
1460 payload_len,
1461 OCE_MBX_VER_V0);
1462
1463 fwcmd->flash_op_type = LE_32(optype);
1464 fwcmd->flash_op_code = LE_32(opcode);
1465 fwcmd->data_buffer_size = LE_32(num_bytes);
1466
1467 mbx.u0.s.embedded = 0; /*Non embeded*/
1468 mbx.payload_length = payload_len;
1469 mbx.u0.s.sge_count = 1;
1470
1471 sgl = &mbx.payload.u0.u1.sgl[0];
1472 sgl->pa_hi = upper_32_bits(pdma_mem->paddr);
1473 sgl->pa_lo = pdma_mem->paddr & 0xFFFFFFFF;
1474 sgl->length = payload_len;
1475
1476 /* post the command */
1477 rc = oce_mbox_post(sc, &mbx, NULL);
1478 if (!rc)
1479 rc = fwcmd->hdr.u0.rsp.status;
1480 if (rc)
1481 device_printf(sc->dev,
1482 "%s failed - cmd status: %d addi status: %d\n",
1483 __FUNCTION__, rc,
1484 fwcmd->hdr.u0.rsp.additional_status);
1485
1486 return rc;
1487
1488 }
1489
1490 int
oce_mbox_get_flashrom_crc(POCE_SOFTC sc,uint8_t * flash_crc,uint32_t offset,uint32_t optype)1491 oce_mbox_get_flashrom_crc(POCE_SOFTC sc, uint8_t *flash_crc,
1492 uint32_t offset, uint32_t optype)
1493 {
1494
1495 int rc = 0, payload_len = 0;
1496 struct oce_mbx mbx;
1497 struct mbx_common_read_write_flashrom *fwcmd;
1498
1499 bzero(&mbx, sizeof(struct oce_mbx));
1500
1501 fwcmd = (struct mbx_common_read_write_flashrom *)&mbx.payload;
1502
1503 /* Firmware requires extra 4 bytes with this ioctl. Since there
1504 is enough room in the mbx payload it should be good enough
1505 Reference: Bug 14853
1506 */
1507 payload_len = sizeof(struct mbx_common_read_write_flashrom) + 4;
1508
1509 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1510 MBX_SUBSYSTEM_COMMON,
1511 OPCODE_COMMON_READ_FLASHROM,
1512 MBX_TIMEOUT_SEC,
1513 payload_len,
1514 OCE_MBX_VER_V0);
1515
1516 fwcmd->flash_op_type = optype;
1517 fwcmd->flash_op_code = FLASHROM_OPER_REPORT;
1518 fwcmd->data_offset = offset;
1519 fwcmd->data_buffer_size = 0x4;
1520
1521 mbx.u0.s.embedded = 1;
1522 mbx.payload_length = payload_len;
1523
1524 /* post the command */
1525 rc = oce_mbox_post(sc, &mbx, NULL);
1526 if (!rc)
1527 rc = fwcmd->hdr.u0.rsp.status;
1528 if (rc) {
1529 device_printf(sc->dev,
1530 "%s failed - cmd status: %d addi status: %d\n",
1531 __FUNCTION__, rc,
1532 fwcmd->hdr.u0.rsp.additional_status);
1533 goto error;
1534 }
1535 bcopy(fwcmd->data_buffer, flash_crc, 4);
1536 error:
1537 return rc;
1538 }
1539
1540 int
oce_mbox_get_phy_info(POCE_SOFTC sc,struct oce_phy_info * phy_info)1541 oce_mbox_get_phy_info(POCE_SOFTC sc, struct oce_phy_info *phy_info)
1542 {
1543
1544 struct oce_mbx mbx;
1545 struct mbx_common_phy_info *fwcmd;
1546 int rc = 0;
1547
1548 bzero(&mbx, sizeof(struct oce_mbx));
1549
1550 fwcmd = (struct mbx_common_phy_info *)&mbx.payload;
1551 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1552 MBX_SUBSYSTEM_COMMON,
1553 OPCODE_COMMON_GET_PHY_CONFIG,
1554 MBX_TIMEOUT_SEC,
1555 sizeof(struct mbx_common_phy_info),
1556 OCE_MBX_VER_V0);
1557
1558 mbx.u0.s.embedded = 1;
1559 mbx.payload_length = sizeof(struct mbx_common_phy_info);
1560
1561 /* now post the command */
1562 rc = oce_mbox_post(sc, &mbx, NULL);
1563 if (!rc)
1564 rc = fwcmd->hdr.u0.rsp.status;
1565 if (rc) {
1566 device_printf(sc->dev,
1567 "%s failed - cmd status: %d addi status: %d\n",
1568 __FUNCTION__, rc,
1569 fwcmd->hdr.u0.rsp.additional_status);
1570 goto error;
1571 }
1572 phy_info->phy_type = HOST_16(fwcmd->params.rsp.phy_info.phy_type);
1573 phy_info->interface_type =
1574 HOST_16(fwcmd->params.rsp.phy_info.interface_type);
1575 phy_info->auto_speeds_supported =
1576 HOST_16(fwcmd->params.rsp.phy_info.auto_speeds_supported);
1577 phy_info->fixed_speeds_supported =
1578 HOST_16(fwcmd->params.rsp.phy_info.fixed_speeds_supported);
1579 phy_info->misc_params = HOST_32(fwcmd->params.rsp.phy_info.misc_params);
1580 error:
1581 return rc;
1582
1583 }
1584
1585 int
oce_mbox_lancer_write_flashrom(POCE_SOFTC sc,uint32_t data_size,uint32_t data_offset,POCE_DMA_MEM pdma_mem,uint32_t * written_data,uint32_t * additional_status)1586 oce_mbox_lancer_write_flashrom(POCE_SOFTC sc, uint32_t data_size,
1587 uint32_t data_offset, POCE_DMA_MEM pdma_mem,
1588 uint32_t *written_data, uint32_t *additional_status)
1589 {
1590
1591 struct oce_mbx mbx;
1592 struct mbx_lancer_common_write_object *fwcmd = NULL;
1593 int rc = 0, payload_len = 0;
1594
1595 bzero(&mbx, sizeof(struct oce_mbx));
1596 payload_len = sizeof(struct mbx_lancer_common_write_object);
1597
1598 mbx.u0.s.embedded = 1;/* Embedded */
1599 mbx.payload_length = payload_len;
1600 fwcmd = (struct mbx_lancer_common_write_object *)&mbx.payload;
1601
1602 /* initialize the ioctl header */
1603 mbx_common_req_hdr_init(&fwcmd->params.req.hdr, 0, 0,
1604 MBX_SUBSYSTEM_COMMON,
1605 OPCODE_COMMON_WRITE_OBJECT,
1606 LONG_TIMEOUT,
1607 payload_len,
1608 OCE_MBX_VER_V0);
1609
1610 fwcmd->params.req.write_length = data_size;
1611 if (data_size == 0)
1612 fwcmd->params.req.eof = 1;
1613 else
1614 fwcmd->params.req.eof = 0;
1615
1616 strcpy(fwcmd->params.req.object_name, "/prg");
1617 fwcmd->params.req.descriptor_count = 1;
1618 fwcmd->params.req.write_offset = data_offset;
1619 fwcmd->params.req.buffer_length = data_size;
1620 fwcmd->params.req.address_lower = pdma_mem->paddr & 0xFFFFFFFF;
1621 fwcmd->params.req.address_upper = upper_32_bits(pdma_mem->paddr);
1622
1623 /* post the command */
1624 rc = oce_mbox_post(sc, &mbx, NULL);
1625 if (!rc)
1626 rc = fwcmd->params.rsp.status;
1627 if (rc) {
1628 device_printf(sc->dev,
1629 "%s failed - cmd status: %d addi status: %d\n",
1630 __FUNCTION__, rc,
1631 fwcmd->params.rsp.additional_status);
1632 goto error;
1633 }
1634 *written_data = HOST_32(fwcmd->params.rsp.actual_write_length);
1635 *additional_status = fwcmd->params.rsp.additional_status;
1636 error:
1637 return rc;
1638
1639 }
1640
1641 int
oce_mbox_create_rq(struct oce_rq * rq)1642 oce_mbox_create_rq(struct oce_rq *rq)
1643 {
1644
1645 struct oce_mbx mbx;
1646 struct mbx_create_nic_rq *fwcmd;
1647 POCE_SOFTC sc = rq->parent;
1648 int rc, num_pages = 0;
1649
1650 if (rq->qstate == QCREATED)
1651 return 0;
1652
1653 bzero(&mbx, sizeof(struct oce_mbx));
1654
1655 fwcmd = (struct mbx_create_nic_rq *)&mbx.payload;
1656 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1657 MBX_SUBSYSTEM_NIC,
1658 NIC_CREATE_RQ, MBX_TIMEOUT_SEC,
1659 sizeof(struct mbx_create_nic_rq),
1660 OCE_MBX_VER_V0);
1661
1662 /* oce_page_list will also prepare pages */
1663 num_pages = oce_page_list(rq->ring, &fwcmd->params.req.pages[0]);
1664
1665 if (IS_XE201(sc)) {
1666 fwcmd->params.req.frag_size = rq->cfg.frag_size/2048;
1667 fwcmd->params.req.page_size = 1;
1668 fwcmd->hdr.u0.req.version = OCE_MBX_VER_V1;
1669 } else
1670 fwcmd->params.req.frag_size = OCE_LOG2(rq->cfg.frag_size);
1671 fwcmd->params.req.num_pages = num_pages;
1672 fwcmd->params.req.cq_id = rq->cq->cq_id;
1673 fwcmd->params.req.if_id = sc->if_id;
1674 fwcmd->params.req.max_frame_size = rq->cfg.mtu;
1675 fwcmd->params.req.is_rss_queue = rq->cfg.is_rss_queue;
1676
1677 mbx.u0.s.embedded = 1;
1678 mbx.payload_length = sizeof(struct mbx_create_nic_rq);
1679
1680 rc = oce_mbox_post(sc, &mbx, NULL);
1681 if (!rc)
1682 rc = fwcmd->hdr.u0.rsp.status;
1683 if (rc) {
1684 device_printf(sc->dev,
1685 "%s failed - cmd status: %d addi status: %d\n",
1686 __FUNCTION__, rc,
1687 fwcmd->hdr.u0.rsp.additional_status);
1688 goto error;
1689 }
1690 rq->rq_id = HOST_16(fwcmd->params.rsp.rq_id);
1691 rq->rss_cpuid = fwcmd->params.rsp.rss_cpuid;
1692 error:
1693 return rc;
1694
1695 }
1696
1697 int
oce_mbox_create_wq(struct oce_wq * wq)1698 oce_mbox_create_wq(struct oce_wq *wq)
1699 {
1700 struct oce_mbx mbx;
1701 struct mbx_create_nic_wq *fwcmd;
1702 POCE_SOFTC sc = wq->parent;
1703 int rc = 0, version, num_pages;
1704
1705 bzero(&mbx, sizeof(struct oce_mbx));
1706
1707 fwcmd = (struct mbx_create_nic_wq *)&mbx.payload;
1708 if (IS_XE201(sc))
1709 version = OCE_MBX_VER_V1;
1710 else if(IS_BE(sc))
1711 IS_PROFILE_SUPER_NIC(sc) ? (version = OCE_MBX_VER_V2)
1712 : (version = OCE_MBX_VER_V0);
1713 else
1714 version = OCE_MBX_VER_V2;
1715
1716 if (version > OCE_MBX_VER_V0)
1717 fwcmd->params.req.if_id = sc->if_id;
1718
1719 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1720 MBX_SUBSYSTEM_NIC,
1721 NIC_CREATE_WQ, MBX_TIMEOUT_SEC,
1722 sizeof(struct mbx_create_nic_wq),
1723 version);
1724
1725 num_pages = oce_page_list(wq->ring, &fwcmd->params.req.pages[0]);
1726
1727 fwcmd->params.req.nic_wq_type = wq->cfg.wq_type;
1728 fwcmd->params.req.num_pages = num_pages;
1729 fwcmd->params.req.wq_size = OCE_LOG2(wq->cfg.q_len) + 1;
1730 fwcmd->params.req.cq_id = wq->cq->cq_id;
1731 fwcmd->params.req.ulp_num = 1;
1732
1733 mbx.u0.s.embedded = 1;
1734 mbx.payload_length = sizeof(struct mbx_create_nic_wq);
1735
1736 rc = oce_mbox_post(sc, &mbx, NULL);
1737 if (!rc)
1738 rc = fwcmd->hdr.u0.rsp.status;
1739 if (rc) {
1740 device_printf(sc->dev,
1741 "%s failed - cmd status: %d addi status: %d\n",
1742 __FUNCTION__, rc,
1743 fwcmd->hdr.u0.rsp.additional_status);
1744 goto error;
1745 }
1746 wq->wq_id = HOST_16(fwcmd->params.rsp.wq_id);
1747 if (version == OCE_MBX_VER_V2)
1748 wq->db_offset = HOST_32(fwcmd->params.rsp.db_offset);
1749 else
1750 wq->db_offset = PD_TXULP_DB;
1751 error:
1752 return rc;
1753
1754 }
1755
1756 int
oce_mbox_create_eq(struct oce_eq * eq)1757 oce_mbox_create_eq(struct oce_eq *eq)
1758 {
1759 struct oce_mbx mbx;
1760 struct mbx_create_common_eq *fwcmd;
1761 POCE_SOFTC sc = eq->parent;
1762 int rc = 0;
1763 uint32_t num_pages;
1764
1765 bzero(&mbx, sizeof(struct oce_mbx));
1766
1767 fwcmd = (struct mbx_create_common_eq *)&mbx.payload;
1768
1769 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1770 MBX_SUBSYSTEM_COMMON,
1771 OPCODE_COMMON_CREATE_EQ, MBX_TIMEOUT_SEC,
1772 sizeof(struct mbx_create_common_eq),
1773 OCE_MBX_VER_V0);
1774
1775 num_pages = oce_page_list(eq->ring, &fwcmd->params.req.pages[0]);
1776 fwcmd->params.req.ctx.num_pages = num_pages;
1777 fwcmd->params.req.ctx.valid = 1;
1778 fwcmd->params.req.ctx.size = (eq->eq_cfg.item_size == 4) ? 0 : 1;
1779 fwcmd->params.req.ctx.count = OCE_LOG2(eq->eq_cfg.q_len / 256);
1780 fwcmd->params.req.ctx.armed = 0;
1781 fwcmd->params.req.ctx.delay_mult = eq->eq_cfg.cur_eqd;
1782
1783 mbx.u0.s.embedded = 1;
1784 mbx.payload_length = sizeof(struct mbx_create_common_eq);
1785
1786 rc = oce_mbox_post(sc, &mbx, NULL);
1787 if (!rc)
1788 rc = fwcmd->hdr.u0.rsp.status;
1789 if (rc) {
1790 device_printf(sc->dev,
1791 "%s failed - cmd status: %d addi status: %d\n",
1792 __FUNCTION__, rc,
1793 fwcmd->hdr.u0.rsp.additional_status);
1794 goto error;
1795 }
1796 eq->eq_id = HOST_16(fwcmd->params.rsp.eq_id);
1797 error:
1798 return rc;
1799 }
1800
1801 int
oce_mbox_cq_create(struct oce_cq * cq,uint32_t ncoalesce,uint32_t is_eventable)1802 oce_mbox_cq_create(struct oce_cq *cq, uint32_t ncoalesce, uint32_t is_eventable)
1803 {
1804 struct oce_mbx mbx;
1805 struct mbx_create_common_cq *fwcmd;
1806 POCE_SOFTC sc = cq->parent;
1807 uint8_t version;
1808 oce_cq_ctx_t *ctx;
1809 uint32_t num_pages, page_size;
1810 int rc = 0;
1811
1812 bzero(&mbx, sizeof(struct oce_mbx));
1813
1814 fwcmd = (struct mbx_create_common_cq *)&mbx.payload;
1815
1816 if (IS_XE201(sc))
1817 version = OCE_MBX_VER_V2;
1818 else
1819 version = OCE_MBX_VER_V0;
1820
1821 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1822 MBX_SUBSYSTEM_COMMON,
1823 OPCODE_COMMON_CREATE_CQ,
1824 MBX_TIMEOUT_SEC,
1825 sizeof(struct mbx_create_common_cq),
1826 version);
1827
1828 ctx = &fwcmd->params.req.cq_ctx;
1829
1830 num_pages = oce_page_list(cq->ring, &fwcmd->params.req.pages[0]);
1831 page_size = 1; /* 1 for 4K */
1832
1833 if (version == OCE_MBX_VER_V2) {
1834 ctx->v2.num_pages = LE_16(num_pages);
1835 ctx->v2.page_size = page_size;
1836 ctx->v2.eventable = is_eventable;
1837 ctx->v2.valid = 1;
1838 ctx->v2.count = OCE_LOG2(cq->cq_cfg.q_len / 256);
1839 ctx->v2.nodelay = cq->cq_cfg.nodelay;
1840 ctx->v2.coalesce_wm = ncoalesce;
1841 ctx->v2.armed = 0;
1842 ctx->v2.eq_id = cq->eq->eq_id;
1843 if (ctx->v2.count == 3) {
1844 if ((u_int)cq->cq_cfg.q_len > (4*1024)-1)
1845 ctx->v2.cqe_count = (4*1024)-1;
1846 else
1847 ctx->v2.cqe_count = cq->cq_cfg.q_len;
1848 }
1849 } else {
1850 ctx->v0.num_pages = LE_16(num_pages);
1851 ctx->v0.eventable = is_eventable;
1852 ctx->v0.valid = 1;
1853 ctx->v0.count = OCE_LOG2(cq->cq_cfg.q_len / 256);
1854 ctx->v0.nodelay = cq->cq_cfg.nodelay;
1855 ctx->v0.coalesce_wm = ncoalesce;
1856 ctx->v0.armed = 0;
1857 ctx->v0.eq_id = cq->eq->eq_id;
1858 }
1859
1860 mbx.u0.s.embedded = 1;
1861 mbx.payload_length = sizeof(struct mbx_create_common_cq);
1862
1863 rc = oce_mbox_post(sc, &mbx, NULL);
1864 if (!rc)
1865 rc = fwcmd->hdr.u0.rsp.status;
1866 if (rc) {
1867 device_printf(sc->dev,
1868 "%s failed - cmd status: %d addi status: %d\n",
1869 __FUNCTION__, rc,
1870 fwcmd->hdr.u0.rsp.additional_status);
1871 goto error;
1872 }
1873 cq->cq_id = HOST_16(fwcmd->params.rsp.cq_id);
1874 error:
1875 return rc;
1876
1877 }
1878
1879 int
oce_mbox_read_transrecv_data(POCE_SOFTC sc,uint32_t page_num)1880 oce_mbox_read_transrecv_data(POCE_SOFTC sc, uint32_t page_num)
1881 {
1882 int rc = 0;
1883 struct oce_mbx mbx;
1884 struct mbx_read_common_transrecv_data *fwcmd;
1885 struct oce_mq_sge *sgl;
1886 OCE_DMA_MEM dma;
1887
1888 /* Allocate DMA mem*/
1889 if (oce_dma_alloc(sc, sizeof(struct mbx_read_common_transrecv_data),
1890 &dma, 0))
1891 return ENOMEM;
1892
1893 fwcmd = OCE_DMAPTR(&dma, struct mbx_read_common_transrecv_data);
1894 bzero(fwcmd, sizeof(struct mbx_read_common_transrecv_data));
1895
1896 bzero(&mbx, sizeof(struct oce_mbx));
1897 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1898 MBX_SUBSYSTEM_COMMON,
1899 OPCODE_COMMON_READ_TRANSRECEIVER_DATA,
1900 MBX_TIMEOUT_SEC,
1901 sizeof(struct mbx_read_common_transrecv_data),
1902 OCE_MBX_VER_V0);
1903
1904 /* fill rest of mbx */
1905 mbx.u0.s.embedded = 0;
1906 mbx.payload_length = sizeof(struct mbx_read_common_transrecv_data);
1907 mbx.u0.s.sge_count = 1;
1908 sgl = &mbx.payload.u0.u1.sgl[0];
1909 sgl->pa_hi = htole32(upper_32_bits(dma.paddr));
1910 sgl->pa_lo = htole32((dma.paddr) & 0xFFFFFFFF);
1911 sgl->length = htole32(mbx.payload_length);
1912 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1913
1914 fwcmd->params.req.port = LE_32(sc->port_id);
1915 fwcmd->params.req.page_num = LE_32(page_num);
1916
1917 /* command post */
1918 rc = oce_mbox_post(sc, &mbx, NULL);
1919 if (!rc)
1920 rc = fwcmd->hdr.u0.rsp.status;
1921 if (rc) {
1922 device_printf(sc->dev,
1923 "%s failed - cmd status: %d addi status: %d\n",
1924 __FUNCTION__, rc,
1925 fwcmd->hdr.u0.rsp.additional_status);
1926 goto error;
1927 }
1928 if(fwcmd->params.rsp.page_num == PAGE_NUM_A0)
1929 {
1930 bcopy((char *)fwcmd->params.rsp.page_data,
1931 &sfp_vpd_dump_buffer[0],
1932 TRANSCEIVER_A0_SIZE);
1933 }
1934
1935 if(fwcmd->params.rsp.page_num == PAGE_NUM_A2)
1936 {
1937 bcopy((char *)fwcmd->params.rsp.page_data,
1938 &sfp_vpd_dump_buffer[TRANSCEIVER_A0_SIZE],
1939 TRANSCEIVER_A2_SIZE);
1940 }
1941 error:
1942 oce_dma_free(sc, &dma);
1943 return rc;
1944 }
1945
1946 void
oce_mbox_eqd_modify_periodic(POCE_SOFTC sc,struct oce_set_eqd * set_eqd,int num)1947 oce_mbox_eqd_modify_periodic(POCE_SOFTC sc, struct oce_set_eqd *set_eqd,
1948 int num)
1949 {
1950 struct oce_mbx mbx;
1951 struct mbx_modify_common_eq_delay *fwcmd;
1952 int rc = 0;
1953 int i = 0;
1954
1955 bzero(&mbx, sizeof(struct oce_mbx));
1956
1957 /* Initialize MODIFY_EQ_DELAY ioctl header */
1958 fwcmd = (struct mbx_modify_common_eq_delay *)&mbx.payload;
1959 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1960 MBX_SUBSYSTEM_COMMON,
1961 OPCODE_COMMON_MODIFY_EQ_DELAY,
1962 MBX_TIMEOUT_SEC,
1963 sizeof(struct mbx_modify_common_eq_delay),
1964 OCE_MBX_VER_V0);
1965 /* fill rest of mbx */
1966 mbx.u0.s.embedded = 1;
1967 mbx.payload_length = sizeof(struct mbx_modify_common_eq_delay);
1968 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1969
1970 fwcmd->params.req.num_eq = num;
1971 for (i = 0; i < num; i++) {
1972 fwcmd->params.req.delay[i].eq_id =
1973 htole32(set_eqd[i].eq_id);
1974 fwcmd->params.req.delay[i].phase = 0;
1975 fwcmd->params.req.delay[i].dm =
1976 htole32(set_eqd[i].delay_multiplier);
1977 }
1978
1979 /* command post */
1980 rc = oce_mbox_post(sc, &mbx, NULL);
1981
1982 if (!rc)
1983 rc = fwcmd->hdr.u0.rsp.status;
1984 if (rc)
1985 device_printf(sc->dev,
1986 "%s failed - cmd status: %d addi status: %d\n",
1987 __FUNCTION__, rc,
1988 fwcmd->hdr.u0.rsp.additional_status);
1989 }
1990
1991 int
oce_get_profile_config(POCE_SOFTC sc,uint32_t max_rss)1992 oce_get_profile_config(POCE_SOFTC sc, uint32_t max_rss)
1993 {
1994 struct oce_mbx mbx;
1995 struct mbx_common_get_profile_config *fwcmd;
1996 int rc = 0;
1997 int version = 0;
1998 struct oce_mq_sge *sgl;
1999 OCE_DMA_MEM dma;
2000 uint32_t desc_count = 0;
2001 struct oce_nic_resc_desc *nic_desc = NULL;
2002 int i;
2003 boolean_t nic_desc_valid = FALSE;
2004
2005 if (IS_BE2(sc))
2006 return -1;
2007
2008 /* Allocate DMA mem*/
2009 if (oce_dma_alloc(sc, sizeof(struct mbx_common_get_profile_config),
2010 &dma, 0))
2011 return ENOMEM;
2012
2013 /* Initialize MODIFY_EQ_DELAY ioctl header */
2014 fwcmd = OCE_DMAPTR(&dma, struct mbx_common_get_profile_config);
2015 bzero(fwcmd, sizeof(struct mbx_common_get_profile_config));
2016
2017 if (!IS_XE201(sc))
2018 version = OCE_MBX_VER_V1;
2019 else
2020 version = OCE_MBX_VER_V0;
2021
2022 bzero(&mbx, sizeof(struct oce_mbx));
2023 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
2024 MBX_SUBSYSTEM_COMMON,
2025 OPCODE_COMMON_GET_PROFILE_CONFIG,
2026 MBX_TIMEOUT_SEC,
2027 sizeof(struct mbx_common_get_profile_config),
2028 version);
2029 /* fill rest of mbx */
2030 mbx.u0.s.embedded = 0;
2031 mbx.payload_length = sizeof(struct mbx_common_get_profile_config);
2032 mbx.u0.s.sge_count = 1;
2033 sgl = &mbx.payload.u0.u1.sgl[0];
2034 sgl->pa_hi = htole32(upper_32_bits(dma.paddr));
2035 sgl->pa_lo = htole32((dma.paddr) & 0xFFFFFFFF);
2036 sgl->length = htole32(mbx.payload_length);
2037 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
2038
2039 fwcmd->params.req.type = ACTIVE_PROFILE;
2040
2041 /* command post */
2042 rc = oce_mbox_post(sc, &mbx, NULL);
2043 if (!rc)
2044 rc = fwcmd->hdr.u0.rsp.status;
2045 if (rc) {
2046 device_printf(sc->dev,
2047 "%s failed - cmd status: %d addi status: %d\n",
2048 __FUNCTION__, rc,
2049 fwcmd->hdr.u0.rsp.additional_status);
2050 goto error;
2051 }
2052
2053 nic_desc = (struct oce_nic_resc_desc *) fwcmd->params.rsp.resources;
2054 desc_count = HOST_32(fwcmd->params.rsp.desc_count);
2055 for (i = 0; i < desc_count; i++) {
2056 if ((nic_desc->desc_type == NIC_RESC_DESC_TYPE_V0) ||
2057 (nic_desc->desc_type == NIC_RESC_DESC_TYPE_V1)) {
2058 nic_desc_valid = TRUE;
2059 break;
2060 }
2061 nic_desc = (struct oce_nic_resc_desc *) \
2062 ((char *)nic_desc + nic_desc->desc_len);
2063 }
2064 if (!nic_desc_valid) {
2065 rc = -1;
2066 goto error;
2067 }
2068 else {
2069 sc->max_vlans = HOST_16(nic_desc->vlan_count);
2070 sc->nwqs = HOST_16(nic_desc->txq_count);
2071 if (sc->nwqs)
2072 sc->nwqs = MIN(sc->nwqs, OCE_MAX_WQ);
2073 else
2074 sc->nwqs = OCE_MAX_WQ;
2075
2076 sc->nrssqs = HOST_16(nic_desc->rssq_count);
2077 if (sc->nrssqs)
2078 sc->nrssqs = MIN(sc->nrssqs, max_rss);
2079 else
2080 sc->nrssqs = max_rss;
2081 sc->nrqs = sc->nrssqs + 1; /* 1 for def RX */
2082 }
2083 error:
2084 oce_dma_free(sc, &dma);
2085 return rc;
2086
2087 }
2088
2089 int
oce_get_func_config(POCE_SOFTC sc)2090 oce_get_func_config(POCE_SOFTC sc)
2091 {
2092 struct oce_mbx mbx;
2093 struct mbx_common_get_func_config *fwcmd;
2094 int rc = 0;
2095 int version = 0;
2096 struct oce_mq_sge *sgl;
2097 OCE_DMA_MEM dma;
2098 uint32_t desc_count = 0;
2099 struct oce_nic_resc_desc *nic_desc = NULL;
2100 int i;
2101 boolean_t nic_desc_valid = FALSE;
2102 uint32_t max_rss = 0;
2103
2104 if ((IS_BE(sc) || IS_SH(sc)) && (!sc->be3_native))
2105 max_rss = OCE_LEGACY_MODE_RSS;
2106 else
2107 max_rss = OCE_MAX_RSS;
2108
2109 /* Allocate DMA mem*/
2110 if (oce_dma_alloc(sc, sizeof(struct mbx_common_get_func_config),
2111 &dma, 0))
2112 return ENOMEM;
2113
2114 /* Initialize MODIFY_EQ_DELAY ioctl header */
2115 fwcmd = OCE_DMAPTR(&dma, struct mbx_common_get_func_config);
2116 bzero(fwcmd, sizeof(struct mbx_common_get_func_config));
2117
2118 if (IS_SH(sc))
2119 version = OCE_MBX_VER_V1;
2120 else
2121 version = OCE_MBX_VER_V0;
2122
2123 bzero(&mbx, sizeof(struct oce_mbx));
2124 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
2125 MBX_SUBSYSTEM_COMMON,
2126 OPCODE_COMMON_GET_FUNCTION_CONFIG,
2127 MBX_TIMEOUT_SEC,
2128 sizeof(struct mbx_common_get_func_config),
2129 version);
2130 /* fill rest of mbx */
2131 mbx.u0.s.embedded = 0;
2132 mbx.payload_length = sizeof(struct mbx_common_get_func_config);
2133 mbx.u0.s.sge_count = 1;
2134 sgl = &mbx.payload.u0.u1.sgl[0];
2135 sgl->pa_hi = htole32(upper_32_bits(dma.paddr));
2136 sgl->pa_lo = htole32((dma.paddr) & 0xFFFFFFFF);
2137 sgl->length = htole32(mbx.payload_length);
2138 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
2139
2140 /* command post */
2141 rc = oce_mbox_post(sc, &mbx, NULL);
2142 if (!rc)
2143 rc = fwcmd->hdr.u0.rsp.status;
2144 if (rc) {
2145 device_printf(sc->dev,
2146 "%s failed - cmd status: %d addi status: %d\n",
2147 __FUNCTION__, rc,
2148 fwcmd->hdr.u0.rsp.additional_status);
2149 goto error;
2150 }
2151
2152 nic_desc = (struct oce_nic_resc_desc *) fwcmd->params.rsp.resources;
2153 desc_count = HOST_32(fwcmd->params.rsp.desc_count);
2154 for (i = 0; i < desc_count; i++) {
2155 if ((nic_desc->desc_type == NIC_RESC_DESC_TYPE_V0) ||
2156 (nic_desc->desc_type == NIC_RESC_DESC_TYPE_V1)) {
2157 nic_desc_valid = TRUE;
2158 break;
2159 }
2160 nic_desc = (struct oce_nic_resc_desc *) \
2161 ((char *)nic_desc + nic_desc->desc_len);
2162 }
2163 if (!nic_desc_valid) {
2164 rc = -1;
2165 goto error;
2166 }
2167 else {
2168 sc->max_vlans = nic_desc->vlan_count;
2169 sc->nwqs = HOST_32(nic_desc->txq_count);
2170 if (sc->nwqs)
2171 sc->nwqs = MIN(sc->nwqs, OCE_MAX_WQ);
2172 else
2173 sc->nwqs = OCE_MAX_WQ;
2174
2175 sc->nrssqs = HOST_32(nic_desc->rssq_count);
2176 if (sc->nrssqs)
2177 sc->nrssqs = MIN(sc->nrssqs, max_rss);
2178 else
2179 sc->nrssqs = max_rss;
2180 sc->nrqs = sc->nrssqs + 1; /* 1 for def RX */
2181 }
2182 error:
2183 oce_dma_free(sc, &dma);
2184 return rc;
2185
2186 }
2187
2188 /* hw lro functions */
2189
2190 int
oce_mbox_nic_query_lro_capabilities(POCE_SOFTC sc,uint32_t * lro_rq_cnt,uint32_t * lro_flags)2191 oce_mbox_nic_query_lro_capabilities(POCE_SOFTC sc, uint32_t *lro_rq_cnt, uint32_t *lro_flags)
2192 {
2193 struct oce_mbx mbx;
2194 struct mbx_nic_query_lro_capabilities *fwcmd;
2195 int rc = 0;
2196
2197 bzero(&mbx, sizeof(struct oce_mbx));
2198
2199 fwcmd = (struct mbx_nic_query_lro_capabilities *)&mbx.payload;
2200 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
2201 MBX_SUBSYSTEM_NIC,
2202 0x20,MBX_TIMEOUT_SEC,
2203 sizeof(struct mbx_nic_query_lro_capabilities),
2204 OCE_MBX_VER_V0);
2205
2206 mbx.u0.s.embedded = 1;
2207 mbx.payload_length = sizeof(struct mbx_nic_query_lro_capabilities);
2208
2209 rc = oce_mbox_post(sc, &mbx, NULL);
2210 if (!rc)
2211 rc = fwcmd->hdr.u0.rsp.status;
2212 if (rc) {
2213 device_printf(sc->dev,
2214 "%s failed - cmd status: %d addi status: %d\n",
2215 __FUNCTION__, rc,
2216 fwcmd->hdr.u0.rsp.additional_status);
2217
2218 return rc;
2219 }
2220 if(lro_flags)
2221 *lro_flags = HOST_32(fwcmd->params.rsp.lro_flags);
2222
2223 if(lro_rq_cnt)
2224 *lro_rq_cnt = HOST_16(fwcmd->params.rsp.lro_rq_cnt);
2225
2226 return rc;
2227 }
2228
2229 int
oce_mbox_nic_set_iface_lro_config(POCE_SOFTC sc,int enable)2230 oce_mbox_nic_set_iface_lro_config(POCE_SOFTC sc, int enable)
2231 {
2232 struct oce_mbx mbx;
2233 struct mbx_nic_set_iface_lro_config *fwcmd;
2234 int rc = 0;
2235
2236 bzero(&mbx, sizeof(struct oce_mbx));
2237
2238 fwcmd = (struct mbx_nic_set_iface_lro_config *)&mbx.payload;
2239 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
2240 MBX_SUBSYSTEM_NIC,
2241 0x26,MBX_TIMEOUT_SEC,
2242 sizeof(struct mbx_nic_set_iface_lro_config),
2243 OCE_MBX_VER_V0);
2244
2245 mbx.u0.s.embedded = 1;
2246 mbx.payload_length = sizeof(struct mbx_nic_set_iface_lro_config);
2247
2248 fwcmd->params.req.iface_id = sc->if_id;
2249 fwcmd->params.req.lro_flags = 0;
2250
2251 if(enable) {
2252 fwcmd->params.req.lro_flags = LRO_FLAGS_HASH_MODE | LRO_FLAGS_RSS_MODE;
2253 fwcmd->params.req.lro_flags |= LRO_FLAGS_CLSC_IPV4 | LRO_FLAGS_CLSC_IPV6;
2254
2255 fwcmd->params.req.max_clsc_byte_cnt = 64*1024; /* min = 2974, max = 0xfa59 */
2256 fwcmd->params.req.max_clsc_seg_cnt = 43; /* min = 2, max = 64 */
2257 fwcmd->params.req.max_clsc_usec_delay = 18; /* min = 1, max = 256 */
2258 fwcmd->params.req.min_clsc_frame_byte_cnt = 0; /* min = 1, max = 9014 */
2259 }
2260
2261 rc = oce_mbox_post(sc, &mbx, NULL);
2262 if (!rc)
2263 rc = fwcmd->hdr.u0.rsp.status;
2264 if (rc) {
2265 device_printf(sc->dev,
2266 "%s failed - cmd status: %d addi status: %d\n",
2267 __FUNCTION__, rc,
2268 fwcmd->hdr.u0.rsp.additional_status);
2269
2270 return rc;
2271 }
2272 return rc;
2273 }
2274
2275 int
oce_mbox_create_rq_v2(struct oce_rq * rq)2276 oce_mbox_create_rq_v2(struct oce_rq *rq)
2277 {
2278 struct oce_mbx mbx;
2279 struct mbx_create_nic_rq_v2 *fwcmd;
2280 POCE_SOFTC sc = rq->parent;
2281 int rc = 0, num_pages = 0;
2282
2283 if (rq->qstate == QCREATED)
2284 return 0;
2285
2286 bzero(&mbx, sizeof(struct oce_mbx));
2287
2288 fwcmd = (struct mbx_create_nic_rq_v2 *)&mbx.payload;
2289 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
2290 MBX_SUBSYSTEM_NIC,
2291 0x08, MBX_TIMEOUT_SEC,
2292 sizeof(struct mbx_create_nic_rq_v2),
2293 OCE_MBX_VER_V2);
2294
2295 /* oce_page_list will also prepare pages */
2296 num_pages = oce_page_list(rq->ring, &fwcmd->params.req.pages[0]);
2297
2298 fwcmd->params.req.cq_id = rq->cq->cq_id;
2299 fwcmd->params.req.frag_size = rq->cfg.frag_size/2048;
2300 fwcmd->params.req.num_pages = num_pages;
2301
2302 fwcmd->params.req.if_id = sc->if_id;
2303
2304 fwcmd->params.req.max_frame_size = rq->cfg.mtu;
2305 fwcmd->params.req.page_size = 1;
2306 if(rq->cfg.is_rss_queue) {
2307 fwcmd->params.req.rq_flags = (NIC_RQ_FLAGS_RSS | NIC_RQ_FLAGS_LRO);
2308 }else {
2309 device_printf(sc->dev,
2310 "non rss lro queue should not be created \n");
2311 goto error;
2312 }
2313 mbx.u0.s.embedded = 1;
2314 mbx.payload_length = sizeof(struct mbx_create_nic_rq_v2);
2315
2316 rc = oce_mbox_post(sc, &mbx, NULL);
2317 if (!rc)
2318 rc = fwcmd->hdr.u0.rsp.status;
2319 if (rc) {
2320 device_printf(sc->dev,
2321 "%s failed - cmd status: %d addi status: %d\n",
2322 __FUNCTION__, rc,
2323 fwcmd->hdr.u0.rsp.additional_status);
2324 goto error;
2325 }
2326 rq->rq_id = HOST_16(fwcmd->params.rsp.rq_id);
2327 rq->rss_cpuid = fwcmd->params.rsp.rss_cpuid;
2328
2329 error:
2330 return rc;
2331 }
2332