1 /*-
2 * Copyright (c) 2016-2017 Microsoft Corp.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 #ifdef NEW_PCIB
29
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/types.h>
33 #include <sys/malloc.h>
34 #include <sys/module.h>
35 #include <sys/kernel.h>
36 #include <sys/queue.h>
37 #include <sys/lock.h>
38 #include <sys/sx.h>
39 #include <sys/smp.h>
40 #include <sys/sysctl.h>
41 #include <sys/bus.h>
42 #include <sys/rman.h>
43 #include <sys/mutex.h>
44 #include <sys/errno.h>
45
46 #include <vm/vm.h>
47 #include <vm/vm_param.h>
48 #include <vm/vm_kern.h>
49 #include <vm/pmap.h>
50
51 #include <machine/atomic.h>
52 #include <machine/bus.h>
53 #include <machine/frame.h>
54 #include <machine/pci_cfgreg.h>
55 #include <machine/resource.h>
56
57 #include <sys/pciio.h>
58 #include <dev/pci/pcireg.h>
59 #include <dev/pci/pcivar.h>
60 #include <dev/pci/pci_private.h>
61 #include <dev/pci/pcib_private.h>
62 #include "pcib_if.h"
63
64 #include <machine/intr_machdep.h>
65 #include <x86/apicreg.h>
66 #include <x86/apicvar.h>
67
68 #include <dev/hyperv/include/hyperv.h>
69 #include <dev/hyperv/include/hyperv_busdma.h>
70 #include <dev/hyperv/include/vmbus_xact.h>
71 #include <dev/hyperv/vmbus/vmbus_reg.h>
72 #include <dev/hyperv/vmbus/vmbus_chanvar.h>
73
74 #include "vmbus_if.h"
75
76 #if __FreeBSD_version < 1100000
77 typedef u_long rman_res_t;
78 #define RM_MAX_END (~(rman_res_t)0)
79 #endif
80
81 struct completion {
82 unsigned int done;
83 struct mtx lock;
84 };
85
86 static void
init_completion(struct completion * c)87 init_completion(struct completion *c)
88 {
89 memset(c, 0, sizeof(*c));
90 mtx_init(&c->lock, "hvcmpl", NULL, MTX_DEF);
91 c->done = 0;
92 }
93
94 static void
free_completion(struct completion * c)95 free_completion(struct completion *c)
96 {
97 mtx_destroy(&c->lock);
98 }
99
100 static void
complete(struct completion * c)101 complete(struct completion *c)
102 {
103 mtx_lock(&c->lock);
104 c->done++;
105 mtx_unlock(&c->lock);
106 wakeup(c);
107 }
108
109 static void
wait_for_completion(struct completion * c)110 wait_for_completion(struct completion *c)
111 {
112 mtx_lock(&c->lock);
113 while (c->done == 0)
114 mtx_sleep(c, &c->lock, 0, "hvwfc", 0);
115 c->done--;
116 mtx_unlock(&c->lock);
117 }
118
119 /*
120 * Return: 0 if completed, a non-zero value if timed out.
121 */
122 static int
wait_for_completion_timeout(struct completion * c,int timeout)123 wait_for_completion_timeout(struct completion *c, int timeout)
124 {
125 int ret;
126
127 mtx_lock(&c->lock);
128
129 if (c->done == 0)
130 mtx_sleep(c, &c->lock, 0, "hvwfc", timeout);
131
132 if (c->done > 0) {
133 c->done--;
134 ret = 0;
135 } else {
136 ret = 1;
137 }
138
139 mtx_unlock(&c->lock);
140
141 return (ret);
142 }
143
144 #define PCI_MAKE_VERSION(major, minor) ((uint32_t)(((major) << 16) | (major)))
145
146 enum {
147 PCI_PROTOCOL_VERSION_1_1 = PCI_MAKE_VERSION(1, 1),
148 PCI_PROTOCOL_VERSION_CURRENT = PCI_PROTOCOL_VERSION_1_1
149 };
150
151 #define PCI_CONFIG_MMIO_LENGTH 0x2000
152 #define CFG_PAGE_OFFSET 0x1000
153 #define CFG_PAGE_SIZE (PCI_CONFIG_MMIO_LENGTH - CFG_PAGE_OFFSET)
154
155 /*
156 * Message Types
157 */
158
159 enum pci_message_type {
160 /*
161 * Version 1.1
162 */
163 PCI_MESSAGE_BASE = 0x42490000,
164 PCI_BUS_RELATIONS = PCI_MESSAGE_BASE + 0,
165 PCI_QUERY_BUS_RELATIONS = PCI_MESSAGE_BASE + 1,
166 PCI_POWER_STATE_CHANGE = PCI_MESSAGE_BASE + 4,
167 PCI_QUERY_RESOURCE_REQUIREMENTS = PCI_MESSAGE_BASE + 5,
168 PCI_QUERY_RESOURCE_RESOURCES = PCI_MESSAGE_BASE + 6,
169 PCI_BUS_D0ENTRY = PCI_MESSAGE_BASE + 7,
170 PCI_BUS_D0EXIT = PCI_MESSAGE_BASE + 8,
171 PCI_READ_BLOCK = PCI_MESSAGE_BASE + 9,
172 PCI_WRITE_BLOCK = PCI_MESSAGE_BASE + 0xA,
173 PCI_EJECT = PCI_MESSAGE_BASE + 0xB,
174 PCI_QUERY_STOP = PCI_MESSAGE_BASE + 0xC,
175 PCI_REENABLE = PCI_MESSAGE_BASE + 0xD,
176 PCI_QUERY_STOP_FAILED = PCI_MESSAGE_BASE + 0xE,
177 PCI_EJECTION_COMPLETE = PCI_MESSAGE_BASE + 0xF,
178 PCI_RESOURCES_ASSIGNED = PCI_MESSAGE_BASE + 0x10,
179 PCI_RESOURCES_RELEASED = PCI_MESSAGE_BASE + 0x11,
180 PCI_INVALIDATE_BLOCK = PCI_MESSAGE_BASE + 0x12,
181 PCI_QUERY_PROTOCOL_VERSION = PCI_MESSAGE_BASE + 0x13,
182 PCI_CREATE_INTERRUPT_MESSAGE = PCI_MESSAGE_BASE + 0x14,
183 PCI_DELETE_INTERRUPT_MESSAGE = PCI_MESSAGE_BASE + 0x15,
184 PCI_MESSAGE_MAXIMUM
185 };
186
187 /*
188 * Structures defining the virtual PCI Express protocol.
189 */
190
191 union pci_version {
192 struct {
193 uint16_t minor_version;
194 uint16_t major_version;
195 } parts;
196 uint32_t version;
197 } __packed;
198
199 /*
200 * This representation is the one used in Windows, which is
201 * what is expected when sending this back and forth with
202 * the Hyper-V parent partition.
203 */
204 union win_slot_encoding {
205 struct {
206 uint32_t slot:5;
207 uint32_t func:3;
208 uint32_t reserved:24;
209 } bits;
210 uint32_t val;
211 } __packed;
212
213 struct pci_func_desc {
214 uint16_t v_id; /* vendor ID */
215 uint16_t d_id; /* device ID */
216 uint8_t rev;
217 uint8_t prog_intf;
218 uint8_t subclass;
219 uint8_t base_class;
220 uint32_t subsystem_id;
221 union win_slot_encoding wslot;
222 uint32_t ser; /* serial number */
223 } __packed;
224
225 struct hv_msi_desc {
226 uint8_t vector;
227 uint8_t delivery_mode;
228 uint16_t vector_count;
229 uint32_t reserved;
230 uint64_t cpu_mask;
231 } __packed;
232
233 struct tran_int_desc {
234 uint16_t reserved;
235 uint16_t vector_count;
236 uint32_t data;
237 uint64_t address;
238 } __packed;
239
240 struct pci_message {
241 uint32_t type;
242 } __packed;
243
244 struct pci_child_message {
245 struct pci_message message_type;
246 union win_slot_encoding wslot;
247 } __packed;
248
249 struct pci_incoming_message {
250 struct vmbus_chanpkt_hdr hdr;
251 struct pci_message message_type;
252 } __packed;
253
254 struct pci_response {
255 struct vmbus_chanpkt_hdr hdr;
256 int32_t status; /* negative values are failures */
257 } __packed;
258
259 struct pci_packet {
260 void (*completion_func)(void *context, struct pci_response *resp,
261 int resp_packet_size);
262 void *compl_ctxt;
263
264 struct pci_message message[0];
265 };
266
267 /*
268 * Specific message types supporting the PCI protocol.
269 */
270
271 struct pci_version_request {
272 struct pci_message message_type;
273 uint32_t protocol_version;
274 uint32_t is_last_attempt:1;
275 uint32_t reservedz:31;
276 } __packed;
277
278 struct pci_bus_d0_entry {
279 struct pci_message message_type;
280 uint32_t reserved;
281 uint64_t mmio_base;
282 } __packed;
283
284 struct pci_bus_relations {
285 struct pci_incoming_message incoming;
286 uint32_t device_count;
287 struct pci_func_desc func[0];
288 } __packed;
289
290 #define MAX_NUM_BARS (PCIR_MAX_BAR_0 + 1)
291 struct pci_q_res_req_response {
292 struct vmbus_chanpkt_hdr hdr;
293 int32_t status; /* negative values are failures */
294 uint32_t probed_bar[MAX_NUM_BARS];
295 } __packed;
296
297 struct pci_resources_assigned {
298 struct pci_message message_type;
299 union win_slot_encoding wslot;
300 uint8_t memory_range[0x14][MAX_NUM_BARS]; /* unused here */
301 uint32_t msi_descriptors;
302 uint32_t reserved[4];
303 } __packed;
304
305 struct pci_create_interrupt {
306 struct pci_message message_type;
307 union win_slot_encoding wslot;
308 struct hv_msi_desc int_desc;
309 } __packed;
310
311 struct pci_create_int_response {
312 struct pci_response response;
313 uint32_t reserved;
314 struct tran_int_desc int_desc;
315 } __packed;
316
317 struct pci_delete_interrupt {
318 struct pci_message message_type;
319 union win_slot_encoding wslot;
320 struct tran_int_desc int_desc;
321 } __packed;
322
323 struct pci_dev_incoming {
324 struct pci_incoming_message incoming;
325 union win_slot_encoding wslot;
326 } __packed;
327
328 struct pci_eject_response {
329 struct pci_message message_type;
330 union win_slot_encoding wslot;
331 uint32_t status;
332 } __packed;
333
334 /*
335 * Driver specific state.
336 */
337
338 enum hv_pcibus_state {
339 hv_pcibus_init = 0,
340 hv_pcibus_installed,
341 };
342
343 struct hv_pcibus {
344 device_t pcib;
345 device_t pci_bus;
346 struct vmbus_pcib_softc *sc;
347
348 uint16_t pci_domain;
349
350 enum hv_pcibus_state state;
351
352 struct resource *cfg_res;
353
354 struct completion query_completion, *query_comp;
355
356 struct mtx config_lock; /* Avoid two threads writing index page */
357 struct mtx device_list_lock; /* Protect lists below */
358 TAILQ_HEAD(, hv_pci_dev) children;
359 TAILQ_HEAD(, hv_dr_state) dr_list;
360
361 volatile int detaching;
362 };
363
364 struct hv_pci_dev {
365 TAILQ_ENTRY(hv_pci_dev) link;
366
367 struct pci_func_desc desc;
368
369 bool reported_missing;
370
371 struct hv_pcibus *hbus;
372 struct task eject_task;
373
374 TAILQ_HEAD(, hv_irq_desc) irq_desc_list;
375
376 /*
377 * What would be observed if one wrote 0xFFFFFFFF to a BAR and then
378 * read it back, for each of the BAR offsets within config space.
379 */
380 uint32_t probed_bar[MAX_NUM_BARS];
381 };
382
383 /*
384 * Tracks "Device Relations" messages from the host, which must be both
385 * processed in order.
386 */
387 struct hv_dr_work {
388 struct task task;
389 struct hv_pcibus *bus;
390 };
391
392 struct hv_dr_state {
393 TAILQ_ENTRY(hv_dr_state) link;
394 uint32_t device_count;
395 struct pci_func_desc func[0];
396 };
397
398 struct hv_irq_desc {
399 TAILQ_ENTRY(hv_irq_desc) link;
400 struct tran_int_desc desc;
401 int irq;
402 };
403
404 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
405 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
406 #define PCI_FUNC(devfn) ((devfn) & 0x07)
407
408 static uint32_t
devfn_to_wslot(unsigned int devfn)409 devfn_to_wslot(unsigned int devfn)
410 {
411 union win_slot_encoding wslot;
412
413 wslot.val = 0;
414 wslot.bits.slot = PCI_SLOT(devfn);
415 wslot.bits.func = PCI_FUNC(devfn);
416
417 return (wslot.val);
418 }
419
420 static unsigned int
wslot_to_devfn(uint32_t wslot)421 wslot_to_devfn(uint32_t wslot)
422 {
423 union win_slot_encoding encoding;
424 unsigned int slot;
425 unsigned int func;
426
427 encoding.val = wslot;
428
429 slot = encoding.bits.slot;
430 func = encoding.bits.func;
431
432 return (PCI_DEVFN(slot, func));
433 }
434
435 struct vmbus_pcib_softc {
436 struct vmbus_channel *chan;
437 void *rx_buf;
438
439 struct taskqueue *taskq;
440
441 struct hv_pcibus *hbus;
442 };
443
444 /* {44C4F61D-4444-4400-9D52-802E27EDE19F} */
445 static const struct hyperv_guid g_pass_through_dev_type = {
446 .hv_guid = {0x1D, 0xF6, 0xC4, 0x44, 0x44, 0x44, 0x00, 0x44,
447 0x9D, 0x52, 0x80, 0x2E, 0x27, 0xED, 0xE1, 0x9F}
448 };
449
450 struct hv_pci_compl {
451 struct completion host_event;
452 int32_t completion_status;
453 };
454
455 struct q_res_req_compl {
456 struct completion host_event;
457 struct hv_pci_dev *hpdev;
458 };
459
460 struct compose_comp_ctxt {
461 struct hv_pci_compl comp_pkt;
462 struct tran_int_desc int_desc;
463 };
464
465 /*
466 * It is possible the device is revoked during initialization.
467 * Check if this happens during wait.
468 * Return: 0 if response arrived, ENODEV if device revoked.
469 */
470 static int
wait_for_response(struct hv_pcibus * hbus,struct completion * c)471 wait_for_response(struct hv_pcibus *hbus, struct completion *c)
472 {
473 do {
474 if (vmbus_chan_is_revoked(hbus->sc->chan)) {
475 device_printf(hbus->pcib,
476 "The device is revoked.\n");
477 return (ENODEV);
478 }
479 } while (wait_for_completion_timeout(c, hz /10) != 0);
480
481 return 0;
482 }
483
484 static void
hv_pci_generic_compl(void * context,struct pci_response * resp,int resp_packet_size)485 hv_pci_generic_compl(void *context, struct pci_response *resp,
486 int resp_packet_size)
487 {
488 struct hv_pci_compl *comp_pkt = context;
489
490 if (resp_packet_size >= sizeof(struct pci_response))
491 comp_pkt->completion_status = resp->status;
492 else
493 comp_pkt->completion_status = -1;
494
495 complete(&comp_pkt->host_event);
496 }
497
498 static void
q_resource_requirements(void * context,struct pci_response * resp,int resp_packet_size)499 q_resource_requirements(void *context, struct pci_response *resp,
500 int resp_packet_size)
501 {
502 struct q_res_req_compl *completion = context;
503 struct pci_q_res_req_response *q_res_req =
504 (struct pci_q_res_req_response *)resp;
505 int i;
506
507 if (resp->status < 0) {
508 printf("vmbus_pcib: failed to query resource requirements\n");
509 } else {
510 for (i = 0; i < MAX_NUM_BARS; i++)
511 completion->hpdev->probed_bar[i] =
512 q_res_req->probed_bar[i];
513 }
514
515 complete(&completion->host_event);
516 }
517
518 static void
hv_pci_compose_compl(void * context,struct pci_response * resp,int resp_packet_size)519 hv_pci_compose_compl(void *context, struct pci_response *resp,
520 int resp_packet_size)
521 {
522 struct compose_comp_ctxt *comp_pkt = context;
523 struct pci_create_int_response *int_resp =
524 (struct pci_create_int_response *)resp;
525
526 comp_pkt->comp_pkt.completion_status = resp->status;
527 comp_pkt->int_desc = int_resp->int_desc;
528 complete(&comp_pkt->comp_pkt.host_event);
529 }
530
531 static void
hv_int_desc_free(struct hv_pci_dev * hpdev,struct hv_irq_desc * hid)532 hv_int_desc_free(struct hv_pci_dev *hpdev, struct hv_irq_desc *hid)
533 {
534 struct pci_delete_interrupt *int_pkt;
535 struct {
536 struct pci_packet pkt;
537 uint8_t buffer[sizeof(struct pci_delete_interrupt)];
538 } ctxt;
539
540 memset(&ctxt, 0, sizeof(ctxt));
541 int_pkt = (struct pci_delete_interrupt *)&ctxt.pkt.message;
542 int_pkt->message_type.type = PCI_DELETE_INTERRUPT_MESSAGE;
543 int_pkt->wslot.val = hpdev->desc.wslot.val;
544 int_pkt->int_desc = hid->desc;
545
546 vmbus_chan_send(hpdev->hbus->sc->chan, VMBUS_CHANPKT_TYPE_INBAND, 0,
547 int_pkt, sizeof(*int_pkt), 0);
548
549 free(hid, M_DEVBUF);
550 }
551
552 static void
hv_pci_delete_device(struct hv_pci_dev * hpdev)553 hv_pci_delete_device(struct hv_pci_dev *hpdev)
554 {
555 struct hv_pcibus *hbus = hpdev->hbus;
556 struct hv_irq_desc *hid, *tmp_hid;
557 device_t pci_dev;
558 int devfn;
559
560 devfn = wslot_to_devfn(hpdev->desc.wslot.val);
561
562 bus_topo_lock();
563
564 pci_dev = pci_find_dbsf(hbus->pci_domain,
565 0, PCI_SLOT(devfn), PCI_FUNC(devfn));
566 if (pci_dev)
567 device_delete_child(hbus->pci_bus, pci_dev);
568
569 bus_topo_unlock();
570
571 mtx_lock(&hbus->device_list_lock);
572 TAILQ_REMOVE(&hbus->children, hpdev, link);
573 mtx_unlock(&hbus->device_list_lock);
574
575 TAILQ_FOREACH_SAFE(hid, &hpdev->irq_desc_list, link, tmp_hid)
576 hv_int_desc_free(hpdev, hid);
577
578 free(hpdev, M_DEVBUF);
579 }
580
581 static struct hv_pci_dev *
new_pcichild_device(struct hv_pcibus * hbus,struct pci_func_desc * desc)582 new_pcichild_device(struct hv_pcibus *hbus, struct pci_func_desc *desc)
583 {
584 struct hv_pci_dev *hpdev;
585 struct pci_child_message *res_req;
586 struct q_res_req_compl comp_pkt;
587 struct {
588 struct pci_packet pkt;
589 uint8_t buffer[sizeof(struct pci_child_message)];
590 } ctxt;
591 int ret;
592
593 hpdev = malloc(sizeof(*hpdev), M_DEVBUF, M_WAITOK | M_ZERO);
594 hpdev->hbus = hbus;
595
596 TAILQ_INIT(&hpdev->irq_desc_list);
597
598 init_completion(&comp_pkt.host_event);
599 comp_pkt.hpdev = hpdev;
600
601 ctxt.pkt.compl_ctxt = &comp_pkt;
602 ctxt.pkt.completion_func = q_resource_requirements;
603
604 res_req = (struct pci_child_message *)&ctxt.pkt.message;
605 res_req->message_type.type = PCI_QUERY_RESOURCE_REQUIREMENTS;
606 res_req->wslot.val = desc->wslot.val;
607
608 ret = vmbus_chan_send(hbus->sc->chan,
609 VMBUS_CHANPKT_TYPE_INBAND, VMBUS_CHANPKT_FLAG_RC,
610 res_req, sizeof(*res_req), (uint64_t)(uintptr_t)&ctxt.pkt);
611 if (ret)
612 goto err;
613
614 if (wait_for_response(hbus, &comp_pkt.host_event))
615 goto err;
616
617 free_completion(&comp_pkt.host_event);
618
619 hpdev->desc = *desc;
620
621 mtx_lock(&hbus->device_list_lock);
622 if (TAILQ_EMPTY(&hbus->children))
623 hbus->pci_domain = desc->ser & 0xFFFF;
624 TAILQ_INSERT_TAIL(&hbus->children, hpdev, link);
625 mtx_unlock(&hbus->device_list_lock);
626 return (hpdev);
627 err:
628 free_completion(&comp_pkt.host_event);
629 free(hpdev, M_DEVBUF);
630 return (NULL);
631 }
632
633 #if __FreeBSD_version < 1100000
634
635 /* Old versions don't have BUS_RESCAN(). Let's copy it from FreeBSD 11. */
636
637 static struct pci_devinfo *
pci_identify_function(device_t pcib,device_t dev,int domain,int busno,int slot,int func,size_t dinfo_size)638 pci_identify_function(device_t pcib, device_t dev, int domain, int busno,
639 int slot, int func, size_t dinfo_size)
640 {
641 struct pci_devinfo *dinfo;
642
643 dinfo = pci_read_device(pcib, domain, busno, slot, func, dinfo_size);
644 if (dinfo != NULL)
645 pci_add_child(dev, dinfo);
646
647 return (dinfo);
648 }
649
650 static int
pci_rescan(device_t dev)651 pci_rescan(device_t dev)
652 {
653 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
654 device_t pcib = device_get_parent(dev);
655 struct pci_softc *sc;
656 device_t child, *devlist, *unchanged;
657 int devcount, error, i, j, maxslots, oldcount;
658 int busno, domain, s, f, pcifunchigh;
659 uint8_t hdrtype;
660
661 /* No need to check for ARI on a rescan. */
662 error = device_get_children(dev, &devlist, &devcount);
663 if (error)
664 return (error);
665 if (devcount != 0) {
666 unchanged = malloc(devcount * sizeof(device_t), M_TEMP,
667 M_NOWAIT | M_ZERO);
668 if (unchanged == NULL) {
669 free(devlist, M_TEMP);
670 return (ENOMEM);
671 }
672 } else
673 unchanged = NULL;
674
675 sc = device_get_softc(dev);
676 domain = pcib_get_domain(dev);
677 busno = pcib_get_bus(dev);
678 maxslots = PCIB_MAXSLOTS(pcib);
679 for (s = 0; s <= maxslots; s++) {
680 /* If function 0 is not present, skip to the next slot. */
681 f = 0;
682 if (REG(PCIR_VENDOR, 2) == 0xffff)
683 continue;
684 pcifunchigh = 0;
685 hdrtype = REG(PCIR_HDRTYPE, 1);
686 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
687 continue;
688 if (hdrtype & PCIM_MFDEV)
689 pcifunchigh = PCIB_MAXFUNCS(pcib);
690 for (f = 0; f <= pcifunchigh; f++) {
691 if (REG(PCIR_VENDOR, 2) == 0xffff)
692 continue;
693
694 /*
695 * Found a valid function. Check if a
696 * device_t for this device already exists.
697 */
698 for (i = 0; i < devcount; i++) {
699 child = devlist[i];
700 if (child == NULL)
701 continue;
702 if (pci_get_slot(child) == s &&
703 pci_get_function(child) == f) {
704 unchanged[i] = child;
705 goto next_func;
706 }
707 }
708
709 pci_identify_function(pcib, dev, domain, busno, s, f,
710 sizeof(struct pci_devinfo));
711 next_func:;
712 }
713 }
714
715 /* Remove devices that are no longer present. */
716 for (i = 0; i < devcount; i++) {
717 if (unchanged[i] != NULL)
718 continue;
719 device_delete_child(dev, devlist[i]);
720 }
721
722 free(devlist, M_TEMP);
723 oldcount = devcount;
724
725 /* Try to attach the devices just added. */
726 error = device_get_children(dev, &devlist, &devcount);
727 if (error) {
728 free(unchanged, M_TEMP);
729 return (error);
730 }
731
732 for (i = 0; i < devcount; i++) {
733 for (j = 0; j < oldcount; j++) {
734 if (devlist[i] == unchanged[j])
735 goto next_device;
736 }
737
738 device_probe_and_attach(devlist[i]);
739 next_device:;
740 }
741
742 free(unchanged, M_TEMP);
743 free(devlist, M_TEMP);
744 return (0);
745 #undef REG
746 }
747
748 #else
749
750 static int
pci_rescan(device_t dev)751 pci_rescan(device_t dev)
752 {
753 return (BUS_RESCAN(dev));
754 }
755
756 #endif
757
758 static void
pci_devices_present_work(void * arg,int pending __unused)759 pci_devices_present_work(void *arg, int pending __unused)
760 {
761 struct hv_dr_work *dr_wrk = arg;
762 struct hv_dr_state *dr = NULL;
763 struct hv_pcibus *hbus;
764 uint32_t child_no;
765 bool found;
766 struct pci_func_desc *new_desc;
767 struct hv_pci_dev *hpdev, *tmp_hpdev;
768 struct completion *query_comp;
769 bool need_rescan = false;
770
771 hbus = dr_wrk->bus;
772 free(dr_wrk, M_DEVBUF);
773
774 /* Pull this off the queue and process it if it was the last one. */
775 mtx_lock(&hbus->device_list_lock);
776 while (!TAILQ_EMPTY(&hbus->dr_list)) {
777 dr = TAILQ_FIRST(&hbus->dr_list);
778 TAILQ_REMOVE(&hbus->dr_list, dr, link);
779
780 /* Throw this away if the list still has stuff in it. */
781 if (!TAILQ_EMPTY(&hbus->dr_list)) {
782 free(dr, M_DEVBUF);
783 continue;
784 }
785 }
786 mtx_unlock(&hbus->device_list_lock);
787
788 if (!dr)
789 return;
790
791 /* First, mark all existing children as reported missing. */
792 mtx_lock(&hbus->device_list_lock);
793 TAILQ_FOREACH(hpdev, &hbus->children, link)
794 hpdev->reported_missing = true;
795 mtx_unlock(&hbus->device_list_lock);
796
797 /* Next, add back any reported devices. */
798 for (child_no = 0; child_no < dr->device_count; child_no++) {
799 found = false;
800 new_desc = &dr->func[child_no];
801
802 mtx_lock(&hbus->device_list_lock);
803 TAILQ_FOREACH(hpdev, &hbus->children, link) {
804 if ((hpdev->desc.wslot.val ==
805 new_desc->wslot.val) &&
806 (hpdev->desc.v_id == new_desc->v_id) &&
807 (hpdev->desc.d_id == new_desc->d_id) &&
808 (hpdev->desc.ser == new_desc->ser)) {
809 hpdev->reported_missing = false;
810 found = true;
811 break;
812 }
813 }
814 mtx_unlock(&hbus->device_list_lock);
815
816 if (!found) {
817 if (!need_rescan)
818 need_rescan = true;
819
820 hpdev = new_pcichild_device(hbus, new_desc);
821 if (!hpdev)
822 printf("vmbus_pcib: failed to add a child\n");
823 }
824 }
825
826 /* Remove missing device(s), if any */
827 TAILQ_FOREACH_SAFE(hpdev, &hbus->children, link, tmp_hpdev) {
828 if (hpdev->reported_missing)
829 hv_pci_delete_device(hpdev);
830 }
831
832 /* Rescan the bus to find any new device, if necessary. */
833 if (hbus->state == hv_pcibus_installed && need_rescan)
834 pci_rescan(hbus->pci_bus);
835
836 /* Wake up hv_pci_query_relations(), if it's waiting. */
837 query_comp = hbus->query_comp;
838 if (query_comp) {
839 hbus->query_comp = NULL;
840 complete(query_comp);
841 }
842
843 free(dr, M_DEVBUF);
844 }
845
846 static struct hv_pci_dev *
get_pcichild_wslot(struct hv_pcibus * hbus,uint32_t wslot)847 get_pcichild_wslot(struct hv_pcibus *hbus, uint32_t wslot)
848 {
849 struct hv_pci_dev *hpdev, *ret = NULL;
850
851 mtx_lock(&hbus->device_list_lock);
852 TAILQ_FOREACH(hpdev, &hbus->children, link) {
853 if (hpdev->desc.wslot.val == wslot) {
854 ret = hpdev;
855 break;
856 }
857 }
858 mtx_unlock(&hbus->device_list_lock);
859
860 return (ret);
861 }
862
863 static void
hv_pci_devices_present(struct hv_pcibus * hbus,struct pci_bus_relations * relations)864 hv_pci_devices_present(struct hv_pcibus *hbus,
865 struct pci_bus_relations *relations)
866 {
867 struct hv_dr_state *dr;
868 struct hv_dr_work *dr_wrk;
869 unsigned long dr_size;
870
871 if (hbus->detaching && relations->device_count > 0)
872 return;
873
874 dr_size = offsetof(struct hv_dr_state, func) +
875 (sizeof(struct pci_func_desc) * relations->device_count);
876 dr = malloc(dr_size, M_DEVBUF, M_WAITOK | M_ZERO);
877
878 dr->device_count = relations->device_count;
879 if (dr->device_count != 0)
880 memcpy(dr->func, relations->func,
881 sizeof(struct pci_func_desc) * dr->device_count);
882
883 mtx_lock(&hbus->device_list_lock);
884 TAILQ_INSERT_TAIL(&hbus->dr_list, dr, link);
885 mtx_unlock(&hbus->device_list_lock);
886
887 dr_wrk = malloc(sizeof(*dr_wrk), M_DEVBUF, M_WAITOK | M_ZERO);
888 dr_wrk->bus = hbus;
889 TASK_INIT(&dr_wrk->task, 0, pci_devices_present_work, dr_wrk);
890 taskqueue_enqueue(hbus->sc->taskq, &dr_wrk->task);
891 }
892
893 static void
hv_eject_device_work(void * arg,int pending __unused)894 hv_eject_device_work(void *arg, int pending __unused)
895 {
896 struct hv_pci_dev *hpdev = arg;
897 union win_slot_encoding wslot = hpdev->desc.wslot;
898 struct hv_pcibus *hbus = hpdev->hbus;
899 struct pci_eject_response *eject_pkt;
900 struct {
901 struct pci_packet pkt;
902 uint8_t buffer[sizeof(struct pci_eject_response)];
903 } ctxt;
904
905 hv_pci_delete_device(hpdev);
906
907 memset(&ctxt, 0, sizeof(ctxt));
908 eject_pkt = (struct pci_eject_response *)&ctxt.pkt.message;
909 eject_pkt->message_type.type = PCI_EJECTION_COMPLETE;
910 eject_pkt->wslot.val = wslot.val;
911 vmbus_chan_send(hbus->sc->chan, VMBUS_CHANPKT_TYPE_INBAND, 0,
912 eject_pkt, sizeof(*eject_pkt), 0);
913 }
914
915 static void
hv_pci_eject_device(struct hv_pci_dev * hpdev)916 hv_pci_eject_device(struct hv_pci_dev *hpdev)
917 {
918 struct hv_pcibus *hbus = hpdev->hbus;
919 struct taskqueue *taskq;
920
921 if (hbus->detaching)
922 return;
923
924 /*
925 * Push this task into the same taskqueue on which
926 * vmbus_pcib_attach() runs, so we're sure this task can't run
927 * concurrently with vmbus_pcib_attach().
928 */
929 TASK_INIT(&hpdev->eject_task, 0, hv_eject_device_work, hpdev);
930 taskq = vmbus_chan_mgmt_tq(hbus->sc->chan);
931 taskqueue_enqueue(taskq, &hpdev->eject_task);
932 }
933
934 #define PCIB_PACKET_SIZE 0x100
935
936 static void
vmbus_pcib_on_channel_callback(struct vmbus_channel * chan,void * arg)937 vmbus_pcib_on_channel_callback(struct vmbus_channel *chan, void *arg)
938 {
939 struct vmbus_pcib_softc *sc = arg;
940 struct hv_pcibus *hbus = sc->hbus;
941
942 void *buffer;
943 int bufferlen = PCIB_PACKET_SIZE;
944
945 struct pci_packet *comp_packet;
946 struct pci_response *response;
947 struct pci_incoming_message *new_msg;
948 struct pci_bus_relations *bus_rel;
949 struct pci_dev_incoming *dev_msg;
950 struct hv_pci_dev *hpdev;
951
952 buffer = sc->rx_buf;
953 do {
954 struct vmbus_chanpkt_hdr *pkt = buffer;
955 uint32_t bytes_rxed;
956 int ret;
957
958 bytes_rxed = bufferlen;
959 ret = vmbus_chan_recv_pkt(chan, pkt, &bytes_rxed);
960
961 if (ret == ENOBUFS) {
962 /* Handle large packet */
963 if (bufferlen > PCIB_PACKET_SIZE) {
964 free(buffer, M_DEVBUF);
965 buffer = NULL;
966 }
967
968 /* alloc new buffer */
969 buffer = malloc(bytes_rxed, M_DEVBUF, M_WAITOK | M_ZERO);
970 bufferlen = bytes_rxed;
971
972 continue;
973 }
974
975 if (ret != 0) {
976 /* ignore EIO or EAGAIN */
977 break;
978 }
979
980 if (bytes_rxed <= sizeof(struct pci_response))
981 continue;
982
983 switch (pkt->cph_type) {
984 case VMBUS_CHANPKT_TYPE_COMP:
985 comp_packet =
986 (struct pci_packet *)(uintptr_t)pkt->cph_xactid;
987 response = (struct pci_response *)pkt;
988 comp_packet->completion_func(comp_packet->compl_ctxt,
989 response, bytes_rxed);
990 break;
991 case VMBUS_CHANPKT_TYPE_INBAND:
992 new_msg = (struct pci_incoming_message *)buffer;
993
994 switch (new_msg->message_type.type) {
995 case PCI_BUS_RELATIONS:
996 bus_rel = (struct pci_bus_relations *)buffer;
997
998 if (bus_rel->device_count == 0)
999 break;
1000
1001 if (bytes_rxed <
1002 offsetof(struct pci_bus_relations, func) +
1003 (sizeof(struct pci_func_desc) *
1004 (bus_rel->device_count)))
1005 break;
1006
1007 hv_pci_devices_present(hbus, bus_rel);
1008 break;
1009
1010 case PCI_EJECT:
1011 dev_msg = (struct pci_dev_incoming *)buffer;
1012 hpdev = get_pcichild_wslot(hbus,
1013 dev_msg->wslot.val);
1014
1015 if (hpdev)
1016 hv_pci_eject_device(hpdev);
1017
1018 break;
1019 default:
1020 printf("vmbus_pcib: Unknown msg type 0x%x\n",
1021 new_msg->message_type.type);
1022 break;
1023 }
1024 break;
1025 default:
1026 printf("vmbus_pcib: Unknown VMBus msg type %hd\n",
1027 pkt->cph_type);
1028 break;
1029 }
1030 } while (1);
1031
1032 if (bufferlen > PCIB_PACKET_SIZE)
1033 free(buffer, M_DEVBUF);
1034 }
1035
1036 static int
hv_pci_protocol_negotiation(struct hv_pcibus * hbus)1037 hv_pci_protocol_negotiation(struct hv_pcibus *hbus)
1038 {
1039 struct pci_version_request *version_req;
1040 struct hv_pci_compl comp_pkt;
1041 struct {
1042 struct pci_packet pkt;
1043 uint8_t buffer[sizeof(struct pci_version_request)];
1044 } ctxt;
1045 int ret;
1046
1047 init_completion(&comp_pkt.host_event);
1048
1049 ctxt.pkt.completion_func = hv_pci_generic_compl;
1050 ctxt.pkt.compl_ctxt = &comp_pkt;
1051 version_req = (struct pci_version_request *)&ctxt.pkt.message;
1052 version_req->message_type.type = PCI_QUERY_PROTOCOL_VERSION;
1053 version_req->protocol_version = PCI_PROTOCOL_VERSION_CURRENT;
1054 version_req->is_last_attempt = 1;
1055
1056 ret = vmbus_chan_send(hbus->sc->chan, VMBUS_CHANPKT_TYPE_INBAND,
1057 VMBUS_CHANPKT_FLAG_RC, version_req, sizeof(*version_req),
1058 (uint64_t)(uintptr_t)&ctxt.pkt);
1059 if (!ret)
1060 ret = wait_for_response(hbus, &comp_pkt.host_event);
1061
1062 if (ret) {
1063 device_printf(hbus->pcib,
1064 "vmbus_pcib failed to request version: %d\n",
1065 ret);
1066 goto out;
1067 }
1068
1069 if (comp_pkt.completion_status < 0) {
1070 device_printf(hbus->pcib,
1071 "vmbus_pcib version negotiation failed: %x\n",
1072 comp_pkt.completion_status);
1073 ret = EPROTO;
1074 } else {
1075 ret = 0;
1076 }
1077 out:
1078 free_completion(&comp_pkt.host_event);
1079 return (ret);
1080 }
1081
1082 /* Ask the host to send along the list of child devices */
1083 static int
hv_pci_query_relations(struct hv_pcibus * hbus)1084 hv_pci_query_relations(struct hv_pcibus *hbus)
1085 {
1086 struct pci_message message;
1087 int ret;
1088
1089 message.type = PCI_QUERY_BUS_RELATIONS;
1090 ret = vmbus_chan_send(hbus->sc->chan, VMBUS_CHANPKT_TYPE_INBAND, 0,
1091 &message, sizeof(message), 0);
1092 return (ret);
1093 }
1094
1095 static int
hv_pci_enter_d0(struct hv_pcibus * hbus)1096 hv_pci_enter_d0(struct hv_pcibus *hbus)
1097 {
1098 struct pci_bus_d0_entry *d0_entry;
1099 struct hv_pci_compl comp_pkt;
1100 struct {
1101 struct pci_packet pkt;
1102 uint8_t buffer[sizeof(struct pci_bus_d0_entry)];
1103 } ctxt;
1104 int ret;
1105
1106 /*
1107 * Tell the host that the bus is ready to use, and moved into the
1108 * powered-on state. This includes telling the host which region
1109 * of memory-mapped I/O space has been chosen for configuration space
1110 * access.
1111 */
1112 init_completion(&comp_pkt.host_event);
1113
1114 ctxt.pkt.completion_func = hv_pci_generic_compl;
1115 ctxt.pkt.compl_ctxt = &comp_pkt;
1116
1117 d0_entry = (struct pci_bus_d0_entry *)&ctxt.pkt.message;
1118 memset(d0_entry, 0, sizeof(*d0_entry));
1119 d0_entry->message_type.type = PCI_BUS_D0ENTRY;
1120 d0_entry->mmio_base = rman_get_start(hbus->cfg_res);
1121
1122 ret = vmbus_chan_send(hbus->sc->chan, VMBUS_CHANPKT_TYPE_INBAND,
1123 VMBUS_CHANPKT_FLAG_RC, d0_entry, sizeof(*d0_entry),
1124 (uint64_t)(uintptr_t)&ctxt.pkt);
1125 if (!ret)
1126 ret = wait_for_response(hbus, &comp_pkt.host_event);
1127
1128 if (ret)
1129 goto out;
1130
1131 if (comp_pkt.completion_status < 0) {
1132 device_printf(hbus->pcib, "vmbus_pcib failed to enable D0\n");
1133 ret = EPROTO;
1134 } else {
1135 ret = 0;
1136 }
1137
1138 out:
1139 free_completion(&comp_pkt.host_event);
1140 return (ret);
1141 }
1142
1143 /*
1144 * It looks this is only needed by Windows VM, but let's send the message too
1145 * just to make the host happy.
1146 */
1147 static int
hv_send_resources_allocated(struct hv_pcibus * hbus)1148 hv_send_resources_allocated(struct hv_pcibus *hbus)
1149 {
1150 struct pci_resources_assigned *res_assigned;
1151 struct hv_pci_compl comp_pkt;
1152 struct hv_pci_dev *hpdev;
1153 struct pci_packet *pkt;
1154 uint32_t wslot;
1155 int ret = 0;
1156
1157 pkt = malloc(sizeof(*pkt) + sizeof(*res_assigned),
1158 M_DEVBUF, M_WAITOK | M_ZERO);
1159
1160 for (wslot = 0; wslot < 256; wslot++) {
1161 hpdev = get_pcichild_wslot(hbus, wslot);
1162 if (!hpdev)
1163 continue;
1164
1165 init_completion(&comp_pkt.host_event);
1166
1167 memset(pkt, 0, sizeof(*pkt) + sizeof(*res_assigned));
1168 pkt->completion_func = hv_pci_generic_compl;
1169 pkt->compl_ctxt = &comp_pkt;
1170
1171 res_assigned = (struct pci_resources_assigned *)&pkt->message;
1172 res_assigned->message_type.type = PCI_RESOURCES_ASSIGNED;
1173 res_assigned->wslot.val = hpdev->desc.wslot.val;
1174
1175 ret = vmbus_chan_send(hbus->sc->chan,
1176 VMBUS_CHANPKT_TYPE_INBAND, VMBUS_CHANPKT_FLAG_RC,
1177 &pkt->message, sizeof(*res_assigned),
1178 (uint64_t)(uintptr_t)pkt);
1179 if (!ret)
1180 ret = wait_for_response(hbus, &comp_pkt.host_event);
1181
1182 free_completion(&comp_pkt.host_event);
1183
1184 if (ret)
1185 break;
1186
1187 if (comp_pkt.completion_status < 0) {
1188 ret = EPROTO;
1189 device_printf(hbus->pcib,
1190 "failed to send PCI_RESOURCES_ASSIGNED\n");
1191 break;
1192 }
1193 }
1194
1195 free(pkt, M_DEVBUF);
1196 return (ret);
1197 }
1198
1199 static int
hv_send_resources_released(struct hv_pcibus * hbus)1200 hv_send_resources_released(struct hv_pcibus *hbus)
1201 {
1202 struct pci_child_message pkt;
1203 struct hv_pci_dev *hpdev;
1204 uint32_t wslot;
1205 int ret;
1206
1207 for (wslot = 0; wslot < 256; wslot++) {
1208 hpdev = get_pcichild_wslot(hbus, wslot);
1209 if (!hpdev)
1210 continue;
1211
1212 pkt.message_type.type = PCI_RESOURCES_RELEASED;
1213 pkt.wslot.val = hpdev->desc.wslot.val;
1214
1215 ret = vmbus_chan_send(hbus->sc->chan,
1216 VMBUS_CHANPKT_TYPE_INBAND, 0, &pkt, sizeof(pkt), 0);
1217 if (ret)
1218 return (ret);
1219 }
1220
1221 return (0);
1222 }
1223
1224 #define hv_cfg_read(x, s) \
1225 static inline uint##x##_t hv_cfg_read_##s(struct hv_pcibus *bus, \
1226 bus_size_t offset) \
1227 { \
1228 return (bus_read_##s(bus->cfg_res, offset)); \
1229 }
1230
1231 #define hv_cfg_write(x, s) \
1232 static inline void hv_cfg_write_##s(struct hv_pcibus *bus, \
1233 bus_size_t offset, uint##x##_t val) \
1234 { \
1235 return (bus_write_##s(bus->cfg_res, offset, val)); \
1236 }
1237
1238 hv_cfg_read(8, 1)
1239 hv_cfg_read(16, 2)
1240 hv_cfg_read(32, 4)
1241
1242 hv_cfg_write(8, 1)
1243 hv_cfg_write(16, 2)
1244 hv_cfg_write(32, 4)
1245
1246 static void
_hv_pcifront_read_config(struct hv_pci_dev * hpdev,int where,int size,uint32_t * val)1247 _hv_pcifront_read_config(struct hv_pci_dev *hpdev, int where, int size,
1248 uint32_t *val)
1249 {
1250 struct hv_pcibus *hbus = hpdev->hbus;
1251 bus_size_t addr = CFG_PAGE_OFFSET + where;
1252
1253 /*
1254 * If the attempt is to read the IDs or the ROM BAR, simulate that.
1255 */
1256 if (where + size <= PCIR_COMMAND) {
1257 memcpy(val, ((uint8_t *)&hpdev->desc.v_id) + where, size);
1258 } else if (where >= PCIR_REVID && where + size <=
1259 PCIR_CACHELNSZ) {
1260 memcpy(val, ((uint8_t *)&hpdev->desc.rev) + where -
1261 PCIR_REVID, size);
1262 } else if (where >= PCIR_SUBVEND_0 && where + size <=
1263 PCIR_BIOS) {
1264 memcpy(val, (uint8_t *)&hpdev->desc.subsystem_id + where -
1265 PCIR_SUBVEND_0, size);
1266 } else if (where >= PCIR_BIOS && where + size <=
1267 PCIR_CAP_PTR) {
1268 /* ROM BARs are unimplemented */
1269 *val = 0;
1270 } else if ((where >= PCIR_INTLINE && where + size <=
1271 PCIR_INTPIN) ||(where == PCIR_INTPIN && size == 1)) {
1272 /*
1273 * Interrupt Line and Interrupt PIN are hard-wired to zero
1274 * because this front-end only supports message-signaled
1275 * interrupts.
1276 */
1277 *val = 0;
1278 } else if (where + size <= CFG_PAGE_SIZE) {
1279 mtx_lock(&hbus->config_lock);
1280
1281 /* Choose the function to be read. */
1282 hv_cfg_write_4(hbus, 0, hpdev->desc.wslot.val);
1283
1284 /* Make sure the function was chosen before we start reading.*/
1285 mb();
1286
1287 /* Read from that function's config space. */
1288 switch (size) {
1289 case 1:
1290 *((uint8_t *)val) = hv_cfg_read_1(hbus, addr);
1291 break;
1292 case 2:
1293 *((uint16_t *)val) = hv_cfg_read_2(hbus, addr);
1294 break;
1295 default:
1296 *((uint32_t *)val) = hv_cfg_read_4(hbus, addr);
1297 break;
1298 }
1299 /*
1300 * Make sure the write was done before we release the lock,
1301 * allowing consecutive reads/writes.
1302 */
1303 mb();
1304
1305 mtx_unlock(&hbus->config_lock);
1306 } else {
1307 /* Invalid config read: it's unlikely to reach here. */
1308 memset(val, 0, size);
1309 }
1310 }
1311
1312 static void
_hv_pcifront_write_config(struct hv_pci_dev * hpdev,int where,int size,uint32_t val)1313 _hv_pcifront_write_config(struct hv_pci_dev *hpdev, int where, int size,
1314 uint32_t val)
1315 {
1316 struct hv_pcibus *hbus = hpdev->hbus;
1317 bus_size_t addr = CFG_PAGE_OFFSET + where;
1318
1319 /* SSIDs and ROM BARs are read-only */
1320 if (where >= PCIR_SUBVEND_0 && where + size <= PCIR_CAP_PTR)
1321 return;
1322
1323 if (where >= PCIR_COMMAND && where + size <= CFG_PAGE_SIZE) {
1324 mtx_lock(&hbus->config_lock);
1325
1326 /* Choose the function to be written. */
1327 hv_cfg_write_4(hbus, 0, hpdev->desc.wslot.val);
1328
1329 /* Make sure the function was chosen before we start writing.*/
1330 wmb();
1331
1332 /* Write to that function's config space. */
1333 switch (size) {
1334 case 1:
1335 hv_cfg_write_1(hbus, addr, (uint8_t)val);
1336 break;
1337 case 2:
1338 hv_cfg_write_2(hbus, addr, (uint16_t)val);
1339 break;
1340 default:
1341 hv_cfg_write_4(hbus, addr, (uint32_t)val);
1342 break;
1343 }
1344
1345 /*
1346 * Make sure the write was done before we release the lock,
1347 * allowing consecutive reads/writes.
1348 */
1349 mb();
1350
1351 mtx_unlock(&hbus->config_lock);
1352 } else {
1353 /* Invalid config write: it's unlikely to reach here. */
1354 return;
1355 }
1356 }
1357
1358 /*
1359 * The vPCI in some Hyper-V releases do not initialize the last 4
1360 * bit of BAR registers. This could result weird problems causing PCI
1361 * code fail to configure BAR correctly.
1362 *
1363 * Just write all 1's to those BARs whose probed values are not zero.
1364 * This seems to make the Hyper-V vPCI and pci_write_bar() to cooperate
1365 * correctly.
1366 */
1367
1368 static void
vmbus_pcib_prepopulate_bars(struct hv_pcibus * hbus)1369 vmbus_pcib_prepopulate_bars(struct hv_pcibus *hbus)
1370 {
1371 struct hv_pci_dev *hpdev;
1372 int i;
1373
1374 mtx_lock(&hbus->device_list_lock);
1375 TAILQ_FOREACH(hpdev, &hbus->children, link) {
1376 for (i = 0; i < 6; i++) {
1377 /* Ignore empty bar */
1378 if (hpdev->probed_bar[i] == 0)
1379 continue;
1380
1381 uint32_t bar_val = 0;
1382
1383 _hv_pcifront_read_config(hpdev, PCIR_BAR(i),
1384 4, &bar_val);
1385
1386 if (hpdev->probed_bar[i] != bar_val) {
1387 if (bootverbose)
1388 printf("vmbus_pcib: initialize bar %d "
1389 "by writing all 1s\n", i);
1390
1391 _hv_pcifront_write_config(hpdev, PCIR_BAR(i),
1392 4, 0xffffffff);
1393 }
1394 }
1395 }
1396 mtx_unlock(&hbus->device_list_lock);
1397 }
1398
1399 static void
vmbus_pcib_set_detaching(void * arg,int pending __unused)1400 vmbus_pcib_set_detaching(void *arg, int pending __unused)
1401 {
1402 struct hv_pcibus *hbus = arg;
1403
1404 atomic_set_int(&hbus->detaching, 1);
1405 }
1406
1407 static void
vmbus_pcib_pre_detach(struct hv_pcibus * hbus)1408 vmbus_pcib_pre_detach(struct hv_pcibus *hbus)
1409 {
1410 struct task task;
1411
1412 TASK_INIT(&task, 0, vmbus_pcib_set_detaching, hbus);
1413
1414 /*
1415 * Make sure the channel callback won't push any possible new
1416 * PCI_BUS_RELATIONS and PCI_EJECT tasks to sc->taskq.
1417 */
1418 vmbus_chan_run_task(hbus->sc->chan, &task);
1419
1420 taskqueue_drain_all(hbus->sc->taskq);
1421 }
1422
1423
1424 /*
1425 * Standard probe entry point.
1426 *
1427 */
1428 static int
vmbus_pcib_probe(device_t dev)1429 vmbus_pcib_probe(device_t dev)
1430 {
1431 if (VMBUS_PROBE_GUID(device_get_parent(dev), dev,
1432 &g_pass_through_dev_type) == 0) {
1433 device_set_desc(dev, "Hyper-V PCI Express Pass Through");
1434 return (BUS_PROBE_DEFAULT);
1435 }
1436 return (ENXIO);
1437 }
1438
1439 /*
1440 * Standard attach entry point.
1441 *
1442 */
1443 static int
vmbus_pcib_attach(device_t dev)1444 vmbus_pcib_attach(device_t dev)
1445 {
1446 const int pci_ring_size = (4 * PAGE_SIZE);
1447 const struct hyperv_guid *inst_guid;
1448 struct vmbus_channel *channel;
1449 struct vmbus_pcib_softc *sc;
1450 struct hv_pcibus *hbus;
1451 int rid = 0;
1452 int ret;
1453
1454 hbus = malloc(sizeof(*hbus), M_DEVBUF, M_WAITOK | M_ZERO);
1455 hbus->pcib = dev;
1456
1457 channel = vmbus_get_channel(dev);
1458 inst_guid = vmbus_chan_guid_inst(channel);
1459 hbus->pci_domain = inst_guid->hv_guid[9] |
1460 (inst_guid->hv_guid[8] << 8);
1461
1462 mtx_init(&hbus->config_lock, "hbcfg", NULL, MTX_DEF);
1463 mtx_init(&hbus->device_list_lock, "hbdl", NULL, MTX_DEF);
1464 TAILQ_INIT(&hbus->children);
1465 TAILQ_INIT(&hbus->dr_list);
1466
1467 hbus->cfg_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1468 0, RM_MAX_END, PCI_CONFIG_MMIO_LENGTH,
1469 RF_ACTIVE | rman_make_alignment_flags(PAGE_SIZE));
1470
1471 if (!hbus->cfg_res) {
1472 device_printf(dev, "failed to get resource for cfg window\n");
1473 ret = ENXIO;
1474 goto free_bus;
1475 }
1476
1477 sc = device_get_softc(dev);
1478 sc->chan = channel;
1479 sc->rx_buf = malloc(PCIB_PACKET_SIZE, M_DEVBUF, M_WAITOK | M_ZERO);
1480 sc->hbus = hbus;
1481
1482 /*
1483 * The taskq is used to handle PCI_BUS_RELATIONS and PCI_EJECT
1484 * messages. NB: we can't handle the messages in the channel callback
1485 * directly, because the message handlers need to send new messages
1486 * to the host and waits for the host's completion messages, which
1487 * must also be handled by the channel callback.
1488 */
1489 sc->taskq = taskqueue_create("vmbus_pcib_tq", M_WAITOK,
1490 taskqueue_thread_enqueue, &sc->taskq);
1491 taskqueue_start_threads(&sc->taskq, 1, PI_NET, "vmbus_pcib_tq");
1492
1493 hbus->sc = sc;
1494
1495 init_completion(&hbus->query_completion);
1496 hbus->query_comp = &hbus->query_completion;
1497
1498 ret = vmbus_chan_open(sc->chan, pci_ring_size, pci_ring_size,
1499 NULL, 0, vmbus_pcib_on_channel_callback, sc);
1500 if (ret)
1501 goto free_res;
1502
1503 ret = hv_pci_protocol_negotiation(hbus);
1504 if (ret)
1505 goto vmbus_close;
1506
1507 ret = hv_pci_query_relations(hbus);
1508 if (!ret)
1509 ret = wait_for_response(hbus, hbus->query_comp);
1510
1511 if (ret)
1512 goto vmbus_close;
1513
1514 ret = hv_pci_enter_d0(hbus);
1515 if (ret)
1516 goto vmbus_close;
1517
1518 ret = hv_send_resources_allocated(hbus);
1519 if (ret)
1520 goto vmbus_close;
1521
1522 vmbus_pcib_prepopulate_bars(hbus);
1523
1524 hbus->pci_bus = device_add_child(dev, "pci", -1);
1525 if (!hbus->pci_bus) {
1526 device_printf(dev, "failed to create pci bus\n");
1527 ret = ENXIO;
1528 goto vmbus_close;
1529 }
1530
1531 bus_generic_attach(dev);
1532
1533 hbus->state = hv_pcibus_installed;
1534
1535 return (0);
1536
1537 vmbus_close:
1538 vmbus_pcib_pre_detach(hbus);
1539 vmbus_chan_close(sc->chan);
1540 free_res:
1541 taskqueue_free(sc->taskq);
1542 free_completion(&hbus->query_completion);
1543 free(sc->rx_buf, M_DEVBUF);
1544 bus_release_resource(dev, SYS_RES_MEMORY, 0, hbus->cfg_res);
1545 free_bus:
1546 mtx_destroy(&hbus->device_list_lock);
1547 mtx_destroy(&hbus->config_lock);
1548 free(hbus, M_DEVBUF);
1549 return (ret);
1550 }
1551
1552 /*
1553 * Standard detach entry point
1554 */
1555 static int
vmbus_pcib_detach(device_t dev)1556 vmbus_pcib_detach(device_t dev)
1557 {
1558 struct vmbus_pcib_softc *sc = device_get_softc(dev);
1559 struct hv_pcibus *hbus = sc->hbus;
1560 struct pci_message teardown_packet;
1561 struct pci_bus_relations relations;
1562 int ret;
1563
1564 vmbus_pcib_pre_detach(hbus);
1565
1566 if (hbus->state == hv_pcibus_installed)
1567 bus_generic_detach(dev);
1568
1569 /* Delete any children which might still exist. */
1570 memset(&relations, 0, sizeof(relations));
1571 hv_pci_devices_present(hbus, &relations);
1572
1573 ret = hv_send_resources_released(hbus);
1574 if (ret)
1575 device_printf(dev, "failed to send PCI_RESOURCES_RELEASED\n");
1576
1577 teardown_packet.type = PCI_BUS_D0EXIT;
1578 ret = vmbus_chan_send(sc->chan, VMBUS_CHANPKT_TYPE_INBAND, 0,
1579 &teardown_packet, sizeof(struct pci_message), 0);
1580 if (ret)
1581 device_printf(dev, "failed to send PCI_BUS_D0EXIT\n");
1582
1583 taskqueue_drain_all(hbus->sc->taskq);
1584 vmbus_chan_close(sc->chan);
1585 taskqueue_free(sc->taskq);
1586
1587 free_completion(&hbus->query_completion);
1588 free(sc->rx_buf, M_DEVBUF);
1589 bus_release_resource(dev, SYS_RES_MEMORY, 0, hbus->cfg_res);
1590
1591 mtx_destroy(&hbus->device_list_lock);
1592 mtx_destroy(&hbus->config_lock);
1593 free(hbus, M_DEVBUF);
1594
1595 return (0);
1596 }
1597
1598 static int
vmbus_pcib_read_ivar(device_t dev,device_t child,int which,uintptr_t * val)1599 vmbus_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *val)
1600 {
1601 struct vmbus_pcib_softc *sc = device_get_softc(dev);
1602
1603 switch (which) {
1604 case PCIB_IVAR_DOMAIN:
1605 *val = sc->hbus->pci_domain;
1606 return (0);
1607
1608 case PCIB_IVAR_BUS:
1609 /* There is only bus 0. */
1610 *val = 0;
1611 return (0);
1612 }
1613 return (ENOENT);
1614 }
1615
1616 static int
vmbus_pcib_write_ivar(device_t dev,device_t child,int which,uintptr_t val)1617 vmbus_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t val)
1618 {
1619 return (ENOENT);
1620 }
1621
1622 static struct resource *
vmbus_pcib_alloc_resource(device_t dev,device_t child,int type,int * rid,rman_res_t start,rman_res_t end,rman_res_t count,u_int flags)1623 vmbus_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
1624 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
1625 {
1626 unsigned int bar_no;
1627 struct hv_pci_dev *hpdev;
1628 struct vmbus_pcib_softc *sc = device_get_softc(dev);
1629 struct resource *res;
1630 unsigned int devfn;
1631
1632 if (type == PCI_RES_BUS)
1633 return (pci_domain_alloc_bus(sc->hbus->pci_domain, child, rid,
1634 start, end, count, flags));
1635
1636 /* Devices with port I/O BAR are not supported. */
1637 if (type == SYS_RES_IOPORT)
1638 return (NULL);
1639
1640 if (type == SYS_RES_MEMORY) {
1641 devfn = PCI_DEVFN(pci_get_slot(child),
1642 pci_get_function(child));
1643 hpdev = get_pcichild_wslot(sc->hbus, devfn_to_wslot(devfn));
1644 if (!hpdev)
1645 return (NULL);
1646
1647 bar_no = PCI_RID2BAR(*rid);
1648 if (bar_no >= MAX_NUM_BARS)
1649 return (NULL);
1650
1651 /* Make sure a 32-bit BAR gets a 32-bit address */
1652 if (!(hpdev->probed_bar[bar_no] & PCIM_BAR_MEM_64))
1653 end = ulmin(end, 0xFFFFFFFF);
1654 }
1655
1656 res = bus_generic_alloc_resource(dev, child, type, rid,
1657 start, end, count, flags);
1658 /*
1659 * If this is a request for a specific range, assume it is
1660 * correct and pass it up to the parent.
1661 */
1662 if (res == NULL && start + count - 1 == end)
1663 res = bus_generic_alloc_resource(dev, child, type, rid,
1664 start, end, count, flags);
1665 return (res);
1666 }
1667
1668 static int
vmbus_pcib_release_resource(device_t dev,device_t child,int type,int rid,struct resource * r)1669 vmbus_pcib_release_resource(device_t dev, device_t child, int type, int rid,
1670 struct resource *r)
1671 {
1672 struct vmbus_pcib_softc *sc = device_get_softc(dev);
1673
1674 if (type == PCI_RES_BUS)
1675 return (pci_domain_release_bus(sc->hbus->pci_domain, child,
1676 rid, r));
1677
1678 if (type == SYS_RES_IOPORT)
1679 return (EINVAL);
1680
1681 return (bus_generic_release_resource(dev, child, type, rid, r));
1682 }
1683
1684 #if __FreeBSD_version >= 1100000
1685 static int
vmbus_pcib_get_cpus(device_t pcib,device_t dev,enum cpu_sets op,size_t setsize,cpuset_t * cpuset)1686 vmbus_pcib_get_cpus(device_t pcib, device_t dev, enum cpu_sets op,
1687 size_t setsize, cpuset_t *cpuset)
1688 {
1689 return (bus_get_cpus(pcib, op, setsize, cpuset));
1690 }
1691 #endif
1692
1693 static uint32_t
vmbus_pcib_read_config(device_t dev,u_int bus,u_int slot,u_int func,u_int reg,int bytes)1694 vmbus_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func,
1695 u_int reg, int bytes)
1696 {
1697 struct vmbus_pcib_softc *sc = device_get_softc(dev);
1698 struct hv_pci_dev *hpdev;
1699 unsigned int devfn = PCI_DEVFN(slot, func);
1700 uint32_t data = 0;
1701
1702 KASSERT(bus == 0, ("bus should be 0, but is %u", bus));
1703
1704 hpdev = get_pcichild_wslot(sc->hbus, devfn_to_wslot(devfn));
1705 if (!hpdev)
1706 return (~0);
1707
1708 _hv_pcifront_read_config(hpdev, reg, bytes, &data);
1709
1710 return (data);
1711 }
1712
1713 static void
vmbus_pcib_write_config(device_t dev,u_int bus,u_int slot,u_int func,u_int reg,uint32_t data,int bytes)1714 vmbus_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func,
1715 u_int reg, uint32_t data, int bytes)
1716 {
1717 struct vmbus_pcib_softc *sc = device_get_softc(dev);
1718 struct hv_pci_dev *hpdev;
1719 unsigned int devfn = PCI_DEVFN(slot, func);
1720
1721 KASSERT(bus == 0, ("bus should be 0, but is %u", bus));
1722
1723 hpdev = get_pcichild_wslot(sc->hbus, devfn_to_wslot(devfn));
1724 if (!hpdev)
1725 return;
1726
1727 _hv_pcifront_write_config(hpdev, reg, bytes, data);
1728 }
1729
1730 static int
vmbus_pcib_route_intr(device_t pcib,device_t dev,int pin)1731 vmbus_pcib_route_intr(device_t pcib, device_t dev, int pin)
1732 {
1733 /* We only support MSI/MSI-X and don't support INTx interrupt. */
1734 return (PCI_INVALID_IRQ);
1735 }
1736
1737 static int
vmbus_pcib_alloc_msi(device_t pcib,device_t dev,int count,int maxcount,int * irqs)1738 vmbus_pcib_alloc_msi(device_t pcib, device_t dev, int count,
1739 int maxcount, int *irqs)
1740 {
1741 return (PCIB_ALLOC_MSI(device_get_parent(pcib), dev, count, maxcount,
1742 irqs));
1743 }
1744
1745 static int
vmbus_pcib_release_msi(device_t pcib,device_t dev,int count,int * irqs)1746 vmbus_pcib_release_msi(device_t pcib, device_t dev, int count, int *irqs)
1747 {
1748 return (PCIB_RELEASE_MSI(device_get_parent(pcib), dev, count, irqs));
1749 }
1750
1751 static int
vmbus_pcib_alloc_msix(device_t pcib,device_t dev,int * irq)1752 vmbus_pcib_alloc_msix(device_t pcib, device_t dev, int *irq)
1753 {
1754 return (PCIB_ALLOC_MSIX(device_get_parent(pcib), dev, irq));
1755 }
1756
1757 static int
vmbus_pcib_release_msix(device_t pcib,device_t dev,int irq)1758 vmbus_pcib_release_msix(device_t pcib, device_t dev, int irq)
1759 {
1760 return (PCIB_RELEASE_MSIX(device_get_parent(pcib), dev, irq));
1761 }
1762
1763 #define MSI_INTEL_ADDR_DEST 0x000ff000
1764 #define MSI_INTEL_DATA_INTVEC IOART_INTVEC /* Interrupt vector. */
1765 #define MSI_INTEL_DATA_DELFIXED IOART_DELFIXED
1766
1767 static int
vmbus_pcib_map_msi(device_t pcib,device_t child,int irq,uint64_t * addr,uint32_t * data)1768 vmbus_pcib_map_msi(device_t pcib, device_t child, int irq,
1769 uint64_t *addr, uint32_t *data)
1770 {
1771 unsigned int devfn;
1772 struct hv_pci_dev *hpdev;
1773
1774 uint64_t v_addr;
1775 uint32_t v_data;
1776 struct hv_irq_desc *hid, *tmp_hid;
1777 unsigned int cpu, vcpu_id;
1778 unsigned int vector;
1779
1780 struct vmbus_pcib_softc *sc = device_get_softc(pcib);
1781 struct pci_create_interrupt *int_pkt;
1782 struct compose_comp_ctxt comp;
1783 struct {
1784 struct pci_packet pkt;
1785 uint8_t buffer[sizeof(struct pci_create_interrupt)];
1786 } ctxt;
1787
1788 int ret;
1789
1790 devfn = PCI_DEVFN(pci_get_slot(child), pci_get_function(child));
1791 hpdev = get_pcichild_wslot(sc->hbus, devfn_to_wslot(devfn));
1792 if (!hpdev)
1793 return (ENOENT);
1794
1795 ret = PCIB_MAP_MSI(device_get_parent(pcib), child, irq,
1796 &v_addr, &v_data);
1797 if (ret)
1798 return (ret);
1799
1800 TAILQ_FOREACH_SAFE(hid, &hpdev->irq_desc_list, link, tmp_hid) {
1801 if (hid->irq == irq) {
1802 TAILQ_REMOVE(&hpdev->irq_desc_list, hid, link);
1803 hv_int_desc_free(hpdev, hid);
1804 break;
1805 }
1806 }
1807
1808 cpu = apic_cpuid((v_addr & MSI_INTEL_ADDR_DEST) >> 12);
1809 vcpu_id = VMBUS_GET_VCPU_ID(device_get_parent(pcib), pcib, cpu);
1810 vector = v_data & MSI_INTEL_DATA_INTVEC;
1811
1812 if (vcpu_id > 63) {
1813 /* We only support vcpu_id < 64 on current vPCI version*/
1814 device_printf(pcib,
1815 "Error: vcpu_id %u overflowed\n", vcpu_id);
1816 return (ENODEV);
1817 }
1818
1819 init_completion(&comp.comp_pkt.host_event);
1820
1821 memset(&ctxt, 0, sizeof(ctxt));
1822 ctxt.pkt.completion_func = hv_pci_compose_compl;
1823 ctxt.pkt.compl_ctxt = ∁
1824
1825 int_pkt = (struct pci_create_interrupt *)&ctxt.pkt.message;
1826 int_pkt->message_type.type = PCI_CREATE_INTERRUPT_MESSAGE;
1827 int_pkt->wslot.val = hpdev->desc.wslot.val;
1828 int_pkt->int_desc.vector = vector;
1829 int_pkt->int_desc.vector_count = 1;
1830 int_pkt->int_desc.delivery_mode = MSI_INTEL_DATA_DELFIXED;
1831 int_pkt->int_desc.cpu_mask = 1ULL << vcpu_id;
1832
1833 ret = vmbus_chan_send(sc->chan, VMBUS_CHANPKT_TYPE_INBAND,
1834 VMBUS_CHANPKT_FLAG_RC, int_pkt, sizeof(*int_pkt),
1835 (uint64_t)(uintptr_t)&ctxt.pkt);
1836 if (ret) {
1837 free_completion(&comp.comp_pkt.host_event);
1838 return (ret);
1839 }
1840
1841 wait_for_completion(&comp.comp_pkt.host_event);
1842 free_completion(&comp.comp_pkt.host_event);
1843
1844 if (comp.comp_pkt.completion_status < 0)
1845 return (EPROTO);
1846
1847 *addr = comp.int_desc.address;
1848 *data = comp.int_desc.data;
1849
1850 hid = malloc(sizeof(struct hv_irq_desc), M_DEVBUF, M_WAITOK | M_ZERO);
1851 hid->irq = irq;
1852 hid->desc = comp.int_desc;
1853 TAILQ_INSERT_TAIL(&hpdev->irq_desc_list, hid, link);
1854
1855 return (0);
1856 }
1857
1858 static device_method_t vmbus_pcib_methods[] = {
1859 /* Device interface */
1860 DEVMETHOD(device_probe, vmbus_pcib_probe),
1861 DEVMETHOD(device_attach, vmbus_pcib_attach),
1862 DEVMETHOD(device_detach, vmbus_pcib_detach),
1863 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1864 DEVMETHOD(device_suspend, bus_generic_suspend),
1865 DEVMETHOD(device_resume, bus_generic_resume),
1866
1867 /* Bus interface */
1868 DEVMETHOD(bus_read_ivar, vmbus_pcib_read_ivar),
1869 DEVMETHOD(bus_write_ivar, vmbus_pcib_write_ivar),
1870 DEVMETHOD(bus_alloc_resource, vmbus_pcib_alloc_resource),
1871 DEVMETHOD(bus_release_resource, vmbus_pcib_release_resource),
1872 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
1873 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
1874 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
1875 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
1876 #if __FreeBSD_version >= 1100000
1877 DEVMETHOD(bus_get_cpus, vmbus_pcib_get_cpus),
1878 #endif
1879
1880 /* pcib interface */
1881 DEVMETHOD(pcib_maxslots, pcib_maxslots),
1882 DEVMETHOD(pcib_read_config, vmbus_pcib_read_config),
1883 DEVMETHOD(pcib_write_config, vmbus_pcib_write_config),
1884 DEVMETHOD(pcib_route_interrupt, vmbus_pcib_route_intr),
1885 DEVMETHOD(pcib_alloc_msi, vmbus_pcib_alloc_msi),
1886 DEVMETHOD(pcib_release_msi, vmbus_pcib_release_msi),
1887 DEVMETHOD(pcib_alloc_msix, vmbus_pcib_alloc_msix),
1888 DEVMETHOD(pcib_release_msix, vmbus_pcib_release_msix),
1889 DEVMETHOD(pcib_map_msi, vmbus_pcib_map_msi),
1890 DEVMETHOD(pcib_request_feature, pcib_request_feature_allow),
1891
1892 DEVMETHOD_END
1893 };
1894
1895 static devclass_t pcib_devclass;
1896
1897 DEFINE_CLASS_0(pcib, vmbus_pcib_driver, vmbus_pcib_methods,
1898 sizeof(struct vmbus_pcib_softc));
1899 DRIVER_MODULE(vmbus_pcib, vmbus, vmbus_pcib_driver, pcib_devclass, 0, 0);
1900 MODULE_DEPEND(vmbus_pcib, vmbus, 1, 1, 1);
1901 MODULE_DEPEND(vmbus_pcib, pci, 1, 1, 1);
1902
1903 #endif /* NEW_PCIB */
1904