1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2001-2024, Intel Corporation
5 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org>
6 * Copyright (c) 2024 Kevin Bowling <kbowling@FreeBSD.org>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 #include "if_em.h"
31 #include <sys/sbuf.h>
32 #include <machine/_inttypes.h>
33
34 #define em_mac_min e1000_82571
35 #define igb_mac_min e1000_82575
36
37 /*********************************************************************
38 * Driver version:
39 *********************************************************************/
40 static const char em_driver_version[] = "7.7.8-fbsd";
41 static const char igb_driver_version[] = "2.5.28-fbsd";
42
43 /*********************************************************************
44 * PCI Device ID Table
45 *
46 * Used by probe to select devices to load on
47 * Last field stores an index into e1000_strings
48 * Last entry must be all 0s
49 *
50 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index }
51 *********************************************************************/
52
53 static const pci_vendor_info_t em_vendor_info_array[] =
54 {
55 /* Intel(R) - lem-class legacy devices */
56 PVID(0x8086, E1000_DEV_ID_82540EM,
57 "Intel(R) Legacy PRO/1000 MT 82540EM"),
58 PVID(0x8086, E1000_DEV_ID_82540EM_LOM,
59 "Intel(R) Legacy PRO/1000 MT 82540EM (LOM)"),
60 PVID(0x8086, E1000_DEV_ID_82540EP,
61 "Intel(R) Legacy PRO/1000 MT 82540EP"),
62 PVID(0x8086, E1000_DEV_ID_82540EP_LOM,
63 "Intel(R) Legacy PRO/1000 MT 82540EP (LOM)"),
64 PVID(0x8086, E1000_DEV_ID_82540EP_LP,
65 "Intel(R) Legacy PRO/1000 MT 82540EP (Mobile)"),
66
67 PVID(0x8086, E1000_DEV_ID_82541EI,
68 "Intel(R) Legacy PRO/1000 MT 82541EI (Copper)"),
69 PVID(0x8086, E1000_DEV_ID_82541ER,
70 "Intel(R) Legacy PRO/1000 82541ER"),
71 PVID(0x8086, E1000_DEV_ID_82541ER_LOM,
72 "Intel(R) Legacy PRO/1000 MT 82541ER"),
73 PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE,
74 "Intel(R) Legacy PRO/1000 MT 82541EI (Mobile)"),
75 PVID(0x8086, E1000_DEV_ID_82541GI,
76 "Intel(R) Legacy PRO/1000 MT 82541GI"),
77 PVID(0x8086, E1000_DEV_ID_82541GI_LF,
78 "Intel(R) Legacy PRO/1000 GT 82541PI"),
79 PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE,
80 "Intel(R) Legacy PRO/1000 MT 82541GI (Mobile)"),
81
82 PVID(0x8086, E1000_DEV_ID_82542,
83 "Intel(R) Legacy PRO/1000 82542 (Fiber)"),
84
85 PVID(0x8086, E1000_DEV_ID_82543GC_FIBER,
86 "Intel(R) Legacy PRO/1000 F 82543GC (Fiber)"),
87 PVID(0x8086, E1000_DEV_ID_82543GC_COPPER,
88 "Intel(R) Legacy PRO/1000 T 82543GC (Copper)"),
89
90 PVID(0x8086, E1000_DEV_ID_82544EI_COPPER,
91 "Intel(R) Legacy PRO/1000 XT 82544EI (Copper)"),
92 PVID(0x8086, E1000_DEV_ID_82544EI_FIBER,
93 "Intel(R) Legacy PRO/1000 XF 82544EI (Fiber)"),
94 PVID(0x8086, E1000_DEV_ID_82544GC_COPPER,
95 "Intel(R) Legacy PRO/1000 T 82544GC (Copper)"),
96 PVID(0x8086, E1000_DEV_ID_82544GC_LOM,
97 "Intel(R) Legacy PRO/1000 XT 82544GC (LOM)"),
98
99 PVID(0x8086, E1000_DEV_ID_82545EM_COPPER,
100 "Intel(R) Legacy PRO/1000 MT 82545EM (Copper)"),
101 PVID(0x8086, E1000_DEV_ID_82545EM_FIBER,
102 "Intel(R) Legacy PRO/1000 MF 82545EM (Fiber)"),
103 PVID(0x8086, E1000_DEV_ID_82545GM_COPPER,
104 "Intel(R) Legacy PRO/1000 MT 82545GM (Copper)"),
105 PVID(0x8086, E1000_DEV_ID_82545GM_FIBER,
106 "Intel(R) Legacy PRO/1000 MF 82545GM (Fiber)"),
107 PVID(0x8086, E1000_DEV_ID_82545GM_SERDES,
108 "Intel(R) Legacy PRO/1000 MB 82545GM (SERDES)"),
109
110 PVID(0x8086, E1000_DEV_ID_82546EB_COPPER,
111 "Intel(R) Legacy PRO/1000 MT 82546EB (Copper)"),
112 PVID(0x8086, E1000_DEV_ID_82546EB_FIBER,
113 "Intel(R) Legacy PRO/1000 MF 82546EB (Fiber)"),
114 PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER,
115 "Intel(R) Legacy PRO/1000 MT 82546EB (Quad Copper"),
116 PVID(0x8086, E1000_DEV_ID_82546GB_COPPER,
117 "Intel(R) Legacy PRO/1000 MT 82546GB (Copper)"),
118 PVID(0x8086, E1000_DEV_ID_82546GB_FIBER,
119 "Intel(R) Legacy PRO/1000 MF 82546GB (Fiber)"),
120 PVID(0x8086, E1000_DEV_ID_82546GB_SERDES,
121 "Intel(R) Legacy PRO/1000 MB 82546GB (SERDES)"),
122 PVID(0x8086, E1000_DEV_ID_82546GB_PCIE,
123 "Intel(R) Legacy PRO/1000 P 82546GB (PCIe)"),
124 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER,
125 "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"),
126 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3,
127 "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"),
128
129 PVID(0x8086, E1000_DEV_ID_82547EI,
130 "Intel(R) Legacy PRO/1000 CT 82547EI"),
131 PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE,
132 "Intel(R) Legacy PRO/1000 CT 82547EI (Mobile)"),
133 PVID(0x8086, E1000_DEV_ID_82547GI,
134 "Intel(R) Legacy PRO/1000 CT 82547GI"),
135
136 /* Intel(R) - em-class devices */
137 PVID(0x8086, E1000_DEV_ID_82571EB_COPPER,
138 "Intel(R) PRO/1000 PT 82571EB/82571GB (Copper)"),
139 PVID(0x8086, E1000_DEV_ID_82571EB_FIBER,
140 "Intel(R) PRO/1000 PF 82571EB/82571GB (Fiber)"),
141 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES,
142 "Intel(R) PRO/1000 PB 82571EB (SERDES)"),
143 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL,
144 "Intel(R) PRO/1000 82571EB (Dual Mezzanine)"),
145 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD,
146 "Intel(R) PRO/1000 82571EB (Quad Mezzanine)"),
147 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER,
148 "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"),
149 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP,
150 "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"),
151 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER,
152 "Intel(R) PRO/1000 PF 82571EB (Quad Fiber)"),
153 PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER,
154 "Intel(R) PRO/1000 PT 82571PT (Quad Copper)"),
155 PVID(0x8086, E1000_DEV_ID_82572EI,
156 "Intel(R) PRO/1000 PT 82572EI (Copper)"),
157 PVID(0x8086, E1000_DEV_ID_82572EI_COPPER,
158 "Intel(R) PRO/1000 PT 82572EI (Copper)"),
159 PVID(0x8086, E1000_DEV_ID_82572EI_FIBER,
160 "Intel(R) PRO/1000 PF 82572EI (Fiber)"),
161 PVID(0x8086, E1000_DEV_ID_82572EI_SERDES,
162 "Intel(R) PRO/1000 82572EI (SERDES)"),
163 PVID(0x8086, E1000_DEV_ID_82573E,
164 "Intel(R) PRO/1000 82573E (Copper)"),
165 PVID(0x8086, E1000_DEV_ID_82573E_IAMT,
166 "Intel(R) PRO/1000 82573E AMT (Copper)"),
167 PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 82573L"),
168 PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) 82583V"),
169 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT,
170 "Intel(R) 80003ES2LAN (Copper)"),
171 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT,
172 "Intel(R) 80003ES2LAN (SERDES)"),
173 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT,
174 "Intel(R) 80003ES2LAN (Dual Copper)"),
175 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT,
176 "Intel(R) 80003ES2LAN (Dual SERDES)"),
177 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT,
178 "Intel(R) 82566MM ICH8 AMT (Mobile)"),
179 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) 82566DM ICH8 AMT"),
180 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) 82566DC ICH8"),
181 PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) 82562V ICH8"),
182 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) 82562GT ICH8"),
183 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) 82562G ICH8"),
184 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) 82566MC ICH8"),
185 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) 82567V-3 ICH8"),
186 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT,
187 "Intel(R) 82567LM ICH9 AMT"),
188 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT,
189 "Intel(R) 82566DM-2 ICH9 AMT"),
190 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) 82566DC-2 ICH9"),
191 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) 82567LF ICH9"),
192 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) 82567V ICH9"),
193 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) 82562V-2 ICH9"),
194 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) 82562GT-2 ICH9"),
195 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) 82562G-2 ICH9"),
196 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) 82567LM-4 ICH9"),
197 PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) Gigabit CT 82574L"),
198 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) 82574L-Apple"),
199 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) 82567LM-2 ICH10"),
200 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) 82567LF-2 ICH10"),
201 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) 82567V-2 ICH10"),
202 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) 82567LM-3 ICH10"),
203 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) 82567LF-3 ICH10"),
204 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) 82567V-4 ICH10"),
205 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) 82577LM"),
206 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) 82577LC"),
207 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) 82578DM"),
208 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) 82578DC"),
209 PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) 82579LM"),
210 PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) 82579V"),
211 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) I217-LM LPT"),
212 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) I217-V LPT"),
213 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM,
214 "Intel(R) I218-LM LPTLP"),
215 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) I218-V LPTLP"),
216 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) I218-LM (2)"),
217 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) I218-V (2)"),
218 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) I218-LM (3)"),
219 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) I218-V (3)"),
220 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) I219-LM SPT"),
221 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) I219-V SPT"),
222 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2,
223 "Intel(R) I219-LM SPT-H(2)"),
224 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2,
225 "Intel(R) I219-V SPT-H(2)"),
226 PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3,
227 "Intel(R) I219-LM LBG(3)"),
228 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4,
229 "Intel(R) I219-LM SPT(4)"),
230 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) I219-V SPT(4)"),
231 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5,
232 "Intel(R) I219-LM SPT(5)"),
233 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) I219-V SPT(5)"),
234 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6,
235 "Intel(R) I219-LM CNP(6)"),
236 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) I219-V CNP(6)"),
237 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7,
238 "Intel(R) I219-LM CNP(7)"),
239 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) I219-V CNP(7)"),
240 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8,
241 "Intel(R) I219-LM ICP(8)"),
242 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) I219-V ICP(8)"),
243 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9,
244 "Intel(R) I219-LM ICP(9)"),
245 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) I219-V ICP(9)"),
246 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM10,
247 "Intel(R) I219-LM CMP(10)"),
248 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V10,
249 "Intel(R) I219-V CMP(10)"),
250 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM11,
251 "Intel(R) I219-LM CMP(11)"),
252 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V11,
253 "Intel(R) I219-V CMP(11)"),
254 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM12,
255 "Intel(R) I219-LM CMP(12)"),
256 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V12,
257 "Intel(R) I219-V CMP(12)"),
258 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM13,
259 "Intel(R) I219-LM TGP(13)"),
260 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V13,
261 "Intel(R) I219-V TGP(13)"),
262 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM14,
263 "Intel(R) I219-LM TGP(14)"),
264 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V14,
265 "Intel(R) I219-V GTP(14)"),
266 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM15,
267 "Intel(R) I219-LM TGP(15)"),
268 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V15,
269 "Intel(R) I219-V TGP(15)"),
270 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM16,
271 "Intel(R) I219-LM ADL(16)"),
272 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V16,
273 "Intel(R) I219-V ADL(16)"),
274 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM17,
275 "Intel(R) I219-LM ADL(17)"),
276 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V17,
277 "Intel(R) I219-V ADL(17)"),
278 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM18,
279 "Intel(R) I219-LM MTP(18)"),
280 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V18,
281 "Intel(R) I219-V MTP(18)"),
282 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM19,
283 "Intel(R) I219-LM ADL(19)"),
284 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V19,
285 "Intel(R) I219-V ADL(19)"),
286 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_LM20,
287 "Intel(R) I219-LM LNL(20)"),
288 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_V20,
289 "Intel(R) I219-V LNL(20)"),
290 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_LM21,
291 "Intel(R) I219-LM LNL(21)"),
292 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_V21,
293 "Intel(R) I219-V LNL(21)"),
294 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_LM22,
295 "Intel(R) I219-LM RPL(22)"),
296 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V22,
297 "Intel(R) I219-V RPL(22)"),
298 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_LM23,
299 "Intel(R) I219-LM RPL(23)"),
300 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V23,
301 "Intel(R) I219-V RPL(23)"),
302 PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_LM24,
303 "Intel(R) I219-LM ARL(24)"),
304 PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_V24,
305 "Intel(R) I219-V ARL(24)"),
306 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM25,
307 "Intel(R) I219-LM PTP(25)"),
308 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V25,
309 "Intel(R) I219-V PTP(25)"),
310 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM26,
311 "Intel(R) I219-LM PTP(26)"),
312 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V26,
313 "Intel(R) I219-V PTP(26)"),
314 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM27,
315 "Intel(R) I219-LM PTP(27)"),
316 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V27,
317 "Intel(R) I219-V PTP(27)"),
318 /* required last entry */
319 PVID_END
320 };
321
322 static const pci_vendor_info_t igb_vendor_info_array[] =
323 {
324 /* Intel(R) - igb-class devices */
325 PVID(0x8086, E1000_DEV_ID_82575EB_COPPER,
326 "Intel(R) PRO/1000 82575EB (Copper)"),
327 PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES,
328 "Intel(R) PRO/1000 82575EB (SERDES)"),
329 PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER,
330 "Intel(R) PRO/1000 VT 82575GB (Quad Copper)"),
331 PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 82576"),
332 PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 82576NS"),
333 PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES,
334 "Intel(R) PRO/1000 82576NS (SERDES)"),
335 PVID(0x8086, E1000_DEV_ID_82576_FIBER,
336 "Intel(R) PRO/1000 EF 82576 (Dual Fiber)"),
337 PVID(0x8086, E1000_DEV_ID_82576_SERDES,
338 "Intel(R) PRO/1000 82576 (Dual SERDES)"),
339 PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD,
340 "Intel(R) PRO/1000 ET 82576 (Quad SERDES)"),
341 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER,
342 "Intel(R) PRO/1000 ET 82576 (Quad Copper)"),
343 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2,
344 "Intel(R) PRO/1000 ET(2) 82576 (Quad Copper)"),
345 PVID(0x8086, E1000_DEV_ID_82576_VF,
346 "Intel(R) PRO/1000 82576 Virtual Function"),
347 PVID(0x8086, E1000_DEV_ID_82580_COPPER,
348 "Intel(R) I340 82580 (Copper)"),
349 PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) I340 82580 (Fiber)"),
350 PVID(0x8086, E1000_DEV_ID_82580_SERDES,
351 "Intel(R) I340 82580 (SERDES)"),
352 PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) I340 82580 (SGMII)"),
353 PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL,
354 "Intel(R) I340-T2 82580 (Dual Copper)"),
355 PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER,
356 "Intel(R) I340-F4 82580 (Quad Fiber)"),
357 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES,
358 "Intel(R) DH89XXCC (SERDES)"),
359 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII,
360 "Intel(R) I347-AT4 DH89XXCC"),
361 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) DH89XXCC (SFP)"),
362 PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE,
363 "Intel(R) DH89XXCC (Backplane)"),
364 PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) I350 (Copper)"),
365 PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) I350 (Fiber)"),
366 PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) I350 (SERDES)"),
367 PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) I350 (SGMII)"),
368 PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) I350 Virtual Function"),
369 PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) I210 (Copper)"),
370 PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT,
371 "Intel(R) I210 IT (Copper)"),
372 PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) I210 (OEM)"),
373 PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS,
374 "Intel(R) I210 Flashless (Copper)"),
375 PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS,
376 "Intel(R) I210 Flashless (SERDES)"),
377 PVID(0x8086, E1000_DEV_ID_I210_SGMII_FLASHLESS,
378 "Intel(R) I210 Flashless (SGMII)"),
379 PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) I210 (Fiber)"),
380 PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) I210 (SERDES)"),
381 PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) I210 (SGMII)"),
382 PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) I211 (Copper)"),
383 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS,
384 "Intel(R) I354 (1.0 GbE Backplane)"),
385 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS,
386 "Intel(R) I354 (2.5 GbE Backplane)"),
387 PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) I354 (SGMII)"),
388 /* required last entry */
389 PVID_END
390 };
391
392 /*********************************************************************
393 * Function prototypes
394 *********************************************************************/
395 static void *em_register(device_t);
396 static void *igb_register(device_t);
397 static int em_if_attach_pre(if_ctx_t);
398 static int em_if_attach_post(if_ctx_t);
399 static int em_if_detach(if_ctx_t);
400 static int em_if_shutdown(if_ctx_t);
401 static int em_if_suspend(if_ctx_t);
402 static int em_if_resume(if_ctx_t);
403
404 static int em_if_tx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int,
405 int);
406 static int em_if_rx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int,
407 int);
408 static void em_if_queues_free(if_ctx_t);
409
410 static uint64_t em_if_get_counter(if_ctx_t, ift_counter);
411 static void em_if_init(if_ctx_t);
412 static void em_if_stop(if_ctx_t);
413 static void em_if_media_status(if_ctx_t, struct ifmediareq *);
414 static int em_if_media_change(if_ctx_t);
415 static int em_if_mtu_set(if_ctx_t, uint32_t);
416 static void em_if_timer(if_ctx_t, uint16_t);
417 static void em_if_vlan_register(if_ctx_t, u16);
418 static void em_if_vlan_unregister(if_ctx_t, u16);
419 static void em_if_watchdog_reset(if_ctx_t);
420 static bool em_if_needs_restart(if_ctx_t, enum iflib_restart_event);
421
422 static void em_identify_hardware(if_ctx_t);
423 static int em_allocate_pci_resources(if_ctx_t);
424 static void em_free_pci_resources(if_ctx_t);
425 static void em_reset(if_ctx_t);
426 static int em_setup_interface(if_ctx_t);
427 static int em_setup_msix(if_ctx_t);
428
429 static void em_initialize_transmit_unit(if_ctx_t);
430 static void em_initialize_receive_unit(if_ctx_t);
431
432 static void em_if_intr_enable(if_ctx_t);
433 static void em_if_intr_disable(if_ctx_t);
434 static void igb_if_intr_enable(if_ctx_t);
435 static void igb_if_intr_disable(if_ctx_t);
436 static int em_if_rx_queue_intr_enable(if_ctx_t, uint16_t);
437 static int em_if_tx_queue_intr_enable(if_ctx_t, uint16_t);
438 static int igb_if_rx_queue_intr_enable(if_ctx_t, uint16_t);
439 static int igb_if_tx_queue_intr_enable(if_ctx_t, uint16_t);
440 static void em_if_multi_set(if_ctx_t);
441 static void em_if_update_admin_status(if_ctx_t);
442 static void em_if_debug(if_ctx_t);
443 static void em_update_stats_counters(struct e1000_softc *);
444 static void em_add_hw_stats(struct e1000_softc *);
445 static int em_if_set_promisc(if_ctx_t, int);
446 static bool em_if_vlan_filter_capable(if_ctx_t);
447 static bool em_if_vlan_filter_used(if_ctx_t);
448 static void em_if_vlan_filter_enable(struct e1000_softc *);
449 static void em_if_vlan_filter_disable(struct e1000_softc *);
450 static void em_if_vlan_filter_write(struct e1000_softc *);
451 static void em_setup_vlan_hw_support(if_ctx_t ctx);
452 static int em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS);
453 static void em_print_nvm_info(struct e1000_softc *);
454 static void em_fw_version_locked(if_ctx_t);
455 static void em_sbuf_fw_version(struct e1000_fw_version *, struct sbuf *);
456 static void em_print_fw_version(struct e1000_softc *);
457 static int em_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS);
458 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
459 static int em_get_rs(SYSCTL_HANDLER_ARGS);
460 static void em_print_debug_info(struct e1000_softc *);
461 static int em_is_valid_ether_addr(u8 *);
462 static void em_newitr(struct e1000_softc *, struct em_rx_queue *,
463 struct tx_ring *, struct rx_ring *);
464 static bool em_automask_tso(if_ctx_t);
465 static int em_sysctl_tso_tcp_flags_mask(SYSCTL_HANDLER_ARGS);
466 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS);
467 static void em_add_int_delay_sysctl(struct e1000_softc *, const char *,
468 const char *, struct em_int_delay_info *, int, int);
469 /* Management and WOL Support */
470 static void em_init_manageability(struct e1000_softc *);
471 static void em_release_manageability(struct e1000_softc *);
472 static void em_get_hw_control(struct e1000_softc *);
473 static void em_release_hw_control(struct e1000_softc *);
474 static void em_get_wakeup(if_ctx_t);
475 static void em_enable_wakeup(if_ctx_t);
476 static int em_enable_phy_wakeup(struct e1000_softc *);
477 static void em_disable_aspm(struct e1000_softc *);
478
479 int em_intr(void *);
480
481 /* MSI-X handlers */
482 static int em_if_msix_intr_assign(if_ctx_t, int);
483 static int em_msix_link(void *);
484 static void em_handle_link(void *);
485
486 static void em_enable_vectors_82574(if_ctx_t);
487
488 static int em_set_flowcntl(SYSCTL_HANDLER_ARGS);
489 static int em_sysctl_eee(SYSCTL_HANDLER_ARGS);
490 static int igb_sysctl_dmac(SYSCTL_HANDLER_ARGS);
491 static void em_if_led_func(if_ctx_t, int);
492
493 static int em_get_regs(SYSCTL_HANDLER_ARGS);
494
495 static void lem_smartspeed(struct e1000_softc *);
496 static void igb_configure_queues(struct e1000_softc *);
497 static void em_flush_desc_rings(struct e1000_softc *);
498
499
500 /*********************************************************************
501 * FreeBSD Device Interface Entry Points
502 *********************************************************************/
503 static device_method_t em_methods[] = {
504 /* Device interface */
505 DEVMETHOD(device_register, em_register),
506 DEVMETHOD(device_probe, iflib_device_probe),
507 DEVMETHOD(device_attach, iflib_device_attach),
508 DEVMETHOD(device_detach, iflib_device_detach),
509 DEVMETHOD(device_shutdown, iflib_device_shutdown),
510 DEVMETHOD(device_suspend, iflib_device_suspend),
511 DEVMETHOD(device_resume, iflib_device_resume),
512 DEVMETHOD_END
513 };
514
515 static device_method_t igb_methods[] = {
516 /* Device interface */
517 DEVMETHOD(device_register, igb_register),
518 DEVMETHOD(device_probe, iflib_device_probe),
519 DEVMETHOD(device_attach, iflib_device_attach),
520 DEVMETHOD(device_detach, iflib_device_detach),
521 DEVMETHOD(device_shutdown, iflib_device_shutdown),
522 DEVMETHOD(device_suspend, iflib_device_suspend),
523 DEVMETHOD(device_resume, iflib_device_resume),
524 DEVMETHOD_END
525 };
526
527
528 static driver_t em_driver = {
529 "em", em_methods, sizeof(struct e1000_softc),
530 };
531
532 static devclass_t em_devclass;
533 DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0);
534
535 MODULE_DEPEND(em, pci, 1, 1, 1);
536 MODULE_DEPEND(em, ether, 1, 1, 1);
537 MODULE_DEPEND(em, iflib, 1, 1, 1);
538
539 IFLIB_PNP_INFO(pci, em, em_vendor_info_array);
540
541 static driver_t igb_driver = {
542 "igb", igb_methods, sizeof(struct e1000_softc),
543 };
544
545 static devclass_t igb_devclass;
546 DRIVER_MODULE(igb, pci, igb_driver, igb_devclass, 0, 0);
547
548 MODULE_DEPEND(igb, pci, 1, 1, 1);
549 MODULE_DEPEND(igb, ether, 1, 1, 1);
550 MODULE_DEPEND(igb, iflib, 1, 1, 1);
551
552 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array);
553
554 static device_method_t em_if_methods[] = {
555 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre),
556 DEVMETHOD(ifdi_attach_post, em_if_attach_post),
557 DEVMETHOD(ifdi_detach, em_if_detach),
558 DEVMETHOD(ifdi_shutdown, em_if_shutdown),
559 DEVMETHOD(ifdi_suspend, em_if_suspend),
560 DEVMETHOD(ifdi_resume, em_if_resume),
561 DEVMETHOD(ifdi_init, em_if_init),
562 DEVMETHOD(ifdi_stop, em_if_stop),
563 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign),
564 DEVMETHOD(ifdi_intr_enable, em_if_intr_enable),
565 DEVMETHOD(ifdi_intr_disable, em_if_intr_disable),
566 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc),
567 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc),
568 DEVMETHOD(ifdi_queues_free, em_if_queues_free),
569 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status),
570 DEVMETHOD(ifdi_multi_set, em_if_multi_set),
571 DEVMETHOD(ifdi_media_status, em_if_media_status),
572 DEVMETHOD(ifdi_media_change, em_if_media_change),
573 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set),
574 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc),
575 DEVMETHOD(ifdi_timer, em_if_timer),
576 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset),
577 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register),
578 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister),
579 DEVMETHOD(ifdi_get_counter, em_if_get_counter),
580 DEVMETHOD(ifdi_led_func, em_if_led_func),
581 DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable),
582 DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable),
583 DEVMETHOD(ifdi_debug, em_if_debug),
584 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart),
585 DEVMETHOD_END
586 };
587
588 static driver_t em_if_driver = {
589 "em_if", em_if_methods, sizeof(struct e1000_softc)
590 };
591
592 static device_method_t igb_if_methods[] = {
593 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre),
594 DEVMETHOD(ifdi_attach_post, em_if_attach_post),
595 DEVMETHOD(ifdi_detach, em_if_detach),
596 DEVMETHOD(ifdi_shutdown, em_if_shutdown),
597 DEVMETHOD(ifdi_suspend, em_if_suspend),
598 DEVMETHOD(ifdi_resume, em_if_resume),
599 DEVMETHOD(ifdi_init, em_if_init),
600 DEVMETHOD(ifdi_stop, em_if_stop),
601 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign),
602 DEVMETHOD(ifdi_intr_enable, igb_if_intr_enable),
603 DEVMETHOD(ifdi_intr_disable, igb_if_intr_disable),
604 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc),
605 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc),
606 DEVMETHOD(ifdi_queues_free, em_if_queues_free),
607 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status),
608 DEVMETHOD(ifdi_multi_set, em_if_multi_set),
609 DEVMETHOD(ifdi_media_status, em_if_media_status),
610 DEVMETHOD(ifdi_media_change, em_if_media_change),
611 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set),
612 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc),
613 DEVMETHOD(ifdi_timer, em_if_timer),
614 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset),
615 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register),
616 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister),
617 DEVMETHOD(ifdi_get_counter, em_if_get_counter),
618 DEVMETHOD(ifdi_led_func, em_if_led_func),
619 DEVMETHOD(ifdi_rx_queue_intr_enable, igb_if_rx_queue_intr_enable),
620 DEVMETHOD(ifdi_tx_queue_intr_enable, igb_if_tx_queue_intr_enable),
621 DEVMETHOD(ifdi_debug, em_if_debug),
622 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart),
623 DEVMETHOD_END
624 };
625
626 static driver_t igb_if_driver = {
627 "igb_if", igb_if_methods, sizeof(struct e1000_softc)
628 };
629
630 /*********************************************************************
631 * Tunable default values.
632 *********************************************************************/
633
634 #define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000)
635 #define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024)
636
637 /* Allow common code without TSO */
638 #ifndef CSUM_TSO
639 #define CSUM_TSO 0
640 #endif
641
642 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
643 "EM driver parameters");
644
645 static int em_disable_crc_stripping = 0;
646 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN,
647 &em_disable_crc_stripping, 0, "Disable CRC Stripping");
648
649 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV);
650 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR);
651 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN,
652 &em_tx_int_delay_dflt, 0, "Default transmit interrupt delay in usecs");
653 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN,
654 &em_rx_int_delay_dflt, 0, "Default receive interrupt delay in usecs");
655
656 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV);
657 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV);
658 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN,
659 &em_tx_abs_int_delay_dflt, 0,
660 "Default transmit interrupt delay limit in usecs");
661 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN,
662 &em_rx_abs_int_delay_dflt, 0,
663 "Default receive interrupt delay limit in usecs");
664
665 static int em_smart_pwr_down = false;
666 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN,
667 &em_smart_pwr_down,
668 0, "Set to true to leave smart power down enabled on newer adapters");
669
670 static bool em_unsupported_tso = false;
671 SYSCTL_BOOL(_hw_em, OID_AUTO, unsupported_tso, CTLFLAG_RDTUN,
672 &em_unsupported_tso, 0, "Allow unsupported em(4) TSO configurations");
673
674 /* Controls whether promiscuous also shows bad packets */
675 static int em_debug_sbp = false;
676 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0,
677 "Show bad packets in promiscuous mode");
678
679 /* Energy efficient ethernet - default to OFF */
680 static int eee_setting = 1;
681 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0,
682 "Enable Energy Efficient Ethernet");
683
684 /*
685 * AIM: Adaptive Interrupt Moderation
686 * which means that the interrupt rate is varied over time based on the
687 * traffic for that interrupt vector
688 */
689 static int em_enable_aim = 1;
690 SYSCTL_INT(_hw_em, OID_AUTO, enable_aim, CTLFLAG_RWTUN, &em_enable_aim,
691 0, "Enable adaptive interrupt moderation (1=normal, 2=lowlatency)");
692
693 /*
694 ** Tuneable Interrupt rate
695 */
696 static int em_max_interrupt_rate = EM_INTS_DEFAULT;
697 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN,
698 &em_max_interrupt_rate, 0, "Maximum interrupts per second");
699
700 /* Global used in WOL setup with multiport cards */
701 static int global_quad_port_a = 0;
702
703 extern struct if_txrx igb_txrx;
704 extern struct if_txrx em_txrx;
705 extern struct if_txrx lem_txrx;
706
707 static struct if_shared_ctx em_sctx_init = {
708 .isc_magic = IFLIB_MAGIC,
709 .isc_q_align = PAGE_SIZE,
710 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
711 .isc_tx_maxsegsize = PAGE_SIZE,
712 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
713 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE,
714 .isc_rx_maxsize = MJUM9BYTES,
715 .isc_rx_nsegments = 1,
716 .isc_rx_maxsegsize = MJUM9BYTES,
717 .isc_nfl = 1,
718 .isc_nrxqs = 1,
719 .isc_ntxqs = 1,
720 .isc_admin_intrcnt = 1,
721 .isc_vendor_info = em_vendor_info_array,
722 .isc_driver_version = em_driver_version,
723 .isc_driver = &em_if_driver,
724 .isc_flags =
725 IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM,
726
727 .isc_nrxd_min = {EM_MIN_RXD},
728 .isc_ntxd_min = {EM_MIN_TXD},
729 .isc_nrxd_max = {EM_MAX_RXD},
730 .isc_ntxd_max = {EM_MAX_TXD},
731 .isc_nrxd_default = {EM_DEFAULT_RXD},
732 .isc_ntxd_default = {EM_DEFAULT_TXD},
733 };
734
735 static struct if_shared_ctx igb_sctx_init = {
736 .isc_magic = IFLIB_MAGIC,
737 .isc_q_align = PAGE_SIZE,
738 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
739 .isc_tx_maxsegsize = PAGE_SIZE,
740 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
741 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE,
742 .isc_rx_maxsize = MJUM9BYTES,
743 .isc_rx_nsegments = 1,
744 .isc_rx_maxsegsize = MJUM9BYTES,
745 .isc_nfl = 1,
746 .isc_nrxqs = 1,
747 .isc_ntxqs = 1,
748 .isc_admin_intrcnt = 1,
749 .isc_vendor_info = igb_vendor_info_array,
750 .isc_driver_version = igb_driver_version,
751 .isc_driver = &igb_if_driver,
752 .isc_flags =
753 IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM,
754
755 .isc_nrxd_min = {EM_MIN_RXD},
756 .isc_ntxd_min = {EM_MIN_TXD},
757 .isc_nrxd_max = {IGB_MAX_RXD},
758 .isc_ntxd_max = {IGB_MAX_TXD},
759 .isc_nrxd_default = {EM_DEFAULT_RXD},
760 .isc_ntxd_default = {EM_DEFAULT_TXD},
761 };
762
763 /*****************************************************************
764 *
765 * Dump Registers
766 *
767 ****************************************************************/
768 #define IGB_REGS_LEN 739
769
em_get_regs(SYSCTL_HANDLER_ARGS)770 static int em_get_regs(SYSCTL_HANDLER_ARGS)
771 {
772 struct e1000_softc *sc = (struct e1000_softc *)arg1;
773 struct e1000_hw *hw = &sc->hw;
774 struct sbuf *sb;
775 u32 *regs_buff;
776 int rc;
777
778 regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK);
779 memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32));
780
781 rc = sysctl_wire_old_buffer(req, 0);
782 MPASS(rc == 0);
783 if (rc != 0) {
784 free(regs_buff, M_DEVBUF);
785 return (rc);
786 }
787
788 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req);
789 MPASS(sb != NULL);
790 if (sb == NULL) {
791 free(regs_buff, M_DEVBUF);
792 return (ENOMEM);
793 }
794
795 /* General Registers */
796 regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL);
797 regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS);
798 regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT);
799 regs_buff[3] = E1000_READ_REG(hw, E1000_ICR);
800 regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL);
801 regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0));
802 regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0));
803 regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0));
804 regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0));
805 regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0));
806 regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0));
807 regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL);
808 regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0));
809 regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0));
810 regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0));
811 regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0));
812 regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0));
813 regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0));
814 regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH);
815 regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT);
816 regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS);
817 regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC);
818
819 sbuf_printf(sb, "General Registers\n");
820 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]);
821 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]);
822 sbuf_printf(sb, "\tCTRL_EXT\t %08x\n\n", regs_buff[2]);
823
824 sbuf_printf(sb, "Interrupt Registers\n");
825 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]);
826
827 sbuf_printf(sb, "RX Registers\n");
828 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]);
829 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]);
830 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]);
831 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]);
832 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]);
833 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]);
834 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]);
835
836 sbuf_printf(sb, "TX Registers\n");
837 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]);
838 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]);
839 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]);
840 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]);
841 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]);
842 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]);
843 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]);
844 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]);
845 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]);
846 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]);
847 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]);
848
849 free(regs_buff, M_DEVBUF);
850
851 #ifdef DUMP_DESCS
852 {
853 if_softc_ctx_t scctx = sc->shared;
854 struct rx_ring *rxr = &rx_que->rxr;
855 struct tx_ring *txr = &tx_que->txr;
856 int ntxd = scctx->isc_ntxd[0];
857 int nrxd = scctx->isc_nrxd[0];
858 int j;
859
860 for (j = 0; j < nrxd; j++) {
861 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error);
862 u32 length = le32toh(rxr->rx_base[j].wb.upper.length);
863 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08"
864 PRIx64 " Error:%d Length:%d\n",
865 j, rxr->rx_base[j].read.buffer_addr, staterr, length);
866 }
867
868 for (j = 0; j < min(ntxd, 256); j++) {
869 unsigned int *ptr = (unsigned int *)&txr->tx_base[j];
870
871 sbuf_printf(sb,
872 "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x"
873 " eop: %d DD=%d\n",
874 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop,
875 buf->eop != -1 ?
876 txr->tx_base[buf->eop].upper.fields.status &
877 E1000_TXD_STAT_DD : 0);
878
879 }
880 }
881 #endif
882
883 rc = sbuf_finish(sb);
884 sbuf_delete(sb);
885 return(rc);
886 }
887
888 static void *
em_register(device_t dev)889 em_register(device_t dev)
890 {
891 return (&em_sctx_init);
892 }
893
894 static void *
igb_register(device_t dev)895 igb_register(device_t dev)
896 {
897 return (&igb_sctx_init);
898 }
899
900 static int
em_set_num_queues(if_ctx_t ctx)901 em_set_num_queues(if_ctx_t ctx)
902 {
903 struct e1000_softc *sc = iflib_get_softc(ctx);
904 int maxqueues;
905
906 /* Sanity check based on HW */
907 switch (sc->hw.mac.type) {
908 case e1000_82576:
909 case e1000_82580:
910 case e1000_i350:
911 case e1000_i354:
912 maxqueues = 8;
913 break;
914 case e1000_i210:
915 case e1000_82575:
916 maxqueues = 4;
917 break;
918 case e1000_i211:
919 case e1000_82574:
920 maxqueues = 2;
921 break;
922 default:
923 maxqueues = 1;
924 break;
925 }
926
927 return (maxqueues);
928 }
929
930 #define LEM_CAPS \
931 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \
932 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \
933 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6
934
935 #define EM_CAPS \
936 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \
937 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \
938 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 | \
939 IFCAP_TSO6
940
941 #define IGB_CAPS \
942 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \
943 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \
944 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 | \
945 IFCAP_TSO6
946
947 /*********************************************************************
948 * Device initialization routine
949 *
950 * The attach entry point is called when the driver is being loaded.
951 * This routine identifies the type of hardware, allocates all resources
952 * and initializes the hardware.
953 *
954 * return 0 on success, positive on failure
955 *********************************************************************/
956 static int
em_if_attach_pre(if_ctx_t ctx)957 em_if_attach_pre(if_ctx_t ctx)
958 {
959 struct e1000_softc *sc;
960 if_softc_ctx_t scctx;
961 device_t dev;
962 struct e1000_hw *hw;
963 struct sysctl_oid_list *child;
964 struct sysctl_ctx_list *ctx_list;
965 int error = 0;
966
967 INIT_DEBUGOUT("em_if_attach_pre: begin");
968 dev = iflib_get_dev(ctx);
969 sc = iflib_get_softc(ctx);
970
971 sc->ctx = sc->osdep.ctx = ctx;
972 sc->dev = sc->osdep.dev = dev;
973 scctx = sc->shared = iflib_get_softc_ctx(ctx);
974 sc->media = iflib_get_media(ctx);
975 hw = &sc->hw;
976
977 /* Determine hardware and mac info */
978 em_identify_hardware(ctx);
979
980 /* SYSCTL stuff */
981 ctx_list = device_get_sysctl_ctx(dev);
982 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
983
984 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "nvm",
985 CTLTYPE_INT | CTLFLAG_RW, sc, 0,
986 em_sysctl_nvm_info, "I", "NVM Information");
987
988 sc->enable_aim = em_enable_aim;
989 SYSCTL_ADD_INT(ctx_list, child, OID_AUTO, "enable_aim",
990 CTLFLAG_RW, &sc->enable_aim, 0,
991 "Interrupt Moderation (1=normal, 2=lowlatency)");
992
993 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fw_version",
994 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
995 em_sysctl_print_fw_version, "A",
996 "Prints FW/NVM Versions");
997
998 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "debug",
999 CTLTYPE_INT | CTLFLAG_RW, sc, 0,
1000 em_sysctl_debug_info, "I", "Debug Information");
1001
1002 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fc",
1003 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
1004 em_set_flowcntl, "I", "Flow Control");
1005
1006 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "reg_dump",
1007 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0,
1008 em_get_regs, "A", "Dump Registers");
1009
1010 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "rs_dump",
1011 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
1012 em_get_rs, "I", "Dump RS indexes");
1013
1014 if (hw->mac.type >= e1000_i350) {
1015 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "dmac",
1016 CTLTYPE_INT | CTLFLAG_RW, sc, 0,
1017 igb_sysctl_dmac, "I", "DMA Coalesce");
1018 }
1019
1020 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO,
1021 "tso_tcp_flags_mask_first_segment",
1022 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
1023 sc, 0, em_sysctl_tso_tcp_flags_mask, "IU",
1024 "TSO TCP flags mask for first segment");
1025
1026 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO,
1027 "tso_tcp_flags_mask_middle_segment",
1028 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
1029 sc, 1, em_sysctl_tso_tcp_flags_mask, "IU",
1030 "TSO TCP flags mask for middle segment");
1031
1032 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO,
1033 "tso_tcp_flags_mask_last_segment",
1034 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
1035 sc, 2, em_sysctl_tso_tcp_flags_mask, "IU",
1036 "TSO TCP flags mask for last segment");
1037
1038 scctx->isc_tx_nsegments = EM_MAX_SCATTER;
1039 scctx->isc_nrxqsets_max =
1040 scctx->isc_ntxqsets_max = em_set_num_queues(ctx);
1041 if (bootverbose)
1042 device_printf(dev, "attach_pre capping queues at %d\n",
1043 scctx->isc_ntxqsets_max);
1044
1045 if (hw->mac.type >= igb_mac_min) {
1046 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] *
1047 sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN);
1048 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] *
1049 sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN);
1050 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc);
1051 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc);
1052 scctx->isc_txrx = &igb_txrx;
1053 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER;
1054 scctx->isc_tx_tso_size_max = EM_TSO_SIZE;
1055 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE;
1056 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS;
1057 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO |
1058 CSUM_IP6_TCP | CSUM_IP6_UDP;
1059 if (hw->mac.type != e1000_82575)
1060 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP;
1061 /*
1062 ** Some new devices, as with ixgbe, now may
1063 ** use a different BAR, so we need to keep
1064 ** track of which is used.
1065 */
1066 scctx->isc_msix_bar = pci_msix_table_bar(dev);
1067 } else if (hw->mac.type >= em_mac_min) {
1068 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] *
1069 sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
1070 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] *
1071 sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN);
1072 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc);
1073 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended);
1074 scctx->isc_txrx = &em_txrx;
1075 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER;
1076 scctx->isc_tx_tso_size_max = EM_TSO_SIZE;
1077 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE;
1078 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS;
1079 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO |
1080 CSUM_IP6_TCP | CSUM_IP6_UDP;
1081
1082 /* Disable TSO on all em(4) until ring stalls are debugged */
1083 scctx->isc_capenable &= ~IFCAP_TSO;
1084
1085 /*
1086 * Disable TSO on SPT due to errata that downclocks DMA
1087 * performance
1088 * i218-i219 Specification Update 1.5.4.5
1089 */
1090 if (hw->mac.type == e1000_pch_spt)
1091 scctx->isc_capenable &= ~IFCAP_TSO;
1092
1093 /*
1094 * We support MSI-X with 82574 only, but indicate to iflib(4)
1095 * that it shall give MSI at least a try with other devices.
1096 */
1097 if (hw->mac.type == e1000_82574) {
1098 scctx->isc_msix_bar = pci_msix_table_bar(dev);;
1099 } else {
1100 scctx->isc_msix_bar = -1;
1101 scctx->isc_disable_msix = 1;
1102 }
1103 } else {
1104 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) *
1105 sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
1106 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) *
1107 sizeof(struct e1000_rx_desc), EM_DBA_ALIGN);
1108 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc);
1109 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc);
1110 scctx->isc_txrx = &lem_txrx;
1111 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER;
1112 scctx->isc_tx_tso_size_max = EM_TSO_SIZE;
1113 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE;
1114 scctx->isc_capabilities = scctx->isc_capenable = LEM_CAPS;
1115 if (em_unsupported_tso)
1116 scctx->isc_capabilities |= IFCAP_TSO6;
1117 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO |
1118 CSUM_IP6_TCP | CSUM_IP6_UDP;
1119
1120 /* Disable TSO on all lem(4) until ring stalls debugged */
1121 scctx->isc_capenable &= ~IFCAP_TSO;
1122
1123 /* 82541ER doesn't do HW tagging */
1124 if (hw->device_id == E1000_DEV_ID_82541ER ||
1125 hw->device_id == E1000_DEV_ID_82541ER_LOM) {
1126 scctx->isc_capabilities &= ~IFCAP_VLAN_HWTAGGING;
1127 scctx->isc_capenable = scctx->isc_capabilities;
1128 }
1129 /* This is the first e1000 chip and it does not do offloads */
1130 if (hw->mac.type == e1000_82542) {
1131 scctx->isc_capabilities &= ~(IFCAP_HWCSUM |
1132 IFCAP_VLAN_HWCSUM | IFCAP_HWCSUM_IPV6 |
1133 IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWFILTER |
1134 IFCAP_TSO | IFCAP_VLAN_HWTSO);
1135 scctx->isc_capenable = scctx->isc_capabilities;
1136 }
1137 /* These can't do TSO for various reasons */
1138 if (hw->mac.type < e1000_82544 ||
1139 hw->mac.type == e1000_82547 ||
1140 hw->mac.type == e1000_82547_rev_2) {
1141 scctx->isc_capabilities &=
1142 ~(IFCAP_TSO |IFCAP_VLAN_HWTSO);
1143 scctx->isc_capenable = scctx->isc_capabilities;
1144 }
1145 /* XXXKB: No IPv6 before this? */
1146 if (hw->mac.type < e1000_82545){
1147 scctx->isc_capabilities &= ~IFCAP_HWCSUM_IPV6;
1148 scctx->isc_capenable = scctx->isc_capabilities;
1149 }
1150 /*
1151 * "PCI/PCI-X SDM 4.0" page 33 (b):
1152 * FDX requirement on these chips
1153 */
1154 if (hw->mac.type == e1000_82547 ||
1155 hw->mac.type == e1000_82547_rev_2)
1156 scctx->isc_capenable &= ~(IFCAP_HWCSUM |
1157 IFCAP_VLAN_HWCSUM | IFCAP_HWCSUM_IPV6);
1158
1159 /* INTx only */
1160 scctx->isc_msix_bar = 0;
1161 }
1162
1163 /* Setup PCI resources */
1164 if (em_allocate_pci_resources(ctx)) {
1165 device_printf(dev, "Allocation of PCI resources failed\n");
1166 error = ENXIO;
1167 goto err_pci;
1168 }
1169
1170 /*
1171 ** For ICH8 and family we need to
1172 ** map the flash memory, and this
1173 ** must happen after the MAC is
1174 ** identified
1175 */
1176 if ((hw->mac.type == e1000_ich8lan) ||
1177 (hw->mac.type == e1000_ich9lan) ||
1178 (hw->mac.type == e1000_ich10lan) ||
1179 (hw->mac.type == e1000_pchlan) ||
1180 (hw->mac.type == e1000_pch2lan) ||
1181 (hw->mac.type == e1000_pch_lpt)) {
1182 int rid = EM_BAR_TYPE_FLASH;
1183 sc->flash = bus_alloc_resource_any(dev,
1184 SYS_RES_MEMORY, &rid, RF_ACTIVE);
1185 if (sc->flash == NULL) {
1186 device_printf(dev, "Mapping of Flash failed\n");
1187 error = ENXIO;
1188 goto err_pci;
1189 }
1190 /* This is used in the shared code */
1191 hw->flash_address = (u8 *)sc->flash;
1192 sc->osdep.flash_bus_space_tag =
1193 rman_get_bustag(sc->flash);
1194 sc->osdep.flash_bus_space_handle =
1195 rman_get_bushandle(sc->flash);
1196 }
1197 /*
1198 ** In the new SPT device flash is not a
1199 ** separate BAR, rather it is also in BAR0,
1200 ** so use the same tag and an offset handle for the
1201 ** FLASH read/write macros in the shared code.
1202 */
1203 else if (hw->mac.type >= e1000_pch_spt) {
1204 sc->osdep.flash_bus_space_tag = sc->osdep.mem_bus_space_tag;
1205 sc->osdep.flash_bus_space_handle =
1206 sc->osdep.mem_bus_space_handle + E1000_FLASH_BASE_ADDR;
1207 }
1208
1209 /* Do Shared Code initialization */
1210 error = e1000_setup_init_funcs(hw, true);
1211 if (error) {
1212 device_printf(dev, "Setup of Shared code failed, error %d\n",
1213 error);
1214 error = ENXIO;
1215 goto err_pci;
1216 }
1217
1218 em_setup_msix(ctx);
1219 e1000_get_bus_info(hw);
1220
1221 /* Set up some sysctls for the tunable interrupt delays */
1222 if (hw->mac.type < igb_mac_min) {
1223 em_add_int_delay_sysctl(sc, "rx_int_delay",
1224 "receive interrupt delay in usecs", &sc->rx_int_delay,
1225 E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt);
1226 em_add_int_delay_sysctl(sc, "tx_int_delay",
1227 "transmit interrupt delay in usecs", &sc->tx_int_delay,
1228 E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt);
1229 }
1230 if (hw->mac.type >= e1000_82540 && hw->mac.type < igb_mac_min) {
1231 em_add_int_delay_sysctl(sc, "rx_abs_int_delay",
1232 "receive interrupt delay limit in usecs",
1233 &sc->rx_abs_int_delay,
1234 E1000_REGISTER(hw, E1000_RADV), em_rx_abs_int_delay_dflt);
1235 em_add_int_delay_sysctl(sc, "tx_abs_int_delay",
1236 "transmit interrupt delay limit in usecs",
1237 &sc->tx_abs_int_delay,
1238 E1000_REGISTER(hw, E1000_TADV), em_tx_abs_int_delay_dflt);
1239 }
1240
1241 hw->mac.autoneg = DO_AUTO_NEG;
1242 hw->phy.autoneg_wait_to_complete = false;
1243 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1244
1245 if (hw->mac.type < em_mac_min) {
1246 e1000_init_script_state_82541(hw, true);
1247 e1000_set_tbi_compatibility_82543(hw, true);
1248 }
1249 /* Copper options */
1250 if (hw->phy.media_type == e1000_media_type_copper) {
1251 hw->phy.mdix = AUTO_ALL_MODES;
1252 hw->phy.disable_polarity_correction = false;
1253 hw->phy.ms_type = EM_MASTER_SLAVE;
1254 }
1255
1256 /*
1257 * Set the frame limits assuming
1258 * standard ethernet sized frames.
1259 */
1260 scctx->isc_max_frame_size = hw->mac.max_frame_size =
1261 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE;
1262
1263 /*
1264 * This controls when hardware reports transmit completion
1265 * status.
1266 */
1267 hw->mac.report_tx_early = 1;
1268
1269 /* Allocate multicast array memory. */
1270 sc->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN *
1271 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT);
1272 if (sc->mta == NULL) {
1273 device_printf(dev,
1274 "Can not allocate multicast setup array\n");
1275 error = ENOMEM;
1276 goto err_late;
1277 }
1278
1279 /* Clear the IFCAP_TSO auto mask */
1280 sc->tso_automasked = 0;
1281
1282 /* Check SOL/IDER usage */
1283 if (e1000_check_reset_block(hw))
1284 device_printf(dev,
1285 "PHY reset is blocked due to SOL/IDER session.\n");
1286
1287 /* Sysctl for setting Energy Efficient Ethernet */
1288 if (hw->mac.type < igb_mac_min)
1289 hw->dev_spec.ich8lan.eee_disable = eee_setting;
1290 else
1291 hw->dev_spec._82575.eee_disable = eee_setting;
1292 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "eee_control",
1293 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
1294 em_sysctl_eee, "I", "Disable Energy Efficient Ethernet");
1295
1296 /*
1297 ** Start from a known state, this is
1298 ** important in reading the nvm and
1299 ** mac from that.
1300 */
1301 e1000_reset_hw(hw);
1302
1303 /* Make sure we have a good EEPROM before we read from it */
1304 if (e1000_validate_nvm_checksum(hw) < 0) {
1305 /*
1306 ** Some PCI-E parts fail the first check due to
1307 ** the link being in sleep state, call it again,
1308 ** if it fails a second time its a real issue.
1309 */
1310 if (e1000_validate_nvm_checksum(hw) < 0) {
1311 device_printf(dev,
1312 "The EEPROM Checksum Is Not Valid\n");
1313 error = EIO;
1314 goto err_late;
1315 }
1316 }
1317
1318 /* Copy the permanent MAC address out of the EEPROM */
1319 if (e1000_read_mac_addr(hw) < 0) {
1320 device_printf(dev,
1321 "EEPROM read error while reading MAC address\n");
1322 error = EIO;
1323 goto err_late;
1324 }
1325
1326 if (!em_is_valid_ether_addr(hw->mac.addr)) {
1327 if (sc->vf_ifp) {
1328 ether_gen_addr(iflib_get_ifp(ctx),
1329 (struct ether_addr *)hw->mac.addr);
1330 } else {
1331 device_printf(dev, "Invalid MAC address\n");
1332 error = EIO;
1333 goto err_late;
1334 }
1335 }
1336
1337 /* Save the EEPROM/NVM versions, must be done under IFLIB_CTX_LOCK */
1338 em_fw_version_locked(ctx);
1339
1340 em_print_fw_version(sc);
1341
1342 /*
1343 * Get Wake-on-Lan and Management info for later use
1344 */
1345 em_get_wakeup(ctx);
1346
1347 /* Enable only WOL MAGIC by default */
1348 scctx->isc_capenable &= ~IFCAP_WOL;
1349 if (sc->wol != 0)
1350 scctx->isc_capenable |= IFCAP_WOL_MAGIC;
1351
1352 iflib_set_mac(ctx, hw->mac.addr);
1353
1354 return (0);
1355
1356 err_late:
1357 em_release_hw_control(sc);
1358 err_pci:
1359 em_free_pci_resources(ctx);
1360 free(sc->mta, M_DEVBUF);
1361
1362 return (error);
1363 }
1364
1365 static int
em_if_attach_post(if_ctx_t ctx)1366 em_if_attach_post(if_ctx_t ctx)
1367 {
1368 struct e1000_softc *sc = iflib_get_softc(ctx);
1369 struct e1000_hw *hw = &sc->hw;
1370 int error = 0;
1371
1372 /* Setup OS specific network interface */
1373 error = em_setup_interface(ctx);
1374 if (error != 0) {
1375 device_printf(sc->dev, "Interface setup failed: %d\n", error);
1376 goto err_late;
1377 }
1378
1379 em_reset(ctx);
1380
1381 /* Initialize statistics */
1382 em_update_stats_counters(sc);
1383 hw->mac.get_link_status = 1;
1384 em_if_update_admin_status(ctx);
1385 em_add_hw_stats(sc);
1386
1387 /* Non-AMT based hardware can now take control from firmware */
1388 if (sc->has_manage && !sc->has_amt)
1389 em_get_hw_control(sc);
1390
1391 INIT_DEBUGOUT("em_if_attach_post: end");
1392
1393 return (0);
1394
1395 err_late:
1396 /*
1397 * Upon em_if_attach_post() error, iflib calls em_if_detach() to
1398 * free resources
1399 */
1400 return (error);
1401 }
1402
1403 /*********************************************************************
1404 * Device removal routine
1405 *
1406 * The detach entry point is called when the driver is being removed.
1407 * This routine stops the adapter and deallocates all the resources
1408 * that were allocated for driver operation.
1409 *
1410 * return 0 on success, positive on failure
1411 *********************************************************************/
1412 static int
em_if_detach(if_ctx_t ctx)1413 em_if_detach(if_ctx_t ctx)
1414 {
1415 struct e1000_softc *sc = iflib_get_softc(ctx);
1416
1417 INIT_DEBUGOUT("em_if_detach: begin");
1418
1419 e1000_phy_hw_reset(&sc->hw);
1420
1421 em_release_manageability(sc);
1422 em_release_hw_control(sc);
1423 em_free_pci_resources(ctx);
1424 free(sc->mta, M_DEVBUF);
1425 sc->mta = NULL;
1426
1427 return (0);
1428 }
1429
1430 /*********************************************************************
1431 *
1432 * Shutdown entry point
1433 *
1434 **********************************************************************/
1435
1436 static int
em_if_shutdown(if_ctx_t ctx)1437 em_if_shutdown(if_ctx_t ctx)
1438 {
1439 return em_if_suspend(ctx);
1440 }
1441
1442 /*
1443 * Suspend/resume device methods.
1444 */
1445 static int
em_if_suspend(if_ctx_t ctx)1446 em_if_suspend(if_ctx_t ctx)
1447 {
1448 struct e1000_softc *sc = iflib_get_softc(ctx);
1449
1450 em_release_manageability(sc);
1451 em_release_hw_control(sc);
1452 em_enable_wakeup(ctx);
1453 return (0);
1454 }
1455
1456 static int
em_if_resume(if_ctx_t ctx)1457 em_if_resume(if_ctx_t ctx)
1458 {
1459 struct e1000_softc *sc = iflib_get_softc(ctx);
1460
1461 if (sc->hw.mac.type == e1000_pch2lan)
1462 e1000_resume_workarounds_pchlan(&sc->hw);
1463 em_if_init(ctx);
1464 em_init_manageability(sc);
1465
1466 return(0);
1467 }
1468
1469 static int
em_if_mtu_set(if_ctx_t ctx,uint32_t mtu)1470 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu)
1471 {
1472 int max_frame_size;
1473 struct e1000_softc *sc = iflib_get_softc(ctx);
1474 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx);
1475
1476 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)");
1477
1478 switch (sc->hw.mac.type) {
1479 case e1000_82571:
1480 case e1000_82572:
1481 case e1000_ich9lan:
1482 case e1000_ich10lan:
1483 case e1000_pch2lan:
1484 case e1000_pch_lpt:
1485 case e1000_pch_spt:
1486 case e1000_pch_cnp:
1487 case e1000_pch_tgp:
1488 case e1000_pch_adp:
1489 case e1000_pch_mtp:
1490 case e1000_pch_ptp:
1491 case e1000_82574:
1492 case e1000_82583:
1493 case e1000_80003es2lan:
1494 /* 9K Jumbo Frame size */
1495 max_frame_size = 9234;
1496 break;
1497 case e1000_pchlan:
1498 max_frame_size = 4096;
1499 break;
1500 case e1000_82542:
1501 case e1000_ich8lan:
1502 /* Adapters that do not support jumbo frames */
1503 max_frame_size = ETHER_MAX_LEN;
1504 break;
1505 default:
1506 if (sc->hw.mac.type >= igb_mac_min)
1507 max_frame_size = 9234;
1508 else /* lem */
1509 max_frame_size = MAX_JUMBO_FRAME_SIZE;
1510 }
1511 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) {
1512 return (EINVAL);
1513 }
1514
1515 scctx->isc_max_frame_size = sc->hw.mac.max_frame_size =
1516 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
1517 return (0);
1518 }
1519
1520 /*********************************************************************
1521 * Init entry point
1522 *
1523 * This routine is used in two ways. It is used by the stack as
1524 * init entry point in network interface structure. It is also used
1525 * by the driver as a hw/sw initialization routine to get to a
1526 * consistent state.
1527 *
1528 **********************************************************************/
1529 static void
em_if_init(if_ctx_t ctx)1530 em_if_init(if_ctx_t ctx)
1531 {
1532 struct e1000_softc *sc = iflib_get_softc(ctx);
1533 if_softc_ctx_t scctx = sc->shared;
1534 struct ifnet *ifp = iflib_get_ifp(ctx);
1535 struct em_tx_queue *tx_que;
1536 int i;
1537
1538 INIT_DEBUGOUT("em_if_init: begin");
1539
1540 /* Get the latest mac address, User can use a LAA */
1541 bcopy(if_getlladdr(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
1542
1543 /* Put the address into the Receive Address Array */
1544 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1545
1546 /*
1547 * With the 82571 adapter, RAR[0] may be overwritten
1548 * when the other port is reset, we make a duplicate
1549 * in RAR[14] for that eventuality, this assures
1550 * the interface continues to function.
1551 */
1552 if (sc->hw.mac.type == e1000_82571) {
1553 e1000_set_laa_state_82571(&sc->hw, true);
1554 e1000_rar_set(&sc->hw, sc->hw.mac.addr,
1555 E1000_RAR_ENTRIES - 1);
1556 }
1557
1558 /* Initialize the hardware */
1559 em_reset(ctx);
1560 em_if_update_admin_status(ctx);
1561
1562 for (i = 0, tx_que = sc->tx_queues; i < sc->tx_num_queues;
1563 i++, tx_que++) {
1564 struct tx_ring *txr = &tx_que->txr;
1565
1566 txr->tx_rs_cidx = txr->tx_rs_pidx;
1567
1568 /* Initialize the last processed descriptor to be the end of
1569 * the ring, rather than the start, so that we avoid an
1570 * off-by-one error when calculating how many descriptors are
1571 * done in the credits_update function.
1572 */
1573 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1;
1574 }
1575
1576 /* Setup VLAN support, basic and offload if available */
1577 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1578
1579 /* Clear bad data from Rx FIFOs */
1580 if (sc->hw.mac.type >= igb_mac_min)
1581 e1000_rx_fifo_flush_base(&sc->hw);
1582
1583 /* Configure for OS presence */
1584 em_init_manageability(sc);
1585
1586 /* Prepare transmit descriptors and buffers */
1587 em_initialize_transmit_unit(ctx);
1588
1589 /* Setup Multicast table */
1590 em_if_multi_set(ctx);
1591
1592 sc->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx);
1593 em_initialize_receive_unit(ctx);
1594
1595 /* Set up VLAN support and filter */
1596 em_setup_vlan_hw_support(ctx);
1597
1598 /* Don't lose promiscuous settings */
1599 em_if_set_promisc(ctx, if_getflags(ifp));
1600 e1000_clear_hw_cntrs_base_generic(&sc->hw);
1601
1602 /* MSI-X configuration for 82574 */
1603 if (sc->hw.mac.type == e1000_82574) {
1604 int tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
1605
1606 tmp |= E1000_CTRL_EXT_PBA_CLR;
1607 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp);
1608 /* Set the IVAR - interrupt vector routing. */
1609 E1000_WRITE_REG(&sc->hw, E1000_IVAR, sc->ivars);
1610 } else if (sc->intr_type == IFLIB_INTR_MSIX) {
1611 /* Set up queue routing */
1612 igb_configure_queues(sc);
1613 }
1614
1615 /* this clears any pending interrupts */
1616 E1000_READ_REG(&sc->hw, E1000_ICR);
1617 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC);
1618
1619 /* AMT based hardware can now take control from firmware */
1620 if (sc->has_manage && sc->has_amt)
1621 em_get_hw_control(sc);
1622
1623 /* Set Energy Efficient Ethernet */
1624 if (sc->hw.mac.type >= igb_mac_min &&
1625 sc->hw.phy.media_type == e1000_media_type_copper) {
1626 if (sc->hw.mac.type == e1000_i354)
1627 e1000_set_eee_i354(&sc->hw, true, true);
1628 else
1629 e1000_set_eee_i350(&sc->hw, true, true);
1630 }
1631 }
1632
1633 enum itr_latency_target {
1634 itr_latency_disabled = 0,
1635 itr_latency_lowest = 1,
1636 itr_latency_low = 2,
1637 itr_latency_bulk = 3
1638 };
1639 /*********************************************************************
1640 *
1641 * Helper to calculate next (E)ITR value for AIM
1642 *
1643 *********************************************************************/
1644 static void
em_newitr(struct e1000_softc * sc,struct em_rx_queue * que,struct tx_ring * txr,struct rx_ring * rxr)1645 em_newitr(struct e1000_softc *sc, struct em_rx_queue *que,
1646 struct tx_ring *txr, struct rx_ring *rxr)
1647 {
1648 struct e1000_hw *hw = &sc->hw;
1649 u32 newitr;
1650 u32 bytes;
1651 u32 bytes_packets;
1652 u32 packets;
1653 u8 nextlatency;
1654
1655 /* Idle, do nothing */
1656 if ((txr->tx_bytes == 0) && (rxr->rx_bytes == 0))
1657 return;
1658
1659 newitr = 0;
1660
1661 if (sc->enable_aim) {
1662 nextlatency = rxr->rx_nextlatency;
1663
1664 /* Use half default (4K) ITR if sub-gig */
1665 if (sc->link_speed != 1000) {
1666 newitr = EM_INTS_4K;
1667 goto em_set_next_itr;
1668 }
1669 /* Want at least enough packet buffer for two frames to AIM */
1670 if (sc->shared->isc_max_frame_size * 2 > (sc->pba << 10)) {
1671 newitr = em_max_interrupt_rate;
1672 sc->enable_aim = 0;
1673 goto em_set_next_itr;
1674 }
1675
1676 /* Get largest values from the associated tx and rx ring */
1677 if (txr->tx_bytes && txr->tx_packets) {
1678 bytes = txr->tx_bytes;
1679 bytes_packets = txr->tx_bytes/txr->tx_packets;
1680 packets = txr->tx_packets;
1681 }
1682 if (rxr->rx_bytes && rxr->rx_packets) {
1683 bytes = max(bytes, rxr->rx_bytes);
1684 bytes_packets =
1685 max(bytes_packets, rxr->rx_bytes/rxr->rx_packets);
1686 packets = max(packets, rxr->rx_packets);
1687 }
1688
1689 /* Latency state machine */
1690 switch (nextlatency) {
1691 case itr_latency_disabled: /* Bootstrapping */
1692 nextlatency = itr_latency_low;
1693 break;
1694 case itr_latency_lowest: /* 70k ints/s */
1695 /* TSO and jumbo frames */
1696 if (bytes_packets > 8000)
1697 nextlatency = itr_latency_bulk;
1698 else if ((packets < 5) && (bytes > 512))
1699 nextlatency = itr_latency_low;
1700 break;
1701 case itr_latency_low: /* 20k ints/s */
1702 if (bytes > 10000) {
1703 /* Handle TSO */
1704 if (bytes_packets > 8000)
1705 nextlatency = itr_latency_bulk;
1706 else if ((packets < 10) ||
1707 (bytes_packets > 1200))
1708 nextlatency = itr_latency_bulk;
1709 else if (packets > 35)
1710 nextlatency = itr_latency_lowest;
1711 } else if (bytes_packets > 2000) {
1712 nextlatency = itr_latency_bulk;
1713 } else if (packets < 3 && bytes < 512) {
1714 nextlatency = itr_latency_lowest;
1715 }
1716 break;
1717 case itr_latency_bulk: /* 4k ints/s */
1718 if (bytes > 25000) {
1719 if (packets > 35)
1720 nextlatency = itr_latency_low;
1721 } else if (bytes < 1500)
1722 nextlatency = itr_latency_low;
1723 break;
1724 default:
1725 nextlatency = itr_latency_low;
1726 device_printf(sc->dev,
1727 "Unexpected newitr transition %d\n", nextlatency);
1728 break;
1729 }
1730
1731 /* Trim itr_latency_lowest for default AIM setting */
1732 if (sc->enable_aim == 1 && nextlatency == itr_latency_lowest)
1733 nextlatency = itr_latency_low;
1734
1735 /* Request new latency */
1736 rxr->rx_nextlatency = nextlatency;
1737 } else {
1738 /* We may have toggled to AIM disabled */
1739 nextlatency = itr_latency_disabled;
1740 rxr->rx_nextlatency = nextlatency;
1741 }
1742
1743 /* ITR state machine */
1744 switch(nextlatency) {
1745 case itr_latency_lowest:
1746 newitr = EM_INTS_70K;
1747 break;
1748 case itr_latency_low:
1749 newitr = EM_INTS_20K;
1750 break;
1751 case itr_latency_bulk:
1752 newitr = EM_INTS_4K;
1753 break;
1754 case itr_latency_disabled:
1755 default:
1756 newitr = em_max_interrupt_rate;
1757 break;
1758 }
1759
1760 em_set_next_itr:
1761 if (hw->mac.type >= igb_mac_min) {
1762 newitr = IGB_INTS_TO_EITR(newitr);
1763
1764 if (hw->mac.type == e1000_82575)
1765 newitr |= newitr << 16;
1766 else
1767 newitr |= E1000_EITR_CNT_IGNR;
1768
1769 if (newitr != que->itr_setting) {
1770 que->itr_setting = newitr;
1771 E1000_WRITE_REG(hw, E1000_EITR(que->msix),
1772 que->itr_setting);
1773 }
1774 } else {
1775 newitr = EM_INTS_TO_ITR(newitr);
1776
1777 if (newitr != que->itr_setting) {
1778 que->itr_setting = newitr;
1779 if (hw->mac.type == e1000_82574 && que->msix) {
1780 E1000_WRITE_REG(hw,
1781 E1000_EITR_82574(que->msix),
1782 que->itr_setting);
1783 } else {
1784 E1000_WRITE_REG(hw, E1000_ITR,
1785 que->itr_setting);
1786 }
1787 }
1788 }
1789 }
1790
1791 /*********************************************************************
1792 *
1793 * Fast Legacy/MSI Combined Interrupt Service routine
1794 *
1795 *********************************************************************/
1796 int
em_intr(void * arg)1797 em_intr(void *arg)
1798 {
1799 struct e1000_softc *sc = arg;
1800 struct e1000_hw *hw = &sc->hw;
1801 struct em_rx_queue *que = &sc->rx_queues[0];
1802 struct tx_ring *txr = &sc->tx_queues[0].txr;
1803 struct rx_ring *rxr = &que->rxr;
1804 if_ctx_t ctx = sc->ctx;
1805 u32 reg_icr;
1806
1807 reg_icr = E1000_READ_REG(hw, E1000_ICR);
1808
1809 /* Hot eject? */
1810 if (reg_icr == 0xffffffff)
1811 return FILTER_STRAY;
1812
1813 /* Definitely not our interrupt. */
1814 if (reg_icr == 0x0)
1815 return FILTER_STRAY;
1816
1817 /*
1818 * Starting with the 82571 chip, bit 31 should be used to
1819 * determine whether the interrupt belongs to us.
1820 */
1821 if (hw->mac.type >= e1000_82571 &&
1822 (reg_icr & E1000_ICR_INT_ASSERTED) == 0)
1823 return FILTER_STRAY;
1824
1825 /*
1826 * Only MSI-X interrupts have one-shot behavior by taking advantage
1827 * of the EIAC register. Thus, explicitly disable interrupts. This
1828 * also works around the MSI message reordering errata on certain
1829 * systems.
1830 */
1831 IFDI_INTR_DISABLE(ctx);
1832
1833 /* Link status change */
1834 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))
1835 em_handle_link(ctx);
1836
1837 if (reg_icr & E1000_ICR_RXO)
1838 sc->rx_overruns++;
1839
1840 if (hw->mac.type >= e1000_82540)
1841 em_newitr(sc, que, txr, rxr);
1842
1843 /* Reset state */
1844 txr->tx_bytes = 0;
1845 txr->tx_packets = 0;
1846 rxr->rx_bytes = 0;
1847 rxr->rx_packets = 0;
1848
1849 return (FILTER_SCHEDULE_THREAD);
1850 }
1851
1852 static int
em_if_rx_queue_intr_enable(if_ctx_t ctx,uint16_t rxqid)1853 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid)
1854 {
1855 struct e1000_softc *sc = iflib_get_softc(ctx);
1856 struct em_rx_queue *rxq = &sc->rx_queues[rxqid];
1857
1858 E1000_WRITE_REG(&sc->hw, E1000_IMS, rxq->eims);
1859 return (0);
1860 }
1861
1862 static int
em_if_tx_queue_intr_enable(if_ctx_t ctx,uint16_t txqid)1863 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid)
1864 {
1865 struct e1000_softc *sc = iflib_get_softc(ctx);
1866 struct em_tx_queue *txq = &sc->tx_queues[txqid];
1867
1868 E1000_WRITE_REG(&sc->hw, E1000_IMS, txq->eims);
1869 return (0);
1870 }
1871
1872 static int
igb_if_rx_queue_intr_enable(if_ctx_t ctx,uint16_t rxqid)1873 igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid)
1874 {
1875 struct e1000_softc *sc = iflib_get_softc(ctx);
1876 struct em_rx_queue *rxq = &sc->rx_queues[rxqid];
1877
1878 E1000_WRITE_REG(&sc->hw, E1000_EIMS, rxq->eims);
1879 return (0);
1880 }
1881
1882 static int
igb_if_tx_queue_intr_enable(if_ctx_t ctx,uint16_t txqid)1883 igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid)
1884 {
1885 struct e1000_softc *sc = iflib_get_softc(ctx);
1886 struct em_tx_queue *txq = &sc->tx_queues[txqid];
1887
1888 E1000_WRITE_REG(&sc->hw, E1000_EIMS, txq->eims);
1889 return (0);
1890 }
1891
1892 /*********************************************************************
1893 *
1894 * MSI-X RX Interrupt Service routine
1895 *
1896 **********************************************************************/
1897 static int
em_msix_que(void * arg)1898 em_msix_que(void *arg)
1899 {
1900 struct em_rx_queue *que = arg;
1901 struct e1000_softc *sc = que->sc;
1902 struct tx_ring *txr = &sc->tx_queues[que->msix].txr;
1903 struct rx_ring *rxr = &que->rxr;
1904
1905 ++que->irqs;
1906
1907 em_newitr(sc, que, txr, rxr);
1908
1909 /* Reset state */
1910 txr->tx_bytes = 0;
1911 txr->tx_packets = 0;
1912 rxr->rx_bytes = 0;
1913 rxr->rx_packets = 0;
1914
1915 return (FILTER_SCHEDULE_THREAD);
1916 }
1917
1918 /*********************************************************************
1919 *
1920 * MSI-X Link Fast Interrupt Service routine
1921 *
1922 **********************************************************************/
1923 static int
em_msix_link(void * arg)1924 em_msix_link(void *arg)
1925 {
1926 struct e1000_softc *sc = arg;
1927 u32 reg_icr;
1928
1929 ++sc->link_irq;
1930 MPASS(sc->hw.back != NULL);
1931 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
1932
1933 if (reg_icr & E1000_ICR_RXO)
1934 sc->rx_overruns++;
1935
1936 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))
1937 em_handle_link(sc->ctx);
1938
1939 /* Re-arm unconditionally */
1940 if (sc->hw.mac.type >= igb_mac_min) {
1941 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC);
1942 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->link_mask);
1943 } else if (sc->hw.mac.type == e1000_82574) {
1944 E1000_WRITE_REG(&sc->hw, E1000_IMS,
1945 E1000_IMS_LSC | E1000_IMS_OTHER);
1946 /*
1947 * Because we must read the ICR for this interrupt it may
1948 * clear other causes using autoclear, for this reason we
1949 * simply create a soft interrupt for all these vectors.
1950 */
1951 if (reg_icr)
1952 E1000_WRITE_REG(&sc->hw, E1000_ICS, sc->ims);
1953 } else
1954 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC);
1955
1956 return (FILTER_HANDLED);
1957 }
1958
1959 static void
em_handle_link(void * context)1960 em_handle_link(void *context)
1961 {
1962 if_ctx_t ctx = context;
1963 struct e1000_softc *sc = iflib_get_softc(ctx);
1964
1965 sc->hw.mac.get_link_status = 1;
1966 iflib_admin_intr_deferred(ctx);
1967 }
1968
1969 /*********************************************************************
1970 *
1971 * Media Ioctl callback
1972 *
1973 * This routine is called whenever the user queries the status of
1974 * the interface using ifconfig.
1975 *
1976 **********************************************************************/
1977 static void
em_if_media_status(if_ctx_t ctx,struct ifmediareq * ifmr)1978 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr)
1979 {
1980 struct e1000_softc *sc = iflib_get_softc(ctx);
1981 u_char fiber_type = IFM_1000_SX;
1982
1983 INIT_DEBUGOUT("em_if_media_status: begin");
1984
1985 iflib_admin_intr_deferred(ctx);
1986
1987 ifmr->ifm_status = IFM_AVALID;
1988 ifmr->ifm_active = IFM_ETHER;
1989
1990 if (!sc->link_active) {
1991 return;
1992 }
1993
1994 ifmr->ifm_status |= IFM_ACTIVE;
1995
1996 if ((sc->hw.phy.media_type == e1000_media_type_fiber) ||
1997 (sc->hw.phy.media_type == e1000_media_type_internal_serdes)) {
1998 if (sc->hw.mac.type == e1000_82545)
1999 fiber_type = IFM_1000_LX;
2000 switch (sc->link_speed) {
2001 case 10:
2002 ifmr->ifm_active |= IFM_10_FL;
2003 break;
2004 case 100:
2005 ifmr->ifm_active |= IFM_100_FX;
2006 break;
2007 case 1000:
2008 default:
2009 ifmr->ifm_active |= fiber_type | IFM_FDX;
2010 break;
2011 }
2012 } else {
2013 switch (sc->link_speed) {
2014 case 10:
2015 ifmr->ifm_active |= IFM_10_T;
2016 break;
2017 case 100:
2018 ifmr->ifm_active |= IFM_100_TX;
2019 break;
2020 case 1000:
2021 ifmr->ifm_active |= IFM_1000_T;
2022 break;
2023 }
2024 }
2025
2026 if (sc->link_duplex == FULL_DUPLEX)
2027 ifmr->ifm_active |= IFM_FDX;
2028 else
2029 ifmr->ifm_active |= IFM_HDX;
2030 }
2031
2032 /*********************************************************************
2033 *
2034 * Media Ioctl callback
2035 *
2036 * This routine is called when the user changes speed/duplex using
2037 * media/mediopt option with ifconfig.
2038 *
2039 **********************************************************************/
2040 static int
em_if_media_change(if_ctx_t ctx)2041 em_if_media_change(if_ctx_t ctx)
2042 {
2043 struct e1000_softc *sc = iflib_get_softc(ctx);
2044 struct ifmedia *ifm = iflib_get_media(ctx);
2045
2046 INIT_DEBUGOUT("em_if_media_change: begin");
2047
2048 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2049 return (EINVAL);
2050
2051 switch (IFM_SUBTYPE(ifm->ifm_media)) {
2052 case IFM_AUTO:
2053 sc->hw.mac.autoneg = DO_AUTO_NEG;
2054 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
2055 break;
2056 case IFM_1000_LX:
2057 case IFM_1000_SX:
2058 case IFM_1000_T:
2059 sc->hw.mac.autoneg = DO_AUTO_NEG;
2060 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
2061 break;
2062 case IFM_100_TX:
2063 sc->hw.mac.autoneg = DO_AUTO_NEG;
2064 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2065 sc->hw.phy.autoneg_advertised = ADVERTISE_100_FULL;
2066 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
2067 } else {
2068 sc->hw.phy.autoneg_advertised = ADVERTISE_100_HALF;
2069 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
2070 }
2071 break;
2072 case IFM_10_T:
2073 sc->hw.mac.autoneg = DO_AUTO_NEG;
2074 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2075 sc->hw.phy.autoneg_advertised = ADVERTISE_10_FULL;
2076 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
2077 } else {
2078 sc->hw.phy.autoneg_advertised = ADVERTISE_10_HALF;
2079 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
2080 }
2081 break;
2082 case IFM_100_FX:
2083 sc->hw.mac.autoneg = false;
2084 sc->hw.phy.autoneg_advertised = 0;
2085 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
2086 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
2087 else
2088 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
2089 break;
2090 case IFM_10_FL:
2091 sc->hw.mac.autoneg = false;
2092 sc->hw.phy.autoneg_advertised = 0;
2093 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
2094 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
2095 else
2096 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
2097 break;
2098 default:
2099 device_printf(sc->dev, "Unsupported media type\n");
2100 }
2101
2102 em_if_init(ctx);
2103
2104 return (0);
2105 }
2106
2107 static int
em_if_set_promisc(if_ctx_t ctx,int flags)2108 em_if_set_promisc(if_ctx_t ctx, int flags)
2109 {
2110 struct e1000_softc *sc = iflib_get_softc(ctx);
2111 struct ifnet *ifp = iflib_get_ifp(ctx);
2112 u32 reg_rctl;
2113 int mcnt = 0;
2114
2115 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
2116 reg_rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_UPE);
2117 if (flags & IFF_ALLMULTI)
2118 mcnt = MAX_NUM_MULTICAST_ADDRESSES;
2119 else
2120 mcnt = min(if_llmaddr_count(ifp),
2121 MAX_NUM_MULTICAST_ADDRESSES);
2122
2123 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES)
2124 reg_rctl &= (~E1000_RCTL_MPE);
2125 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
2126
2127 if (flags & IFF_PROMISC) {
2128 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2129 em_if_vlan_filter_disable(sc);
2130 /* Turn this on if you want to see bad packets */
2131 if (em_debug_sbp)
2132 reg_rctl |= E1000_RCTL_SBP;
2133 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
2134 } else {
2135 if (flags & IFF_ALLMULTI) {
2136 reg_rctl |= E1000_RCTL_MPE;
2137 reg_rctl &= ~E1000_RCTL_UPE;
2138 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
2139 }
2140 if (em_if_vlan_filter_used(ctx))
2141 em_if_vlan_filter_enable(sc);
2142 }
2143 return (0);
2144 }
2145
2146 static u_int
em_copy_maddr(void * arg,struct sockaddr_dl * sdl,u_int idx)2147 em_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int idx)
2148 {
2149 u8 *mta = arg;
2150
2151 if (idx == MAX_NUM_MULTICAST_ADDRESSES)
2152 return (0);
2153
2154 bcopy(LLADDR(sdl), &mta[idx * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
2155
2156 return (1);
2157 }
2158
2159 /*********************************************************************
2160 * Multicast Update
2161 *
2162 * This routine is called whenever multicast address list is updated.
2163 *
2164 **********************************************************************/
2165 static void
em_if_multi_set(if_ctx_t ctx)2166 em_if_multi_set(if_ctx_t ctx)
2167 {
2168 struct e1000_softc *sc = iflib_get_softc(ctx);
2169 struct ifnet *ifp = iflib_get_ifp(ctx);
2170 u8 *mta; /* Multicast array memory */
2171 u32 reg_rctl = 0;
2172 int mcnt = 0;
2173
2174 IOCTL_DEBUGOUT("em_set_multi: begin");
2175
2176 mta = sc->mta;
2177 bzero(mta, sizeof(u8) * ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
2178
2179 if (sc->hw.mac.type == e1000_82542 &&
2180 sc->hw.revision_id == E1000_REVISION_2) {
2181 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
2182 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
2183 e1000_pci_clear_mwi(&sc->hw);
2184 reg_rctl |= E1000_RCTL_RST;
2185 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
2186 msec_delay(5);
2187 }
2188
2189 mcnt = if_foreach_llmaddr(ifp, em_copy_maddr, mta);
2190
2191 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES)
2192 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
2193
2194 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
2195
2196 if (if_getflags(ifp) & IFF_PROMISC)
2197 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2198 else if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES ||
2199 if_getflags(ifp) & IFF_ALLMULTI) {
2200 reg_rctl |= E1000_RCTL_MPE;
2201 reg_rctl &= ~E1000_RCTL_UPE;
2202 } else
2203 reg_rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
2204
2205 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
2206
2207 if (sc->hw.mac.type == e1000_82542 &&
2208 sc->hw.revision_id == E1000_REVISION_2) {
2209 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
2210 reg_rctl &= ~E1000_RCTL_RST;
2211 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
2212 msec_delay(5);
2213 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
2214 e1000_pci_set_mwi(&sc->hw);
2215 }
2216 }
2217
2218 /*********************************************************************
2219 * Timer routine
2220 *
2221 * This routine schedules em_if_update_admin_status() to check for
2222 * link status and to gather statistics as well as to perform some
2223 * controller-specific hardware patting.
2224 *
2225 **********************************************************************/
2226 static void
em_if_timer(if_ctx_t ctx,uint16_t qid)2227 em_if_timer(if_ctx_t ctx, uint16_t qid)
2228 {
2229 if (qid != 0)
2230 return;
2231
2232 iflib_admin_intr_deferred(ctx);
2233 }
2234
2235 static void
em_if_update_admin_status(if_ctx_t ctx)2236 em_if_update_admin_status(if_ctx_t ctx)
2237 {
2238 struct e1000_softc *sc = iflib_get_softc(ctx);
2239 struct e1000_hw *hw = &sc->hw;
2240 device_t dev = iflib_get_dev(ctx);
2241 u32 link_check, thstat, ctrl;
2242 bool automasked = false;
2243
2244 link_check = thstat = ctrl = 0;
2245 /* Get the cached link value or read phy for real */
2246 switch (hw->phy.media_type) {
2247 case e1000_media_type_copper:
2248 if (hw->mac.get_link_status) {
2249 if (hw->mac.type == e1000_pch_spt)
2250 msec_delay(50);
2251 /* Do the work to read phy */
2252 e1000_check_for_link(hw);
2253 link_check = !hw->mac.get_link_status;
2254 if (link_check) /* ESB2 fix */
2255 e1000_cfg_on_link_up(hw);
2256 } else {
2257 link_check = true;
2258 }
2259 break;
2260 case e1000_media_type_fiber:
2261 e1000_check_for_link(hw);
2262 link_check =
2263 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU);
2264 break;
2265 case e1000_media_type_internal_serdes:
2266 e1000_check_for_link(hw);
2267 link_check = hw->mac.serdes_has_link;
2268 break;
2269 /* VF device is type_unknown */
2270 case e1000_media_type_unknown:
2271 e1000_check_for_link(hw);
2272 link_check = !hw->mac.get_link_status;
2273 /* FALLTHROUGH */
2274 default:
2275 break;
2276 }
2277
2278 /* Check for thermal downshift or shutdown */
2279 if (hw->mac.type == e1000_i350) {
2280 thstat = E1000_READ_REG(hw, E1000_THSTAT);
2281 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
2282 }
2283
2284 /* Now check for a transition */
2285 if (link_check && (sc->link_active == 0)) {
2286 e1000_get_speed_and_duplex(hw, &sc->link_speed,
2287 &sc->link_duplex);
2288 /* Check if we must disable SPEED_MODE bit on PCI-E */
2289 if ((sc->link_speed != SPEED_1000) &&
2290 ((hw->mac.type == e1000_82571) ||
2291 (hw->mac.type == e1000_82572))) {
2292 int tarc0;
2293 tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
2294 tarc0 &= ~TARC_SPEED_MODE_BIT;
2295 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
2296 }
2297 if (bootverbose)
2298 device_printf(dev, "Link is up %d Mbps %s\n",
2299 sc->link_speed,
2300 ((sc->link_duplex == FULL_DUPLEX) ?
2301 "Full Duplex" : "Half Duplex"));
2302 sc->link_active = 1;
2303 sc->smartspeed = 0;
2304 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) ==
2305 E1000_CTRL_EXT_LINK_MODE_GMII &&
2306 (thstat & E1000_THSTAT_LINK_THROTTLE))
2307 device_printf(dev, "Link: thermal downshift\n");
2308 /* Delay Link Up for Phy update */
2309 if (((hw->mac.type == e1000_i210) ||
2310 (hw->mac.type == e1000_i211)) &&
2311 (hw->phy.id == I210_I_PHY_ID))
2312 msec_delay(I210_LINK_DELAY);
2313 /* Reset if the media type changed. */
2314 if (hw->dev_spec._82575.media_changed &&
2315 hw->mac.type >= igb_mac_min) {
2316 hw->dev_spec._82575.media_changed = false;
2317 sc->flags |= IGB_MEDIA_RESET;
2318 em_reset(ctx);
2319 }
2320 /* Only do TSO on gigabit for older chips due to errata */
2321 if (hw->mac.type < igb_mac_min)
2322 automasked = em_automask_tso(ctx);
2323
2324 /* Automasking resets the interface so don't mark it up yet */
2325 if (!automasked)
2326 iflib_link_state_change(ctx, LINK_STATE_UP,
2327 IF_Mbps(sc->link_speed));
2328 } else if (!link_check && (sc->link_active == 1)) {
2329 sc->link_speed = 0;
2330 sc->link_duplex = 0;
2331 sc->link_active = 0;
2332 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0);
2333 }
2334 em_update_stats_counters(sc);
2335
2336 /* Reset LAA into RAR[0] on 82571 */
2337 if (hw->mac.type == e1000_82571 && e1000_get_laa_state_82571(hw))
2338 e1000_rar_set(hw, hw->mac.addr, 0);
2339
2340 if (hw->mac.type < em_mac_min)
2341 lem_smartspeed(sc);
2342 }
2343
2344 static void
em_if_watchdog_reset(if_ctx_t ctx)2345 em_if_watchdog_reset(if_ctx_t ctx)
2346 {
2347 struct e1000_softc *sc = iflib_get_softc(ctx);
2348
2349 /*
2350 * Just count the event; iflib(4) will already trigger a
2351 * sufficient reset of the controller.
2352 */
2353 sc->watchdog_events++;
2354 }
2355
2356 /*********************************************************************
2357 *
2358 * This routine disables all traffic on the adapter by issuing a
2359 * global reset on the MAC.
2360 *
2361 **********************************************************************/
2362 static void
em_if_stop(if_ctx_t ctx)2363 em_if_stop(if_ctx_t ctx)
2364 {
2365 struct e1000_softc *sc = iflib_get_softc(ctx);
2366
2367 INIT_DEBUGOUT("em_if_stop: begin");
2368
2369 /* I219 needs special flushing to avoid hangs */
2370 if (sc->hw.mac.type >= e1000_pch_spt && sc->hw.mac.type < igb_mac_min)
2371 em_flush_desc_rings(sc);
2372
2373 e1000_reset_hw(&sc->hw);
2374 if (sc->hw.mac.type >= e1000_82544)
2375 E1000_WRITE_REG(&sc->hw, E1000_WUFC, 0);
2376
2377 e1000_led_off(&sc->hw);
2378 e1000_cleanup_led(&sc->hw);
2379 }
2380
2381 /*********************************************************************
2382 *
2383 * Determine hardware revision.
2384 *
2385 **********************************************************************/
2386 static void
em_identify_hardware(if_ctx_t ctx)2387 em_identify_hardware(if_ctx_t ctx)
2388 {
2389 device_t dev = iflib_get_dev(ctx);
2390 struct e1000_softc *sc = iflib_get_softc(ctx);
2391
2392 /* Make sure our PCI config space has the necessary stuff set */
2393 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
2394
2395 /* Save off the information about this board */
2396 sc->hw.vendor_id = pci_get_vendor(dev);
2397 sc->hw.device_id = pci_get_device(dev);
2398 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
2399 sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2);
2400 sc->hw.subsystem_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
2401
2402 /* Do Shared Code Init and Setup */
2403 if (e1000_set_mac_type(&sc->hw)) {
2404 device_printf(dev, "Setup init failure\n");
2405 return;
2406 }
2407
2408 /* Are we a VF device? */
2409 if ((sc->hw.mac.type == e1000_vfadapt) ||
2410 (sc->hw.mac.type == e1000_vfadapt_i350))
2411 sc->vf_ifp = 1;
2412 else
2413 sc->vf_ifp = 0;
2414 }
2415
2416 static int
em_allocate_pci_resources(if_ctx_t ctx)2417 em_allocate_pci_resources(if_ctx_t ctx)
2418 {
2419 struct e1000_softc *sc = iflib_get_softc(ctx);
2420 device_t dev = iflib_get_dev(ctx);
2421 int rid, val;
2422
2423 rid = PCIR_BAR(0);
2424 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
2425 RF_ACTIVE);
2426 if (sc->memory == NULL) {
2427 device_printf(dev,
2428 "Unable to allocate bus resource: memory\n");
2429 return (ENXIO);
2430 }
2431 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory);
2432 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->memory);
2433 sc->hw.hw_addr = (u8 *)&sc->osdep.mem_bus_space_handle;
2434
2435 /* Only older adapters use IO mapping */
2436 if (sc->hw.mac.type < em_mac_min && sc->hw.mac.type > e1000_82543) {
2437 /* Figure our where our IO BAR is ? */
2438 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) {
2439 val = pci_read_config(dev, rid, 4);
2440 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) {
2441 break;
2442 }
2443 rid += 4;
2444 /* check for 64bit BAR */
2445 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT)
2446 rid += 4;
2447 }
2448 if (rid >= PCIR_CIS) {
2449 device_printf(dev, "Unable to locate IO BAR\n");
2450 return (ENXIO);
2451 }
2452 sc->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
2453 &rid, RF_ACTIVE);
2454 if (sc->ioport == NULL) {
2455 device_printf(dev,
2456 "Unable to allocate bus resource: ioport\n");
2457 return (ENXIO);
2458 }
2459 sc->hw.io_base = 0;
2460 sc->osdep.io_bus_space_tag =
2461 rman_get_bustag(sc->ioport);
2462 sc->osdep.io_bus_space_handle =
2463 rman_get_bushandle(sc->ioport);
2464 }
2465
2466 sc->hw.back = &sc->osdep;
2467
2468 return (0);
2469 }
2470
2471 /*********************************************************************
2472 *
2473 * Set up the MSI-X Interrupt handlers
2474 *
2475 **********************************************************************/
2476 static int
em_if_msix_intr_assign(if_ctx_t ctx,int msix)2477 em_if_msix_intr_assign(if_ctx_t ctx, int msix)
2478 {
2479 struct e1000_softc *sc = iflib_get_softc(ctx);
2480 struct em_rx_queue *rx_que = sc->rx_queues;
2481 struct em_tx_queue *tx_que = sc->tx_queues;
2482 int error, rid, i, vector = 0, rx_vectors;
2483 char buf[16];
2484
2485 /* First set up ring resources */
2486 for (i = 0; i < sc->rx_num_queues; i++, rx_que++, vector++) {
2487 rid = vector + 1;
2488 snprintf(buf, sizeof(buf), "rxq%d", i);
2489 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid,
2490 IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf);
2491 if (error) {
2492 device_printf(iflib_get_dev(ctx),
2493 "Failed to allocate que int %d err: %d",
2494 i, error);
2495 sc->rx_num_queues = i + 1;
2496 goto fail;
2497 }
2498
2499 rx_que->msix = vector;
2500
2501 /*
2502 * Set the bit to enable interrupt
2503 * in E1000_IMS -- bits 20 and 21
2504 * are for RX0 and RX1, note this has
2505 * NOTHING to do with the MSI-X vector
2506 */
2507 if (sc->hw.mac.type == e1000_82574) {
2508 rx_que->eims = 1 << (20 + i);
2509 sc->ims |= rx_que->eims;
2510 sc->ivars |= (8 | rx_que->msix) << (i * 4);
2511 } else if (sc->hw.mac.type == e1000_82575)
2512 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector;
2513 else
2514 rx_que->eims = 1 << vector;
2515 }
2516 rx_vectors = vector;
2517
2518 vector = 0;
2519 for (i = 0; i < sc->tx_num_queues; i++, tx_que++, vector++) {
2520 snprintf(buf, sizeof(buf), "txq%d", i);
2521 tx_que = &sc->tx_queues[i];
2522 iflib_softirq_alloc_generic(ctx,
2523 &sc->rx_queues[i % sc->rx_num_queues].que_irq,
2524 IFLIB_INTR_TX, tx_que, tx_que->me, buf);
2525
2526 tx_que->msix = (vector % sc->rx_num_queues);
2527
2528 /*
2529 * Set the bit to enable interrupt
2530 * in E1000_IMS -- bits 22 and 23
2531 * are for TX0 and TX1, note this has
2532 * NOTHING to do with the MSI-X vector
2533 */
2534 if (sc->hw.mac.type == e1000_82574) {
2535 tx_que->eims = 1 << (22 + i);
2536 sc->ims |= tx_que->eims;
2537 sc->ivars |= (8 | tx_que->msix) << (8 + (i * 4));
2538 } else if (sc->hw.mac.type == e1000_82575) {
2539 tx_que->eims = E1000_EICR_TX_QUEUE0 << i;
2540 } else {
2541 tx_que->eims = 1 << i;
2542 }
2543 }
2544
2545 /* Link interrupt */
2546 rid = rx_vectors + 1;
2547 error = iflib_irq_alloc_generic(ctx, &sc->irq, rid, IFLIB_INTR_ADMIN,
2548 em_msix_link, sc, 0, "aq");
2549
2550 if (error) {
2551 device_printf(iflib_get_dev(ctx),
2552 "Failed to register admin handler");
2553 goto fail;
2554 }
2555 sc->linkvec = rx_vectors;
2556 if (sc->hw.mac.type < igb_mac_min) {
2557 sc->ivars |= (8 | rx_vectors) << 16;
2558 sc->ivars |= 0x80000000;
2559 /* Enable the "Other" interrupt type for link status change */
2560 sc->ims |= E1000_IMS_OTHER;
2561 }
2562
2563 return (0);
2564 fail:
2565 iflib_irq_free(ctx, &sc->irq);
2566 rx_que = sc->rx_queues;
2567 for (int i = 0; i < sc->rx_num_queues; i++, rx_que++)
2568 iflib_irq_free(ctx, &rx_que->que_irq);
2569 return (error);
2570 }
2571
2572 static void
igb_configure_queues(struct e1000_softc * sc)2573 igb_configure_queues(struct e1000_softc *sc)
2574 {
2575 struct e1000_hw *hw = &sc->hw;
2576 struct em_rx_queue *rx_que;
2577 struct em_tx_queue *tx_que;
2578 u32 tmp, ivar = 0, newitr = 0;
2579
2580 /* First turn on RSS capability */
2581 if (hw->mac.type != e1000_82575)
2582 E1000_WRITE_REG(hw, E1000_GPIE,
2583 E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME |
2584 E1000_GPIE_PBA | E1000_GPIE_NSICR);
2585
2586 /* Turn on MSI-X */
2587 switch (hw->mac.type) {
2588 case e1000_82580:
2589 case e1000_i350:
2590 case e1000_i354:
2591 case e1000_i210:
2592 case e1000_i211:
2593 case e1000_vfadapt:
2594 case e1000_vfadapt_i350:
2595 /* RX entries */
2596 for (int i = 0; i < sc->rx_num_queues; i++) {
2597 u32 index = i >> 1;
2598 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2599 rx_que = &sc->rx_queues[i];
2600 if (i & 1) {
2601 ivar &= 0xFF00FFFF;
2602 ivar |= (rx_que->msix | E1000_IVAR_VALID) <<
2603 16;
2604 } else {
2605 ivar &= 0xFFFFFF00;
2606 ivar |= rx_que->msix | E1000_IVAR_VALID;
2607 }
2608 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2609 }
2610 /* TX entries */
2611 for (int i = 0; i < sc->tx_num_queues; i++) {
2612 u32 index = i >> 1;
2613 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2614 tx_que = &sc->tx_queues[i];
2615 if (i & 1) {
2616 ivar &= 0x00FFFFFF;
2617 ivar |= (tx_que->msix | E1000_IVAR_VALID) <<
2618 24;
2619 } else {
2620 ivar &= 0xFFFF00FF;
2621 ivar |= (tx_que->msix | E1000_IVAR_VALID) <<
2622 8;
2623 }
2624 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2625 sc->que_mask |= tx_que->eims;
2626 }
2627
2628 /* And for the link interrupt */
2629 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8;
2630 sc->link_mask = 1 << sc->linkvec;
2631 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
2632 break;
2633 case e1000_82576:
2634 /* RX entries */
2635 for (int i = 0; i < sc->rx_num_queues; i++) {
2636 u32 index = i & 0x7; /* Each IVAR has two entries */
2637 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2638 rx_que = &sc->rx_queues[i];
2639 if (i < 8) {
2640 ivar &= 0xFFFFFF00;
2641 ivar |= rx_que->msix | E1000_IVAR_VALID;
2642 } else {
2643 ivar &= 0xFF00FFFF;
2644 ivar |= (rx_que->msix | E1000_IVAR_VALID) <<
2645 16;
2646 }
2647 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2648 sc->que_mask |= rx_que->eims;
2649 }
2650 /* TX entries */
2651 for (int i = 0; i < sc->tx_num_queues; i++) {
2652 u32 index = i & 0x7; /* Each IVAR has two entries */
2653 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2654 tx_que = &sc->tx_queues[i];
2655 if (i < 8) {
2656 ivar &= 0xFFFF00FF;
2657 ivar |= (tx_que->msix | E1000_IVAR_VALID) <<
2658 8;
2659 } else {
2660 ivar &= 0x00FFFFFF;
2661 ivar |= (tx_que->msix | E1000_IVAR_VALID) <<
2662 24;
2663 }
2664 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2665 sc->que_mask |= tx_que->eims;
2666 }
2667
2668 /* And for the link interrupt */
2669 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8;
2670 sc->link_mask = 1 << sc->linkvec;
2671 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
2672 break;
2673
2674 case e1000_82575:
2675 /* enable MSI-X support*/
2676 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
2677 tmp |= E1000_CTRL_EXT_PBA_CLR;
2678 /* Auto-Mask interrupts upon ICR read. */
2679 tmp |= E1000_CTRL_EXT_EIAME;
2680 tmp |= E1000_CTRL_EXT_IRCA;
2681 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
2682
2683 /* Queues */
2684 for (int i = 0; i < sc->rx_num_queues; i++) {
2685 rx_que = &sc->rx_queues[i];
2686 tmp = E1000_EICR_RX_QUEUE0 << i;
2687 tmp |= E1000_EICR_TX_QUEUE0 << i;
2688 rx_que->eims = tmp;
2689 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), i,
2690 rx_que->eims);
2691 sc->que_mask |= rx_que->eims;
2692 }
2693
2694 /* Link */
2695 E1000_WRITE_REG(hw, E1000_MSIXBM(sc->linkvec),
2696 E1000_EIMS_OTHER);
2697 sc->link_mask |= E1000_EIMS_OTHER;
2698 default:
2699 break;
2700 }
2701
2702 /* Set the igb starting interrupt rate */
2703 if (em_max_interrupt_rate > 0) {
2704 newitr = IGB_INTS_TO_EITR(em_max_interrupt_rate);
2705
2706 if (hw->mac.type == e1000_82575)
2707 newitr |= newitr << 16;
2708 else
2709 newitr |= E1000_EITR_CNT_IGNR;
2710
2711 for (int i = 0; i < sc->rx_num_queues; i++) {
2712 rx_que = &sc->rx_queues[i];
2713 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr);
2714 }
2715 }
2716
2717 return;
2718 }
2719
2720 static void
em_free_pci_resources(if_ctx_t ctx)2721 em_free_pci_resources(if_ctx_t ctx)
2722 {
2723 struct e1000_softc *sc = iflib_get_softc(ctx);
2724 struct em_rx_queue *que = sc->rx_queues;
2725 device_t dev = iflib_get_dev(ctx);
2726
2727 /* Release all MSI-X queue resources */
2728 if (sc->intr_type == IFLIB_INTR_MSIX)
2729 iflib_irq_free(ctx, &sc->irq);
2730
2731 if (que != NULL) {
2732 for (int i = 0; i < sc->rx_num_queues; i++, que++) {
2733 iflib_irq_free(ctx, &que->que_irq);
2734 }
2735 }
2736
2737 if (sc->memory != NULL) {
2738 bus_release_resource(dev, SYS_RES_MEMORY,
2739 rman_get_rid(sc->memory), sc->memory);
2740 sc->memory = NULL;
2741 }
2742
2743 if (sc->flash != NULL) {
2744 bus_release_resource(dev, SYS_RES_MEMORY,
2745 rman_get_rid(sc->flash), sc->flash);
2746 sc->flash = NULL;
2747 }
2748
2749 if (sc->ioport != NULL) {
2750 bus_release_resource(dev, SYS_RES_IOPORT,
2751 rman_get_rid(sc->ioport), sc->ioport);
2752 sc->ioport = NULL;
2753 }
2754 }
2755
2756 /* Set up MSI or MSI-X */
2757 static int
em_setup_msix(if_ctx_t ctx)2758 em_setup_msix(if_ctx_t ctx)
2759 {
2760 struct e1000_softc *sc = iflib_get_softc(ctx);
2761
2762 if (sc->hw.mac.type == e1000_82574) {
2763 em_enable_vectors_82574(ctx);
2764 }
2765 return (0);
2766 }
2767
2768 /*********************************************************************
2769 *
2770 * Workaround for SmartSpeed on 82541 and 82547 controllers
2771 *
2772 **********************************************************************/
2773 static void
lem_smartspeed(struct e1000_softc * sc)2774 lem_smartspeed(struct e1000_softc *sc)
2775 {
2776 u16 phy_tmp;
2777
2778 if (sc->link_active || (sc->hw.phy.type != e1000_phy_igp) ||
2779 sc->hw.mac.autoneg == 0 ||
2780 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
2781 return;
2782
2783 if (sc->smartspeed == 0) {
2784 /* If Master/Slave config fault is asserted twice,
2785 * we assume back-to-back */
2786 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
2787 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
2788 return;
2789 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
2790 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
2791 e1000_read_phy_reg(&sc->hw,
2792 PHY_1000T_CTRL, &phy_tmp);
2793 if(phy_tmp & CR_1000T_MS_ENABLE) {
2794 phy_tmp &= ~CR_1000T_MS_ENABLE;
2795 e1000_write_phy_reg(&sc->hw,
2796 PHY_1000T_CTRL, phy_tmp);
2797 sc->smartspeed++;
2798 if(sc->hw.mac.autoneg &&
2799 !e1000_copper_link_autoneg(&sc->hw) &&
2800 !e1000_read_phy_reg(&sc->hw,
2801 PHY_CONTROL, &phy_tmp)) {
2802 phy_tmp |= (MII_CR_AUTO_NEG_EN |
2803 MII_CR_RESTART_AUTO_NEG);
2804 e1000_write_phy_reg(&sc->hw,
2805 PHY_CONTROL, phy_tmp);
2806 }
2807 }
2808 }
2809 return;
2810 } else if(sc->smartspeed == EM_SMARTSPEED_DOWNSHIFT) {
2811 /* If still no link, perhaps using 2/3 pair cable */
2812 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp);
2813 phy_tmp |= CR_1000T_MS_ENABLE;
2814 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp);
2815 if(sc->hw.mac.autoneg &&
2816 !e1000_copper_link_autoneg(&sc->hw) &&
2817 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) {
2818 phy_tmp |= (MII_CR_AUTO_NEG_EN |
2819 MII_CR_RESTART_AUTO_NEG);
2820 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp);
2821 }
2822 }
2823 /* Restart process after EM_SMARTSPEED_MAX iterations */
2824 if(sc->smartspeed++ == EM_SMARTSPEED_MAX)
2825 sc->smartspeed = 0;
2826 }
2827
2828 /*********************************************************************
2829 *
2830 * Initialize the DMA Coalescing feature
2831 *
2832 **********************************************************************/
2833 static void
igb_init_dmac(struct e1000_softc * sc,u32 pba)2834 igb_init_dmac(struct e1000_softc *sc, u32 pba)
2835 {
2836 device_t dev = sc->dev;
2837 struct e1000_hw *hw = &sc->hw;
2838 u32 dmac, reg = ~E1000_DMACR_DMAC_EN;
2839 u16 hwm;
2840 u16 max_frame_size;
2841
2842 if (hw->mac.type == e1000_i211)
2843 return;
2844
2845 max_frame_size = sc->shared->isc_max_frame_size;
2846 if (hw->mac.type > e1000_82580) {
2847
2848 if (sc->dmac == 0) { /* Disabling it */
2849 E1000_WRITE_REG(hw, E1000_DMACR, reg);
2850 return;
2851 } else
2852 device_printf(dev, "DMA Coalescing enabled\n");
2853
2854 /* Set starting threshold */
2855 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0);
2856
2857 hwm = 64 * pba - max_frame_size / 16;
2858 if (hwm < 64 * (pba - 6))
2859 hwm = 64 * (pba - 6);
2860 reg = E1000_READ_REG(hw, E1000_FCRTC);
2861 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
2862 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
2863 & E1000_FCRTC_RTH_COAL_MASK);
2864 E1000_WRITE_REG(hw, E1000_FCRTC, reg);
2865
2866
2867 dmac = pba - max_frame_size / 512;
2868 if (dmac < pba - 10)
2869 dmac = pba - 10;
2870 reg = E1000_READ_REG(hw, E1000_DMACR);
2871 reg &= ~E1000_DMACR_DMACTHR_MASK;
2872 reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT)
2873 & E1000_DMACR_DMACTHR_MASK);
2874
2875 /* transition to L0x or L1 if available..*/
2876 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
2877
2878 /* Check if status is 2.5Gb backplane connection
2879 * before configuration of watchdog timer, which is
2880 * in msec values in 12.8usec intervals
2881 * watchdog timer= msec values in 32usec intervals
2882 * for non 2.5Gb connection
2883 */
2884 if (hw->mac.type == e1000_i354) {
2885 int status = E1000_READ_REG(hw, E1000_STATUS);
2886 if ((status & E1000_STATUS_2P5_SKU) &&
2887 (!(status & E1000_STATUS_2P5_SKU_OVER)))
2888 reg |= ((sc->dmac * 5) >> 6);
2889 else
2890 reg |= (sc->dmac >> 5);
2891 } else {
2892 reg |= (sc->dmac >> 5);
2893 }
2894
2895 E1000_WRITE_REG(hw, E1000_DMACR, reg);
2896
2897 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
2898
2899 /* Set the interval before transition */
2900 reg = E1000_READ_REG(hw, E1000_DMCTLX);
2901 if (hw->mac.type == e1000_i350)
2902 reg |= IGB_DMCTLX_DCFLUSH_DIS;
2903 /*
2904 ** in 2.5Gb connection, TTLX unit is 0.4 usec
2905 ** which is 0x4*2 = 0xA. But delay is still 4 usec
2906 */
2907 if (hw->mac.type == e1000_i354) {
2908 int status = E1000_READ_REG(hw, E1000_STATUS);
2909 if ((status & E1000_STATUS_2P5_SKU) &&
2910 (!(status & E1000_STATUS_2P5_SKU_OVER)))
2911 reg |= 0xA;
2912 else
2913 reg |= 0x4;
2914 } else {
2915 reg |= 0x4;
2916 }
2917
2918 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
2919
2920 /* free space in tx packet buffer to wake from DMA coal */
2921 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE -
2922 (2 * max_frame_size)) >> 6);
2923
2924 /* make low power state decision controlled by DMA coal */
2925 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
2926 reg &= ~E1000_PCIEMISC_LX_DECISION;
2927 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg);
2928
2929 } else if (hw->mac.type == e1000_82580) {
2930 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
2931 E1000_WRITE_REG(hw, E1000_PCIEMISC,
2932 reg & ~E1000_PCIEMISC_LX_DECISION);
2933 E1000_WRITE_REG(hw, E1000_DMACR, 0);
2934 }
2935 }
2936 /*********************************************************************
2937 * The 3 following flush routines are used as a workaround in the
2938 * I219 client parts and only for them.
2939 *
2940 * em_flush_tx_ring - remove all descriptors from the tx_ring
2941 *
2942 * We want to clear all pending descriptors from the TX ring.
2943 * zeroing happens when the HW reads the regs. We assign the ring itself as
2944 * the data of the next descriptor. We don't care about the data we are about
2945 * to reset the HW.
2946 **********************************************************************/
2947 static void
em_flush_tx_ring(struct e1000_softc * sc)2948 em_flush_tx_ring(struct e1000_softc *sc)
2949 {
2950 struct e1000_hw *hw = &sc->hw;
2951 struct tx_ring *txr = &sc->tx_queues->txr;
2952 struct e1000_tx_desc *txd;
2953 u32 tctl, txd_lower = E1000_TXD_CMD_IFCS;
2954 u16 size = 512;
2955
2956 tctl = E1000_READ_REG(hw, E1000_TCTL);
2957 E1000_WRITE_REG(hw, E1000_TCTL, tctl | E1000_TCTL_EN);
2958
2959 txd = &txr->tx_base[txr->tx_cidx_processed];
2960
2961 /* Just use the ring as a dummy buffer addr */
2962 txd->buffer_addr = txr->tx_paddr;
2963 txd->lower.data = htole32(txd_lower | size);
2964 txd->upper.data = 0;
2965
2966 /* flush descriptors to memory before notifying the HW */
2967 wmb();
2968
2969 E1000_WRITE_REG(hw, E1000_TDT(0), txr->tx_cidx_processed);
2970 mb();
2971 usec_delay(250);
2972 }
2973
2974 /*********************************************************************
2975 * em_flush_rx_ring - remove all descriptors from the rx_ring
2976 *
2977 * Mark all descriptors in the RX ring as consumed and disable the rx ring
2978 **********************************************************************/
2979 static void
em_flush_rx_ring(struct e1000_softc * sc)2980 em_flush_rx_ring(struct e1000_softc *sc)
2981 {
2982 struct e1000_hw *hw = &sc->hw;
2983 u32 rctl, rxdctl;
2984
2985 rctl = E1000_READ_REG(hw, E1000_RCTL);
2986 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2987 E1000_WRITE_FLUSH(hw);
2988 usec_delay(150);
2989
2990 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0));
2991 /* zero the lower 14 bits (prefetch and host thresholds) */
2992 rxdctl &= 0xffffc000;
2993 /*
2994 * update thresholds: prefetch threshold to 31, host threshold to 1
2995 * and make sure the granularity is "descriptors" and not
2996 * "cache lines"
2997 */
2998 rxdctl |= (0x1F | (1 << 8) | E1000_RXDCTL_THRESH_UNIT_DESC);
2999 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl);
3000
3001 /* momentarily enable the RX ring for the changes to take effect */
3002 E1000_WRITE_REG(hw, E1000_RCTL, rctl | E1000_RCTL_EN);
3003 E1000_WRITE_FLUSH(hw);
3004 usec_delay(150);
3005 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
3006 }
3007
3008 /*********************************************************************
3009 * em_flush_desc_rings - remove all descriptors from the descriptor rings
3010 *
3011 * In I219, the descriptor rings must be emptied before resetting the HW
3012 * or before changing the device state to D3 during runtime (runtime PM).
3013 *
3014 * Failure to do this will cause the HW to enter a unit hang state which can
3015 * only be released by PCI reset on the device
3016 *
3017 **********************************************************************/
3018 static void
em_flush_desc_rings(struct e1000_softc * sc)3019 em_flush_desc_rings(struct e1000_softc *sc)
3020 {
3021 struct e1000_hw *hw = &sc->hw;
3022 device_t dev = sc->dev;
3023 u16 hang_state;
3024 u32 fext_nvm11, tdlen;
3025
3026 /* First, disable MULR fix in FEXTNVM11 */
3027 fext_nvm11 = E1000_READ_REG(hw, E1000_FEXTNVM11);
3028 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX;
3029 E1000_WRITE_REG(hw, E1000_FEXTNVM11, fext_nvm11);
3030
3031 /* do nothing if we're not in faulty state, or the queue is empty */
3032 tdlen = E1000_READ_REG(hw, E1000_TDLEN(0));
3033 hang_state = pci_read_config(dev, PCICFG_DESC_RING_STATUS, 2);
3034 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen)
3035 return;
3036 em_flush_tx_ring(sc);
3037
3038 /* recheck, maybe the fault is caused by the rx ring */
3039 hang_state = pci_read_config(dev, PCICFG_DESC_RING_STATUS, 2);
3040 if (hang_state & FLUSH_DESC_REQUIRED)
3041 em_flush_rx_ring(sc);
3042 }
3043
3044
3045 /*********************************************************************
3046 *
3047 * Initialize the hardware to a configuration as specified by the
3048 * sc structure.
3049 *
3050 **********************************************************************/
3051 static void
em_reset(if_ctx_t ctx)3052 em_reset(if_ctx_t ctx)
3053 {
3054 device_t dev = iflib_get_dev(ctx);
3055 struct e1000_softc *sc = iflib_get_softc(ctx);
3056 struct ifnet *ifp = iflib_get_ifp(ctx);
3057 struct e1000_hw *hw = &sc->hw;
3058 u32 rx_buffer_size;
3059 u32 pba;
3060
3061 INIT_DEBUGOUT("em_reset: begin");
3062 /* Let the firmware know the OS is in control */
3063 em_get_hw_control(sc);
3064
3065 /* Set up smart power down as default off on newer adapters. */
3066 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 ||
3067 hw->mac.type == e1000_82572)) {
3068 u16 phy_tmp = 0;
3069
3070 /* Speed up time to link by disabling smart power down. */
3071 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
3072 phy_tmp &= ~IGP02E1000_PM_SPD;
3073 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp);
3074 }
3075
3076 /*
3077 * Packet Buffer Allocation (PBA)
3078 * Writing PBA sets the receive portion of the buffer
3079 * the remainder is used for the transmit buffer.
3080 */
3081 switch (hw->mac.type) {
3082 /* 82547: Total Packet Buffer is 40K */
3083 case e1000_82547:
3084 case e1000_82547_rev_2:
3085 if (hw->mac.max_frame_size > 8192)
3086 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
3087 else
3088 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */
3089 break;
3090 /* 82571/82572/80003es2lan: Total Packet Buffer is 48K */
3091 case e1000_82571:
3092 case e1000_82572:
3093 case e1000_80003es2lan:
3094 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
3095 break;
3096 /* 82573: Total Packet Buffer is 32K */
3097 case e1000_82573:
3098 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
3099 break;
3100 case e1000_82574:
3101 case e1000_82583:
3102 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
3103 break;
3104 case e1000_ich8lan:
3105 pba = E1000_PBA_8K;
3106 break;
3107 case e1000_ich9lan:
3108 case e1000_ich10lan:
3109 /* Boost Receive side for jumbo frames */
3110 if (hw->mac.max_frame_size > 4096)
3111 pba = E1000_PBA_14K;
3112 else
3113 pba = E1000_PBA_10K;
3114 break;
3115 case e1000_pchlan:
3116 case e1000_pch2lan:
3117 case e1000_pch_lpt:
3118 case e1000_pch_spt:
3119 case e1000_pch_cnp:
3120 case e1000_pch_tgp:
3121 case e1000_pch_adp:
3122 case e1000_pch_mtp:
3123 case e1000_pch_ptp:
3124 pba = E1000_PBA_26K;
3125 break;
3126 case e1000_82575:
3127 pba = E1000_PBA_32K;
3128 break;
3129 case e1000_82576:
3130 case e1000_vfadapt:
3131 pba = E1000_READ_REG(hw, E1000_RXPBS);
3132 pba &= E1000_RXPBS_SIZE_MASK_82576;
3133 break;
3134 case e1000_82580:
3135 case e1000_i350:
3136 case e1000_i354:
3137 case e1000_vfadapt_i350:
3138 pba = E1000_READ_REG(hw, E1000_RXPBS);
3139 pba = e1000_rxpbs_adjust_82580(pba);
3140 break;
3141 case e1000_i210:
3142 case e1000_i211:
3143 pba = E1000_PBA_34K;
3144 break;
3145 default:
3146 /* Remaining devices assumed to have Packet Buffer of 64K. */
3147 if (hw->mac.max_frame_size > 8192)
3148 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
3149 else
3150 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
3151 }
3152
3153 /* Special needs in case of Jumbo frames */
3154 if ((hw->mac.type == e1000_82575) && (ifp->if_mtu > ETHERMTU)) {
3155 u32 tx_space, min_tx, min_rx;
3156 pba = E1000_READ_REG(hw, E1000_PBA);
3157 tx_space = pba >> 16;
3158 pba &= 0xffff;
3159 min_tx = (hw->mac.max_frame_size +
3160 sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2;
3161 min_tx = roundup2(min_tx, 1024);
3162 min_tx >>= 10;
3163 min_rx = hw->mac.max_frame_size;
3164 min_rx = roundup2(min_rx, 1024);
3165 min_rx >>= 10;
3166 if (tx_space < min_tx &&
3167 ((min_tx - tx_space) < pba)) {
3168 pba = pba - (min_tx - tx_space);
3169 /*
3170 * if short on rx space, rx wins
3171 * and must trump tx adjustment
3172 */
3173 if (pba < min_rx)
3174 pba = min_rx;
3175 }
3176 E1000_WRITE_REG(hw, E1000_PBA, pba);
3177 }
3178
3179 if (hw->mac.type < igb_mac_min)
3180 E1000_WRITE_REG(hw, E1000_PBA, pba);
3181
3182 INIT_DEBUGOUT1("em_reset: pba=%dK",pba);
3183
3184 /*
3185 * These parameters control the automatic generation (Tx) and
3186 * response (Rx) to Ethernet PAUSE frames.
3187 * - High water mark should allow for at least two frames to be
3188 * received after sending an XOFF.
3189 * - Low water mark works best when it is very near the high water
3190 mark.
3191 * This allows the receiver to restart by sending XON when it has
3192 * drained a bit. Here we use an arbitrary value of 1500 which will
3193 * restart after one full frame is pulled from the buffer. There
3194 * could be several smaller frames in the buffer and if so they will
3195 * not trigger the XON until their total number reduces the buffer
3196 * by 1500.
3197 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
3198 */
3199 rx_buffer_size = (pba & 0xffff) << 10;
3200 hw->fc.high_water = rx_buffer_size -
3201 roundup2(hw->mac.max_frame_size, 1024);
3202 hw->fc.low_water = hw->fc.high_water - 1500;
3203
3204 if (sc->fc) /* locally set flow control value? */
3205 hw->fc.requested_mode = sc->fc;
3206 else
3207 hw->fc.requested_mode = e1000_fc_full;
3208
3209 if (hw->mac.type == e1000_80003es2lan)
3210 hw->fc.pause_time = 0xFFFF;
3211 else
3212 hw->fc.pause_time = EM_FC_PAUSE_TIME;
3213
3214 hw->fc.send_xon = true;
3215
3216 /* Device specific overrides/settings */
3217 switch (hw->mac.type) {
3218 case e1000_pchlan:
3219 /* Workaround: no TX flow ctrl for PCH */
3220 hw->fc.requested_mode = e1000_fc_rx_pause;
3221 hw->fc.pause_time = 0xFFFF; /* override */
3222 if (if_getmtu(ifp) > ETHERMTU) {
3223 hw->fc.high_water = 0x3500;
3224 hw->fc.low_water = 0x1500;
3225 } else {
3226 hw->fc.high_water = 0x5000;
3227 hw->fc.low_water = 0x3000;
3228 }
3229 hw->fc.refresh_time = 0x1000;
3230 break;
3231 case e1000_pch2lan:
3232 case e1000_pch_lpt:
3233 case e1000_pch_spt:
3234 case e1000_pch_cnp:
3235 case e1000_pch_tgp:
3236 case e1000_pch_adp:
3237 case e1000_pch_mtp:
3238 case e1000_pch_ptp:
3239 hw->fc.high_water = 0x5C20;
3240 hw->fc.low_water = 0x5048;
3241 hw->fc.pause_time = 0x0650;
3242 hw->fc.refresh_time = 0x0400;
3243 /* Jumbos need adjusted PBA */
3244 if (if_getmtu(ifp) > ETHERMTU)
3245 E1000_WRITE_REG(hw, E1000_PBA, 12);
3246 else
3247 E1000_WRITE_REG(hw, E1000_PBA, 26);
3248 break;
3249 case e1000_82575:
3250 case e1000_82576:
3251 /* 8-byte granularity */
3252 hw->fc.low_water = hw->fc.high_water - 8;
3253 break;
3254 case e1000_82580:
3255 case e1000_i350:
3256 case e1000_i354:
3257 case e1000_i210:
3258 case e1000_i211:
3259 case e1000_vfadapt:
3260 case e1000_vfadapt_i350:
3261 /* 16-byte granularity */
3262 hw->fc.low_water = hw->fc.high_water - 16;
3263 break;
3264 case e1000_ich9lan:
3265 case e1000_ich10lan:
3266 if (if_getmtu(ifp) > ETHERMTU) {
3267 hw->fc.high_water = 0x2800;
3268 hw->fc.low_water = hw->fc.high_water - 8;
3269 break;
3270 }
3271 /* FALLTHROUGH */
3272 default:
3273 if (hw->mac.type == e1000_80003es2lan)
3274 hw->fc.pause_time = 0xFFFF;
3275 break;
3276 }
3277
3278 /* I219 needs some special flushing to avoid hangs */
3279 if (sc->hw.mac.type >= e1000_pch_spt && sc->hw.mac.type < igb_mac_min)
3280 em_flush_desc_rings(sc);
3281
3282 /* Issue a global reset */
3283 e1000_reset_hw(hw);
3284 if (hw->mac.type >= igb_mac_min) {
3285 E1000_WRITE_REG(hw, E1000_WUC, 0);
3286 } else {
3287 E1000_WRITE_REG(hw, E1000_WUFC, 0);
3288 em_disable_aspm(sc);
3289 }
3290 if (sc->flags & IGB_MEDIA_RESET) {
3291 e1000_setup_init_funcs(hw, true);
3292 e1000_get_bus_info(hw);
3293 sc->flags &= ~IGB_MEDIA_RESET;
3294 }
3295 /* and a re-init */
3296 if (e1000_init_hw(hw) < 0) {
3297 device_printf(dev, "Hardware Initialization Failed\n");
3298 return;
3299 }
3300 if (hw->mac.type >= igb_mac_min)
3301 igb_init_dmac(sc, pba);
3302
3303 /* Save the final PBA off if it needs to be used elsewhere i.e. AIM */
3304 sc->pba = pba;
3305
3306 E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN);
3307 e1000_get_phy_info(hw);
3308 e1000_check_for_link(hw);
3309 }
3310
3311 /*
3312 * Initialise the RSS mapping for NICs that support multiple transmit/
3313 * receive rings.
3314 */
3315
3316 #define RSSKEYLEN 10
3317 static void
em_initialize_rss_mapping(struct e1000_softc * sc)3318 em_initialize_rss_mapping(struct e1000_softc *sc)
3319 {
3320 uint8_t rss_key[4 * RSSKEYLEN];
3321 uint32_t reta = 0;
3322 struct e1000_hw *hw = &sc->hw;
3323 int i;
3324
3325 /*
3326 * Configure RSS key
3327 */
3328 arc4rand(rss_key, sizeof(rss_key), 0);
3329 for (i = 0; i < RSSKEYLEN; ++i) {
3330 uint32_t rssrk = 0;
3331
3332 rssrk = EM_RSSRK_VAL(rss_key, i);
3333 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk);
3334 }
3335
3336 /*
3337 * Configure RSS redirect table in following fashion:
3338 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
3339 */
3340 for (i = 0; i < sizeof(reta); ++i) {
3341 uint32_t q;
3342
3343 q = (i % sc->rx_num_queues) << 7;
3344 reta |= q << (8 * i);
3345 }
3346
3347 for (i = 0; i < 32; ++i)
3348 E1000_WRITE_REG(hw, E1000_RETA(i), reta);
3349
3350 E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q |
3351 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3352 E1000_MRQC_RSS_FIELD_IPV4 |
3353 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX |
3354 E1000_MRQC_RSS_FIELD_IPV6_EX |
3355 E1000_MRQC_RSS_FIELD_IPV6);
3356 }
3357
3358 static void
igb_initialize_rss_mapping(struct e1000_softc * sc)3359 igb_initialize_rss_mapping(struct e1000_softc *sc)
3360 {
3361 struct e1000_hw *hw = &sc->hw;
3362 int i;
3363 int queue_id;
3364 u32 reta;
3365 u32 rss_key[10], mrqc, shift = 0;
3366
3367 /* XXX? */
3368 if (hw->mac.type == e1000_82575)
3369 shift = 6;
3370
3371 /*
3372 * The redirection table controls which destination
3373 * queue each bucket redirects traffic to.
3374 * Each DWORD represents four queues, with the LSB
3375 * being the first queue in the DWORD.
3376 *
3377 * This just allocates buckets to queues using round-robin
3378 * allocation.
3379 *
3380 * NOTE: It Just Happens to line up with the default
3381 * RSS allocation method.
3382 */
3383
3384 /* Warning FM follows */
3385 reta = 0;
3386 for (i = 0; i < 128; i++) {
3387 #ifdef RSS
3388 queue_id = rss_get_indirection_to_bucket(i);
3389 /*
3390 * If we have more queues than buckets, we'll
3391 * end up mapping buckets to a subset of the
3392 * queues.
3393 *
3394 * If we have more buckets than queues, we'll
3395 * end up instead assigning multiple buckets
3396 * to queues.
3397 *
3398 * Both are suboptimal, but we need to handle
3399 * the case so we don't go out of bounds
3400 * indexing arrays and such.
3401 */
3402 queue_id = queue_id % sc->rx_num_queues;
3403 #else
3404 queue_id = (i % sc->rx_num_queues);
3405 #endif
3406 /* Adjust if required */
3407 queue_id = queue_id << shift;
3408
3409 /*
3410 * The low 8 bits are for hash value (n+0);
3411 * The next 8 bits are for hash value (n+1), etc.
3412 */
3413 reta = reta >> 8;
3414 reta = reta | ( ((uint32_t) queue_id) << 24);
3415 if ((i & 3) == 3) {
3416 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3417 reta = 0;
3418 }
3419 }
3420
3421 /* Now fill in hash table */
3422
3423 /*
3424 * MRQC: Multiple Receive Queues Command
3425 * Set queuing to RSS control, number depends on the device.
3426 */
3427 mrqc = E1000_MRQC_ENABLE_RSS_MQ;
3428
3429 #ifdef RSS
3430 /* XXX ew typecasting */
3431 rss_getkey((uint8_t *) &rss_key);
3432 #else
3433 arc4rand(&rss_key, sizeof(rss_key), 0);
3434 #endif
3435 for (i = 0; i < 10; i++)
3436 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]);
3437
3438 /*
3439 * Configure the RSS fields to hash upon.
3440 */
3441 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
3442 E1000_MRQC_RSS_FIELD_IPV4_TCP);
3443 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
3444 E1000_MRQC_RSS_FIELD_IPV6_TCP);
3445 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP |
3446 E1000_MRQC_RSS_FIELD_IPV6_UDP);
3447 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
3448 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3449
3450 E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
3451 }
3452
3453 /*********************************************************************
3454 *
3455 * Setup networking device structure and register interface media.
3456 *
3457 **********************************************************************/
3458 static int
em_setup_interface(if_ctx_t ctx)3459 em_setup_interface(if_ctx_t ctx)
3460 {
3461 struct ifnet *ifp = iflib_get_ifp(ctx);
3462 struct e1000_softc *sc = iflib_get_softc(ctx);
3463 if_softc_ctx_t scctx = sc->shared;
3464
3465 INIT_DEBUGOUT("em_setup_interface: begin");
3466
3467 /* Single Queue */
3468 if (sc->tx_num_queues == 1) {
3469 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1);
3470 if_setsendqready(ifp);
3471 }
3472
3473 /*
3474 * Specify the media types supported by this adapter and register
3475 * callbacks to update media and link information
3476 */
3477 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
3478 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
3479 u_char fiber_type = IFM_1000_SX; /* default type */
3480
3481 if (sc->hw.mac.type == e1000_82545)
3482 fiber_type = IFM_1000_LX;
3483 ifmedia_add(sc->media,
3484 IFM_ETHER | fiber_type | IFM_FDX, 0, NULL);
3485 ifmedia_add(sc->media, IFM_ETHER | fiber_type, 0, NULL);
3486 } else {
3487 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
3488 ifmedia_add(sc->media,
3489 IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
3490 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
3491 ifmedia_add(sc->media,
3492 IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
3493 if (sc->hw.phy.type != e1000_phy_ife) {
3494 ifmedia_add(sc->media,
3495 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
3496 ifmedia_add(sc->media,
3497 IFM_ETHER | IFM_1000_T, 0, NULL);
3498 }
3499 }
3500 ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
3501 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO);
3502 return (0);
3503 }
3504
3505 static int
em_if_tx_queues_alloc(if_ctx_t ctx,caddr_t * vaddrs,uint64_t * paddrs,int ntxqs,int ntxqsets)3506 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs,
3507 int ntxqs, int ntxqsets)
3508 {
3509 struct e1000_softc *sc = iflib_get_softc(ctx);
3510 if_softc_ctx_t scctx = sc->shared;
3511 int error = E1000_SUCCESS;
3512 struct em_tx_queue *que;
3513 int i, j;
3514
3515 MPASS(sc->tx_num_queues > 0);
3516 MPASS(sc->tx_num_queues == ntxqsets);
3517
3518 /* First allocate the top level queue structs */
3519 if (!(sc->tx_queues =
3520 (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) *
3521 sc->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
3522 device_printf(iflib_get_dev(ctx),
3523 "Unable to allocate queue memory\n");
3524 return(ENOMEM);
3525 }
3526
3527 for (i = 0, que = sc->tx_queues; i < sc->tx_num_queues; i++, que++) {
3528 /* Set up some basics */
3529
3530 struct tx_ring *txr = &que->txr;
3531 txr->sc = que->sc = sc;
3532 que->me = txr->me = i;
3533
3534 /* Allocate report status array */
3535 if (!(txr->tx_rsq =
3536 (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0],
3537 M_DEVBUF, M_NOWAIT | M_ZERO))) {
3538 device_printf(iflib_get_dev(ctx),
3539 "failed to allocate rs_idxs memory\n");
3540 error = ENOMEM;
3541 goto fail;
3542 }
3543 for (j = 0; j < scctx->isc_ntxd[0]; j++)
3544 txr->tx_rsq[j] = QIDX_INVALID;
3545 /* get the virtual and physical address of hardware queues */
3546 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs];
3547 txr->tx_paddr = paddrs[i*ntxqs];
3548 }
3549
3550 if (bootverbose)
3551 device_printf(iflib_get_dev(ctx),
3552 "allocated for %d tx_queues\n", sc->tx_num_queues);
3553 return (0);
3554 fail:
3555 em_if_queues_free(ctx);
3556 return (error);
3557 }
3558
3559 static int
em_if_rx_queues_alloc(if_ctx_t ctx,caddr_t * vaddrs,uint64_t * paddrs,int nrxqs,int nrxqsets)3560 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs,
3561 int nrxqs, int nrxqsets)
3562 {
3563 struct e1000_softc *sc = iflib_get_softc(ctx);
3564 int error = E1000_SUCCESS;
3565 struct em_rx_queue *que;
3566 int i;
3567
3568 MPASS(sc->rx_num_queues > 0);
3569 MPASS(sc->rx_num_queues == nrxqsets);
3570
3571 /* First allocate the top level queue structs */
3572 if (!(sc->rx_queues =
3573 (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) *
3574 sc->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
3575 device_printf(iflib_get_dev(ctx),
3576 "Unable to allocate queue memory\n");
3577 error = ENOMEM;
3578 goto fail;
3579 }
3580
3581 for (i = 0, que = sc->rx_queues; i < nrxqsets; i++, que++) {
3582 /* Set up some basics */
3583 struct rx_ring *rxr = &que->rxr;
3584 rxr->sc = que->sc = sc;
3585 rxr->que = que;
3586 que->me = rxr->me = i;
3587
3588 /* get the virtual and physical address of hardware queues */
3589 rxr->rx_base =
3590 (union e1000_rx_desc_extended *)vaddrs[i*nrxqs];
3591 rxr->rx_paddr = paddrs[i*nrxqs];
3592 }
3593
3594 if (bootverbose)
3595 device_printf(iflib_get_dev(ctx),
3596 "allocated for %d rx_queues\n", sc->rx_num_queues);
3597
3598 return (0);
3599 fail:
3600 em_if_queues_free(ctx);
3601 return (error);
3602 }
3603
3604 static void
em_if_queues_free(if_ctx_t ctx)3605 em_if_queues_free(if_ctx_t ctx)
3606 {
3607 struct e1000_softc *sc = iflib_get_softc(ctx);
3608 struct em_tx_queue *tx_que = sc->tx_queues;
3609 struct em_rx_queue *rx_que = sc->rx_queues;
3610
3611 if (tx_que != NULL) {
3612 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) {
3613 struct tx_ring *txr = &tx_que->txr;
3614 if (txr->tx_rsq == NULL)
3615 break;
3616
3617 free(txr->tx_rsq, M_DEVBUF);
3618 txr->tx_rsq = NULL;
3619 }
3620 free(sc->tx_queues, M_DEVBUF);
3621 sc->tx_queues = NULL;
3622 }
3623
3624 if (rx_que != NULL) {
3625 free(sc->rx_queues, M_DEVBUF);
3626 sc->rx_queues = NULL;
3627 }
3628 }
3629
3630 /*********************************************************************
3631 *
3632 * Enable transmit unit.
3633 *
3634 **********************************************************************/
3635 static void
em_initialize_transmit_unit(if_ctx_t ctx)3636 em_initialize_transmit_unit(if_ctx_t ctx)
3637 {
3638 struct e1000_softc *sc = iflib_get_softc(ctx);
3639 if_softc_ctx_t scctx = sc->shared;
3640 struct em_tx_queue *que;
3641 struct tx_ring *txr;
3642 struct e1000_hw *hw = &sc->hw;
3643 u32 tctl, txdctl = 0, tarc, tipg = 0;
3644
3645 INIT_DEBUGOUT("em_initialize_transmit_unit: begin");
3646
3647 for (int i = 0; i < sc->tx_num_queues; i++, txr++) {
3648 u64 bus_addr;
3649 caddr_t offp, endp;
3650
3651 que = &sc->tx_queues[i];
3652 txr = &que->txr;
3653 bus_addr = txr->tx_paddr;
3654
3655 /* Clear checksum offload context. */
3656 offp = (caddr_t)&txr->csum_flags;
3657 endp = (caddr_t)(txr + 1);
3658 bzero(offp, endp - offp);
3659
3660 /* Base and Len of TX Ring */
3661 E1000_WRITE_REG(hw, E1000_TDLEN(i),
3662 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc));
3663 E1000_WRITE_REG(hw, E1000_TDBAH(i), (u32)(bus_addr >> 32));
3664 E1000_WRITE_REG(hw, E1000_TDBAL(i), (u32)bus_addr);
3665 /* Init the HEAD/TAIL indices */
3666 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
3667 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
3668
3669 HW_DEBUGOUT2("Base = %x, Length = %x\n",
3670 E1000_READ_REG(hw, E1000_TDBAL(i)),
3671 E1000_READ_REG(hw, E1000_TDLEN(i)));
3672
3673 txdctl = 0; /* clear txdctl */
3674 txdctl |= 0x1f; /* PTHRESH */
3675 txdctl |= 1 << 8; /* HTHRESH */
3676 txdctl |= 1 << 16;/* WTHRESH */
3677 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */
3678 txdctl |= E1000_TXDCTL_GRAN;
3679 txdctl |= 1 << 25; /* LWTHRESH */
3680
3681 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
3682 }
3683
3684 /* Set the default values for the Tx Inter Packet Gap timer */
3685 switch (hw->mac.type) {
3686 case e1000_80003es2lan:
3687 tipg = DEFAULT_82543_TIPG_IPGR1;
3688 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
3689 E1000_TIPG_IPGR2_SHIFT;
3690 break;
3691 case e1000_82542:
3692 tipg = DEFAULT_82542_TIPG_IPGT;
3693 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
3694 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
3695 break;
3696 default:
3697 if (hw->phy.media_type == e1000_media_type_fiber ||
3698 hw->phy.media_type == e1000_media_type_internal_serdes)
3699 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
3700 else
3701 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
3702 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
3703 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
3704 }
3705
3706 if (hw->mac.type < igb_mac_min) {
3707 E1000_WRITE_REG(hw, E1000_TIPG, tipg);
3708 E1000_WRITE_REG(hw, E1000_TIDV, sc->tx_int_delay.value);
3709
3710 if (sc->tx_int_delay.value > 0)
3711 sc->txd_cmd |= E1000_TXD_CMD_IDE;
3712 }
3713
3714 if (hw->mac.type >= e1000_82540)
3715 E1000_WRITE_REG(hw, E1000_TADV, sc->tx_abs_int_delay.value);
3716
3717 if (hw->mac.type == e1000_82571 || hw->mac.type == e1000_82572) {
3718 tarc = E1000_READ_REG(hw, E1000_TARC(0));
3719 tarc |= TARC_SPEED_MODE_BIT;
3720 E1000_WRITE_REG(hw, E1000_TARC(0), tarc);
3721 } else if (hw->mac.type == e1000_80003es2lan) {
3722 /* errata: program both queues to unweighted RR */
3723 tarc = E1000_READ_REG(hw, E1000_TARC(0));
3724 tarc |= 1;
3725 E1000_WRITE_REG(hw, E1000_TARC(0), tarc);
3726 tarc = E1000_READ_REG(hw, E1000_TARC(1));
3727 tarc |= 1;
3728 E1000_WRITE_REG(hw, E1000_TARC(1), tarc);
3729 } else if (hw->mac.type == e1000_82574) {
3730 tarc = E1000_READ_REG(hw, E1000_TARC(0));
3731 tarc |= TARC_ERRATA_BIT;
3732 if ( sc->tx_num_queues > 1) {
3733 tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX);
3734 E1000_WRITE_REG(hw, E1000_TARC(0), tarc);
3735 E1000_WRITE_REG(hw, E1000_TARC(1), tarc);
3736 } else
3737 E1000_WRITE_REG(hw, E1000_TARC(0), tarc);
3738 }
3739
3740 /* Program the Transmit Control Register */
3741 tctl = E1000_READ_REG(hw, E1000_TCTL);
3742 tctl &= ~E1000_TCTL_CT;
3743 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
3744 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
3745
3746 if (hw->mac.type >= e1000_82571 && hw->mac.type < igb_mac_min)
3747 tctl |= E1000_TCTL_MULR;
3748
3749 /* This write will effectively turn on the transmit unit. */
3750 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
3751
3752 /* SPT and KBL errata workarounds */
3753 if (hw->mac.type == e1000_pch_spt) {
3754 u32 reg;
3755 reg = E1000_READ_REG(hw, E1000_IOSFPC);
3756 reg |= E1000_RCTL_RDMTS_HEX;
3757 E1000_WRITE_REG(hw, E1000_IOSFPC, reg);
3758 /* i218-i219 Specification Update 1.5.4.5 */
3759 reg = E1000_READ_REG(hw, E1000_TARC(0));
3760 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ;
3761 reg |= E1000_TARC0_CB_MULTIQ_2_REQ;
3762 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
3763 }
3764 }
3765
3766 /*********************************************************************
3767 *
3768 * Enable receive unit.
3769 *
3770 **********************************************************************/
3771 #define BSIZEPKT_ROUNDUP ((1<<E1000_SRRCTL_BSIZEPKT_SHIFT)-1)
3772
3773 static void
em_initialize_receive_unit(if_ctx_t ctx)3774 em_initialize_receive_unit(if_ctx_t ctx)
3775 {
3776 struct e1000_softc *sc = iflib_get_softc(ctx);
3777 if_softc_ctx_t scctx = sc->shared;
3778 struct ifnet *ifp = iflib_get_ifp(ctx);
3779 struct e1000_hw *hw = &sc->hw;
3780 struct em_rx_queue *que;
3781 int i;
3782 uint32_t rctl, rxcsum;
3783
3784 INIT_DEBUGOUT("em_initialize_receive_units: begin");
3785
3786 /*
3787 * Make sure receives are disabled while setting
3788 * up the descriptor ring
3789 */
3790 rctl = E1000_READ_REG(hw, E1000_RCTL);
3791 /* Do not disable if ever enabled on this hardware */
3792 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583))
3793 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
3794
3795 /* Setup the Receive Control Register */
3796 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3797 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
3798 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
3799 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3800
3801 /* Do not store bad packets */
3802 rctl &= ~E1000_RCTL_SBP;
3803
3804 /* Enable Long Packet receive */
3805 if (if_getmtu(ifp) > ETHERMTU)
3806 rctl |= E1000_RCTL_LPE;
3807 else
3808 rctl &= ~E1000_RCTL_LPE;
3809
3810 /* Strip the CRC */
3811 if (!em_disable_crc_stripping)
3812 rctl |= E1000_RCTL_SECRC;
3813
3814 /* lem/em default interrupt moderation */
3815 if (hw->mac.type < igb_mac_min) {
3816 if (hw->mac.type >= e1000_82540) {
3817 E1000_WRITE_REG(hw, E1000_RADV,
3818 sc->rx_abs_int_delay.value);
3819
3820 /* Set the default interrupt throttling rate */
3821 E1000_WRITE_REG(hw, E1000_ITR,
3822 EM_INTS_TO_ITR(em_max_interrupt_rate));
3823 }
3824
3825 /* XXX TEMPORARY WORKAROUND: on some systems with 82573
3826 * long latencies are observed, like Lenovo X60. This
3827 * change eliminates the problem, but since having positive
3828 * values in RDTR is a known source of problems on other
3829 * platforms another solution is being sought.
3830 */
3831 if (hw->mac.type == e1000_82573)
3832 E1000_WRITE_REG(hw, E1000_RDTR, 0x20);
3833 else
3834 E1000_WRITE_REG(hw, E1000_RDTR,
3835 sc->rx_int_delay.value);
3836 }
3837
3838 if (hw->mac.type >= em_mac_min) {
3839 uint32_t rfctl;
3840 /* Use extended rx descriptor formats */
3841 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3842 rfctl |= E1000_RFCTL_EXTEN;
3843
3844 /*
3845 * When using MSI-X interrupts we need to throttle
3846 * using the EITR register (82574 only)
3847 */
3848 if (hw->mac.type == e1000_82574) {
3849 for (int i = 0; i < 4; i++)
3850 E1000_WRITE_REG(hw, E1000_EITR_82574(i),
3851 EM_INTS_TO_ITR(em_max_interrupt_rate));
3852 /* Disable accelerated acknowledge */
3853 rfctl |= E1000_RFCTL_ACK_DIS;
3854 }
3855 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3856 }
3857
3858 /* Set up L3 and L4 csum Rx descriptor offloads */
3859 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
3860 if (if_getcapenable(ifp) & IFCAP_RXCSUM) {
3861 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL;
3862 if (hw->mac.type > e1000_82575)
3863 rxcsum |= E1000_RXCSUM_CRCOFL;
3864 else if (hw->mac.type < em_mac_min &&
3865 if_getcapenable(ifp) & IFCAP_HWCSUM_IPV6)
3866 rxcsum |= E1000_RXCSUM_IPV6OFL;
3867 } else {
3868 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL);
3869 if (hw->mac.type > e1000_82575)
3870 rxcsum &= ~E1000_RXCSUM_CRCOFL;
3871 else if (hw->mac.type < em_mac_min)
3872 rxcsum &= ~E1000_RXCSUM_IPV6OFL;
3873 }
3874
3875 if (sc->rx_num_queues > 1) {
3876 /* RSS hash needed in the Rx descriptor */
3877 rxcsum |= E1000_RXCSUM_PCSD;
3878
3879 if (hw->mac.type >= igb_mac_min)
3880 igb_initialize_rss_mapping(sc);
3881 else
3882 em_initialize_rss_mapping(sc);
3883 }
3884 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
3885
3886 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) {
3887 struct rx_ring *rxr = &que->rxr;
3888 /* Setup the Base and Length of the Rx Descriptor Ring */
3889 u64 bus_addr = rxr->rx_paddr;
3890 #if 0
3891 u32 rdt = sc->rx_num_queues -1; /* default */
3892 #endif
3893
3894 E1000_WRITE_REG(hw, E1000_RDLEN(i),
3895 scctx->isc_nrxd[0] *
3896 sizeof(union e1000_rx_desc_extended));
3897 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32));
3898 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr);
3899 /* Setup the Head and Tail Descriptor Pointers */
3900 E1000_WRITE_REG(hw, E1000_RDH(i), 0);
3901 E1000_WRITE_REG(hw, E1000_RDT(i), 0);
3902 }
3903
3904 /*
3905 * Set PTHRESH for improved jumbo performance
3906 * According to 10.2.5.11 of Intel 82574 Datasheet,
3907 * RXDCTL(1) is written whenever RXDCTL(0) is written.
3908 * Only write to RXDCTL(1) if there is a need for different
3909 * settings.
3910 */
3911 if ((hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_pch2lan ||
3912 hw->mac.type == e1000_ich10lan) && if_getmtu(ifp) > ETHERMTU) {
3913 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0));
3914 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3);
3915 } else if (hw->mac.type == e1000_82574) {
3916 for (int i = 0; i < sc->rx_num_queues; i++) {
3917 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
3918 rxdctl |= 0x20; /* PTHRESH */
3919 rxdctl |= 4 << 8; /* HTHRESH */
3920 rxdctl |= 4 << 16;/* WTHRESH */
3921 rxdctl |= 1 << 24; /* Switch to granularity */
3922 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
3923 }
3924 } else if (hw->mac.type >= igb_mac_min) {
3925 u32 psize, srrctl = 0;
3926
3927 if (if_getmtu(ifp) > ETHERMTU) {
3928 psize = scctx->isc_max_frame_size;
3929 /* are we on a vlan? */
3930 if (ifp->if_vlantrunk != NULL)
3931 psize += VLAN_TAG_SIZE;
3932
3933 if (sc->vf_ifp)
3934 e1000_rlpml_set_vf(hw, psize);
3935 else
3936 E1000_WRITE_REG(hw, E1000_RLPML, psize);
3937 }
3938
3939 /* Set maximum packet buffer len */
3940 srrctl |= (sc->rx_mbuf_sz + BSIZEPKT_ROUNDUP) >>
3941 E1000_SRRCTL_BSIZEPKT_SHIFT;
3942
3943 /*
3944 * If TX flow control is disabled and there's >1 queue
3945 * defined, enable DROP.
3946 *
3947 * This drops frames rather than hanging the RX MAC for all
3948 * queues.
3949 */
3950 if ((sc->rx_num_queues > 1) &&
3951 (sc->fc == e1000_fc_none ||
3952 sc->fc == e1000_fc_rx_pause)) {
3953 srrctl |= E1000_SRRCTL_DROP_EN;
3954 }
3955 /* Setup the Base and Length of the Rx Descriptor Rings */
3956 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues;
3957 i++, que++) {
3958 struct rx_ring *rxr = &que->rxr;
3959 u64 bus_addr = rxr->rx_paddr;
3960 u32 rxdctl;
3961
3962 #ifdef notyet
3963 /* Configure for header split? -- ignore for now */
3964 rxr->hdr_split = igb_header_split;
3965 #else
3966 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
3967 #endif
3968
3969 E1000_WRITE_REG(hw, E1000_RDLEN(i),
3970 scctx->isc_nrxd[0] *
3971 sizeof(struct e1000_rx_desc));
3972 E1000_WRITE_REG(hw, E1000_RDBAH(i),
3973 (uint32_t)(bus_addr >> 32));
3974 E1000_WRITE_REG(hw, E1000_RDBAL(i),
3975 (uint32_t)bus_addr);
3976 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
3977 /* Enable this Queue */
3978 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
3979 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3980 rxdctl &= 0xFFF00000;
3981 rxdctl |= IGB_RX_PTHRESH;
3982 rxdctl |= IGB_RX_HTHRESH << 8;
3983 rxdctl |= IGB_RX_WTHRESH << 16;
3984 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
3985 }
3986 } else if (hw->mac.type >= e1000_pch2lan) {
3987 if (if_getmtu(ifp) > ETHERMTU)
3988 e1000_lv_jumbo_workaround_ich8lan(hw, true);
3989 else
3990 e1000_lv_jumbo_workaround_ich8lan(hw, false);
3991 }
3992
3993 /* Make sure VLAN Filters are off */
3994 rctl &= ~E1000_RCTL_VFE;
3995
3996 /* Set up packet buffer size, overridden by per queue srrctl on igb */
3997 if (hw->mac.type < igb_mac_min) {
3998 if (sc->rx_mbuf_sz > 2048 && sc->rx_mbuf_sz <= 4096)
3999 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
4000 else if (sc->rx_mbuf_sz > 4096 && sc->rx_mbuf_sz <= 8192)
4001 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
4002 else if (sc->rx_mbuf_sz > 8192)
4003 rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX;
4004 else {
4005 rctl |= E1000_RCTL_SZ_2048;
4006 rctl &= ~E1000_RCTL_BSEX;
4007 }
4008 } else
4009 rctl |= E1000_RCTL_SZ_2048;
4010
4011 /*
4012 * rctl bits 11:10 are as follows
4013 * lem: reserved
4014 * em: DTYPE
4015 * igb: reserved
4016 * and should be 00 on all of the above
4017 */
4018 rctl &= ~0x00000C00;
4019
4020 /* Write out the settings */
4021 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4022
4023 return;
4024 }
4025
4026 static void
em_if_vlan_register(if_ctx_t ctx,u16 vtag)4027 em_if_vlan_register(if_ctx_t ctx, u16 vtag)
4028 {
4029 struct e1000_softc *sc = iflib_get_softc(ctx);
4030 u32 index, bit;
4031
4032 index = (vtag >> 5) & 0x7F;
4033 bit = vtag & 0x1F;
4034 sc->shadow_vfta[index] |= (1 << bit);
4035 ++sc->num_vlans;
4036 em_if_vlan_filter_write(sc);
4037 }
4038
4039 static void
em_if_vlan_unregister(if_ctx_t ctx,u16 vtag)4040 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag)
4041 {
4042 struct e1000_softc *sc = iflib_get_softc(ctx);
4043 u32 index, bit;
4044
4045 index = (vtag >> 5) & 0x7F;
4046 bit = vtag & 0x1F;
4047 sc->shadow_vfta[index] &= ~(1 << bit);
4048 --sc->num_vlans;
4049 em_if_vlan_filter_write(sc);
4050 }
4051
4052 static bool
em_if_vlan_filter_capable(if_ctx_t ctx)4053 em_if_vlan_filter_capable(if_ctx_t ctx)
4054 {
4055 if_t ifp = iflib_get_ifp(ctx);
4056
4057 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) &&
4058 !em_disable_crc_stripping)
4059 return (true);
4060
4061 return (false);
4062 }
4063
4064 static bool
em_if_vlan_filter_used(if_ctx_t ctx)4065 em_if_vlan_filter_used(if_ctx_t ctx)
4066 {
4067 struct e1000_softc *sc = iflib_get_softc(ctx);
4068
4069 if (!em_if_vlan_filter_capable(ctx))
4070 return (false);
4071
4072 for (int i = 0; i < EM_VFTA_SIZE; i++)
4073 if (sc->shadow_vfta[i] != 0)
4074 return (true);
4075
4076 return (false);
4077 }
4078
4079 static void
em_if_vlan_filter_enable(struct e1000_softc * sc)4080 em_if_vlan_filter_enable(struct e1000_softc *sc)
4081 {
4082 struct e1000_hw *hw = &sc->hw;
4083 u32 reg;
4084
4085 reg = E1000_READ_REG(hw, E1000_RCTL);
4086 reg &= ~E1000_RCTL_CFIEN;
4087 reg |= E1000_RCTL_VFE;
4088 E1000_WRITE_REG(hw, E1000_RCTL, reg);
4089 }
4090
4091 static void
em_if_vlan_filter_disable(struct e1000_softc * sc)4092 em_if_vlan_filter_disable(struct e1000_softc *sc)
4093 {
4094 struct e1000_hw *hw = &sc->hw;
4095 u32 reg;
4096
4097 reg = E1000_READ_REG(hw, E1000_RCTL);
4098 reg &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN);
4099 E1000_WRITE_REG(hw, E1000_RCTL, reg);
4100 }
4101
4102 static void
em_if_vlan_filter_write(struct e1000_softc * sc)4103 em_if_vlan_filter_write(struct e1000_softc *sc)
4104 {
4105 struct e1000_hw *hw = &sc->hw;
4106
4107 if (sc->vf_ifp)
4108 return;
4109
4110 /* Disable interrupts for lem(4) devices during the filter change */
4111 if (hw->mac.type < em_mac_min)
4112 em_if_intr_disable(sc->ctx);
4113
4114 for (int i = 0; i < EM_VFTA_SIZE; i++)
4115 if (sc->shadow_vfta[i] != 0) {
4116 /* XXXKB: incomplete VF support, we returned above */
4117 if (sc->vf_ifp)
4118 e1000_vfta_set_vf(hw, sc->shadow_vfta[i],
4119 true);
4120 else
4121 e1000_write_vfta(hw, i, sc->shadow_vfta[i]);
4122 }
4123
4124 /* Re-enable interrupts for lem-class devices */
4125 if (hw->mac.type < em_mac_min)
4126 em_if_intr_enable(sc->ctx);
4127 }
4128
4129 static void
em_setup_vlan_hw_support(if_ctx_t ctx)4130 em_setup_vlan_hw_support(if_ctx_t ctx)
4131 {
4132 struct e1000_softc *sc = iflib_get_softc(ctx);
4133 struct e1000_hw *hw = &sc->hw;
4134 struct ifnet *ifp = iflib_get_ifp(ctx);
4135 u32 reg;
4136
4137 /* XXXKB: Return early if we are a VF until VF decap and filter
4138 * management is ready and tested.
4139 */
4140 if (sc->vf_ifp)
4141 return;
4142
4143 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING &&
4144 !em_disable_crc_stripping) {
4145 reg = E1000_READ_REG(hw, E1000_CTRL);
4146 reg |= E1000_CTRL_VME;
4147 E1000_WRITE_REG(hw, E1000_CTRL, reg);
4148 } else {
4149 reg = E1000_READ_REG(hw, E1000_CTRL);
4150 reg &= ~E1000_CTRL_VME;
4151 E1000_WRITE_REG(hw, E1000_CTRL, reg);
4152 }
4153
4154 /* If we aren't doing HW filtering, we're done */
4155 if (!em_if_vlan_filter_capable(ctx)) {
4156 em_if_vlan_filter_disable(sc);
4157 return;
4158 }
4159
4160 /*
4161 * A soft reset zero's out the VFTA, so
4162 * we need to repopulate it now.
4163 * We also insert VLAN 0 in the filter list, so we pass VLAN 0 tagged
4164 * traffic through. This will write the entire table.
4165 */
4166 em_if_vlan_register(ctx, 0);
4167
4168 /* Enable the Filter Table */
4169 em_if_vlan_filter_enable(sc);
4170 }
4171
4172 static void
em_if_intr_enable(if_ctx_t ctx)4173 em_if_intr_enable(if_ctx_t ctx)
4174 {
4175 struct e1000_softc *sc = iflib_get_softc(ctx);
4176 struct e1000_hw *hw = &sc->hw;
4177 u32 ims_mask = IMS_ENABLE_MASK;
4178
4179 if (sc->intr_type == IFLIB_INTR_MSIX) {
4180 E1000_WRITE_REG(hw, EM_EIAC, sc->ims);
4181 ims_mask |= sc->ims;
4182 }
4183
4184 E1000_WRITE_REG(hw, E1000_IMS, ims_mask);
4185 E1000_WRITE_FLUSH(hw);
4186 }
4187
4188 static void
em_if_intr_disable(if_ctx_t ctx)4189 em_if_intr_disable(if_ctx_t ctx)
4190 {
4191 struct e1000_softc *sc = iflib_get_softc(ctx);
4192 struct e1000_hw *hw = &sc->hw;
4193
4194 if (sc->intr_type == IFLIB_INTR_MSIX)
4195 E1000_WRITE_REG(hw, EM_EIAC, 0);
4196 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
4197 E1000_WRITE_FLUSH(hw);
4198 }
4199
4200 static void
igb_if_intr_enable(if_ctx_t ctx)4201 igb_if_intr_enable(if_ctx_t ctx)
4202 {
4203 struct e1000_softc *sc = iflib_get_softc(ctx);
4204 struct e1000_hw *hw = &sc->hw;
4205 u32 mask;
4206
4207 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) {
4208 mask = (sc->que_mask | sc->link_mask);
4209 E1000_WRITE_REG(hw, E1000_EIAC, mask);
4210 E1000_WRITE_REG(hw, E1000_EIAM, mask);
4211 E1000_WRITE_REG(hw, E1000_EIMS, mask);
4212 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC);
4213 } else
4214 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK);
4215 E1000_WRITE_FLUSH(hw);
4216 }
4217
4218 static void
igb_if_intr_disable(if_ctx_t ctx)4219 igb_if_intr_disable(if_ctx_t ctx)
4220 {
4221 struct e1000_softc *sc = iflib_get_softc(ctx);
4222 struct e1000_hw *hw = &sc->hw;
4223
4224 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) {
4225 E1000_WRITE_REG(hw, E1000_EIMC, 0xffffffff);
4226 E1000_WRITE_REG(hw, E1000_EIAC, 0);
4227 }
4228 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
4229 E1000_WRITE_FLUSH(hw);
4230 }
4231
4232 /*
4233 * Bit of a misnomer, what this really means is
4234 * to enable OS management of the system... aka
4235 * to disable special hardware management features
4236 */
4237 static void
em_init_manageability(struct e1000_softc * sc)4238 em_init_manageability(struct e1000_softc *sc)
4239 {
4240 /* A shared code workaround */
4241 #define E1000_82542_MANC2H E1000_MANC2H
4242 if (sc->has_manage) {
4243 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
4244 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
4245
4246 /* disable hardware interception of ARP */
4247 manc &= ~(E1000_MANC_ARP_EN);
4248
4249 /* enable receiving management packets to the host */
4250 manc |= E1000_MANC_EN_MNG2HOST;
4251 #define E1000_MNG2HOST_PORT_623 (1 << 5)
4252 #define E1000_MNG2HOST_PORT_664 (1 << 6)
4253 manc2h |= E1000_MNG2HOST_PORT_623;
4254 manc2h |= E1000_MNG2HOST_PORT_664;
4255 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
4256 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
4257 }
4258 }
4259
4260 /*
4261 * Give control back to hardware management
4262 * controller if there is one.
4263 */
4264 static void
em_release_manageability(struct e1000_softc * sc)4265 em_release_manageability(struct e1000_softc *sc)
4266 {
4267 if (sc->has_manage) {
4268 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
4269
4270 /* re-enable hardware interception of ARP */
4271 manc |= E1000_MANC_ARP_EN;
4272 manc &= ~E1000_MANC_EN_MNG2HOST;
4273
4274 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
4275 }
4276 }
4277
4278 /*
4279 * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit.
4280 * For ASF and Pass Through versions of f/w this means
4281 * that the driver is loaded. For AMT version type f/w
4282 * this means that the network i/f is open.
4283 */
4284 static void
em_get_hw_control(struct e1000_softc * sc)4285 em_get_hw_control(struct e1000_softc *sc)
4286 {
4287 u32 ctrl_ext, swsm;
4288
4289 if (sc->vf_ifp)
4290 return;
4291
4292 if (sc->hw.mac.type == e1000_82573) {
4293 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
4294 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
4295 swsm | E1000_SWSM_DRV_LOAD);
4296 return;
4297 }
4298 /* else */
4299 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
4300 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
4301 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
4302 }
4303
4304 /*
4305 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
4306 * For ASF and Pass Through versions of f/w this means that
4307 * the driver is no longer loaded. For AMT versions of the
4308 * f/w this means that the network i/f is closed.
4309 */
4310 static void
em_release_hw_control(struct e1000_softc * sc)4311 em_release_hw_control(struct e1000_softc *sc)
4312 {
4313 u32 ctrl_ext, swsm;
4314
4315 if (!sc->has_manage)
4316 return;
4317
4318 if (sc->hw.mac.type == e1000_82573) {
4319 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
4320 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
4321 swsm & ~E1000_SWSM_DRV_LOAD);
4322 return;
4323 }
4324 /* else */
4325 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
4326 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
4327 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
4328 return;
4329 }
4330
4331 static int
em_is_valid_ether_addr(u8 * addr)4332 em_is_valid_ether_addr(u8 *addr)
4333 {
4334 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 };
4335
4336 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) {
4337 return (false);
4338 }
4339
4340 return (true);
4341 }
4342
4343 static bool
em_automask_tso(if_ctx_t ctx)4344 em_automask_tso(if_ctx_t ctx)
4345 {
4346 struct e1000_softc *sc = iflib_get_softc(ctx);
4347 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx);
4348 if_t ifp = iflib_get_ifp(ctx);
4349
4350 if (!em_unsupported_tso && sc->link_speed &&
4351 sc->link_speed != SPEED_1000 &&
4352 scctx->isc_capenable & IFCAP_TSO) {
4353 device_printf(sc->dev,
4354 "Disabling TSO for 10/100 Ethernet.\n");
4355 sc->tso_automasked = scctx->isc_capenable & IFCAP_TSO;
4356 scctx->isc_capenable &= ~IFCAP_TSO;
4357 if_setcapenablebit(ifp, 0, IFCAP_TSO);
4358 /* iflib_init_locked handles ifnet hwassistbits */
4359 iflib_request_reset(ctx);
4360 return true;
4361 } else if (sc->link_speed == SPEED_1000 && sc->tso_automasked) {
4362 device_printf(sc->dev, "Re-enabling TSO for GbE.\n");
4363 scctx->isc_capenable |= sc->tso_automasked;
4364 if_setcapenablebit(ifp, sc->tso_automasked, 0);
4365 sc->tso_automasked = 0;
4366 /* iflib_init_locked handles ifnet hwassistbits */
4367 iflib_request_reset(ctx);
4368 return true;
4369 }
4370
4371 return false;
4372 }
4373
4374 /*
4375 ** Parse the interface capabilities with regard
4376 ** to both system management and wake-on-lan for
4377 ** later use.
4378 */
4379 static void
em_get_wakeup(if_ctx_t ctx)4380 em_get_wakeup(if_ctx_t ctx)
4381 {
4382 struct e1000_softc *sc = iflib_get_softc(ctx);
4383 device_t dev = iflib_get_dev(ctx);
4384 u16 eeprom_data = 0, device_id, apme_mask;
4385
4386 sc->has_manage = e1000_enable_mng_pass_thru(&sc->hw);
4387 apme_mask = EM_EEPROM_APME;
4388
4389 switch (sc->hw.mac.type) {
4390 case e1000_82542:
4391 case e1000_82543:
4392 break;
4393 case e1000_82544:
4394 e1000_read_nvm(&sc->hw,
4395 NVM_INIT_CONTROL2_REG, 1, &eeprom_data);
4396 apme_mask = EM_82544_APME;
4397 break;
4398 case e1000_82546:
4399 case e1000_82546_rev_3:
4400 if (sc->hw.bus.func == 1) {
4401 e1000_read_nvm(&sc->hw,
4402 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
4403 break;
4404 } else
4405 e1000_read_nvm(&sc->hw,
4406 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
4407 break;
4408 case e1000_82573:
4409 case e1000_82583:
4410 sc->has_amt = true;
4411 /* FALLTHROUGH */
4412 case e1000_82571:
4413 case e1000_82572:
4414 case e1000_80003es2lan:
4415 if (sc->hw.bus.func == 1) {
4416 e1000_read_nvm(&sc->hw,
4417 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
4418 break;
4419 } else
4420 e1000_read_nvm(&sc->hw,
4421 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
4422 break;
4423 case e1000_ich8lan:
4424 case e1000_ich9lan:
4425 case e1000_ich10lan:
4426 case e1000_pchlan:
4427 case e1000_pch2lan:
4428 case e1000_pch_lpt:
4429 case e1000_pch_spt:
4430 case e1000_82575: /* listing all igb devices */
4431 case e1000_82576:
4432 case e1000_82580:
4433 case e1000_i350:
4434 case e1000_i354:
4435 case e1000_i210:
4436 case e1000_i211:
4437 case e1000_vfadapt:
4438 case e1000_vfadapt_i350:
4439 apme_mask = E1000_WUC_APME;
4440 sc->has_amt = true;
4441 eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC);
4442 break;
4443 default:
4444 e1000_read_nvm(&sc->hw,
4445 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
4446 break;
4447 }
4448 if (eeprom_data & apme_mask)
4449 sc->wol = (E1000_WUFC_MAG | E1000_WUFC_MC);
4450 /*
4451 * We have the eeprom settings, now apply the special cases
4452 * where the eeprom may be wrong or the board won't support
4453 * wake on lan on a particular port
4454 */
4455 device_id = pci_get_device(dev);
4456 switch (device_id) {
4457 case E1000_DEV_ID_82546GB_PCIE:
4458 sc->wol = 0;
4459 break;
4460 case E1000_DEV_ID_82546EB_FIBER:
4461 case E1000_DEV_ID_82546GB_FIBER:
4462 /* Wake events only supported on port A for dual fiber
4463 * regardless of eeprom setting */
4464 if (E1000_READ_REG(&sc->hw, E1000_STATUS) &
4465 E1000_STATUS_FUNC_1)
4466 sc->wol = 0;
4467 break;
4468 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
4469 /* if quad port adapter, disable WoL on all but port A */
4470 if (global_quad_port_a != 0)
4471 sc->wol = 0;
4472 /* Reset for multiple quad port adapters */
4473 if (++global_quad_port_a == 4)
4474 global_quad_port_a = 0;
4475 break;
4476 case E1000_DEV_ID_82571EB_FIBER:
4477 /* Wake events only supported on port A for dual fiber
4478 * regardless of eeprom setting */
4479 if (E1000_READ_REG(&sc->hw, E1000_STATUS) &
4480 E1000_STATUS_FUNC_1)
4481 sc->wol = 0;
4482 break;
4483 case E1000_DEV_ID_82571EB_QUAD_COPPER:
4484 case E1000_DEV_ID_82571EB_QUAD_FIBER:
4485 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
4486 /* if quad port adapter, disable WoL on all but port A */
4487 if (global_quad_port_a != 0)
4488 sc->wol = 0;
4489 /* Reset for multiple quad port adapters */
4490 if (++global_quad_port_a == 4)
4491 global_quad_port_a = 0;
4492 break;
4493 }
4494 return;
4495 }
4496
4497
4498 /*
4499 * Enable PCI Wake On Lan capability
4500 */
4501 static void
em_enable_wakeup(if_ctx_t ctx)4502 em_enable_wakeup(if_ctx_t ctx)
4503 {
4504 struct e1000_softc *sc = iflib_get_softc(ctx);
4505 device_t dev = iflib_get_dev(ctx);
4506 if_t ifp = iflib_get_ifp(ctx);
4507 int error = 0;
4508 u32 pmc, ctrl, ctrl_ext, rctl;
4509 u16 status;
4510
4511 if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0)
4512 return;
4513
4514 /*
4515 * Determine type of Wakeup: note that wol
4516 * is set with all bits on by default.
4517 */
4518 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0)
4519 sc->wol &= ~E1000_WUFC_MAG;
4520
4521 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0)
4522 sc->wol &= ~E1000_WUFC_EX;
4523
4524 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0)
4525 sc->wol &= ~E1000_WUFC_MC;
4526 else {
4527 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
4528 rctl |= E1000_RCTL_MPE;
4529 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl);
4530 }
4531
4532 if (!(sc->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC)))
4533 goto pme;
4534
4535 /* Advertise the wakeup capability */
4536 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL);
4537 ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3);
4538 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl);
4539
4540 /* Keep the laser running on Fiber adapters */
4541 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
4542 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
4543 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
4544 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
4545 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, ctrl_ext);
4546 }
4547
4548 if ((sc->hw.mac.type == e1000_ich8lan) ||
4549 (sc->hw.mac.type == e1000_pchlan) ||
4550 (sc->hw.mac.type == e1000_ich9lan) ||
4551 (sc->hw.mac.type == e1000_ich10lan))
4552 e1000_suspend_workarounds_ich8lan(&sc->hw);
4553
4554 if ( sc->hw.mac.type >= e1000_pchlan) {
4555 error = em_enable_phy_wakeup(sc);
4556 if (error)
4557 goto pme;
4558 } else {
4559 /* Enable wakeup by the MAC */
4560 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
4561 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
4562 }
4563
4564 if (sc->hw.phy.type == e1000_phy_igp_3)
4565 e1000_igp3_phy_powerdown_workaround_ich8lan(&sc->hw);
4566
4567 pme:
4568 status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2);
4569 status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
4570 if (!error && (if_getcapenable(ifp) & IFCAP_WOL))
4571 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
4572 pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2);
4573
4574 return;
4575 }
4576
4577 /*
4578 * WOL in the newer chipset interfaces (pchlan)
4579 * require thing to be copied into the phy
4580 */
4581 static int
em_enable_phy_wakeup(struct e1000_softc * sc)4582 em_enable_phy_wakeup(struct e1000_softc *sc)
4583 {
4584 struct e1000_hw *hw = &sc->hw;
4585 u32 mreg, ret = 0;
4586 u16 preg;
4587
4588 /* copy MAC RARs to PHY RARs */
4589 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
4590
4591 /* copy MAC MTA to PHY MTA */
4592 for (int i = 0; i < hw->mac.mta_reg_count; i++) {
4593 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
4594 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF));
4595 e1000_write_phy_reg(hw, BM_MTA(i) + 1,
4596 (u16)((mreg >> 16) & 0xFFFF));
4597 }
4598
4599 /* configure PHY Rx Control register */
4600 e1000_read_phy_reg(hw, BM_RCTL, &preg);
4601 mreg = E1000_READ_REG(hw, E1000_RCTL);
4602 if (mreg & E1000_RCTL_UPE)
4603 preg |= BM_RCTL_UPE;
4604 if (mreg & E1000_RCTL_MPE)
4605 preg |= BM_RCTL_MPE;
4606 preg &= ~(BM_RCTL_MO_MASK);
4607 if (mreg & E1000_RCTL_MO_3)
4608 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
4609 << BM_RCTL_MO_SHIFT);
4610 if (mreg & E1000_RCTL_BAM)
4611 preg |= BM_RCTL_BAM;
4612 if (mreg & E1000_RCTL_PMCF)
4613 preg |= BM_RCTL_PMCF;
4614 mreg = E1000_READ_REG(hw, E1000_CTRL);
4615 if (mreg & E1000_CTRL_RFCE)
4616 preg |= BM_RCTL_RFCE;
4617 e1000_write_phy_reg(hw, BM_RCTL, preg);
4618
4619 /* enable PHY wakeup in MAC register */
4620 E1000_WRITE_REG(hw, E1000_WUC,
4621 E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME);
4622 E1000_WRITE_REG(hw, E1000_WUFC, sc->wol);
4623
4624 /* configure and enable PHY wakeup in PHY registers */
4625 e1000_write_phy_reg(hw, BM_WUFC, sc->wol);
4626 e1000_write_phy_reg(hw, BM_WUC, E1000_WUC_PME_EN);
4627
4628 /* activate PHY wakeup */
4629 ret = hw->phy.ops.acquire(hw);
4630 if (ret) {
4631 printf("Could not acquire PHY\n");
4632 return ret;
4633 }
4634 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
4635 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
4636 ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg);
4637 if (ret) {
4638 printf("Could not read PHY page 769\n");
4639 goto out;
4640 }
4641 preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
4642 ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg);
4643 if (ret)
4644 printf("Could not set PHY Host Wakeup bit\n");
4645 out:
4646 hw->phy.ops.release(hw);
4647
4648 return ret;
4649 }
4650
4651 static void
em_if_led_func(if_ctx_t ctx,int onoff)4652 em_if_led_func(if_ctx_t ctx, int onoff)
4653 {
4654 struct e1000_softc *sc = iflib_get_softc(ctx);
4655
4656 if (onoff) {
4657 e1000_setup_led(&sc->hw);
4658 e1000_led_on(&sc->hw);
4659 } else {
4660 e1000_led_off(&sc->hw);
4661 e1000_cleanup_led(&sc->hw);
4662 }
4663 }
4664
4665 /*
4666 * Disable the L0S and L1 LINK states
4667 */
4668 static void
em_disable_aspm(struct e1000_softc * sc)4669 em_disable_aspm(struct e1000_softc *sc)
4670 {
4671 int base, reg;
4672 u16 link_cap,link_ctrl;
4673 device_t dev = sc->dev;
4674
4675 switch (sc->hw.mac.type) {
4676 case e1000_82573:
4677 case e1000_82574:
4678 case e1000_82583:
4679 break;
4680 default:
4681 return;
4682 }
4683 if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0)
4684 return;
4685 reg = base + PCIER_LINK_CAP;
4686 link_cap = pci_read_config(dev, reg, 2);
4687 if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0)
4688 return;
4689 reg = base + PCIER_LINK_CTL;
4690 link_ctrl = pci_read_config(dev, reg, 2);
4691 link_ctrl &= ~PCIEM_LINK_CTL_ASPMC;
4692 pci_write_config(dev, reg, link_ctrl, 2);
4693 return;
4694 }
4695
4696 /**********************************************************************
4697 *
4698 * Update the board statistics counters.
4699 *
4700 **********************************************************************/
4701 static void
em_update_stats_counters(struct e1000_softc * sc)4702 em_update_stats_counters(struct e1000_softc *sc)
4703 {
4704 u64 prev_xoffrxc = sc->stats.xoffrxc;
4705
4706 if(sc->hw.phy.media_type == e1000_media_type_copper ||
4707 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) {
4708 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS);
4709 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC);
4710 }
4711 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS);
4712 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC);
4713 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC);
4714 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL);
4715
4716 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC);
4717 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL);
4718 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC);
4719 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC);
4720 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC);
4721 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC);
4722 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC);
4723 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC);
4724 /*
4725 ** For watchdog management we need to know if we have been
4726 ** paused during the last interval, so capture that here.
4727 */
4728 if (sc->stats.xoffrxc != prev_xoffrxc)
4729 sc->shared->isc_pause_frames = 1;
4730 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC);
4731 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC);
4732 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64);
4733 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127);
4734 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255);
4735 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511);
4736 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023);
4737 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522);
4738 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC);
4739 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC);
4740 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC);
4741 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC);
4742
4743 /* For the 64-bit byte counters the low dword must be read first. */
4744 /* Both registers clear on the read of the high dword */
4745
4746 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCL) +
4747 ((u64)E1000_READ_REG(&sc->hw, E1000_GORCH) << 32);
4748 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCL) +
4749 ((u64)E1000_READ_REG(&sc->hw, E1000_GOTCH) << 32);
4750
4751 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC);
4752 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC);
4753 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC);
4754 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC);
4755 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC);
4756
4757 sc->stats.mgprc += E1000_READ_REG(&sc->hw, E1000_MGTPRC);
4758 sc->stats.mgpdc += E1000_READ_REG(&sc->hw, E1000_MGTPDC);
4759 sc->stats.mgptc += E1000_READ_REG(&sc->hw, E1000_MGTPTC);
4760
4761 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH);
4762 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH);
4763
4764 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR);
4765 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT);
4766 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64);
4767 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127);
4768 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255);
4769 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511);
4770 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023);
4771 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522);
4772 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC);
4773 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC);
4774
4775 /* Interrupt Counts */
4776
4777 sc->stats.iac += E1000_READ_REG(&sc->hw, E1000_IAC);
4778 sc->stats.icrxptc += E1000_READ_REG(&sc->hw, E1000_ICRXPTC);
4779 sc->stats.icrxatc += E1000_READ_REG(&sc->hw, E1000_ICRXATC);
4780 sc->stats.ictxptc += E1000_READ_REG(&sc->hw, E1000_ICTXPTC);
4781 sc->stats.ictxatc += E1000_READ_REG(&sc->hw, E1000_ICTXATC);
4782 sc->stats.ictxqec += E1000_READ_REG(&sc->hw, E1000_ICTXQEC);
4783 sc->stats.ictxqmtc += E1000_READ_REG(&sc->hw, E1000_ICTXQMTC);
4784 sc->stats.icrxdmtc += E1000_READ_REG(&sc->hw, E1000_ICRXDMTC);
4785 sc->stats.icrxoc += E1000_READ_REG(&sc->hw, E1000_ICRXOC);
4786
4787 if (sc->hw.mac.type >= e1000_82543) {
4788 sc->stats.algnerrc +=
4789 E1000_READ_REG(&sc->hw, E1000_ALGNERRC);
4790 sc->stats.rxerrc +=
4791 E1000_READ_REG(&sc->hw, E1000_RXERRC);
4792 sc->stats.tncrs +=
4793 E1000_READ_REG(&sc->hw, E1000_TNCRS);
4794 sc->stats.cexterr +=
4795 E1000_READ_REG(&sc->hw, E1000_CEXTERR);
4796 sc->stats.tsctc +=
4797 E1000_READ_REG(&sc->hw, E1000_TSCTC);
4798 sc->stats.tsctfc +=
4799 E1000_READ_REG(&sc->hw, E1000_TSCTFC);
4800 }
4801 }
4802
4803 static uint64_t
em_if_get_counter(if_ctx_t ctx,ift_counter cnt)4804 em_if_get_counter(if_ctx_t ctx, ift_counter cnt)
4805 {
4806 struct e1000_softc *sc = iflib_get_softc(ctx);
4807 struct ifnet *ifp = iflib_get_ifp(ctx);
4808
4809 switch (cnt) {
4810 case IFCOUNTER_COLLISIONS:
4811 return (sc->stats.colc);
4812 case IFCOUNTER_IERRORS:
4813 return (sc->dropped_pkts + sc->stats.rxerrc +
4814 sc->stats.crcerrs + sc->stats.algnerrc +
4815 sc->stats.ruc + sc->stats.roc +
4816 sc->stats.mpc + sc->stats.cexterr);
4817 case IFCOUNTER_OERRORS:
4818 return (sc->stats.ecol + sc->stats.latecol +
4819 sc->watchdog_events);
4820 default:
4821 return (if_get_counter_default(ifp, cnt));
4822 }
4823 }
4824
4825 /* em_if_needs_restart - Tell iflib when the driver needs to be reinitialized
4826 * @ctx: iflib context
4827 * @event: event code to check
4828 *
4829 * Defaults to returning false for unknown events.
4830 *
4831 * @returns true if iflib needs to reinit the interface
4832 */
4833 static bool
em_if_needs_restart(if_ctx_t ctx __unused,enum iflib_restart_event event)4834 em_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event)
4835 {
4836 switch (event) {
4837 case IFLIB_RESTART_VLAN_CONFIG:
4838 default:
4839 return (false);
4840 }
4841 }
4842
4843 /* Export a single 32-bit register via a read-only sysctl. */
4844 static int
em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS)4845 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS)
4846 {
4847 struct e1000_softc *sc;
4848 u_int val;
4849
4850 sc = oidp->oid_arg1;
4851 val = E1000_READ_REG(&sc->hw, oidp->oid_arg2);
4852 return (sysctl_handle_int(oidp, &val, 0, req));
4853 }
4854
4855 /* Per queue holdoff interrupt rate handler */
4856 static int
em_sysctl_interrupt_rate_handler(SYSCTL_HANDLER_ARGS)4857 em_sysctl_interrupt_rate_handler(SYSCTL_HANDLER_ARGS)
4858 {
4859 struct em_rx_queue *rque;
4860 struct em_tx_queue *tque;
4861 struct e1000_hw *hw;
4862 int error;
4863 u32 reg, usec, rate;
4864
4865 bool tx = oidp->oid_arg2;
4866
4867 if (tx) {
4868 tque = oidp->oid_arg1;
4869 hw = &tque->sc->hw;
4870 if (hw->mac.type >= igb_mac_min)
4871 reg = E1000_READ_REG(hw, E1000_EITR(tque->me));
4872 else if (hw->mac.type == e1000_82574 && tque->msix)
4873 reg = E1000_READ_REG(hw, E1000_EITR_82574(tque->me));
4874 else
4875 reg = E1000_READ_REG(hw, E1000_ITR);
4876 } else {
4877 rque = oidp->oid_arg1;
4878 hw = &rque->sc->hw;
4879 if (hw->mac.type >= igb_mac_min)
4880 reg = E1000_READ_REG(hw, E1000_EITR(rque->msix));
4881 else if (hw->mac.type == e1000_82574 && rque->msix)
4882 reg = E1000_READ_REG(hw,
4883 E1000_EITR_82574(rque->msix));
4884 else
4885 reg = E1000_READ_REG(hw, E1000_ITR);
4886 }
4887
4888 if (hw->mac.type < igb_mac_min) {
4889 if (reg > 0)
4890 rate = EM_INTS_TO_ITR(reg);
4891 else
4892 rate = 0;
4893 } else {
4894 usec = (reg & IGB_QVECTOR_MASK);
4895 if (usec > 0)
4896 rate = IGB_INTS_TO_EITR(usec);
4897 else
4898 rate = 0;
4899 }
4900
4901 error = sysctl_handle_int(oidp, &rate, 0, req);
4902 if (error || !req->newptr)
4903 return error;
4904 return 0;
4905 }
4906
4907 /*
4908 * Add sysctl variables, one per statistic, to the system.
4909 */
4910 static void
em_add_hw_stats(struct e1000_softc * sc)4911 em_add_hw_stats(struct e1000_softc *sc)
4912 {
4913 device_t dev = iflib_get_dev(sc->ctx);
4914 struct em_tx_queue *tx_que = sc->tx_queues;
4915 struct em_rx_queue *rx_que = sc->rx_queues;
4916
4917 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
4918 struct sysctl_oid *tree = device_get_sysctl_tree(dev);
4919 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree);
4920 struct e1000_hw_stats *stats = &sc->stats;
4921
4922 struct sysctl_oid *stat_node, *queue_node, *int_node;
4923 struct sysctl_oid_list *stat_list, *queue_list, *int_list;
4924
4925 #define QUEUE_NAME_LEN 32
4926 char namebuf[QUEUE_NAME_LEN];
4927
4928 /* Driver Statistics */
4929 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped",
4930 CTLFLAG_RD, &sc->dropped_pkts,
4931 "Driver dropped packets");
4932 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq",
4933 CTLFLAG_RD, &sc->link_irq,
4934 "Link MSI-X IRQ Handled");
4935 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns",
4936 CTLFLAG_RD, &sc->rx_overruns,
4937 "RX overruns");
4938 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts",
4939 CTLFLAG_RD, &sc->watchdog_events,
4940 "Watchdog timeouts");
4941 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control",
4942 CTLTYPE_UINT | CTLFLAG_RD,
4943 sc, E1000_CTRL, em_sysctl_reg_handler, "IU",
4944 "Device Control Register");
4945 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control",
4946 CTLTYPE_UINT | CTLFLAG_RD,
4947 sc, E1000_RCTL, em_sysctl_reg_handler, "IU",
4948 "Receiver Control Register");
4949 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water",
4950 CTLFLAG_RD, &sc->hw.fc.high_water, 0,
4951 "Flow Control High Watermark");
4952 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water",
4953 CTLFLAG_RD, &sc->hw.fc.low_water, 0,
4954 "Flow Control Low Watermark");
4955
4956 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) {
4957 struct tx_ring *txr = &tx_que->txr;
4958 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i);
4959 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
4960 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Name");
4961 queue_list = SYSCTL_CHILDREN(queue_node);
4962
4963 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "interrupt_rate",
4964 CTLTYPE_UINT | CTLFLAG_RD, tx_que,
4965 true, em_sysctl_interrupt_rate_handler,
4966 "IU", "Interrupt Rate");
4967
4968 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head",
4969 CTLTYPE_UINT | CTLFLAG_RD, sc,
4970 E1000_TDH(txr->me), em_sysctl_reg_handler, "IU",
4971 "Transmit Descriptor Head");
4972 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail",
4973 CTLTYPE_UINT | CTLFLAG_RD, sc,
4974 E1000_TDT(txr->me), em_sysctl_reg_handler, "IU",
4975 "Transmit Descriptor Tail");
4976 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq",
4977 CTLFLAG_RD, &txr->tx_irq,
4978 "Queue MSI-X Transmit Interrupts");
4979 }
4980
4981 for (int j = 0; j < sc->rx_num_queues; j++, rx_que++) {
4982 struct rx_ring *rxr = &rx_que->rxr;
4983 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j);
4984 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
4985 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Name");
4986 queue_list = SYSCTL_CHILDREN(queue_node);
4987
4988 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "interrupt_rate",
4989 CTLTYPE_UINT | CTLFLAG_RD, rx_que,
4990 false, em_sysctl_interrupt_rate_handler,
4991 "IU", "Interrupt Rate");
4992
4993 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head",
4994 CTLTYPE_UINT | CTLFLAG_RD, sc,
4995 E1000_RDH(rxr->me), em_sysctl_reg_handler, "IU",
4996 "Receive Descriptor Head");
4997 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail",
4998 CTLTYPE_UINT | CTLFLAG_RD, sc,
4999 E1000_RDT(rxr->me), em_sysctl_reg_handler, "IU",
5000 "Receive Descriptor Tail");
5001 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq",
5002 CTLFLAG_RD, &rxr->rx_irq,
5003 "Queue MSI-X Receive Interrupts");
5004 }
5005
5006 /* MAC stats get their own sub node */
5007 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats",
5008 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics");
5009 stat_list = SYSCTL_CHILDREN(stat_node);
5010
5011 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll",
5012 CTLFLAG_RD, &stats->ecol,
5013 "Excessive collisions");
5014 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll",
5015 CTLFLAG_RD, &stats->scc,
5016 "Single collisions");
5017 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll",
5018 CTLFLAG_RD, &stats->mcc,
5019 "Multiple collisions");
5020 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll",
5021 CTLFLAG_RD, &stats->latecol,
5022 "Late collisions");
5023 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count",
5024 CTLFLAG_RD, &stats->colc,
5025 "Collision Count");
5026 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors",
5027 CTLFLAG_RD, &sc->stats.symerrs,
5028 "Symbol Errors");
5029 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors",
5030 CTLFLAG_RD, &sc->stats.sec,
5031 "Sequence Errors");
5032 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count",
5033 CTLFLAG_RD, &sc->stats.dc,
5034 "Defer Count");
5035 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets",
5036 CTLFLAG_RD, &sc->stats.mpc,
5037 "Missed Packets");
5038 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_length_errors",
5039 CTLFLAG_RD, &sc->stats.rlec,
5040 "Receive Length Errors");
5041 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff",
5042 CTLFLAG_RD, &sc->stats.rnbc,
5043 "Receive No Buffers");
5044 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize",
5045 CTLFLAG_RD, &sc->stats.ruc,
5046 "Receive Undersize");
5047 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented",
5048 CTLFLAG_RD, &sc->stats.rfc,
5049 "Fragmented Packets Received ");
5050 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize",
5051 CTLFLAG_RD, &sc->stats.roc,
5052 "Oversized Packets Received");
5053 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber",
5054 CTLFLAG_RD, &sc->stats.rjc,
5055 "Recevied Jabber");
5056 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs",
5057 CTLFLAG_RD, &sc->stats.rxerrc,
5058 "Receive Errors");
5059 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs",
5060 CTLFLAG_RD, &sc->stats.crcerrs,
5061 "CRC errors");
5062 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs",
5063 CTLFLAG_RD, &sc->stats.algnerrc,
5064 "Alignment Errors");
5065 /* On 82575 these are collision counts */
5066 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs",
5067 CTLFLAG_RD, &sc->stats.cexterr,
5068 "Collision/Carrier extension errors");
5069 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd",
5070 CTLFLAG_RD, &sc->stats.xonrxc,
5071 "XON Received");
5072 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd",
5073 CTLFLAG_RD, &sc->stats.xontxc,
5074 "XON Transmitted");
5075 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd",
5076 CTLFLAG_RD, &sc->stats.xoffrxc,
5077 "XOFF Received");
5078 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd",
5079 CTLFLAG_RD, &sc->stats.xofftxc,
5080 "XOFF Transmitted");
5081 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "unsupported_fc_recvd",
5082 CTLFLAG_RD, &sc->stats.fcruc,
5083 "Unsupported Flow Control Received");
5084 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mgmt_pkts_recvd",
5085 CTLFLAG_RD, &sc->stats.mgprc,
5086 "Management Packets Received");
5087 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mgmt_pkts_drop",
5088 CTLFLAG_RD, &sc->stats.mgpdc,
5089 "Management Packets Dropped");
5090 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mgmt_pkts_txd",
5091 CTLFLAG_RD, &sc->stats.mgptc,
5092 "Management Packets Transmitted");
5093
5094 /* Packet Reception Stats */
5095 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd",
5096 CTLFLAG_RD, &sc->stats.tpr,
5097 "Total Packets Received ");
5098 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd",
5099 CTLFLAG_RD, &sc->stats.gprc,
5100 "Good Packets Received");
5101 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd",
5102 CTLFLAG_RD, &sc->stats.bprc,
5103 "Broadcast Packets Received");
5104 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd",
5105 CTLFLAG_RD, &sc->stats.mprc,
5106 "Multicast Packets Received");
5107 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64",
5108 CTLFLAG_RD, &sc->stats.prc64,
5109 "64 byte frames received ");
5110 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127",
5111 CTLFLAG_RD, &sc->stats.prc127,
5112 "65-127 byte frames received");
5113 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255",
5114 CTLFLAG_RD, &sc->stats.prc255,
5115 "128-255 byte frames received");
5116 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511",
5117 CTLFLAG_RD, &sc->stats.prc511,
5118 "256-511 byte frames received");
5119 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023",
5120 CTLFLAG_RD, &sc->stats.prc1023,
5121 "512-1023 byte frames received");
5122 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522",
5123 CTLFLAG_RD, &sc->stats.prc1522,
5124 "1023-1522 byte frames received");
5125 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd",
5126 CTLFLAG_RD, &sc->stats.gorc,
5127 "Good Octets Received");
5128
5129 /* Packet Transmission Stats */
5130 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd",
5131 CTLFLAG_RD, &sc->stats.gotc,
5132 "Good Octets Transmitted");
5133 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd",
5134 CTLFLAG_RD, &sc->stats.tpt,
5135 "Total Packets Transmitted");
5136 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd",
5137 CTLFLAG_RD, &sc->stats.gptc,
5138 "Good Packets Transmitted");
5139 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd",
5140 CTLFLAG_RD, &sc->stats.bptc,
5141 "Broadcast Packets Transmitted");
5142 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd",
5143 CTLFLAG_RD, &sc->stats.mptc,
5144 "Multicast Packets Transmitted");
5145 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64",
5146 CTLFLAG_RD, &sc->stats.ptc64,
5147 "64 byte frames transmitted ");
5148 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127",
5149 CTLFLAG_RD, &sc->stats.ptc127,
5150 "65-127 byte frames transmitted");
5151 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255",
5152 CTLFLAG_RD, &sc->stats.ptc255,
5153 "128-255 byte frames transmitted");
5154 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511",
5155 CTLFLAG_RD, &sc->stats.ptc511,
5156 "256-511 byte frames transmitted");
5157 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023",
5158 CTLFLAG_RD, &sc->stats.ptc1023,
5159 "512-1023 byte frames transmitted");
5160 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522",
5161 CTLFLAG_RD, &sc->stats.ptc1522,
5162 "1024-1522 byte frames transmitted");
5163 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd",
5164 CTLFLAG_RD, &sc->stats.tsctc,
5165 "TSO Contexts Transmitted");
5166 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail",
5167 CTLFLAG_RD, &sc->stats.tsctfc,
5168 "TSO Contexts Failed");
5169
5170 /* Interrupt Stats */
5171 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts",
5172 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Interrupt Statistics");
5173 int_list = SYSCTL_CHILDREN(int_node);
5174
5175 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts",
5176 CTLFLAG_RD, &sc->stats.iac,
5177 "Interrupt Assertion Count");
5178
5179 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer",
5180 CTLFLAG_RD, &sc->stats.icrxptc,
5181 "Interrupt Cause Rx Pkt Timer Expire Count");
5182
5183 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer",
5184 CTLFLAG_RD, &sc->stats.icrxatc,
5185 "Interrupt Cause Rx Abs Timer Expire Count");
5186
5187 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer",
5188 CTLFLAG_RD, &sc->stats.ictxptc,
5189 "Interrupt Cause Tx Pkt Timer Expire Count");
5190
5191 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer",
5192 CTLFLAG_RD, &sc->stats.ictxatc,
5193 "Interrupt Cause Tx Abs Timer Expire Count");
5194
5195 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty",
5196 CTLFLAG_RD, &sc->stats.ictxqec,
5197 "Interrupt Cause Tx Queue Empty Count");
5198
5199 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh",
5200 CTLFLAG_RD, &sc->stats.ictxqmtc,
5201 "Interrupt Cause Tx Queue Min Thresh Count");
5202
5203 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh",
5204 CTLFLAG_RD, &sc->stats.icrxdmtc,
5205 "Interrupt Cause Rx Desc Min Thresh Count");
5206
5207 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun",
5208 CTLFLAG_RD, &sc->stats.icrxoc,
5209 "Interrupt Cause Receiver Overrun Count");
5210 }
5211
5212 static void
em_fw_version_locked(if_ctx_t ctx)5213 em_fw_version_locked(if_ctx_t ctx)
5214 {
5215 struct e1000_softc *sc = iflib_get_softc(ctx);
5216 struct e1000_hw *hw = &sc->hw;
5217 struct e1000_fw_version *fw_ver = &sc->fw_ver;
5218 uint16_t eep = 0;
5219
5220 /*
5221 * em_fw_version_locked() must run under the IFLIB_CTX_LOCK to meet
5222 * the NVM locking model, so we do it in em_if_attach_pre() and store
5223 * the info in the softc
5224 */
5225 ASSERT_CTX_LOCK_HELD(hw);
5226
5227 *fw_ver = (struct e1000_fw_version){0};
5228
5229 if (hw->mac.type >= igb_mac_min) {
5230 /*
5231 * Use the Shared Code for igb(4)
5232 */
5233 e1000_get_fw_version(hw, fw_ver);
5234 } else {
5235 /*
5236 * Otherwise, EEPROM version should be present on (almost?)
5237 * all devices here
5238 */
5239 if(e1000_read_nvm(hw, NVM_VERSION, 1, &eep)) {
5240 INIT_DEBUGOUT("can't get EEPROM version");
5241 return;
5242 }
5243
5244 fw_ver->eep_major = (eep & NVM_MAJOR_MASK) >> NVM_MAJOR_SHIFT;
5245 fw_ver->eep_minor = (eep & NVM_MINOR_MASK) >> NVM_MINOR_SHIFT;
5246 fw_ver->eep_build = (eep & NVM_IMAGE_ID_MASK);
5247 }
5248 }
5249
5250 static void
em_sbuf_fw_version(struct e1000_fw_version * fw_ver,struct sbuf * buf)5251 em_sbuf_fw_version(struct e1000_fw_version *fw_ver, struct sbuf *buf)
5252 {
5253 const char *space = "";
5254
5255 if (fw_ver->eep_major || fw_ver->eep_minor || fw_ver->eep_build) {
5256 sbuf_printf(buf, "EEPROM V%d.%d-%d", fw_ver->eep_major,
5257 fw_ver->eep_minor, fw_ver->eep_build);
5258 space = " ";
5259 }
5260
5261 if (fw_ver->invm_major || fw_ver->invm_minor ||
5262 fw_ver->invm_img_type) {
5263 sbuf_printf(buf, "%sNVM V%d.%d imgtype%d",
5264 space, fw_ver->invm_major, fw_ver->invm_minor,
5265 fw_ver->invm_img_type);
5266 space = " ";
5267 }
5268
5269 if (fw_ver->or_valid) {
5270 sbuf_printf(buf, "%sOption ROM V%d-b%d-p%d",
5271 space, fw_ver->or_major, fw_ver->or_build,
5272 fw_ver->or_patch);
5273 space = " ";
5274 }
5275
5276 if (fw_ver->etrack_id)
5277 sbuf_printf(buf, "%seTrack 0x%08x", space, fw_ver->etrack_id);
5278 }
5279
5280 static void
em_print_fw_version(struct e1000_softc * sc)5281 em_print_fw_version(struct e1000_softc *sc )
5282 {
5283 device_t dev = sc->dev;
5284 struct sbuf *buf;
5285 int error = 0;
5286
5287 buf = sbuf_new_auto();
5288 if (!buf) {
5289 device_printf(dev, "Could not allocate sbuf for output.\n");
5290 return;
5291 }
5292
5293 em_sbuf_fw_version(&sc->fw_ver, buf);
5294
5295 error = sbuf_finish(buf);
5296 if (error)
5297 device_printf(dev, "Error finishing sbuf: %d\n", error);
5298 else if (sbuf_len(buf))
5299 device_printf(dev, "%s\n", sbuf_data(buf));
5300
5301 sbuf_delete(buf);
5302 }
5303
5304 static int
em_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS)5305 em_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS)
5306 {
5307 struct e1000_softc *sc = (struct e1000_softc *)arg1;
5308 device_t dev = sc->dev;
5309 struct sbuf *buf;
5310 int error = 0;
5311
5312 buf = sbuf_new_for_sysctl(NULL, NULL, 128, req);
5313 if (!buf) {
5314 device_printf(dev, "Could not allocate sbuf for output.\n");
5315 return (ENOMEM);
5316 }
5317
5318 em_sbuf_fw_version(&sc->fw_ver, buf);
5319
5320 error = sbuf_finish(buf);
5321 if (error)
5322 device_printf(dev, "Error finishing sbuf: %d\n", error);
5323
5324 sbuf_delete(buf);
5325
5326 return (0);
5327 }
5328
5329 /**********************************************************************
5330 *
5331 * This routine provides a way to dump out the adapter eeprom,
5332 * often a useful debug/service tool. This only dumps the first
5333 * 32 words, stuff that matters is in that extent.
5334 *
5335 **********************************************************************/
5336 static int
em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS)5337 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS)
5338 {
5339 struct e1000_softc *sc = (struct e1000_softc *)arg1;
5340 int error;
5341 int result;
5342
5343 result = -1;
5344 error = sysctl_handle_int(oidp, &result, 0, req);
5345
5346 if (error || !req->newptr)
5347 return (error);
5348
5349 /*
5350 * This value will cause a hex dump of the
5351 * first 32 16-bit words of the EEPROM to
5352 * the screen.
5353 */
5354 if (result == 1)
5355 em_print_nvm_info(sc);
5356
5357 return (error);
5358 }
5359
5360 static void
em_print_nvm_info(struct e1000_softc * sc)5361 em_print_nvm_info(struct e1000_softc *sc)
5362 {
5363 struct e1000_hw *hw = &sc->hw;
5364 struct sx *iflib_ctx_lock = iflib_ctx_lock_get(sc->ctx);
5365 u16 eeprom_data;
5366 int i, j, row = 0;
5367
5368 /* Its a bit crude, but it gets the job done */
5369 printf("\nInterface EEPROM Dump:\n");
5370 printf("Offset\n0x0000 ");
5371
5372 /* We rely on the IFLIB_CTX_LOCK as part of NVM locking model */
5373 sx_xlock(iflib_ctx_lock);
5374 ASSERT_CTX_LOCK_HELD(hw);
5375 for (i = 0, j = 0; i < 32; i++, j++) {
5376 if (j == 8) { /* Make the offset block */
5377 j = 0; ++row;
5378 printf("\n0x00%x0 ",row);
5379 }
5380 e1000_read_nvm(hw, i, 1, &eeprom_data);
5381 printf("%04x ", eeprom_data);
5382 }
5383 sx_xunlock(iflib_ctx_lock);
5384 printf("\n");
5385 }
5386
5387 static int
em_sysctl_int_delay(SYSCTL_HANDLER_ARGS)5388 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
5389 {
5390 struct em_int_delay_info *info;
5391 struct e1000_softc *sc;
5392 u32 regval;
5393 int error, usecs, ticks;
5394
5395 info = (struct em_int_delay_info *) arg1;
5396 usecs = info->value;
5397 error = sysctl_handle_int(oidp, &usecs, 0, req);
5398 if (error != 0 || req->newptr == NULL)
5399 return (error);
5400 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535))
5401 return (EINVAL);
5402 info->value = usecs;
5403 ticks = EM_USECS_TO_TICKS(usecs);
5404
5405 sc = info->sc;
5406
5407 regval = E1000_READ_OFFSET(&sc->hw, info->offset);
5408 regval = (regval & ~0xffff) | (ticks & 0xffff);
5409 /* Handle a few special cases. */
5410 switch (info->offset) {
5411 case E1000_RDTR:
5412 break;
5413 case E1000_TIDV:
5414 if (ticks == 0) {
5415 sc->txd_cmd &= ~E1000_TXD_CMD_IDE;
5416 /* Don't write 0 into the TIDV register. */
5417 regval++;
5418 } else
5419 sc->txd_cmd |= E1000_TXD_CMD_IDE;
5420 break;
5421 }
5422 E1000_WRITE_OFFSET(&sc->hw, info->offset, regval);
5423 return (0);
5424 }
5425
5426 static int
em_sysctl_tso_tcp_flags_mask(SYSCTL_HANDLER_ARGS)5427 em_sysctl_tso_tcp_flags_mask(SYSCTL_HANDLER_ARGS)
5428 {
5429 struct e1000_softc *sc;
5430 u32 reg, val, shift;
5431 int error, mask;
5432
5433 sc = oidp->oid_arg1;
5434 switch (oidp->oid_arg2) {
5435 case 0:
5436 reg = E1000_DTXTCPFLGL;
5437 shift = 0;
5438 break;
5439 case 1:
5440 reg = E1000_DTXTCPFLGL;
5441 shift = 16;
5442 break;
5443 case 2:
5444 reg = E1000_DTXTCPFLGH;
5445 shift = 0;
5446 break;
5447 default:
5448 return (EINVAL);
5449 break;
5450 }
5451 val = E1000_READ_REG(&sc->hw, reg);
5452 mask = (val >> shift) & 0xfff;
5453 error = sysctl_handle_int(oidp, &mask, 0, req);
5454 if (error != 0 || req->newptr == NULL)
5455 return (error);
5456 if (mask < 0 || mask > 0xfff)
5457 return (EINVAL);
5458 val = (val & ~(0xfff << shift)) | (mask << shift);
5459 E1000_WRITE_REG(&sc->hw, reg, val);
5460 return (0);
5461 }
5462
5463 static void
em_add_int_delay_sysctl(struct e1000_softc * sc,const char * name,const char * description,struct em_int_delay_info * info,int offset,int value)5464 em_add_int_delay_sysctl(struct e1000_softc *sc, const char *name,
5465 const char *description, struct em_int_delay_info *info, int offset,
5466 int value)
5467 {
5468 info->sc = sc;
5469 info->offset = offset;
5470 info->value = value;
5471 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev),
5472 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)),
5473 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
5474 info, 0, em_sysctl_int_delay, "I", description);
5475 }
5476
5477 /*
5478 * Set flow control using sysctl:
5479 * Flow control values:
5480 * 0 - off
5481 * 1 - rx pause
5482 * 2 - tx pause
5483 * 3 - full
5484 */
5485 static int
em_set_flowcntl(SYSCTL_HANDLER_ARGS)5486 em_set_flowcntl(SYSCTL_HANDLER_ARGS)
5487 {
5488 int error;
5489 static int input = 3; /* default is full */
5490 struct e1000_softc *sc = (struct e1000_softc *) arg1;
5491
5492 error = sysctl_handle_int(oidp, &input, 0, req);
5493
5494 if ((error) || (req->newptr == NULL))
5495 return (error);
5496
5497 if (input == sc->fc) /* no change? */
5498 return (error);
5499
5500 switch (input) {
5501 case e1000_fc_rx_pause:
5502 case e1000_fc_tx_pause:
5503 case e1000_fc_full:
5504 case e1000_fc_none:
5505 sc->hw.fc.requested_mode = input;
5506 sc->fc = input;
5507 break;
5508 default:
5509 /* Do nothing */
5510 return (error);
5511 }
5512
5513 sc->hw.fc.current_mode = sc->hw.fc.requested_mode;
5514 e1000_force_mac_fc(&sc->hw);
5515 return (error);
5516 }
5517
5518 /*
5519 * Manage DMA Coalesce:
5520 * Control values:
5521 * 0/1 - off/on
5522 * Legal timer values are:
5523 * 250,500,1000-10000 in thousands
5524 */
5525 static int
igb_sysctl_dmac(SYSCTL_HANDLER_ARGS)5526 igb_sysctl_dmac(SYSCTL_HANDLER_ARGS)
5527 {
5528 struct e1000_softc *sc = (struct e1000_softc *) arg1;
5529 int error;
5530
5531 error = sysctl_handle_int(oidp, &sc->dmac, 0, req);
5532
5533 if ((error) || (req->newptr == NULL))
5534 return (error);
5535
5536 switch (sc->dmac) {
5537 case 0:
5538 /* Disabling */
5539 break;
5540 case 1: /* Just enable and use default */
5541 sc->dmac = 1000;
5542 break;
5543 case 250:
5544 case 500:
5545 case 1000:
5546 case 2000:
5547 case 3000:
5548 case 4000:
5549 case 5000:
5550 case 6000:
5551 case 7000:
5552 case 8000:
5553 case 9000:
5554 case 10000:
5555 /* Legal values - allow */
5556 break;
5557 default:
5558 /* Do nothing, illegal value */
5559 sc->dmac = 0;
5560 return (EINVAL);
5561 }
5562 /* Reinit the interface */
5563 em_if_init(sc->ctx);
5564 return (error);
5565 }
5566
5567 /*
5568 * Manage Energy Efficient Ethernet:
5569 * Control values:
5570 * 0/1 - enabled/disabled
5571 */
5572 static int
em_sysctl_eee(SYSCTL_HANDLER_ARGS)5573 em_sysctl_eee(SYSCTL_HANDLER_ARGS)
5574 {
5575 struct e1000_softc *sc = (struct e1000_softc *) arg1;
5576 int error, value;
5577
5578 if (sc->hw.mac.type < igb_mac_min)
5579 value = sc->hw.dev_spec.ich8lan.eee_disable;
5580 else
5581 value = sc->hw.dev_spec._82575.eee_disable;
5582 error = sysctl_handle_int(oidp, &value, 0, req);
5583 if (error || req->newptr == NULL)
5584 return (error);
5585 if (sc->hw.mac.type < igb_mac_min)
5586 sc->hw.dev_spec.ich8lan.eee_disable = (value != 0);
5587 else
5588 sc->hw.dev_spec._82575.eee_disable = (value != 0);
5589 em_if_init(sc->ctx);
5590
5591 return (0);
5592 }
5593
5594 static int
em_sysctl_debug_info(SYSCTL_HANDLER_ARGS)5595 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
5596 {
5597 struct e1000_softc *sc;
5598 int error;
5599 int result;
5600
5601 result = -1;
5602 error = sysctl_handle_int(oidp, &result, 0, req);
5603
5604 if (error || !req->newptr)
5605 return (error);
5606
5607 if (result == 1) {
5608 sc = (struct e1000_softc *) arg1;
5609 em_print_debug_info(sc);
5610 }
5611
5612 return (error);
5613 }
5614
5615 static int
em_get_rs(SYSCTL_HANDLER_ARGS)5616 em_get_rs(SYSCTL_HANDLER_ARGS)
5617 {
5618 struct e1000_softc *sc = (struct e1000_softc *) arg1;
5619 int error;
5620 int result;
5621
5622 result = 0;
5623 error = sysctl_handle_int(oidp, &result, 0, req);
5624
5625 if (error || !req->newptr || result != 1)
5626 return (error);
5627 em_dump_rs(sc);
5628
5629 return (error);
5630 }
5631
5632 static void
em_if_debug(if_ctx_t ctx)5633 em_if_debug(if_ctx_t ctx)
5634 {
5635 em_dump_rs(iflib_get_softc(ctx));
5636 }
5637
5638 /*
5639 * This routine is meant to be fluid, add whatever is
5640 * needed for debugging a problem. -jfv
5641 */
5642 static void
em_print_debug_info(struct e1000_softc * sc)5643 em_print_debug_info(struct e1000_softc *sc)
5644 {
5645 device_t dev = iflib_get_dev(sc->ctx);
5646 struct ifnet *ifp = iflib_get_ifp(sc->ctx);
5647 struct tx_ring *txr = &sc->tx_queues->txr;
5648 struct rx_ring *rxr = &sc->rx_queues->rxr;
5649
5650 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
5651 printf("Interface is RUNNING ");
5652 else
5653 printf("Interface is NOT RUNNING\n");
5654
5655 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE)
5656 printf("and INACTIVE\n");
5657 else
5658 printf("and ACTIVE\n");
5659
5660 for (int i = 0; i < sc->tx_num_queues; i++, txr++) {
5661 device_printf(dev, "TX Queue %d ------\n", i);
5662 device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
5663 E1000_READ_REG(&sc->hw, E1000_TDH(i)),
5664 E1000_READ_REG(&sc->hw, E1000_TDT(i)));
5665
5666 }
5667 for (int j=0; j < sc->rx_num_queues; j++, rxr++) {
5668 device_printf(dev, "RX Queue %d ------\n", j);
5669 device_printf(dev, "hw rdh = %d, hw rdt = %d\n",
5670 E1000_READ_REG(&sc->hw, E1000_RDH(j)),
5671 E1000_READ_REG(&sc->hw, E1000_RDT(j)));
5672 }
5673 }
5674
5675 /*
5676 * 82574 only:
5677 * Write a new value to the EEPROM increasing the number of MSI-X
5678 * vectors from 3 to 5, for proper multiqueue support.
5679 */
5680 static void
em_enable_vectors_82574(if_ctx_t ctx)5681 em_enable_vectors_82574(if_ctx_t ctx)
5682 {
5683 struct e1000_softc *sc = iflib_get_softc(ctx);
5684 struct e1000_hw *hw = &sc->hw;
5685 device_t dev = iflib_get_dev(ctx);
5686 u16 edata;
5687
5688 e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata);
5689 if (bootverbose)
5690 device_printf(dev, "EM_NVM_PCIE_CTRL = %#06x\n", edata);
5691 if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) {
5692 device_printf(dev, "Writing to eeprom: increasing "
5693 "reported MSI-X vectors from 3 to 5...\n");
5694 edata &= ~(EM_NVM_MSIX_N_MASK);
5695 edata |= 4 << EM_NVM_MSIX_N_SHIFT;
5696 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata);
5697 e1000_update_nvm_checksum(hw);
5698 device_printf(dev, "Writing to eeprom: done\n");
5699 }
5700 }
5701