1 /*
2 * Copyright (C) 2015 Alexander Kabaev
3 * Copyright (C) 2010 Andrew Turner
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 /* A driver for the Davicom DM9000 MAC. */
29
30 #include <sys/cdefs.h>
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/module.h>
35 #include <sys/bus.h>
36 #include <sys/lock.h>
37 #include <sys/mbuf.h>
38 #include <sys/mutex.h>
39 #include <sys/rman.h>
40 #include <sys/socket.h>
41 #include <sys/sockio.h>
42 #include <sys/gpio.h>
43
44 #include <machine/bus.h>
45 #include <machine/resource.h>
46
47 #include <net/if.h>
48 #include <net/if_arp.h>
49 #include <net/if_dl.h>
50 #include <net/if_media.h>
51 #include <net/if_types.h>
52 #include <net/ethernet.h>
53 #include <net/bpf.h>
54
55 #include <dev/mii/mii.h>
56 #include <dev/mii/miivar.h>
57
58 #include <dev/dme/if_dmereg.h>
59 #include <dev/dme/if_dmevar.h>
60
61 #include <dev/ofw/ofw_bus.h>
62 #include <dev/ofw/ofw_bus_subr.h>
63
64 #include <dev/extres/regulator/regulator.h>
65 #include <dev/gpio/gpiobusvar.h>
66
67 #include "miibus_if.h"
68
69 struct dme_softc {
70 struct ifnet *dme_ifp;
71 device_t dme_dev;
72 device_t dme_miibus;
73 bus_space_handle_t dme_handle;
74 bus_space_tag_t dme_tag;
75 int dme_rev;
76 int dme_bits;
77 struct resource *dme_res;
78 struct resource *dme_irq;
79 void *dme_intrhand;
80 struct mtx dme_mtx;
81 struct callout dme_tick_ch;
82 struct gpiobus_pin *gpio_rset;
83 uint32_t dme_ticks;
84 uint8_t dme_macaddr[ETHER_ADDR_LEN];
85 regulator_t dme_vcc_regulator;
86 uint8_t dme_txbusy: 1;
87 uint8_t dme_txready: 1;
88 uint16_t dme_txlen;
89 };
90
91 #define DME_CHIP_DM9000 0x00
92 #define DME_CHIP_DM9000A 0x19
93 #define DME_CHIP_DM9000B 0x1a
94
95 #define DME_INT_PHY 1
96
97 static int dme_probe(device_t);
98 static int dme_attach(device_t);
99 static int dme_detach(device_t);
100
101 static void dme_intr(void *arg);
102 static void dme_init_locked(struct dme_softc *);
103
104 static void dme_prepare(struct dme_softc *);
105 static void dme_transmit(struct dme_softc *);
106
107 static int dme_miibus_writereg(device_t dev, int phy, int reg, int data);
108 static int dme_miibus_readreg(device_t dev, int phy, int reg);
109
110 /* The bit on the address bus attached to the CMD pin */
111 #define BASE_ADDR 0x000
112 #define CMD_ADDR BASE_ADDR
113 #define DATA_BIT 1
114 #define DATA_ADDR 0x002
115
116 #undef DME_TRACE
117
118 #ifdef DME_TRACE
119 #define DTR3 TR3
120 #define DTR4 TR4
121 #else
122 #define NOTR(args...) (void)0
123 #define DTR3 NOTR
124 #define DTR4 NOTR
125 #endif
126
127 static uint8_t
dme_read_reg(struct dme_softc * sc,uint8_t reg)128 dme_read_reg(struct dme_softc *sc, uint8_t reg)
129 {
130
131 /* Send the register to read from */
132 bus_space_write_1(sc->dme_tag, sc->dme_handle, CMD_ADDR, reg);
133 bus_space_barrier(sc->dme_tag, sc->dme_handle, CMD_ADDR, 1,
134 BUS_SPACE_BARRIER_WRITE);
135
136 /* Get the value of the register */
137 return bus_space_read_1(sc->dme_tag, sc->dme_handle, DATA_ADDR);
138 }
139
140 static void
dme_write_reg(struct dme_softc * sc,uint8_t reg,uint8_t value)141 dme_write_reg(struct dme_softc *sc, uint8_t reg, uint8_t value)
142 {
143
144 /* Send the register to write to */
145 bus_space_write_1(sc->dme_tag, sc->dme_handle, CMD_ADDR, reg);
146 bus_space_barrier(sc->dme_tag, sc->dme_handle, CMD_ADDR, 1,
147 BUS_SPACE_BARRIER_WRITE);
148
149 /* Write the value to the register */
150 bus_space_write_1(sc->dme_tag, sc->dme_handle, DATA_ADDR, value);
151 bus_space_barrier(sc->dme_tag, sc->dme_handle, DATA_ADDR, 1,
152 BUS_SPACE_BARRIER_WRITE);
153 }
154
155 static void
dme_reset(struct dme_softc * sc)156 dme_reset(struct dme_softc *sc)
157 {
158 u_int ncr;
159
160 /* Send a soft reset #1 */
161 dme_write_reg(sc, DME_NCR, NCR_RST | NCR_LBK_MAC);
162 DELAY(100); /* Wait for the MAC to reset */
163 ncr = dme_read_reg(sc, DME_NCR);
164 if (ncr & NCR_RST)
165 device_printf(sc->dme_dev, "device did not complete first reset\n");
166
167 /* Send a soft reset #2 per Application Notes v1.22 */
168 dme_write_reg(sc, DME_NCR, 0);
169 dme_write_reg(sc, DME_NCR, NCR_RST | NCR_LBK_MAC);
170 DELAY(100); /* Wait for the MAC to reset */
171 ncr = dme_read_reg(sc, DME_NCR);
172 if (ncr & NCR_RST)
173 device_printf(sc->dme_dev, "device did not complete second reset\n");
174
175 /* Reset trasmit state */
176 sc->dme_txbusy = 0;
177 sc->dme_txready = 0;
178
179 DTR3("dme_reset, flags %#x busy %d ready %d",
180 sc->dme_ifp ? sc->dme_ifp->if_drv_flags : 0,
181 sc->dme_txbusy, sc->dme_txready);
182 }
183
184 /*
185 * Parse string MAC address into usable form
186 */
187 static int
dme_parse_macaddr(const char * str,uint8_t * mac)188 dme_parse_macaddr(const char *str, uint8_t *mac)
189 {
190 int count, i;
191 unsigned int amac[ETHER_ADDR_LEN]; /* Aligned version */
192
193 count = sscanf(str, "%x%*c%x%*c%x%*c%x%*c%x%*c%x",
194 &amac[0], &amac[1], &amac[2],
195 &amac[3], &amac[4], &amac[5]);
196 if (count < ETHER_ADDR_LEN) {
197 memset(mac, 0, ETHER_ADDR_LEN);
198 return (1);
199 }
200
201 /* Copy aligned to result */
202 for (i = 0; i < ETHER_ADDR_LEN; i ++)
203 mac[i] = (amac[i] & 0xff);
204
205 return (0);
206 }
207
208 /*
209 * Try to determine our own MAC address
210 */
211 static void
dme_get_macaddr(struct dme_softc * sc)212 dme_get_macaddr(struct dme_softc *sc)
213 {
214 char devid_str[32];
215 char *var;
216 int i;
217
218 /* Cannot use resource_string_value with static hints mode */
219 snprintf(devid_str, 32, "hint.%s.%d.macaddr",
220 device_get_name(sc->dme_dev),
221 device_get_unit(sc->dme_dev));
222
223 /* Try resource hints */
224 if ((var = kern_getenv(devid_str)) != NULL) {
225 if (!dme_parse_macaddr(var, sc->dme_macaddr)) {
226 device_printf(sc->dme_dev, "MAC address: %s (hints)\n", var);
227 return;
228 }
229 }
230
231 /*
232 * Try to read MAC address from the device, in case U-Boot has
233 * pre-programmed one for us.
234 */
235 for (i = 0; i < ETHER_ADDR_LEN; i++)
236 sc->dme_macaddr[i] = dme_read_reg(sc, DME_PAR(i));
237
238 device_printf(sc->dme_dev, "MAC address %6D (existing)\n",
239 sc->dme_macaddr, ":");
240 }
241
242 static void
dme_config(struct dme_softc * sc)243 dme_config(struct dme_softc *sc)
244 {
245 int i;
246
247 /* Mask all interrupts and reset receive pointer */
248 dme_write_reg(sc, DME_IMR, IMR_PAR);
249
250 /* Disable GPIO0 to enable the internal PHY */
251 dme_write_reg(sc, DME_GPCR, 1);
252 dme_write_reg(sc, DME_GPR, 0);
253
254 #if 0
255 /*
256 * Supposedly requires special initialization for DSP PHYs
257 * used by DM9000B. Maybe belongs in dedicated PHY driver?
258 */
259 if (sc->dme_rev == DME_CHIP_DM9000B) {
260 dme_miibus_writereg(sc->dme_dev, DME_INT_PHY, MII_BMCR,
261 BMCR_RESET);
262 dme_miibus_writereg(sc->dme_dev, DME_INT_PHY, MII_DME_DSPCR,
263 DSPCR_INIT);
264 /* Wait 100ms for it to complete. */
265 for (i = 0; i < 100; i++) {
266 int reg;
267
268 reg = dme_miibus_readreg(sc->dme_dev, DME_INT_PHY, MII_BMCR);
269 if ((reg & BMCR_RESET) == 0)
270 break;
271 DELAY(1000);
272 }
273 }
274 #endif
275
276 /* Select the internal PHY and normal loopback */
277 dme_write_reg(sc, DME_NCR, NCR_LBK_NORMAL);
278 /* Clear any TX requests */
279 dme_write_reg(sc, DME_TCR, 0);
280 /* Setup backpressure thresholds to 4k and 600us */
281 dme_write_reg(sc, DME_BPTR, BPTR_BPHW(3) | BPTR_JPT(0x0f));
282 /* Setup flow control */
283 dme_write_reg(sc, DME_FCTR, FCTR_HWOT(0x3) | FCTR_LWOT(0x08));
284 /* Enable flow control */
285 dme_write_reg(sc, DME_FCR, 0xff);
286 /* Clear special modes */
287 dme_write_reg(sc, DME_SMCR, 0);
288 /* Clear TX status */
289 dme_write_reg(sc, DME_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END);
290 /* Clear interrrupts */
291 dme_write_reg(sc, DME_ISR, 0xff);
292 /* Set multicast address filter */
293 for (i = 0; i < 8; i++)
294 dme_write_reg(sc, DME_MAR(i), 0xff);
295 /* Set the MAC address */
296 for (i = 0; i < ETHER_ADDR_LEN; i++)
297 dme_write_reg(sc, DME_PAR(i), sc->dme_macaddr[i]);
298 /* Enable the RX buffer */
299 dme_write_reg(sc, DME_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN);
300
301 /* Enable interrupts we care about */
302 dme_write_reg(sc, DME_IMR, IMR_PAR | IMR_PRI | IMR_PTI);
303 }
304
305 void
dme_prepare(struct dme_softc * sc)306 dme_prepare(struct dme_softc *sc)
307 {
308 struct ifnet *ifp;
309 struct mbuf *m, *mp;
310 uint16_t total_len, len;
311
312 DME_ASSERT_LOCKED(sc);
313
314 KASSERT(sc->dme_txready == 0,
315 ("dme_prepare: called with txready set\n"));
316
317 ifp = sc->dme_ifp;
318 IFQ_DEQUEUE(&ifp->if_snd, m);
319 if (m == NULL) {
320 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
321 DTR3("dme_prepare none, flags %#x busy %d ready %d",
322 sc->dme_ifp->if_drv_flags, sc->dme_txbusy, sc->dme_txready);
323 return; /* Nothing to transmit */
324 }
325
326 /* Element has now been removed from the queue, so we better send it */
327 BPF_MTAP(ifp, m);
328
329 /* Setup the controller to accept the writes */
330 bus_space_write_1(sc->dme_tag, sc->dme_handle, CMD_ADDR, DME_MWCMD);
331
332 /*
333 * TODO: Fix the case where an mbuf is
334 * not a multiple of the write size.
335 */
336 total_len = 0;
337 for (mp = m; mp != NULL; mp = mp->m_next) {
338 len = mp->m_len;
339
340 /* Ignore empty parts */
341 if (len == 0)
342 continue;
343
344 total_len += len;
345
346 #if 0
347 bus_space_write_multi_2(sc->dme_tag, sc->dme_handle,
348 DATA_ADDR, mtod(mp, uint16_t *), (len + 1) / 2);
349 #else
350 bus_space_write_multi_1(sc->dme_tag, sc->dme_handle,
351 DATA_ADDR, mtod(mp, uint8_t *), len);
352 #endif
353 }
354
355 if (total_len % (sc->dme_bits >> 3) != 0)
356 panic("dme_prepare: length is not compatible with IO_MODE");
357
358 sc->dme_txlen = total_len;
359 sc->dme_txready = 1;
360 DTR3("dme_prepare done, flags %#x busy %d ready %d",
361 sc->dme_ifp->if_drv_flags, sc->dme_txbusy, sc->dme_txready);
362
363 m_freem(m);
364 }
365
366 void
dme_transmit(struct dme_softc * sc)367 dme_transmit(struct dme_softc *sc)
368 {
369
370 DME_ASSERT_LOCKED(sc);
371 KASSERT(sc->dme_txready, ("transmit without txready"));
372
373 dme_write_reg(sc, DME_TXPLL, sc->dme_txlen & 0xff);
374 dme_write_reg(sc, DME_TXPLH, (sc->dme_txlen >> 8) & 0xff );
375
376 /* Request to send the packet */
377 dme_read_reg(sc, DME_ISR);
378
379 dme_write_reg(sc, DME_TCR, TCR_TXREQ);
380
381 sc->dme_txready = 0;
382 sc->dme_txbusy = 1;
383 DTR3("dme_transmit done, flags %#x busy %d ready %d",
384 sc->dme_ifp->if_drv_flags, sc->dme_txbusy, sc->dme_txready);
385 }
386
387
388 static void
dme_start_locked(struct ifnet * ifp)389 dme_start_locked(struct ifnet *ifp)
390 {
391 struct dme_softc *sc;
392
393 sc = ifp->if_softc;
394 DME_ASSERT_LOCKED(sc);
395
396 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
397 IFF_DRV_RUNNING)
398 return;
399
400 DTR3("dme_start, flags %#x busy %d ready %d",
401 sc->dme_ifp->if_drv_flags, sc->dme_txbusy, sc->dme_txready);
402 KASSERT(sc->dme_txbusy == 0 || sc->dme_txready == 0,
403 ("dme: send without empty queue\n"));
404
405 dme_prepare(sc);
406
407 if (sc->dme_txbusy == 0) {
408 /* We are ready to transmit right away */
409 dme_transmit(sc);
410 dme_prepare(sc); /* Prepare next one */
411 }
412 /*
413 * We need to wait until the current packet has
414 * been transmitted.
415 */
416 if (sc->dme_txready != 0)
417 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
418 }
419
420 static void
dme_start(struct ifnet * ifp)421 dme_start(struct ifnet *ifp)
422 {
423 struct dme_softc *sc;
424
425 sc = ifp->if_softc;
426 DME_LOCK(sc);
427 dme_start_locked(ifp);
428 DME_UNLOCK(sc);
429 }
430
431 static void
dme_stop(struct dme_softc * sc)432 dme_stop(struct dme_softc *sc)
433 {
434 struct ifnet *ifp;
435
436 DME_ASSERT_LOCKED(sc);
437 /* Disable receiver */
438 dme_write_reg(sc, DME_RCR, 0x00);
439 /* Mask interrupts */
440 dme_write_reg(sc, DME_IMR, 0x00);
441 /* Stop poll */
442 callout_stop(&sc->dme_tick_ch);
443
444 ifp = sc->dme_ifp;
445 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
446
447 DTR3("dme_stop, flags %#x busy %d ready %d",
448 sc->dme_ifp->if_drv_flags, sc->dme_txbusy, sc->dme_txready);
449 sc->dme_txbusy = 0;
450 sc->dme_txready = 0;
451 }
452
453 static int
dme_rxeof(struct dme_softc * sc)454 dme_rxeof(struct dme_softc *sc)
455 {
456 struct ifnet *ifp;
457 struct mbuf *m;
458 int len, i;
459
460 DME_ASSERT_LOCKED(sc);
461
462 ifp = sc->dme_ifp;
463
464 /* Read the first byte to check it correct */
465 (void)dme_read_reg(sc, DME_MRCMDX);
466 i = bus_space_read_1(sc->dme_tag, sc->dme_handle, DATA_ADDR);
467 switch(bus_space_read_1(sc->dme_tag, sc->dme_handle, DATA_ADDR)) {
468 case 1:
469 /* Correct value */
470 break;
471 case 0:
472 return 1;
473 default:
474 /* Error */
475 return -1;
476 }
477
478 i = dme_read_reg(sc, DME_MRRL);
479 i |= dme_read_reg(sc, DME_MRRH) << 8;
480
481 len = dme_read_reg(sc, DME_ROCR);
482
483 bus_space_write_1(sc->dme_tag, sc->dme_handle, CMD_ADDR, DME_MRCMD);
484 len = 0;
485 switch(sc->dme_bits) {
486 case 8:
487 i = bus_space_read_1(sc->dme_tag, sc->dme_handle, DATA_ADDR);
488 i <<= 8;
489 i |= bus_space_read_1(sc->dme_tag, sc->dme_handle, DATA_ADDR);
490
491 len = bus_space_read_1(sc->dme_tag, sc->dme_handle, DATA_ADDR);
492 len |= bus_space_read_1(sc->dme_tag, sc->dme_handle,
493 DATA_ADDR) << 8;
494 break;
495 case 16:
496 bus_space_read_2(sc->dme_tag, sc->dme_handle, DATA_ADDR);
497 len = bus_space_read_2(sc->dme_tag, sc->dme_handle, DATA_ADDR);
498 break;
499 case 32:
500 {
501 uint32_t reg;
502
503 reg = bus_space_read_4(sc->dme_tag, sc->dme_handle, DATA_ADDR);
504 len = reg & 0xFFFF;
505 break;
506 }
507 }
508
509 MGETHDR(m, M_NOWAIT, MT_DATA);
510 if (m == NULL)
511 return -1;
512
513 if (len > MHLEN - ETHER_ALIGN) {
514 MCLGET(m, M_NOWAIT);
515 if (!(m->m_flags & M_EXT)) {
516 m_freem(m);
517 return -1;
518 }
519 }
520
521 m->m_pkthdr.rcvif = ifp;
522 m->m_len = m->m_pkthdr.len = len;
523 m_adj(m, ETHER_ALIGN);
524
525 /* Read the data */
526 #if 0
527 bus_space_read_multi_2(sc->dme_tag, sc->dme_handle, DATA_ADDR,
528 mtod(m, uint16_t *), (len + 1) / 2);
529 #else
530 bus_space_read_multi_1(sc->dme_tag, sc->dme_handle, DATA_ADDR,
531 mtod(m, uint8_t *), len);
532 #endif
533 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
534 DME_UNLOCK(sc);
535 (*ifp->if_input)(ifp, m);
536 DME_LOCK(sc);
537
538 return 0;
539 }
540
541 static void
dme_tick(void * arg)542 dme_tick(void *arg)
543 {
544 struct dme_softc *sc;
545 struct mii_data *mii;
546
547 sc = (struct dme_softc *)arg;
548
549 /* Probably too frequent? */
550 mii = device_get_softc(sc->dme_miibus);
551 mii_tick(mii);
552
553 callout_reset(&sc->dme_tick_ch, hz, dme_tick, sc);
554 }
555
556 static void
dme_intr(void * arg)557 dme_intr(void *arg)
558 {
559 struct dme_softc *sc;
560 uint32_t intr_status;
561
562 sc = (struct dme_softc *)arg;
563
564 DME_LOCK(sc);
565
566 intr_status = dme_read_reg(sc, DME_ISR);
567 dme_write_reg(sc, DME_ISR, intr_status);
568
569 DTR4("dme_intr flags %#x busy %d ready %d intr %#x",
570 sc->dme_ifp->if_drv_flags, sc->dme_txbusy,
571 sc->dme_txready, intr_status);
572
573 if (intr_status & ISR_PT) {
574 uint8_t nsr, tx_status;
575
576 sc->dme_txbusy = 0;
577
578 nsr = dme_read_reg(sc, DME_NSR);
579
580 if (nsr & NSR_TX1END)
581 tx_status = dme_read_reg(sc, DME_TSR1);
582 else if (nsr & NSR_TX2END)
583 tx_status = dme_read_reg(sc, DME_TSR2);
584 else
585 tx_status = 1;
586
587 DTR4("dme_intr flags %#x busy %d ready %d nsr %#x",
588 sc->dme_ifp->if_drv_flags, sc->dme_txbusy,
589 sc->dme_txready, nsr);
590
591 /* Prepare packet to send if none is currently pending */
592 if (sc->dme_txready == 0)
593 dme_prepare(sc);
594 /* Send the packet out of one is waiting for transmit */
595 if (sc->dme_txready != 0) {
596 /* Initiate transmission of the prepared packet */
597 dme_transmit(sc);
598 /* Prepare next packet to send */
599 dme_prepare(sc);
600 /*
601 * We need to wait until the current packet has
602 * been transmitted.
603 */
604 if (sc->dme_txready != 0)
605 sc->dme_ifp->if_drv_flags |= IFF_DRV_OACTIVE;
606 }
607 }
608
609 if (intr_status & ISR_PR) {
610 /* Read the packets off the device */
611 while (dme_rxeof(sc) == 0)
612 continue;
613 }
614 DME_UNLOCK(sc);
615 }
616
617 static void
dme_setmode(struct dme_softc * sc)618 dme_setmode(struct dme_softc *sc)
619 {
620 }
621
622 static int
dme_ioctl(struct ifnet * ifp,u_long command,caddr_t data)623 dme_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
624 {
625 struct dme_softc *sc;
626 struct mii_data *mii;
627 struct ifreq *ifr;
628 int error = 0;
629
630 sc = ifp->if_softc;
631 ifr = (struct ifreq *)data;
632
633 switch (command) {
634 case SIOCSIFFLAGS:
635 /*
636 * Switch interface state between "running" and
637 * "stopped", reflecting the UP flag.
638 */
639 DME_LOCK(sc);
640 if (ifp->if_flags & IFF_UP) {
641 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
642 dme_init_locked(sc);
643 }
644 } else {
645 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
646 dme_stop(sc);
647 }
648 }
649 dme_setmode(sc);
650 DME_UNLOCK(sc);
651 break;
652 case SIOCGIFMEDIA:
653 case SIOCSIFMEDIA:
654 mii = device_get_softc(sc->dme_miibus);
655 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
656 break;
657 default:
658 error = ether_ioctl(ifp, command, data);
659 break;
660 }
661 return (error);
662 }
663
dme_init_locked(struct dme_softc * sc)664 static void dme_init_locked(struct dme_softc *sc)
665 {
666 struct ifnet *ifp = sc->dme_ifp;
667
668 DME_ASSERT_LOCKED(sc);
669
670 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
671 return;
672
673 dme_reset(sc);
674 dme_config(sc);
675
676 ifp->if_drv_flags |= IFF_DRV_RUNNING;
677 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
678
679 callout_reset(&sc->dme_tick_ch, hz, dme_tick, sc);
680 }
681
682 static void
dme_init(void * xcs)683 dme_init(void *xcs)
684 {
685 struct dme_softc *sc = xcs;
686
687 DME_LOCK(sc);
688 dme_init_locked(sc);
689 DME_UNLOCK(sc);
690 }
691
692 static int
dme_ifmedia_upd(struct ifnet * ifp)693 dme_ifmedia_upd(struct ifnet *ifp)
694 {
695 struct dme_softc *sc;
696 struct mii_data *mii;
697
698 sc = ifp->if_softc;
699 mii = device_get_softc(sc->dme_miibus);
700
701 DME_LOCK(sc);
702 mii_mediachg(mii);
703 DME_UNLOCK(sc);
704
705 return (0);
706 }
707
708 static void
dme_ifmedia_sts(struct ifnet * ifp,struct ifmediareq * ifmr)709 dme_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
710 {
711 struct dme_softc *sc;
712 struct mii_data *mii;
713
714 sc = ifp->if_softc;
715 mii = device_get_softc(sc->dme_miibus);
716
717 DME_LOCK(sc);
718 mii_pollstat(mii);
719 ifmr->ifm_active = mii->mii_media_active;
720 ifmr->ifm_status = mii->mii_media_status;
721 DME_UNLOCK(sc);
722 }
723
724 static struct ofw_compat_data compat_data[] = {
725 { "davicom,dm9000", true },
726 { NULL, false }
727 };
728
729 static int
dme_probe(device_t dev)730 dme_probe(device_t dev)
731 {
732 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
733 return (ENXIO);
734 device_set_desc(dev, "Davicom DM9000");
735 return (0);
736 }
737
738 static int
dme_attach(device_t dev)739 dme_attach(device_t dev)
740 {
741 struct dme_softc *sc;
742 struct ifnet *ifp;
743 int error, rid;
744 uint32_t data;
745
746 sc = device_get_softc(dev);
747 sc->dme_dev = dev;
748
749 error = 0;
750
751 mtx_init(&sc->dme_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
752 MTX_DEF);
753 callout_init_mtx(&sc->dme_tick_ch, &sc->dme_mtx, 0);
754
755 rid = 0;
756 sc->dme_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
757 RF_ACTIVE);
758 if (sc->dme_res == NULL) {
759 device_printf(dev, "unable to map memory\n");
760 error = ENXIO;
761 goto fail;
762 }
763
764 rid = 0;
765 sc->dme_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
766 RF_ACTIVE);
767 if (sc->dme_irq == NULL) {
768 device_printf(dev, "unable to map memory\n");
769 error = ENXIO;
770 goto fail;
771 }
772 /*
773 * Power the chip up, if necessary
774 */
775 error = regulator_get_by_ofw_property(dev, 0, "vcc-supply", &sc->dme_vcc_regulator);
776 if (error == 0) {
777 error = regulator_enable(sc->dme_vcc_regulator);
778 if (error != 0) {
779 device_printf(dev, "unable to enable power supply\n");
780 error = ENXIO;
781 goto fail;
782 }
783 }
784
785 /*
786 * Delay a little. This seems required on rev-1 boards (green.)
787 */
788 DELAY(100000);
789
790 /* Bring controller out of reset */
791 error = ofw_gpiobus_parse_gpios(dev, "reset-gpios", &sc->gpio_rset);
792 if (error > 1) {
793 device_printf(dev, "too many reset gpios\n");
794 sc->gpio_rset = NULL;
795 error = ENXIO;
796 goto fail;
797 }
798
799 if (sc->gpio_rset != NULL) {
800 error = GPIO_PIN_SET(sc->gpio_rset->dev, sc->gpio_rset->pin, 0);
801 if (error != 0) {
802 device_printf(dev, "Cannot configure GPIO pin %d on %s\n",
803 sc->gpio_rset->pin, device_get_nameunit(sc->gpio_rset->dev));
804 goto fail;
805 }
806
807 error = GPIO_PIN_SETFLAGS(sc->gpio_rset->dev, sc->gpio_rset->pin,
808 GPIO_PIN_OUTPUT);
809 if (error != 0) {
810 device_printf(dev, "Cannot configure GPIO pin %d on %s\n",
811 sc->gpio_rset->pin, device_get_nameunit(sc->gpio_rset->dev));
812 goto fail;
813 }
814
815 DELAY(2000);
816
817 error = GPIO_PIN_SET(sc->gpio_rset->dev, sc->gpio_rset->pin, 1);
818 if (error != 0) {
819 device_printf(dev, "Cannot configure GPIO pin %d on %s\n",
820 sc->gpio_rset->pin, device_get_nameunit(sc->gpio_rset->dev));
821 goto fail;
822 }
823
824 DELAY(4000);
825 } else
826 device_printf(dev, "Unable to find reset GPIO\n");
827
828 sc->dme_tag = rman_get_bustag(sc->dme_res);
829 sc->dme_handle = rman_get_bushandle(sc->dme_res);
830
831 /* Reset the chip as soon as possible */
832 dme_reset(sc);
833
834 /* Figure IO mode */
835 switch((dme_read_reg(sc, DME_ISR) >> 6) & 0x03) {
836 case 0:
837 /* 16 bit */
838 sc->dme_bits = 16;
839 break;
840 case 1:
841 /* 32 bit */
842 sc->dme_bits = 32;
843 break;
844 case 2:
845 /* 8 bit */
846 sc->dme_bits = 8;
847 break;
848 default:
849 /* reserved */
850 device_printf(dev, "Unable to determine device mode\n");
851 error = ENXIO;
852 goto fail;
853 }
854
855 DELAY(100000);
856
857 /* Read vendor and device id's */
858 data = dme_read_reg(sc, DME_VIDH) << 8;
859 data |= dme_read_reg(sc, DME_VIDL);
860 device_printf(dev, "Vendor ID: 0x%04x\n", data);
861
862 /* Read vendor and device id's */
863 data = dme_read_reg(sc, DME_PIDH) << 8;
864 data |= dme_read_reg(sc, DME_PIDL);
865 device_printf(dev, "Product ID: 0x%04x\n", data);
866
867 /* Chip revision */
868 data = dme_read_reg(sc, DME_CHIPR);
869 device_printf(dev, "Revision: 0x%04x\n", data);
870 if (data != DME_CHIP_DM9000A && data != DME_CHIP_DM9000B)
871 data = DME_CHIP_DM9000;
872 sc->dme_rev = data;
873
874 device_printf(dev, "using %d-bit IO mode\n", sc->dme_bits);
875 KASSERT(sc->dme_bits == 8, ("wrong io mode"));
876
877 /* Try to figure our mac address */
878 dme_get_macaddr(sc);
879
880 /* Configure chip after reset */
881 dme_config(sc);
882
883 ifp = sc->dme_ifp = if_alloc(IFT_ETHER);
884 if (ifp == NULL) {
885 device_printf(dev, "unable to allocate ifp\n");
886 error = ENOSPC;
887 goto fail;
888 }
889 ifp->if_softc = sc;
890
891 /* Setup MII */
892 error = mii_attach(dev, &sc->dme_miibus, ifp, dme_ifmedia_upd,
893 dme_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
894 /* This should never happen as the DM9000 contains it's own PHY */
895 if (error != 0) {
896 device_printf(dev, "PHY probe failed\n");
897 goto fail;
898 }
899
900 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
901 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
902 ifp->if_start = dme_start;
903 ifp->if_ioctl = dme_ioctl;
904 ifp->if_init = dme_init;
905 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
906
907 ether_ifattach(ifp, sc->dme_macaddr);
908
909 error = bus_setup_intr(dev, sc->dme_irq, INTR_TYPE_NET | INTR_MPSAFE,
910 NULL, dme_intr, sc, &sc->dme_intrhand);
911 if (error) {
912 device_printf(dev, "couldn't set up irq\n");
913 ether_ifdetach(ifp);
914 goto fail;
915 }
916
917 fail:
918 if (error != 0)
919 dme_detach(dev);
920 return (error);
921 }
922
923 static int
dme_detach(device_t dev)924 dme_detach(device_t dev)
925 {
926 struct dme_softc *sc;
927 struct ifnet *ifp;
928
929 sc = device_get_softc(dev);
930 KASSERT(mtx_initialized(&sc->dme_mtx), ("dme mutex not initialized"));
931
932 ifp = sc->dme_ifp;
933
934 if (device_is_attached(dev)) {
935 DME_LOCK(sc);
936 dme_stop(sc);
937 DME_UNLOCK(sc);
938 ether_ifdetach(ifp);
939 callout_drain(&sc->dme_tick_ch);
940 }
941
942 if (sc->dme_miibus)
943 device_delete_child(dev, sc->dme_miibus);
944 bus_generic_detach(dev);
945
946 if (sc->dme_vcc_regulator != 0)
947 regulator_release(sc->dme_vcc_regulator);
948 if (sc->dme_intrhand)
949 bus_teardown_intr(dev, sc->dme_irq, sc->dme_intrhand);
950 if (sc->dme_irq)
951 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dme_irq);
952 if (sc->dme_res)
953 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->dme_res);
954
955 if (ifp != NULL)
956 if_free(ifp);
957
958 mtx_destroy(&sc->dme_mtx);
959
960 return (0);
961 }
962
963 /*
964 * The MII bus interface
965 */
966 static int
dme_miibus_readreg(device_t dev,int phy,int reg)967 dme_miibus_readreg(device_t dev, int phy, int reg)
968 {
969 struct dme_softc *sc;
970 int i, rval;
971
972 /* We have up to 4 PHY's */
973 if (phy >= 4)
974 return (0);
975
976 sc = device_get_softc(dev);
977
978 /* Send the register to read to the phy and start the read */
979 dme_write_reg(sc, DME_EPAR, (phy << 6) | reg);
980 dme_write_reg(sc, DME_EPCR, EPCR_EPOS | EPCR_ERPRR);
981
982 /* Wait for the data to be read */
983 for (i = 0; i < DME_TIMEOUT; i++) {
984 if ((dme_read_reg(sc, DME_EPCR) & EPCR_ERRE) == 0)
985 break;
986 DELAY(1);
987 }
988
989 /* Clear the comand */
990 dme_write_reg(sc, DME_EPCR, 0);
991
992 if (i == DME_TIMEOUT)
993 return (0);
994
995 rval = (dme_read_reg(sc, DME_EPDRH) << 8) | dme_read_reg(sc, DME_EPDRL);
996 return (rval);
997 }
998
999 static int
dme_miibus_writereg(device_t dev,int phy,int reg,int data)1000 dme_miibus_writereg(device_t dev, int phy, int reg, int data)
1001 {
1002 struct dme_softc *sc;
1003 int i;
1004
1005 /* We have up to 4 PHY's */
1006 if (phy > 3)
1007 return (0);
1008
1009 sc = device_get_softc(dev);
1010
1011 /* Send the register and data to write to the phy */
1012 dme_write_reg(sc, DME_EPAR, (phy << 6) | reg);
1013 dme_write_reg(sc, DME_EPDRL, data & 0xFF);
1014 dme_write_reg(sc, DME_EPDRH, (data >> 8) & 0xFF);
1015 /* Start the write */
1016 dme_write_reg(sc, DME_EPCR, EPCR_EPOS | EPCR_ERPRW);
1017
1018 /* Wait for the data to be written */
1019 for (i = 0; i < DME_TIMEOUT; i++) {
1020 if ((dme_read_reg(sc, DME_EPCR) & EPCR_ERRE) == 0)
1021 break;
1022 DELAY(1);
1023 }
1024
1025 /* Clear the comand */
1026 dme_write_reg(sc, DME_EPCR, 0);
1027
1028 return (0);
1029 }
1030
1031 static device_method_t dme_methods[] = {
1032 /* Device interface */
1033 DEVMETHOD(device_probe, dme_probe),
1034 DEVMETHOD(device_attach, dme_attach),
1035 DEVMETHOD(device_detach, dme_detach),
1036
1037 /* bus interface, for miibus */
1038 DEVMETHOD(bus_print_child, bus_generic_print_child),
1039 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
1040
1041 /* MII interface */
1042 DEVMETHOD(miibus_readreg, dme_miibus_readreg),
1043 DEVMETHOD(miibus_writereg, dme_miibus_writereg),
1044
1045 { 0, 0 }
1046 };
1047
1048 static driver_t dme_driver = {
1049 "dme",
1050 dme_methods,
1051 sizeof(struct dme_softc)
1052 };
1053
1054 static devclass_t dme_devclass;
1055
1056 MODULE_DEPEND(dme, ether, 1, 1, 1);
1057 MODULE_DEPEND(dme, miibus, 1, 1, 1);
1058 DRIVER_MODULE(dme, simplebus, dme_driver, dme_devclass, 0, 0);
1059 DRIVER_MODULE(miibus, dme, miibus_driver, miibus_devclass, 0, 0);
1060
1061